diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index 58d00d0a1..50951bd09 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -57,6 +57,7 @@ module csr #(parameter input logic SelHPTW, // hardware page table walker active, so base endianness on supervisor mode // inputs for performance counters input logic LoadStallD, + input logic StoreStallD, input logic BPDirPredWrongM, input logic BTBPredPCWrongM, input logic RASPredPCWrongM, @@ -257,7 +258,7 @@ module csr #(parameter if (`ZICOUNTERS_SUPPORTED) begin:counters csrc counters(.clk, .reset, .StallE, .StallM, .FlushM, - .InstrValidNotFlushedM, .LoadStallD, .CSRMWriteM, + .InstrValidNotFlushedM, .LoadStallD, .StoreStallD, .CSRMWriteM, .BPDirPredWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .IClassWrongM, .BPWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .CSRAdrM, .PrivilegeModeW, .CSRWriteValM, diff --git a/src/privileged/csrc.sv b/src/privileged/csrc.sv index 2ea0a0540..7a166effa 100644 --- a/src/privileged/csrc.sv +++ b/src/privileged/csrc.sv @@ -43,7 +43,7 @@ module csrc #(parameter input logic clk, reset, input logic StallE, StallM, input logic FlushM, - input logic InstrValidNotFlushedM, LoadStallD, CSRMWriteM, + input logic InstrValidNotFlushedM, LoadStallD, CSRMWriteM, StoreStallD, input logic BPDirPredWrongM, input logic BTBPredPCWrongM, input logic RASPredPCWrongM, @@ -55,7 +55,7 @@ module csrc #(parameter input logic ICacheMiss, input logic ICacheAccess, input logic [11:0] CSRAdrM, - input logic [1:0] PrivilegeModeW, + input logic [1:0] PrivilegeModeW, input logic [`XLEN-1:0] CSRWriteValM, input logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW, input logic [63:0] MTIME_CLINT, @@ -67,6 +67,7 @@ module csrc #(parameter logic [`XLEN-1:0] HPMCOUNTER_REGW[`COUNTERS-1:0]; logic [`XLEN-1:0] HPMCOUNTERH_REGW[`COUNTERS-1:0]; logic LoadStallE, LoadStallM; + logic StoreStallE, StoreStallM; logic [`COUNTERS-1:0] WriteHPMCOUNTERM; logic [`COUNTERS-1:0] CounterEvent; logic [63:0] HPMCOUNTERPlusM[`COUNTERS-1:0]; @@ -74,8 +75,8 @@ module csrc #(parameter genvar i; // Interface signals - flopenrc #(1) LoadStallEReg(.clk, .reset, .clear(1'b0), .en(~StallE), .d(LoadStallD), .q(LoadStallE)); // don't flush the load stall during a load stall. - flopenrc #(1) LoadStallMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d(LoadStallE), .q(LoadStallM)); + flopenrc #(2) LoadStallEReg(.clk, .reset, .clear(1'b0), .en(~StallE), .d({StoreStallD, LoadStallD}), .q({StoreStallE, LoadStallE})); // don't flush the load stall during a load stall. + flopenrc #(2) LoadStallMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d({StoreStallE, LoadStallE}), .q({StoreStallM, LoadStallM})); // Determine when to increment each counter assign CounterEvent[0] = 1'b1; // MCYCLE always increments @@ -92,8 +93,8 @@ module csrc #(parameter assign CounterEvent[8] = BTBPredPCWrongM & InstrValidNotFlushedM; // branch predictor wrong target assign CounterEvent[9] = RASPredPCWrongM & InstrValidNotFlushedM; // return address stack wrong address assign CounterEvent[10] = IClassWrongM & InstrValidNotFlushedM; // instruction class predictor wrong - assign CounterEvent[11] = LoadStallM & InstrValidNotFlushedM; // Load Stalls. don't want to suppress on flush as this only happens if flushed. - assign CounterEvent[12] = '0 & InstrValidNotFlushedM; // /// ********** store + assign CounterEvent[11] = LoadStallM & InstrValidNotFlushedM; // Load Stalls. don't want to suppress on flush as this only happens if flushed. + assign CounterEvent[12] = StoreStallM & InstrValidNotFlushedM; // Store Stall assign CounterEvent[13] = DCacheAccess & InstrValidNotFlushedM; // data cache access assign CounterEvent[14] = DCacheMiss; // data cache miss. Miss asserted 1 cycle at start of cache miss assign CounterEvent[15] = '0; // //// ******* d cache miss cycles diff --git a/src/privileged/privileged.sv b/src/privileged/privileged.sv index 3cecc6fcd..5f6c17752 100644 --- a/src/privileged/privileged.sv +++ b/src/privileged/privileged.sv @@ -46,11 +46,12 @@ module privileged ( // processor events for performance counter logging input logic FRegWriteM, // instruction will write floating-point registers input logic LoadStallD, // load instruction is stalling - input logic BPDirPredWrongM, // branch predictor guessed wrong directoin - input logic BTBPredPCWrongM, // branch predictor guessed wrong target - input logic RASPredPCWrongM, // return adddress stack guessed wrong target - input logic IClassWrongM, // branch predictor guessed wrong instruction class - input logic BPWrongM, // branch predictor is wrong + input logic StoreStallD, // load instruction is stalling + input logic BPDirPredWrongM, // branch predictor guessed wrong direction + input logic BTBPredPCWrongM, // branch predictor guessed wrong target + input logic RASPredPCWrongM, // return adddress stack guessed wrong target + input logic IClassWrongM, // branch predictor guessed wrong instruction class + input logic BPWrongM, // branch predictor is wrong input logic [3:0] InstrClassM, // actual instruction class input logic DCacheMiss, // data cache miss input logic DCacheAccess, // data cache accessed (hit or miss) @@ -123,7 +124,7 @@ module privileged ( .InstrM, .PCM, .SrcAM, .IEUAdrM, .PC2NextF, .CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .wfiM, .IntPendingM, .InterruptM, .MTimerInt, .MExtInt, .SExtInt, .MSwInt, - .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, + .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .StoreStallD, .BPDirPredWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPWrongM, .IClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .NextPrivilegeModeM, .PrivilegeModeW, .CauseM, .SelHPTW, diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index be85420f7..6acd96924 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -287,7 +287,7 @@ module wallypipelinedcore ( .InstrM, .CSRReadValW, .UnalignedPCNextF, .RetM, .TrapM, .sfencevmaM, .InstrValidM, .CommittedM, .CommittedF, - .FRegWriteM, .LoadStallD, + .FRegWriteM, .LoadStallD, .StoreStallD, .BPDirPredWrongM, .BTBPredPCWrongM, .BPWrongM, .RASPredPCWrongM, .IClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,