From a722c3c0a1c6f06df5771f4107f7fe087748ba71 Mon Sep 17 00:00:00 2001
From: Jacob Pease <jacobpease@protonmail.com>
Date: Mon, 22 Jul 2024 12:36:39 -0500
Subject: [PATCH] Removed the old SDC. Added a second SPI peripheral that now
 will be used to control the SD card. SPI peripheral now outputs SPICLK.
 Removed references to the now non-existent external SDC in uncore. Removed
 all of the AXI Xilinx IP.

---
 fpga/src/fpgaTopArtyA7.sv      | 828 ++++-----------------------------
 src/uncore/spi_apb.sv          |  17 +-
 src/uncore/uncore.sv           |  47 +-
 src/wally/wallypipelinedsoc.sv |  10 +-
 4 files changed, 144 insertions(+), 758 deletions(-)

diff --git a/fpga/src/fpgaTopArtyA7.sv b/fpga/src/fpgaTopArtyA7.sv
index 9ddf958a7..6a2f055ba 100644
--- a/fpga/src/fpgaTopArtyA7.sv
+++ b/fpga/src/fpgaTopArtyA7.sv
@@ -29,38 +29,43 @@
 import cvw::*;
 
 module fpgaTop 
-  (input           default_100mhz_clk,
-(* mark_debug = "true" *)   input           resetn,
-   input           south_reset,
+  (input         default_100mhz_clk,
+   input         resetn,
+   input         south_reset,
 
-   input [3:0]     GPI,
-   output [4:0]    GPO,
+   // GPIO signals
+   input [3:0]   GPI,
+   output [4:0]  GPO,
 
-   input           UARTSin,
-   output          UARTSout,
+   // UART Signals
+   input         UARTSin,
+   output        UARTSout,
 
-   inout [3:0]     SDCDat,
-   output          SDCCLK,
-   inout           SDCCmd,
-   input           SDCCD,
+   // SDC Signals connecting to an SPI peripheral
+   input [3:0]   SDCDat,
+   output        SDCCLK,
+   output        SDCCmd,
+   output        SDCCD,
 
-   inout [15:0]    ddr3_dq,
-   inout [1:0]     ddr3_dqs_n,
-   inout [1:0]     ddr3_dqs_p,
-   output [13:0]   ddr3_addr,
-   output [2:0]    ddr3_ba,
-   output          ddr3_ras_n,
-   output          ddr3_cas_n,
-   output          ddr3_we_n,
-   output          ddr3_reset_n,
-   output [0:0]    ddr3_ck_p,
-   output [0:0]    ddr3_ck_n,
-   output [0:0]    ddr3_cke,
-   output [0:0]    ddr3_cs_n,
-   output [1:0]    ddr3_dm,
-   output [0:0]    ddr3_odt
+   // Memory signals
+   inout [15:0]  ddr3_dq,
+   inout [1:0]   ddr3_dqs_n,
+   inout [1:0]   ddr3_dqs_p,
+   output [13:0] ddr3_addr,
+   output [2:0]  ddr3_ba,
+   output        ddr3_ras_n,
+   output        ddr3_cas_n,
+   output        ddr3_we_n,
+   output        ddr3_reset_n,
+   output [0:0]  ddr3_ck_p,
+   output [0:0]  ddr3_ck_n,
+   output [0:0]  ddr3_cke,
+   output [0:0]  ddr3_cs_n,
+   output [1:0]  ddr3_dm,
+   output [0:0]  ddr3_odt
    );
 
+  // MMCM Signals
   wire 			   CPUCLK;
   wire 			   c0_ddr4_ui_clk_sync_rst;
   wire 			   bus_struct_reset;
@@ -69,6 +74,7 @@ module fpgaTop
   wire 			   peripheral_aresetn;
   wire 			   mb_reset;
   
+  // AHB Signals from Wally
   wire 			   HCLKOpen;
   wire 			   HRESETnOpen;
   wire [63:0]      HRDATAEXT;
@@ -87,12 +93,10 @@ module fpgaTop
   wire [3:0] 	   HPROT;
   wire 			   HMASTLOCK;
 
+  // GPIO Signals
   wire [31:0] 	   GPIOIN, GPIOOUT, GPIOEN;
 
-  wire 			   SDCCmdIn;
-  wire 			   SDCCmdOE;
-  wire 			   SDCCmdOut;
-
+  // AHB to AXI Bridge Signals
   wire [3:0] 	   m_axi_awid;
   wire [7:0] 	   m_axi_awlen;
   wire [2:0] 	   m_axi_awsize;
@@ -100,40 +104,40 @@ module fpgaTop
   wire [3:0] 	   m_axi_awcache;
   wire [31:0] 	   m_axi_awaddr;
   wire [2:0] 	   m_axi_awprot;
-  wire 		   m_axi_awvalid;
-  wire 		   m_axi_awready;
-  wire 		   m_axi_awlock;
+  wire             m_axi_awvalid;
+  wire             m_axi_awready;
+  wire             m_axi_awlock;
   wire [63:0] 	   m_axi_wdata;
   wire [7:0] 	   m_axi_wstrb;
-  wire 		   m_axi_wlast;
-  wire 		   m_axi_wvalid;
-  wire 		   m_axi_wready;
+  wire             m_axi_wlast;
+  wire             m_axi_wvalid;
+  wire             m_axi_wready;
   wire [3:0] 	   m_axi_bid;
   wire [1:0] 	   m_axi_bresp;
-  wire 		   m_axi_bvalid;
-  wire 		   m_axi_bready;
+  wire             m_axi_bvalid;
+  wire             m_axi_bready;
   wire [3:0] 	   m_axi_arid;
   wire [7:0] 	   m_axi_arlen;
   wire [2:0] 	   m_axi_arsize;
   wire [1:0] 	   m_axi_arburst;
   wire [2:0] 	   m_axi_arprot;
   wire [3:0] 	   m_axi_arcache;
-  wire 		   m_axi_arvalid;
+  wire             m_axi_arvalid;
   wire [31:0] 	   m_axi_araddr;
   wire 			   m_axi_arlock;
-  wire 		   m_axi_arready;
+  wire             m_axi_arready;
   wire [3:0] 	   m_axi_rid;
   wire [63:0] 	   m_axi_rdata;
   wire [1:0] 	   m_axi_rresp;
-  wire 		   m_axi_rvalid;
-  wire 		   m_axi_rlast;
-  wire 		   m_axi_rready;
+  wire             m_axi_rvalid;
+  wire             m_axi_rlast;
+  wire             m_axi_rready;
 
+  // AXI Signals going out of Clock Converter
   wire [3:0] 	   BUS_axi_arregion;
   wire [3:0] 	   BUS_axi_arqos;
   wire [3:0] 	   BUS_axi_awregion;
   wire [3:0] 	   BUS_axi_awqos;
-
   wire [3:0] 	   BUS_axi_awid;
   wire [7:0] 	   BUS_axi_awlen;
   wire [2:0] 	   BUS_axi_awsize;
@@ -173,250 +177,10 @@ module fpgaTop
   wire 			   BUSCLK;
   wire             sdio_reset_open;
   
-  // Crossbar to Bus ------------------------------------------------
-
-  wire s00_axi_aclk;
-  wire s00_axi_aresetn;
-  wire [3:0] s00_axi_awid;
-  wire [31:0]s00_axi_awaddr;
-  wire [7:0]s00_axi_awlen;
-  wire [2:0]s00_axi_awsize;
-  wire [1:0]s00_axi_awburst;
-  wire [0:0]s00_axi_awlock;
-  wire [3:0]s00_axi_awcache;
-  wire [2:0]s00_axi_awprot;
-  wire [3:0]s00_axi_awregion;
-  wire [3:0]s00_axi_awqos;
-   wire s00_axi_awvalid;
-   wire s00_axi_awready;
-  wire [63:0]s00_axi_wdata;
-  wire [7:0]s00_axi_wstrb;
-  wire s00_axi_wlast;
-  wire s00_axi_wvalid;
-  wire s00_axi_wready;
-  wire [1:0]s00_axi_bresp;
-  wire s00_axi_bvalid;
-  wire s00_axi_bready;
-  wire [3:0]       s00_axi_arid;
-  wire [31:0]s00_axi_araddr;
-  wire [7:0]s00_axi_arlen;
-  wire [2:0]s00_axi_arsize;
-  wire [1:0]s00_axi_arburst;
-  wire [0:0]s00_axi_arlock;
-  wire [3:0]s00_axi_arcache;
-  wire [2:0]s00_axi_arprot;
-  wire [3:0]s00_axi_arregion;
-  wire [3:0]s00_axi_arqos;
-  wire s00_axi_arvalid;
-  wire s00_axi_arready;
-  wire [63:0]s00_axi_rdata;
-  wire [1:0]s00_axi_rresp;
-  wire s00_axi_rlast;
-  wire s00_axi_rvalid;
-  wire s00_axi_rready;
-
-  wire [3:0] s00_axi_bid;
-  wire [3:0] s00_axi_rid;
-   
-  // 64to32 dwidth converter input interface-------------------------
-  wire s01_axi_aclk;
-  wire s01_axi_aresetn;
-  wire [3:0]s01_axi_awid;
-  wire [31:0]s01_axi_awaddr;
-  wire [7:0]s01_axi_awlen;
-  wire [2:0]s01_axi_awsize;
-  wire [1:0]s01_axi_awburst;
-  wire [0:0]s01_axi_awlock;
-  wire [3:0]s01_axi_awcache;
-  wire [2:0]s01_axi_awprot;
-  wire [3:0]s01_axi_awregion;
-  wire [3:0]s01_axi_awqos; // qos signals need to be 0 for SDC
-   wire s01_axi_awvalid;
-   wire s01_axi_awready;
-  wire [63:0]s01_axi_wdata;
-  wire [7:0]s01_axi_wstrb;
-  wire s01_axi_wlast;
-  wire s01_axi_wvalid;
-  wire s01_axi_wready;
-  wire [1:0]s01_axi_bresp;
-  wire s01_axi_bvalid;
-  wire s01_axi_bready;
-  wire [31:0]s01_axi_araddr;
-  wire [7:0]s01_axi_arlen;
-  wire [3:0] s01_axi_arid;
-  wire [2:0]s01_axi_arsize;
-  wire [1:0]s01_axi_arburst;
-  wire [0:0]s01_axi_arlock;
-  wire [3:0]s01_axi_arcache;
-  wire [2:0]s01_axi_arprot;
-  wire [3:0]s01_axi_arregion;
-  wire [3:0]s01_axi_arqos; //
-  wire s01_axi_arvalid;
-  wire s01_axi_arready;
-  wire [63:0]s01_axi_rdata;
-  wire [1:0]s01_axi_rresp;
-  wire s01_axi_rlast;
-  wire s01_axi_rvalid;
-  wire s01_axi_rready;
-
-  // Output Interface
-  wire [31:0]axi4in_axi_awaddr;
-  wire [7:0]axi4in_axi_awlen;
-  wire [2:0]axi4in_axi_awsize;
-  wire [1:0]axi4in_axi_awburst;
-  wire [0:0]axi4in_axi_awlock;
-  wire [3:0]axi4in_axi_awcache;
-  wire [2:0]axi4in_axi_awprot;
-  wire [3:0]axi4in_axi_awregion;
-  wire [3:0]axi4in_axi_awqos;
-   wire axi4in_axi_awvalid;
-   wire axi4in_axi_awready;
-  wire [31:0]axi4in_axi_wdata;
-  wire [3:0]axi4in_axi_wstrb;
-  wire axi4in_axi_wlast;
-  wire axi4in_axi_wvalid;
-  wire axi4in_axi_wready;
-  wire [1:0]axi4in_axi_bresp;
-  wire axi4in_axi_bvalid;
-  wire axi4in_axi_bready;
-  wire [31:0]axi4in_axi_araddr;
-  wire [7:0]axi4in_axi_arlen;
-  wire [2:0]axi4in_axi_arsize;
-  wire [1:0]axi4in_axi_arburst;
-  wire [0:0]axi4in_axi_arlock;
-  wire [3:0]axi4in_axi_arcache;
-  wire [2:0]axi4in_axi_arprot;
-  wire [3:0]axi4in_axi_arregion;
-  wire [3:0]axi4in_axi_arqos;
-  wire axi4in_axi_arvalid;
-  wire axi4in_axi_arready;
-  wire [31:0]axi4in_axi_rdata;
-  wire [1:0]axi4in_axi_rresp;
-  wire axi4in_axi_rlast;
-  wire axi4in_axi_rvalid;
-  wire axi4in_axi_rready;
-
-  // AXI4 to AXI4-Lite Protocol converter output
-   wire [31:0]SDCin_axi_awaddr;
-   wire [2:0]SDCin_axi_awprot;
-   wire SDCin_axi_awvalid;
-   wire SDCin_axi_awready;
-   wire [31:0]SDCin_axi_wdata;
-   wire [3:0]SDCin_axi_wstrb;
-   wire SDCin_axi_wvalid;
-   wire SDCin_axi_wready;
-   wire [1:0]SDCin_axi_bresp;
-   wire SDCin_axi_bvalid;
-   wire SDCin_axi_bready;
-   wire [31:0]SDCin_axi_araddr;
-   wire [2:0]SDCin_axi_arprot;
-   wire SDCin_axi_arvalid;
-   wire SDCin_axi_arready;
-   wire [31:0]SDCin_axi_rdata;
-   wire [1:0]SDCin_axi_rresp;
-   wire SDCin_axi_rvalid;
-   wire SDCin_axi_rready;
-  // ----------------------------------------------------------------
-
-  // 32to64 dwidth converter input interface -----------------------
-   wire [31:0]SDCout_axi_awaddr;
-   wire [7:0]SDCout_axi_awlen;
-  wire [2:0]SDCout_axi_awsize;
-  wire [1:0]SDCout_axi_awburst;
-  wire [0:0]SDCout_axi_awlock;
-  wire [3:0]SDCout_axi_awcache;
-  wire [2:0]SDCout_axi_awprot;
-  wire [3:0]SDCout_axi_awregion;
-  wire [3:0]SDCout_axi_awqos;
-   wire SDCout_axi_awvalid;
-   wire SDCout_axi_awready;
-   wire [31:0]SDCout_axi_wdata;
-  wire [3:0]SDCout_axi_wstrb;
-   wire SDCout_axi_wlast;
-   wire SDCout_axi_wvalid;
-  wire SDCout_axi_wready;
-   wire [1:0]SDCout_axi_bresp;
-   wire SDCout_axi_bvalid;
-   wire SDCout_axi_bready;
-  wire [31:0]SDCout_axi_araddr;
-  wire [7:0]SDCout_axi_arlen;
-  wire [2:0]SDCout_axi_arsize;
-  wire [1:0]SDCout_axi_arburst;
-  wire [0:0]SDCout_axi_arlock;
-  wire [3:0]SDCout_axi_arcache;
-  wire [2:0]SDCout_axi_arprot;
-  wire [3:0]SDCout_axi_arregion;
-  wire [3:0]SDCout_axi_arqos;
-  wire SDCout_axi_arvalid;
-  wire SDCout_axi_arready;
-  wire [31:0]SDCout_axi_rdata;
-  wire [1:0]SDCout_axi_rresp;
-  wire SDCout_axi_rlast;
-  wire SDCout_axi_rvalid;
-  wire SDCout_axi_rready;
-
-  // Output Interface
-   wire [3:0]m01_axi_awid;
-    wire [31:0]m01_axi_awaddr;
-    wire [7:0]m01_axi_awlen;
-    wire [2:0]m01_axi_awsize;
-    wire [1:0]m01_axi_awburst;
-    wire [0:0]m01_axi_awlock;
-    wire [3:0]m01_axi_awcache;
-    wire [2:0]m01_axi_awprot;
-    wire [3:0]m01_axi_awregion;
-    wire [3:0]m01_axi_awqos;
-   wire m01_axi_awvalid;
-   wire m01_axi_awready;
-    wire [63:0]m01_axi_wdata;
-    wire [7:0]m01_axi_wstrb;
-    wire m01_axi_wlast;
-    wire m01_axi_wvalid;
-    wire m01_axi_wready;
-    wire [3:0] m01_axi_bid;
-    wire [1:0]m01_axi_bresp;
-    wire m01_axi_bvalid;
-    wire m01_axi_bready;
-    wire [3:0] m01_axi_arid;
-    wire [31:0]m01_axi_araddr;
-    wire [7:0]m01_axi_arlen;
-    wire [2:0]m01_axi_arsize;
-    wire [1:0]m01_axi_arburst;
-    wire [0:0]m01_axi_arlock;
-    wire [3:0]m01_axi_arcache;
-    wire [2:0]m01_axi_arprot;
-    wire [3:0]m01_axi_arregion;
-    wire [3:0]m01_axi_arqos;
-    wire m01_axi_arvalid;
-    wire m01_axi_arready;
-    wire [3:0] m01_axi_rid;
-    wire [63:0]m01_axi_rdata;
-    wire [1:0]m01_axi_rresp;
-    wire m01_axi_rlast;
-    wire m01_axi_rvalid;
-   wire m01_axi_rready;
-
-  // Old SDC input
-  // wire [3:0] SDCDatIn;
-
-  // New SDC Command IOBUF connections
-  wire       sd_cmd_i;
-  wire        sd_cmd_reg_o;
-  wire        sd_cmd_reg_t;
-
-  // SD Card Interrupt signal
-   wire        SDCIntr;
-
-  // New SDC Data IOBUF connections
-  wire [3:0] sd_dat_i;
-  wire  [3:0] sd_dat_reg_o;
-  wire        sd_dat_reg_t;
-  
-
-    wire 			   c0_init_calib_complete;
+  wire             c0_init_calib_complete;
   wire 			   dbg_clk;
   wire [511 : 0]   dbg_bus;
-     wire             ui_clk_sync_rst;
+  wire             ui_clk_sync_rst;
   
   wire 			   CLK208;
   wire             clk167;
@@ -425,9 +189,9 @@ module fpgaTop
   wire             app_sr_active;
   wire             app_ref_ack;
   wire             app_zq_ack;
-    wire             mmcm_locked;
+  wire             mmcm_locked;
   wire [11:0]      device_temp;
-    wire             mmcm1_locked;
+  wire             mmcm1_locked;
   
 
   assign GPIOIN = {28'b0, GPI};
@@ -436,6 +200,11 @@ module fpgaTop
   assign cpu_reset = bus_struct_reset;
   assign calib = c0_init_calib_complete;
 
+  logic [3:0] SDCCS;
+  assign SDCCD = SDCCS[0];
+  logic SDCIn;
+  assign SDCIn = SDCDat[0];
+
   // mmcm
 
   // the ddr3 mig7 requires 2 input clocks 
@@ -449,26 +218,7 @@ module fpgaTop
                      .reset(1'b0),
                      .locked(mmcm1_locked),
                      .clk_in1(default_100mhz_clk));
-  
-/* -----\/----- EXCLUDED -----\/-----
-  // SD Card Tristate
-  IOBUF iobufSDCMD(.T(~SDCCmdOE), // iobuf's T is active low
-				   .I(SDCCmdOut),
-				   .O(SDCCmdIn),
-				   .IO(SDCCmd));
- -----/\----- EXCLUDED -----/\----- */
 
-   // IOBUFS for new SDC peripheral
-   IOBUF IOBUF_cmd (.O(sd_cmd_i), .IO(SDCCmd), .I(sd_cmd_reg_o), .T(sd_cmd_reg_t));
-   genvar    i;
-   generate
-      for (i = 0; i < 4; i = i + 1) begin
-         IOBUF iobufSDCDat(.T(sd_dat_reg_t),
-                           .I(sd_dat_reg_o[i]),
-                           .O(sd_dat_i[i]),
-                           .IO(SDCDat[i]) );
-      end
-   endgenerate
   
 
   // reset controller XILINX IP
@@ -484,11 +234,9 @@ module fpgaTop
      .interconnect_aresetn(interconnect_aresetn), //open
      .peripheral_aresetn(peripheral_aresetn));
 
-  // wally
-  // RT and JP: FIXME add sdc interrupt and HSELEXTSDC, remove old sdc after the new sdc ahb version is implemented
-
   `include "parameter-defs.vh"
-
+  
+  // Wally 
   wallypipelinedsoc  #(P) 
   wallypipelinedsoc(.clk(CPUCLK), .reset_ext(bus_struct_reset), .reset(), 
                     .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT,
@@ -496,7 +244,7 @@ module fpgaTop
                     .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
                     .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), 
                     .GPIOIN, .GPIOOUT, .GPIOEN,
-                    .UARTSin, .UARTSout, .SDCIntr); 
+                    .UARTSin, .UARTSout, .SDCIn, .SDCCmd, .SDCCS, .SDCCLK); 
 
 
   // ahb lite to axi bridge
@@ -551,432 +299,49 @@ module fpgaTop
      .m_axi_rlast(m_axi_rlast),
      .m_axi_rready(m_axi_rready));
 
-  // AXI Crossbar for arbitrating the SDC and CPU --------------
-  xlnx_axi_crossbar xlnx_axi_crossbar_0
-   	(.aclk(CPUCLK),
-	 .aresetn(peripheral_aresetn),
-
-	 // Connect Masters
-	 .s_axi_awid({4'b1000, m_axi_awid}),
-	 .s_axi_awaddr({m01_axi_awaddr, m_axi_awaddr}),
-	 .s_axi_awlen({m01_axi_awlen, m_axi_awlen}),
-	 .s_axi_awsize({m01_axi_awsize, m_axi_awsize}),
-	 .s_axi_awburst({m01_axi_awburst, m_axi_awburst}),
-	 .s_axi_awlock({m01_axi_awlock, m_axi_awlock}),
-	 .s_axi_awcache({m01_axi_awcache, m_axi_awcache}),
-	 .s_axi_awprot({m01_axi_awprot, m_axi_awprot}),
-	 .s_axi_awqos(8'b0),
-	 .s_axi_awvalid({m01_axi_awvalid, m_axi_awvalid}),
-	 .s_axi_awready({m01_axi_awready, m_axi_awready}),
-	 .s_axi_wdata({m01_axi_wdata, m_axi_wdata}),
-	 .s_axi_wstrb({m01_axi_wstrb, m_axi_wstrb}),
-	 .s_axi_wlast({m01_axi_wlast, m_axi_wlast}),
-	 .s_axi_wvalid({m01_axi_wvalid, m_axi_wvalid}),
-	 .s_axi_wready({m01_axi_wready, m_axi_wready}),
-	 .s_axi_bid({m01_axi_bid, m_axi_bid}),
-	 .s_axi_bresp({m01_axi_bresp, m_axi_bresp}),
-	 .s_axi_bvalid({m01_axi_bvalid, m_axi_bvalid}),
-	 .s_axi_bready({m01_axi_bready, m_axi_bready}),
-	 .s_axi_arid({4'b1000, m_axi_arid}),
-	 .s_axi_araddr({m01_axi_araddr, m_axi_araddr}),
-	 .s_axi_arlen({m01_axi_arlen, m_axi_arlen}),
-	 .s_axi_arsize({m01_axi_arsize, m_axi_arsize}),
-	 .s_axi_arburst({m01_axi_arburst, m_axi_arburst}),
-	 .s_axi_arlock({m01_axi_arlock, m_axi_arlock}),
-	 .s_axi_arcache({m01_axi_arcache, m_axi_arcache}),
-	 .s_axi_arprot({m01_axi_arprot, m_axi_arprot}),
-	 .s_axi_arqos(8'b0),
-	 .s_axi_arvalid({m01_axi_arvalid, m_axi_arvalid}),
-	 .s_axi_arready({m01_axi_arready, m_axi_arready}),
-	 .s_axi_rid({m01_axi_rid, m_axi_rid}),
-	 .s_axi_rdata({m01_axi_rdata, m_axi_rdata}),
-	 .s_axi_rresp({m01_axi_rresp, m_axi_rresp}),
-	 .s_axi_rlast({m01_axi_rlast, m_axi_rlast}),
-	 .s_axi_rvalid({m01_axi_rvalid, m_axi_rvalid}),
-	 .s_axi_rready({m01_axi_rready, m_axi_rready}),
-	 
-	 // Connect Slaves
-     .m_axi_awid({s01_axi_awid, s00_axi_awid}),
-     .m_axi_awlen({s01_axi_awlen, s00_axi_awlen}),
-     .m_axi_awsize({s01_axi_awsize, s00_axi_awsize}),
-     .m_axi_awburst({s01_axi_awburst, s00_axi_awburst}),
-     .m_axi_awcache({s01_axi_awcache, s00_axi_awcache}),
-     .m_axi_awaddr({s01_axi_awaddr, s00_axi_awaddr}),
-     .m_axi_awprot({s01_axi_awprot, s00_axi_awprot}),
-     .m_axi_awregion({s01_axi_awregion, s00_axi_awregion}),
-     .m_axi_awqos({s01_axi_awqos, s00_axi_awqos}),
-     .m_axi_awvalid({s01_axi_awvalid, s00_axi_awvalid}),
-     .m_axi_awready({s01_axi_awready, s00_axi_awready}),
-     .m_axi_awlock({s01_axi_awlock, s00_axi_awlock}),
-     .m_axi_wdata({s01_axi_wdata, s00_axi_wdata}),
-     .m_axi_wstrb({s01_axi_wstrb, s00_axi_wstrb}),
-     .m_axi_wlast({s01_axi_wlast, s00_axi_wlast}),
-     .m_axi_wvalid({s01_axi_wvalid, s00_axi_wvalid}),
-     .m_axi_wready({s01_axi_wready, s00_axi_wready}),
-     .m_axi_bid({4'b1000, s00_axi_bid}),
-     .m_axi_bresp({s01_axi_bresp, s00_axi_bresp}),
-     .m_axi_bvalid({s01_axi_bvalid, s00_axi_bvalid}),
-     .m_axi_bready({s01_axi_bready, s00_axi_bready}),
-     .m_axi_arid({s01_axi_arid, s00_axi_arid}),
-     .m_axi_arlen({s01_axi_arlen, s00_axi_arlen}),
-     .m_axi_arsize({s01_axi_arsize, s00_axi_arsize}),
-     .m_axi_arburst({s01_axi_arburst, s00_axi_arburst}),
-     .m_axi_arprot({s01_axi_arprot, s00_axi_arprot}),
-     .m_axi_arregion({s01_axi_arregion, s00_axi_arregion}),
-     .m_axi_arqos({s01_axi_arqos, s00_axi_arqos}),
-     .m_axi_arcache({s01_axi_arcache, s00_axi_arcache}),
-     .m_axi_arvalid({s01_axi_arvalid, s00_axi_arvalid}),
-     .m_axi_araddr({s01_axi_araddr, s00_axi_araddr}),
-     .m_axi_arlock({s01_axi_arlock, s00_axi_arlock}),
-     .m_axi_arready({s01_axi_arready, s00_axi_arready}),
-     .m_axi_rid({4'b1000, s00_axi_rid}),
-     .m_axi_rdata({s01_axi_rdata, s00_axi_rdata}),
-     .m_axi_rresp({s01_axi_rresp, s00_axi_rresp}),
-     .m_axi_rvalid({s01_axi_rvalid, s00_axi_rvalid}),
-     .m_axi_rlast({s01_axi_rlast, s00_axi_rlast}),
-     .m_axi_rready({s01_axi_rready, s00_axi_rready})
-	 );
-   
-   // -----------------------------------------------------
-
-   // SDC Implementation ----------------------------------
-   //
-   // The SDC peripheral from Eugene Tarassov takes in an AXI4Lite
-   // interface and outputs an AXI4 interface. In order to convert from
-   // one to the other, we use these dwidth converters to make sure the
-   // bit widths match the rest of the bus.
-   
-   xlnx_axi_dwidth_conv_64to32 axi_conv_down
-	(.s_axi_aclk(CPUCLK),
-	 .s_axi_aresetn(peripheral_aresetn),
-
-	 // Slave interface
-	 .s_axi_awaddr(s01_axi_awaddr),
-	 .s_axi_awlen(s01_axi_awlen),
-	 .s_axi_awsize(s01_axi_awsize),
-	 .s_axi_awburst(s01_axi_awburst),
-	 .s_axi_awlock(s01_axi_awlock),
-	 .s_axi_awcache(s01_axi_awcache),
-	 .s_axi_awprot(s01_axi_awprot),
-	 .s_axi_awregion(s01_axi_awregion),
-	 .s_axi_awqos(4'b0),
-	 .s_axi_awvalid(s01_axi_awvalid),
-	 .s_axi_awready(s01_axi_awready),
-	 .s_axi_wdata(s01_axi_wdata),
-	 .s_axi_wstrb(s01_axi_wstrb),
-	 .s_axi_wlast(s01_axi_wlast),
-	 .s_axi_wvalid(s01_axi_wvalid),
-	 .s_axi_wready(s01_axi_wready),
-	 .s_axi_bresp(s01_axi_bresp),
-	 .s_axi_bvalid(s01_axi_bvalid),
-	 .s_axi_bready(s01_axi_bready),
-	 .s_axi_araddr(s01_axi_araddr),
-	 .s_axi_arlen(s01_axi_arlen),
-	 .s_axi_arsize(s01_axi_arsize),
-	 .s_axi_arburst(s01_axi_arburst),
-	 .s_axi_arlock(s01_axi_arlock),
-	 .s_axi_arcache(s01_axi_arcache),
-	 .s_axi_arprot(s01_axi_arprot),
-	 .s_axi_arregion(s01_axi_arregion),
-	 .s_axi_arqos(4'b0),
-	 .s_axi_arvalid(s01_axi_arvalid),
-	 .s_axi_arready(s01_axi_arready),
-	 .s_axi_rdata(s01_axi_rdata),
-	 .s_axi_rresp(s01_axi_rresp),
-	 .s_axi_rlast(s01_axi_rlast),
-	 .s_axi_rvalid(s01_axi_rvalid),
-	 .s_axi_rready(s01_axi_rready),
-
-	 // Master interface
-	 .m_axi_awaddr(axi4in_axi_awaddr),
-	 .m_axi_awlen(axi4in_axi_awlen),
-	 .m_axi_awsize(axi4in_axi_awsize),
-	 .m_axi_awburst(axi4in_axi_awburst),
-	 .m_axi_awlock(axi4in_axi_awlock),
-	 .m_axi_awcache(axi4in_axi_awcache),
-	 .m_axi_awprot(axi4in_axi_awprot),
-	 .m_axi_awregion(axi4in_axi_awregion),
-	 .m_axi_awqos(axi4in_axi_awqos),
-	 .m_axi_awvalid(axi4in_axi_awvalid),
-	 .m_axi_awready(axi4in_axi_awready),
-	 .m_axi_wdata(axi4in_axi_wdata),
-	 .m_axi_wstrb(axi4in_axi_wstrb),
-	 .m_axi_wlast(axi4in_axi_wlast),
-	 .m_axi_wvalid(axi4in_axi_wvalid),
-	 .m_axi_wready(axi4in_axi_wready),
-	 .m_axi_bresp(axi4in_axi_bresp),
-	 .m_axi_bvalid(axi4in_axi_bvalid),
-	 .m_axi_bready(axi4in_axi_bready),
-	 .m_axi_araddr(axi4in_axi_araddr),
-	 .m_axi_arlen(axi4in_axi_arlen),
-	 .m_axi_arsize(axi4in_axi_arsize),
-	 .m_axi_arburst(axi4in_axi_arburst),
-	 .m_axi_arlock(axi4in_axi_arlock),
-	 .m_axi_arcache(axi4in_axi_arcache),
-	 .m_axi_arprot(axi4in_axi_arprot),
-	 .m_axi_arregion(axi4in_axi_arregion),
-	 .m_axi_arqos(axi4in_axi_arqos),
-	 .m_axi_arvalid(axi4in_axi_arvalid),
-	 .m_axi_arready(axi4in_axi_arready),
-	 .m_axi_rdata(axi4in_axi_rdata),
-	 .m_axi_rresp(axi4in_axi_rresp),
-	 .m_axi_rlast(axi4in_axi_rlast),
-	 .m_axi_rvalid(axi4in_axi_rvalid),
-	 .m_axi_rready(axi4in_axi_rready)
-	 );
-   
-  xlnx_axi_prtcl_conv axi4tolite
-    (.aclk(CPUCLK),
-     .aresetn(peripheral_aresetn),
-
-     // AXI4 In
-     .s_axi_awaddr(axi4in_axi_awaddr),
-     .s_axi_awlen(axi4in_axi_awlen),
-     .s_axi_awsize(axi4in_axi_awsize),
-     .s_axi_awburst(axi4in_axi_awburst),
-     .s_axi_awlock(axi4in_axi_awlock),
-     .s_axi_awcache(axi4in_axi_awcache),
-     .s_axi_awprot(axi4in_axi_awprot),
-     .s_axi_awregion(axi4in_axi_awregion),
-     .s_axi_awqos(axi4in_axi_awqos),
-     .s_axi_awvalid(axi4in_axi_awvalid),
-     .s_axi_awready(axi4in_axi_awready),
-     .s_axi_wdata(axi4in_axi_wdata),
-     .s_axi_wstrb(axi4in_axi_wstrb),
-     .s_axi_wlast(axi4in_axi_wlast),
-     .s_axi_wvalid(axi4in_axi_wvalid),
-     .s_axi_wready(axi4in_axi_wready),
-     .s_axi_bresp(axi4in_axi_bresp),
-     .s_axi_bvalid(axi4in_axi_bvalid),
-     .s_axi_bready(axi4in_axi_bready),
-     .s_axi_araddr(axi4in_axi_araddr),
-     .s_axi_arlen(axi4in_axi_arlen),
-     .s_axi_arsize(axi4in_axi_arsize),
-     .s_axi_arburst(axi4in_axi_arburst),
-     .s_axi_arlock(axi4in_axi_arlock),
-     .s_axi_arcache(axi4in_axi_arcache),
-     .s_axi_arprot(axi4in_axi_arprot),
-     .s_axi_arregion(axi4in_axi_arregion),
-     .s_axi_arqos(axi4in_axi_arqos),
-     .s_axi_arvalid(axi4in_axi_arvalid),
-     .s_axi_arready(axi4in_axi_arready),
-     .s_axi_rdata(axi4in_axi_rdata),
-     .s_axi_rresp(axi4in_axi_rresp),
-     .s_axi_rlast(axi4in_axi_rlast),
-     .s_axi_rvalid(axi4in_axi_rvalid),
-     .s_axi_rready(axi4in_axi_rready),
-
-     // AXI4Lite Out
-     .m_axi_awaddr(SDCin_axi_awaddr),
-     .m_axi_awprot(SDCin_axi_awprot),
-     .m_axi_awvalid(SDCin_axi_awvalid),
-     .m_axi_awready(SDCin_axi_awready),
-     .m_axi_wdata(SDCin_axi_wdata),
-     .m_axi_wstrb(SDCin_axi_wstrb),
-     .m_axi_wvalid(SDCin_axi_wvalid),
-     .m_axi_wready(SDCin_axi_wready),
-     .m_axi_bresp(SDCin_axi_bresp),
-     .m_axi_bvalid(SDCin_axi_bvalid),
-     .m_axi_bready(SDCin_axi_bready),
-     .m_axi_araddr(SDCin_axi_araddr),
-     .m_axi_arprot(SDCin_axi_arprot),
-     .m_axi_arvalid(SDCin_axi_arvalid),
-     .m_axi_arready(SDCin_axi_arready),
-     .m_axi_rdata(SDCin_axi_rdata),
-     .m_axi_rresp(SDCin_axi_rresp),
-     .m_axi_rvalid(SDCin_axi_rvalid),
-     .m_axi_rready(SDCin_axi_rready)
-     
-     );
-   
-
-  sdc_controller axiSDC
-	(.clock(CPUCLK),
-	 .async_resetn(peripheral_aresetn),
-	 
-	 // Slave Interface
-	 .s_axi_awaddr({8'b0, SDCin_axi_awaddr[7:0]}),
-	 .s_axi_awvalid(SDCin_axi_awvalid),
-	 .s_axi_awready(SDCin_axi_awready),
-	 .s_axi_wdata(SDCin_axi_wdata),
-	 .s_axi_wvalid(SDCin_axi_wvalid),
-	 .s_axi_wready(SDCin_axi_wready),
-	 .s_axi_bresp(SDCin_axi_bresp),
-	 .s_axi_bvalid(SDCin_axi_bvalid),
-	 .s_axi_bready(SDCin_axi_bready),
-	 .s_axi_araddr({8'b0, SDCin_axi_araddr[7:0]}),
-	 .s_axi_arvalid(SDCin_axi_arvalid),
-	 .s_axi_arready(SDCin_axi_arready),
-	 .s_axi_rdata(SDCin_axi_rdata),
-	 .s_axi_rresp(SDCin_axi_rresp),
-	 .s_axi_rvalid(SDCin_axi_rvalid),
-	 .s_axi_rready(SDCin_axi_rready),
-     .sdio_reset(sdio_reset_open),
-	 
-	 // Master Interface
-	 .m_axi_awaddr(SDCout_axi_awaddr),
-	 .m_axi_awlen(SDCout_axi_awlen),
-	 .m_axi_awvalid(SDCout_axi_awvalid),
-	 .m_axi_awready(SDCout_axi_awready),
-	 .m_axi_wdata(SDCout_axi_wdata),
-	 .m_axi_wlast(SDCout_axi_wlast),
-	 .m_axi_wvalid(SDCout_axi_wvalid),
-	 .m_axi_wready(SDCout_axi_wready),
-	 .m_axi_bresp(SDCout_axi_bresp),
-	 .m_axi_bvalid(SDCout_axi_bvalid),
-	 .m_axi_bready(SDCout_axi_bready),
-	 .m_axi_araddr(SDCout_axi_araddr),
-	 .m_axi_arlen(SDCout_axi_arlen),
-	 .m_axi_arvalid(SDCout_axi_arvalid),
-	 .m_axi_arready(SDCout_axi_arready),
-	 .m_axi_rdata(SDCout_axi_rdata),
-	 .m_axi_rlast(SDCout_axi_rlast),
-	 .m_axi_rresp(SDCout_axi_rresp),
-	 .m_axi_rvalid(SDCout_axi_rvalid),
-	 .m_axi_rready(SDCout_axi_rready),
-
-	 // SDC interface
-	 //.sdio_cmd(1'b0),
-	 //.sdio_dat(4'b0),
-	 //.sdio_cd(1'b0)
-
-     .sd_dat_reg_t(sd_dat_reg_t),
-     .sd_dat_reg_o(sd_dat_reg_o),
-     .sd_dat_i(sd_dat_i),
-     
-     .sd_cmd_reg_t(sd_cmd_reg_t),
-     .sd_cmd_reg_o(sd_cmd_reg_o),
-     .sd_cmd_i(sd_cmd_i),
-
-     .sdio_clk(SDCCLK),
-     .sdio_cd(SDCCD),
-
-     .interrupt(SDCIntr)
-	 );
-
-  xlnx_axi_dwidth_conv_32to64 axi_conv_up
-	(.s_axi_aclk(CPUCLK),
-	 .s_axi_aresetn(peripheral_aresetn),
-	 
-	 // Slave interface
-	 .s_axi_awaddr(SDCout_axi_awaddr),
-	 .s_axi_awlen(SDCout_axi_awlen),
-	 .s_axi_awsize(3'b010),
-	 .s_axi_awburst(2'b01),
-	 .s_axi_awlock(1'b0),
-	 .s_axi_awcache(4'b0),
-	 .s_axi_awprot(3'b0),
-	 .s_axi_awregion(4'b0),
-	 .s_axi_awqos(4'b0),
-	 .s_axi_awvalid(SDCout_axi_awvalid),
-	 .s_axi_awready(SDCout_axi_awready),
-	 .s_axi_wdata(SDCout_axi_wdata),
-	 .s_axi_wstrb(8'b11111111),
-	 .s_axi_wlast(SDCout_axi_wlast),
-	 .s_axi_wvalid(SDCout_axi_wvalid),
-	 .s_axi_wready(SDCout_axi_wready),
-	 .s_axi_bresp(SDCout_axi_bresp),
-	 .s_axi_bvalid(SDCout_axi_bvalid),
-	 .s_axi_bready(SDCout_axi_bready),
-	 .s_axi_araddr(SDCout_axi_araddr),
-	 .s_axi_arlen(SDCout_axi_arlen),
-	 .s_axi_arsize(3'b010),
-	 .s_axi_arburst(2'b01),
-	 .s_axi_arlock(1'b0),
-	 .s_axi_arcache(4'b0),
-	 .s_axi_arprot(3'b0),
-	 .s_axi_arregion(4'b0),
-	 .s_axi_arqos(4'b0),
-	 .s_axi_arvalid(SDCout_axi_arvalid),
-	 .s_axi_arready(SDCout_axi_arready),
-	 .s_axi_rdata(SDCout_axi_rdata),
-	 .s_axi_rresp(SDCout_axi_rresp),
-	 .s_axi_rlast(SDCout_axi_rlast),
-	 .s_axi_rvalid(SDCout_axi_rvalid),
-	 .s_axi_rready(SDCout_axi_rready),
-
-	 // Master interface
-	 .m_axi_awaddr(m01_axi_awaddr),
-	 .m_axi_awlen(m01_axi_awlen),
-	 .m_axi_awsize(m01_axi_awsize),
-	 .m_axi_awburst(m01_axi_awburst),
-	 .m_axi_awlock(m01_axi_awlock),
-	 .m_axi_awcache(m01_axi_awcache),
-	 .m_axi_awprot(m01_axi_awprot),
-	 .m_axi_awregion(m01_axi_awregion),
-	 .m_axi_awqos(m01_axi_awqos),
-	 .m_axi_awvalid(m01_axi_awvalid),
-	 .m_axi_awready(m01_axi_awready),
-	 .m_axi_wdata(m01_axi_wdata),
-	 .m_axi_wstrb(m01_axi_wstrb),
-	 .m_axi_wlast(m01_axi_wlast),
-	 .m_axi_wvalid(m01_axi_wvalid),
-	 .m_axi_wready(m01_axi_wready),
-	 .m_axi_bresp(m01_axi_bresp),
-	 .m_axi_bvalid(m01_axi_bvalid),
-	 .m_axi_bready(m01_axi_bready),
-	 .m_axi_araddr(m01_axi_araddr),
-	 .m_axi_arlen(m01_axi_arlen),
-	 .m_axi_arsize(m01_axi_arsize),
-	 .m_axi_arburst(m01_axi_arburst),
-	 .m_axi_arlock(m01_axi_arlock),
-	 .m_axi_arcache(m01_axi_arcache),
-	 .m_axi_arprot(m01_axi_arprot),
-	 .m_axi_arregion(m01_axi_arregion),
-	 .m_axi_arqos(m01_axi_arqos),
-	 .m_axi_arvalid(m01_axi_arvalid),
-	 .m_axi_arready(m01_axi_arready),
-	 .m_axi_rdata(m01_axi_rdata),
-	 .m_axi_rresp(m01_axi_rresp),
-	 .m_axi_rlast(m01_axi_rlast),
-	 .m_axi_rvalid(m01_axi_rvalid),
-	 .m_axi_rready(m01_axi_rready)
-	 );
-
-  // End SDC signals --------------------------------------------
-   
+  // AXI Clock Converter
   xlnx_axi_clock_converter xlnx_axi_clock_converter_0
     (.s_axi_aclk(CPUCLK),
      .s_axi_aresetn(peripheral_aresetn),
-     .s_axi_awid(s00_axi_awid),
-     .s_axi_awlen(s00_axi_awlen),
-     .s_axi_awsize(s00_axi_awsize),
-     .s_axi_awburst(s00_axi_awburst),
-     .s_axi_awcache(s00_axi_awcache),
-     .s_axi_awaddr(s00_axi_awaddr[30:0] ),
-     .s_axi_awprot(s00_axi_awprot),
+     .s_axi_awid(m_axi_awid),
+     .s_axi_awlen(m_axi_awlen),
+     .s_axi_awsize(m_axi_awsize),
+     .s_axi_awburst(m_axi_awburst),
+     .s_axi_awcache(m_axi_awcache),
+     .s_axi_awaddr(m_axi_awaddr[30:0] ),
+     .s_axi_awprot(m_axi_awprot),
      .s_axi_awregion(4'b0), // this could be a bug. bridge does not have these outputs
      .s_axi_awqos(4'b0),    // this could be a bug. bridge does not have these outputs
-     .s_axi_awvalid(s00_axi_awvalid),
-     .s_axi_awready(s00_axi_awready),
-     .s_axi_awlock(s00_axi_awlock),
-     .s_axi_wdata(s00_axi_wdata),
-     .s_axi_wstrb(s00_axi_wstrb),
-     .s_axi_wlast(s00_axi_wlast),
-     .s_axi_wvalid(s00_axi_wvalid),
-     .s_axi_wready(s00_axi_wready),
-     .s_axi_bid(s00_axi_bid),
-     .s_axi_bresp(s00_axi_bresp),
-     .s_axi_bvalid(s00_axi_bvalid),
-     .s_axi_bready(s00_axi_bready),
-     .s_axi_arid(s00_axi_arid),
-     .s_axi_arlen(s00_axi_arlen),
-     .s_axi_arsize(s00_axi_arsize),
-     .s_axi_arburst(s00_axi_arburst),
-     .s_axi_arprot(s00_axi_arprot),
+     .s_axi_awvalid(m_axi_awvalid),
+     .s_axi_awready(m_axi_awready),
+     .s_axi_awlock(m_axi_awlock),
+     .s_axi_wdata(m_axi_wdata),
+     .s_axi_wstrb(m_axi_wstrb),
+     .s_axi_wlast(m_axi_wlast),
+     .s_axi_wvalid(m_axi_wvalid),
+     .s_axi_wready(m_axi_wready),
+     .s_axi_bid(m_axi_bid),
+     .s_axi_bresp(m_axi_bresp),
+     .s_axi_bvalid(m_axi_bvalid),
+     .s_axi_bready(m_axi_bready),
+     .s_axi_arid(m_axi_arid),
+     .s_axi_arlen(m_axi_arlen),
+     .s_axi_arsize(m_axi_arsize),
+     .s_axi_arburst(m_axi_arburst),
+     .s_axi_arprot(m_axi_arprot),
      .s_axi_arregion(4'b0), // this could be a bug. bridge does not have these outputs
      .s_axi_arqos(4'b0),    // this could be a bug. bridge does not have these outputs
-     .s_axi_arcache(s00_axi_arcache),
-     .s_axi_arvalid(s00_axi_arvalid),
-     .s_axi_araddr(s00_axi_araddr[30:0]),
-     .s_axi_arlock(s00_axi_arlock),
-     .s_axi_arready(s00_axi_arready),
-     .s_axi_rid(s00_axi_rid),
-     .s_axi_rdata(s00_axi_rdata),
-     .s_axi_rresp(s00_axi_rresp),
-     .s_axi_rvalid(s00_axi_rvalid),
-     .s_axi_rlast(s00_axi_rlast),
-     .s_axi_rready(s00_axi_rready),
+     .s_axi_arcache(m_axi_arcache),
+     .s_axi_arvalid(m_axi_arvalid),
+     .s_axi_araddr(m_axi_araddr[30:0]),
+     .s_axi_arlock(m_axi_arlock),
+     .s_axi_arready(m_axi_arready),
+     .s_axi_rid(m_axi_rid),
+     .s_axi_rdata(m_axi_rdata),
+     .s_axi_rresp(m_axi_rresp),
+     .s_axi_rvalid(m_axi_rvalid),
+     .s_axi_rlast(m_axi_rlast),
+     .s_axi_rready(m_axi_rready),
 
      .m_axi_aclk(BUSCLK),
      .m_axi_aresetn(resetn),
@@ -1020,6 +385,7 @@ module fpgaTop
      .m_axi_rlast(BUS_axi_rlast),
      .m_axi_rready(BUS_axi_rready));
 
+  // DDR3 Controller
   xlnx_ddr3 xlnx_ddr3_c0
     (
      // ddr3 I/O
diff --git a/src/uncore/spi_apb.sv b/src/uncore/spi_apb.sv
index 94f188120..e9c04bca8 100644
--- a/src/uncore/spi_apb.sv
+++ b/src/uncore/spi_apb.sv
@@ -42,7 +42,8 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
     output logic                SPIOut,
     input  logic                SPIIn,
     output logic [3:0]          SPICS,
-    output logic                SPIIntr
+    output logic                SPIIntr,
+    output logic                SPICLK
 );
 
     // register map
@@ -99,7 +100,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
     rsrstatetype ReceiveState;
 
     // Transmission signals
-    logic sck;
+    // logic sck;
     logic [11:0] DivCounter;                        // Counter for sck 
     logic SCLKenable;                               // Flip flop enable high every sclk edge
 
@@ -358,7 +359,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
 
     assign DelayMode = SckMode[0] ? (state == DELAY_1) : (state == ACTIVE_1 & ReceiveShiftFull);
     assign ChipSelectInternal = (state == CS_INACTIVE | state == INTER_CS | DelayMode & ~|(Delay0[15:8])) ? ChipSelectDef : ~ChipSelectDef;
-    assign sck = (state == ACTIVE_0) ? ~SckMode[1] : SckMode[1];
+    assign SPICLK = (state == ACTIVE_0) ? ~SckMode[1] : SckMode[1];
     assign Active = (state == ACTIVE_0 | state == ACTIVE_1);
     assign SampleEdge = SckMode[0] ? (state == ACTIVE_1) : (state == ACTIVE_0);
     assign ZeroDelayHoldMode = ((ChipSelectMode == 2'b10) & (~|(Delay1[7:4])));
@@ -368,11 +369,11 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
     // Signal tracks which edge of sck to shift data
     always_comb
         case(SckMode[1:0])
-            2'b00: ShiftEdge = ~sck & SCLKenable;
-            2'b01: ShiftEdge = (sck & |(FrameCount) & SCLKenable);
-            2'b10: ShiftEdge = sck & SCLKenable;
-            2'b11: ShiftEdge = (~sck & |(FrameCount) & SCLKenable);
-            default: ShiftEdge = sck & SCLKenable;
+            2'b00: ShiftEdge = ~SPICLK & SCLKenable;
+            2'b01: ShiftEdge = (SPICLK & |(FrameCount) & SCLKenable);
+            2'b10: ShiftEdge = SPICLK & SCLKenable;
+            2'b11: ShiftEdge = (~SPICLK & |(FrameCount) & SCLKenable);
+            default: ShiftEdge = SPICLK & SCLKenable;
         endcase
 
     // Transmit shift register
diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv
index 39a2be09a..dad558c19 100644
--- a/src/uncore/uncore.sv
+++ b/src/uncore/uncore.sv
@@ -46,7 +46,6 @@ module uncore import cvw::*;  #(parameter cvw_t P)(
   output logic [P.AHBW-1:0]    HRDATA,
   output logic                 HREADY, HRESP,
   output logic                 HSELEXT,
-  output logic                 HSELEXTSDC,
   // peripheral pins          
   output logic                 MTimerInt, MSwInt,         // Timer and software interrupts from CLINT
   output logic                 MExtInt, SExtInt,          // External interrupts from PLIC
@@ -55,16 +54,20 @@ module uncore import cvw::*;  #(parameter cvw_t P)(
   output logic [31:0]          GPIOOUT, GPIOEN,           // GPIO pin output value and enable
   input  logic                 UARTSin,                   // UART serial input
   output logic                 UARTSout,                  // UART serial output
-  input  logic                 SDCIntr,
   input  logic                 SPIIn,
   output logic                 SPIOut,
-  output logic [3:0]           SPICS                  
+  output logic [3:0]           SPICS,
+  output logic                 SPICLK,
+  input  logic                 SDCIn,                                                 
+  output logic                 SDCCmd,
+  output logic [3:0]           SDCCS,
+  output logic                 SDCCLK
 );
   
   logic [P.XLEN-1:0]           HREADRam, HREADSDC;
 
   logic [11:0]                 HSELRegions;
-  logic                        HSELDTIM, HSELIROM, HSELRam, HSELCLINT, HSELPLIC, HSELGPIO, HSELUART, HSELSPI;
+  logic                        HSELDTIM, HSELIROM, HSELRam, HSELCLINT, HSELPLIC, HSELGPIO, HSELUART,HSELSDC, HSELSPI;
   logic                        HSELDTIMD, HSELIROMD, HSELEXTD, HSELRamD, HSELCLINTD, HSELPLICD, HSELGPIOD, HSELUARTD, HSELSDCD, HSELSPID;
   logic                        HRESPRam,  HRESPSDC;
   logic                        HREADYRam, HRESPSDCD;
@@ -85,8 +88,8 @@ module uncore import cvw::*;  #(parameter cvw_t P)(
   /* verilator lint_on UNDRIVEN */
   logic [P.XLEN-1:0]           HREADBRIDGE;
   logic                        HRESPBRIDGE, HREADYBRIDGE, HSELBRIDGE, HSELBRIDGED;
-
-  (* mark_debug = "true" *) logic             HSELEXTSDCD;
+  /* SDC Interrupt (SPI Controller) */
+  logic                        SDCIntr;
   
 
   // Determine which region of physical memory (if any) is being accessed
@@ -95,14 +98,14 @@ module uncore import cvw::*;  #(parameter cvw_t P)(
   adrdecs #(P) adrdecs(HADDR, 1'b1, 1'b1, 1'b1, HSIZE[1:0], HSELRegions);
 
   // unswizzle HSEL signals
-  assign {HSELSPI, HSELEXTSDC, HSELPLIC, HSELUART, HSELGPIO, HSELCLINT, HSELRam, HSELBootRom, HSELEXT, HSELIROM, HSELDTIM} = HSELRegions[11:1];
+  assign {HSELSPI, HSELSDC, HSELPLIC, HSELUART, HSELGPIO, HSELCLINT, HSELRam, HSELBootRom, HSELEXT, HSELIROM, HSELDTIM} = HSELRegions[11:1];
 
   // AHB -> APB bridge
-  ahbapbbridge #(P, 5) ahbapbbridge (
-    .HCLK, .HRESETn, .HSEL({HSELSPI, HSELUART, HSELPLIC, HSELCLINT, HSELGPIO}), .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HTRANS, .HREADY, 
+  ahbapbbridge #(P, 6) ahbapbbridge (
+    .HCLK, .HRESETn, .HSEL({HSELSPI, HSELUART, HSELPLIC, HSELCLINT, HSELGPIO, HSELSDC}), .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HTRANS, .HREADY, 
     .HRDATA(HREADBRIDGE), .HRESP(HRESPBRIDGE), .HREADYOUT(HREADYBRIDGE),
     .PCLK, .PRESETn, .PSEL, .PWRITE, .PENABLE, .PADDR, .PWDATA, .PSTRB, .PREADY, .PRDATA);
-  assign HSELBRIDGE = HSELGPIO | HSELCLINT | HSELPLIC | HSELUART | HSELSPI; // if any of the bridge signals are selected
+  assign HSELBRIDGE = HSELGPIO | HSELCLINT | HSELPLIC | HSELUART | HSELSPI | HSELSDC; // if any of the bridge signals are selected
                 
   // on-chip RAM
   if (P.UNCORE_RAM_SUPPORTED) begin : ram
@@ -142,6 +145,7 @@ module uncore import cvw::*;  #(parameter cvw_t P)(
   end else begin : gpio
     assign GPIOOUT = '0; assign GPIOEN = '0; assign GPIOIntr = 1'b0;
   end
+  
   if (P.UART_SUPPORTED == 1) begin : uartgen // Hack to work around Verilator bug https://github.com/verilator/verilator/issues/4769
     uart_apb #(P) uart(
       .PCLK, .PRESETn, .PSEL(PSEL[3]), .PADDR(PADDR[2:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, 
@@ -152,28 +156,39 @@ module uncore import cvw::*;  #(parameter cvw_t P)(
   end else begin : uart
     assign UARTSout = 1'b0; assign UARTIntr = 1'b0; 
   end
+  
   if (P.SPI_SUPPORTED == 1) begin : spi
     spi_apb  #(P) spi (
       .PCLK, .PRESETn, .PSEL(PSEL[4]), .PADDR(PADDR[7:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, 
       .PREADY(PREADY[4]), .PRDATA(PRDATA[4]), 
-      .SPIOut, .SPIIn, .SPICS, .SPIIntr);
+      .SPIOut, .SPIIn, .SPICS, .SPICLK, .SPIIntr);
   end else begin : spi
-    assign SPIOut = 1'b0; assign SPICS = '0; assign SPIIntr = 1'b0;
+    assign SPIOut = 1'b0; assign SPICS = '0; assign SPIIntr = 1'b0; assign SPICLK = 1'b0;
   end
 
+  if (P.SDC_SUPPORTED == 1) begin : sdc
+    spi_apb #(P) sdc(
+      .PCLK, .PRESETN, .PSEL(.PSEL[5]), .PADDR(PADDR[7:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE,
+      .PREADY(PREADY[5]), .PRDATA(PRDATA[5]),
+      .SPIOut(SDCCmd), .SPIIn(SDCIn), .SPICS(SDCCS), .SPICLK(SDCCLK), .SPIIntr(.SDCIntr));                                      
+  end else begin : sdc
+    assign SDCCmd = '0; assign SDCCD = 1'b0; assign SDCIntr = 1'b0; assign SDCCLK = 1'b0;
+  end
+  
+
   // AHB Read Multiplexer
   assign HRDATA = ({P.XLEN{HSELRamD}} & HREADRam) |
-                  ({P.XLEN{HSELEXTD | HSELEXTSDCD}} & HRDATAEXT) |   
+                  ({P.XLEN{HSELEXTD}} & HRDATAEXT) |
                   ({P.XLEN{HSELBRIDGED}} & HREADBRIDGE) |
                   ({P.XLEN{HSELBootRomD}} & HREADBootRom);
 
   assign HRESP = HSELRamD & HRESPRam |
-                 (HSELEXTD | HSELEXTSDCD) & HRESPEXT |
+                 HSELEXTD & HRESPEXT |
                  HSELBRIDGE & HRESPBRIDGE |
                  HSELBootRomD & HRESPBootRom;
   
   assign HREADY = HSELRamD & HREADYRam |
-		          (HSELEXTD | HSELEXTSDCD) & HREADYEXT |		  
+		          HSELEXTD & HREADYEXT |		  
                   HSELBRIDGED & HREADYBRIDGE |
                   HSELBootRomD & HREADYBootRom |
                   HSELNoneD; // don't lock up the bus if no region is being accessed
@@ -184,7 +199,7 @@ module uncore import cvw::*;  #(parameter cvw_t P)(
   // device is ready.  Hense this register must be selectively enabled by HREADY.
   // However on reset None must be seleted.
   flopenl #(12) hseldelayreg(HCLK, ~HRESETn, HREADY, HSELRegions, 12'b1, 
-    {HSELSPID, HSELEXTSDCD, HSELPLICD, HSELUARTD, HSELGPIOD, HSELCLINTD,
+    {HSELSPID, HSELSDCD, HSELPLICD, HSELUARTD, HSELGPIOD, HSELCLINTD,
       HSELRamD, HSELBootRomD, HSELEXTD, HSELIROMD, HSELDTIMD, HSELNoneD});
   flopenr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HREADY, HSELBRIDGE, HSELBRIDGED);
 endmodule
diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv
index 9f5e5ee00..af9f0ff26 100644
--- a/src/wally/wallypipelinedsoc.sv
+++ b/src/wally/wallypipelinedsoc.sv
@@ -55,10 +55,14 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P)  (
   output logic [31:0]         GPIOEN,           // output enables for GPIO
   input  logic                UARTSin,          // UART serial data input
   output logic                UARTSout,         // UART serial data output
-  input  logic                SDCIntr,
   input  logic                SPIIn,            // SPI pins in
   output logic                SPIOut,           // SPI pins out
-  output logic [3:0]          SPICS             // SPI chip select pins                    
+  output logic [3:0]          SPICS,            // SPI chip select pins
+  output logic                SPICLK,           // SPI clock
+  input  logic                SDCIn,            // SDC DATA[0]     to     SPI DI
+  output logic                SDCCmd,           // SDC CMD         from   SPI DO
+  output logic [3:0]          SDCCS,            // SDC Card Detect from   SPI CS
+  output logic                SDCCLK            // SDC Clock       from   SPI Clock
 );
 
   // Uncore signals
@@ -84,7 +88,7 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P)  (
       .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
       .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, .HSELEXTSDC,
       .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin, 
-      .UARTSout, .MTIME_CLINT, .SDCIntr, .SPIIn, .SPIOut, .SPICS);
+      .UARTSout, .MTIME_CLINT, .SPIIn, .SPIOut, .SPICS, .SPICLK, .SDCIn, .SDCCmd, .SDCCS, .SDCCLK);
   end else begin
     assign {HRDATA, HREADY, HRESP, HSELEXT, HSELEXTSDC, MTimerInt, MSwInt, MExtInt, SExtInt,
             MTIME_CLINT, GPIOOUT, GPIOEN, UARTSout, SPIOut, SPICS} = '0;