From a799c8bdd998945d66466a740dcf7b24eee69e69 Mon Sep 17 00:00:00 2001
From: Corey Hickson <chickson@hmc.edu>
Date: Thu, 13 Mar 2025 04:52:24 -0700
Subject: [PATCH] 100% fctrl code coverage

---
 src/fpu/fctrl.sv     | 4 ++--
 tests/coverage/fpu.S | 9 +++++++++
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv
index 2b8dbc411..597cdd25f 100755
--- a/src/fpu/fctrl.sv
+++ b/src/fpu/fctrl.sv
@@ -154,7 +154,7 @@ module fctrl import cvw::*;  #(parameter cvw_t P) (
                       7'b11100??: if (Funct3D == 3'b001 & Rs2D == 5'b00000)          
                                                 ControlsD = `FCTRLW'b0_1_10_00_000_0_0_0_0_0; // fclass
                                   else if (Funct3D == 3'b000 & Rs2D == 5'b00000) begin
-                                    if (Fmt[1:0] == 2'b00 | Fmt[1:0] == 2'b10 | (P.XLEN == 64 & Fmt[1:0] == 2'b01)) 
+                                    if (~(P.XLEN != 64 & Fmt[1:0] == 2'b01))
                                                 ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_0_0; // fmv.x.w/d/h  fp to int register (double only in RV64)
                                   end else if (P.ZFA_SUPPORTED & P.XLEN == 32 & P.D_SUPPORTED & Funct7D[1:0] == 2'b01 & Funct3D == 3'b000 & Rs2D == 5'b00001) 
                                                 ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_1_0; // fmvh.x.d  (Zfa) 
@@ -164,7 +164,7 @@ module fctrl import cvw::*;  #(parameter cvw_t P) (
                                                 ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_1_0; // fmvh.x.q  (Zfa)
                                   // coverage on
                       7'b11110??: if (Funct3D == 3'b000 & Rs2D == 5'b00000) begin
-                                    if (Fmt[1:0] == 2'b00 | Fmt[1:0] == 2'b10 | (P.XLEN == 64 & Fmt[1:0] == 2'b01)) 
+                                    if (~(P.XLEN != 64 & Fmt[1:0] == 2'b01))
                                                 ControlsD = `FCTRLW'b1_0_00_00_011_0_0_0_0_0; // fmv.w/d/h.x  int to fp reg (double only in RV64)
                                   end else if (P.ZFA_SUPPORTED & Funct3D == 3'b000 & Rs2D == 5'b00001) 
                                                 ControlsD = `FCTRLW'b1_0_00_00_111_0_0_0_1_0; // fli  (Zfa)
diff --git a/tests/coverage/fpu.S b/tests/coverage/fpu.S
index 760898306..66f5b021e 100644
--- a/tests/coverage/fpu.S
+++ b/tests/coverage/fpu.S
@@ -154,6 +154,15 @@ main:
     fdiv.s ft2, ft1, ft0 # should get interrupted, triggering a flush
     csrci mstatus, 0b1000   # disable interrupts with mstatus.MIE
 
+    // fcrtl: unsupported rm with dyn rounding
+    csrrwi t0, frm, 0b111  # save previous rm, set frm csr to 111 (unsupported)
+    fadd.s f0, f0, f0, dyn # try to use unsupported rounding mode in csr
+    csrrwi x0, frm, 0b110  # set frm csr to 110 (unsupported)
+    fadd.s f0, f0, f0, dyn # try to use unsupported rounding mode in csr
+    csrrwi x0, frm, 0b101  # set frm csr to 101 (unsupported)
+    fadd.s f0, f0, f0, dyn # try to use unsupported rounding mode in csr
+    csrrw  x0, frm, t0     # restore previous rm
+
     # Completing branch coverage in fctrl.sv
     .word 0x38007553    // Testing the all False case for 119 - funct7 under, op = 101 0011
     .word 0x40000053    // Line 145 All False Test case - illegal instruction?