diff --git a/.gitignore b/.gitignore index 57fb63b4a..fb2d17e9b 100644 --- a/.gitignore +++ b/.gitignore @@ -1,5 +1,7 @@ **/work* **/wally_*.log +/**/obj_dir* +/**/gmon* .nfs* @@ -46,7 +48,6 @@ linux/buildroot linux/testvector-generation/boottrace.S linux/testvector-generation/boottrace_disasm.log sim/slack-notifier/slack-webhook-url.txt -sim/logs fpga/generator/IP fpga/generator/vivado.* fpga/generator/.Xil/* @@ -61,8 +62,13 @@ examples/asm/example/example examples/C/sum/sum examples/C/fir/fir examples/fp/softfloat_demo/softfloat_demo +examples/fp/softfloat_demo/softfloat_demoDP +examples/fp/softfloat_demo/softfloat_demoQP +examples/fp/softfloat_demo/softfloat_demoSP examples/fp/fpcalc/fpcalc +examples/fp/sqrttest/sqrttest examples/C/inline/inline +examples/C/mcmodel/mcmodel examples/C/sum_mixed/sum_mixed examples/asm/trap/trap examples/asm/etc/pause @@ -89,7 +95,6 @@ synthDC/hdl sim/power.saif tests/fp/vectors/*.tv synthDC/Summary.csv -sim/wkdir tests/custom/work tests/custom/*/*/*.list tests/custom/*/*/*.elf @@ -112,8 +117,6 @@ tests/wally-riscv-arch-test/riscv-test-suite/rv*i_m/I/src/*.S tests/wally-riscv-arch-test/riscv-test-suite/rv*i_m/I/Makefrag sim/branch_BP_GSHARE10.log sim/branch_BP_GSHARE16.log -sim/cov/ -sim/covhtmlreport/ sim/imperas.log sim/results-error/ sim/test1.rep @@ -186,7 +189,17 @@ sim/branch/* sim/obj_dir examples/verilog/fulladder/obj_dir config/deriv - -# docs/docker docs/docker/buildroot-config-src docs/docker/testvector-generation +sim/questa/cov +sim/questa/covhtmlreport/ +sim/questa/logs +sim/questa/wkdir +sim/verilator/logs +sim/verilator/wkdir +sim/vcs/logs +sim/vcs/wkdir +benchmarks/coremark/coremark_results.csv +fpga/zsbl/OBJ/* +fpga/zsbl/bin/* +sim/*.svg diff --git a/Makefile b/Makefile index 97e61f47e..7f085de40 100644 --- a/Makefile +++ b/Makefile @@ -48,14 +48,16 @@ imperasdv_cov: vcover report -details -html sim/riscv.ucdb funcovreg: - iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m --cover + #iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m --cover #iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m/I --cover #iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege --cover #iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m/Q --cover + rm -f ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/*/src/*/dut/my.elf + iter-elf.bash --search ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I --cover vcover report -details -html sim/riscv.ucdb coverage: - cd ${WALLY}/sim; ./regression-wally -coverage -fp + regression-wally -coverage -fp benchmarks: make coremark diff --git a/benchmarks/coremark/Makefile b/benchmarks/coremark/Makefile index a73dc6eea..9ac905950 100644 --- a/benchmarks/coremark/Makefile +++ b/benchmarks/coremark/Makefile @@ -28,7 +28,8 @@ PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \ all: $(work_dir)/coremark.bare.riscv.elf.memfile run: - (cd ../../sim && (time vsim -c -do "do wally-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log)) + time wsim rv$(XLEN)gc coremark 2>&1 | tee $(work_dir)/coremark.sim.log + #(cd ../../sim && (time vsim -c -do "do wally-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log)) $(work_dir)/coremark.bare.riscv.elf.memfile: $(work_dir)/coremark.bare.riscv riscv64-unknown-elf-objdump -D $< > $<.elf.objdump diff --git a/benchmarks/coremark/coremark_sweep.py b/benchmarks/coremark/coremark_sweep.py index e1b6c6573..527f5f44f 100755 --- a/benchmarks/coremark/coremark_sweep.py +++ b/benchmarks/coremark/coremark_sweep.py @@ -4,8 +4,8 @@ ## Written: Shreesh Kulkarni, kshreesh5@gmail.com ## Created: 20 March 2024 -## Modified: 22 March 2024 -## Purpose: Wally Coremark sweep Script for both 32 and 64 bit configs. +## Modified: 08 April 2024 +## Purpose: Wally Coremark sweep Script for both 32 and 64 bit configs with csv file extraction. ## Documentation: @@ -30,16 +30,16 @@ import os +import re +import csv # list of architectures to run. -arch32_list = [ +arch_list = [ "rv32gc_zba_zbb_zbc", "rv32im_zicsr_zba_zbb_zbc", "rv32gc", "rv32imc_zicsr", "rv32im_zicsr", - "rv32i_zicsr" -] -arch64_list = [ + "rv32i_zicsr", "rv64gc_zba_zbb_zbc", "rv64im_zicsr_zba_zbb_zbc", "rv64gc", @@ -47,24 +47,61 @@ arch64_list = [ "rv64im_zicsr", "rv64i_zicsr" ] -xlen_values = ['32','64'] -for xlen_value in xlen_values: - if(xlen_value=='32'): - for arch in arch32_list: - os.system("make clean") - make_all = f"make all XLEN={xlen_value} ARCH={arch}" - os.system(make_all) - make_run = f"make run XLEN={xlen_value} ARCH={arch}" - os.system(make_run) - else: - for arch in arch64_list: - os.system("make clean") - make_all = f"make all XLEN={xlen_value} ARCH={arch}" - os.system(make_all) - make_run = f"make run XLEN={xlen_value} ARCH={arch}" - os.system(make_run) +str="32" +# Define regular expressions to match the desired fields +mt_regex = r"Elapsed MTIME: (\d+).*?Elapsed MINSTRET: (\d+).*?COREMARK/MHz Score: [\d,]+ / [\d,]+ = (\d+\.\d+).*?CPI: \d+ / \d+ = (\d+\.\d+).*?Load Stalls (\d+).*?Store Stalls (\d+).*?D-Cache Accesses (\d+).*?D-Cache Misses (\d+).*?I-Cache Accesses (\d+).*?I-Cache Misses (\d+).*?Branches (\d+).*?Branches Miss Predictions (\d+).*?BTB Misses (\d+).*?Jump and JR (\d+).*?RAS Wrong (\d+).*?Returns (\d+).*?BP Class Wrong (\d+)" +#cpi_regex = r"CPI: \d+ / \d+ = (\d+\.\d+)" +#cmhz_regex = r"COREMARK/MHz Score: [\d,]+ / [\d,]+ = (\d+\.\d+)" +# Open a CSV file to write the results +with open('coremark_results.csv', mode='w', newline='') as csvfile: + fieldnames = ['Architecture', 'MTIME','MINSTRET','CM / MHz','CPI','Load Stalls','Store Stalls','D$ Accesses', + 'D$ Misses','I$ Accesses','I$ Misses','Branches','Branch Mispredicts','BTB Misses', + 'Jump/JR','RAS Wrong','Returns','BP Class Pred Wrong'] + writer = csv.DictWriter(csvfile, fieldnames=fieldnames) + writer.writeheader() + # Loop through each architecture and run the make commands + for arch in arch_list: + if(str in arch): + xlen_value='32' + else: + xlen_value='64' + os.system("make clean") + make_all = f"make all XLEN={xlen_value} ARCH={arch}" + os.system(make_all) + make_run = f"make run XLEN={xlen_value} ARCH={arch}" + print("Running: " + make_run) + output = os.popen(make_run).read() # Capture the output of the command + # Extract the Coremark values using regular expressions + mt_match = re.search(mt_regex, output,re.DOTALL) + #cpi_match = re.search(cpi_regex,output,re.DOTALL) + #cmhz_match = re.search(cmhz_regex,output,re.DOTALL) + #minstret_match = re.search(minstret_regex,output) + # Write the architecture and extracted values to the CSV file + + mtime = mt_match.group(1) + minstret= mt_match.group(2) + cmhz= mt_match.group(3) + cpi= mt_match.group(4) + lstalls= mt_match.group(5) + swtalls= mt_match.group(6) + dacc= mt_match.group(7) + dmiss= mt_match.group(8) + iacc= mt_match.group(9) + imiss= mt_match.group(10) + br= mt_match.group(11) + brm= mt_match.group(12) + btb= mt_match.group(13) + jmp= mt_match.group(14) + ras= mt_match.group(15) + ret= mt_match.group(16) + bpc= mt_match.group(17) + #minstret = mt_instret_match.group(2) + writer.writerow({'Architecture': arch, 'MTIME': mtime,'MINSTRET':minstret,'CM / MHz':cmhz,'CPI':cpi, + 'Load Stalls':lstalls, + 'Store Stalls':swtalls,'D$ Accesses':dacc,'D$ Misses':dmiss,'I$ Accesses':iacc,'I$ Misses':imiss, + 'Branches':br,'Branch Mispredicts':brm,'BTB Misses':btb,'Jump/JR':jmp,'RAS Wrong':ras,'Returns':ret,'BP Class Pred Wrong':bpc}) diff --git a/sim/lint-wally b/bin/lint-wally similarity index 94% rename from sim/lint-wally rename to bin/lint-wally index 5964d20ed..4187b0429 100755 --- a/sim/lint-wally +++ b/bin/lint-wally @@ -21,7 +21,7 @@ if [ "$1" == "-nightly" ]; then fi done else - configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i div_2_1i_rv64gc ) # add fdqh_rv64gc when working + configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i ) # add fdqh_rv64gc when working fi for config in ${configs[@]}; do diff --git a/bin/regression-wally b/bin/regression-wally new file mode 100755 index 000000000..bdb58fea0 --- /dev/null +++ b/bin/regression-wally @@ -0,0 +1,419 @@ +#!/usr/bin/python3 +################################## +# +# regression-wally +# David_Harris@Hmc.edu 25 January 2021 +# Modified by Jarred Allen +# +# Run a regression with multiple configurations in parallel and exit with +# non-zero status code if an error happened, as well as printing human-readable +# output. +# +################################## +import sys,os,shutil +import multiprocessing +#import os +from collections import namedtuple +from multiprocessing import Pool, TimeoutError + +################################## +# Define lists of configurations and tests to run on each configuration +################################## + +# The tests are a list with one element for each configuration +# The element consists of the configuration name, a list of test suites to run, +# optionally a string to pass to the simulator, and optionally a nonstandard grep string to check for success + +INSTR_LIMIT = 1000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM +tests = [ + ["rv32e", ["arch32e"]], + ["rv32i", ["arch32i"]], + ["rv32imc", ["arch32i", "arch32c", "arch32m", "wally32periph"]], + ["rv32gc", ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32f_divsqrt", "arch32d_divsqrt", + "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zicond", + "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfh_fma", + "arch32zfh_divsqrt", "arch32zfaf", "wally32a", "wally32priv", "wally32periph", + "arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh"]], # "arch32zcb", "arch32zfad", + ["rv64i", ["arch64i"]], + ["buildroot", ["buildroot"], [f"+INSTR_LIMIT={INSTR_LIMIT}"], str(INSTR_LIMIT)+" instructions"] + ] + +# Separate out floating-point tests for RV64 to speed up coverage +tests64gc_nofp = [ + ["rv64gc", ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m", + "arch64zifencei", "arch64zicond", "arch64a", "wally64a", "wally64periph", "wally64priv", + "arch64zbkb", "arch64zbkc", "arch64zbkx", "arch64zknd", "arch64zkne", "arch64zknh", + "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs"]] # add when working: "arch64zcb", "arch64zicboz" + ] + +tests64gc_fp = [ + ["rv64gc", ["arch64f", "arch64d", "arch64zfh", + "arch64f_fma", "arch64d_fma", "arch64zfh_fma", + "arch64f_divsqrt", "arch64d_divsqrt", "arch64zfh_divsqrt", + "arch64zfaf", "arch64zfad"]] + ] + +derivconfigtests = [ + # memory system + ["tlb2_rv32gc", ["wally32priv"]], + ["tlb16_rv32gc", ["wally32priv"]], + ["tlb2_rv64gc", ["wally64priv"]], + ["tlb16_rv64gc", ["wally64priv"]], + ["way_1_4096_512_rv32gc", ["arch32i"]], + ["way_2_4096_512_rv32gc", ["arch32i"]], + ["way_8_4096_512_rv32gc", ["arch32i"]], + ["way_4_2048_512_rv32gc", ["arch32i"]], + ["way_4_4096_256_rv32gc", ["arch32i"]], + ["way_1_4096_512_rv64gc", ["arch64i"]], + ["way_2_4096_512_rv64gc", ["arch64i"]], + ["way_8_4096_512_rv64gc", ["arch64i"]], + ["way_4_2048_512_rv64gc", ["arch64i"]], + ["way_4_4096_256_rv64gc", ["arch64i"]], + ["way_4_4096_1024_rv64gc", ["arch64i"]], + ["ram_0_0_rv64gc", ["ahb64"]], + ["ram_1_0_rv64gc", ["ahb64"]], + ["ram_1_1_rv64gc", ["ahb64"]], + ["ram_2_0_rv64gc", ["ahb64"]], + ["ram_2_1_rv64gc", ["ahb64"]], +# RV32 cacheless designs will not work unless DTIM supports FLEN > XLEN. This support is not planned. +# ["nodcache_rv32gc", ["ahb32"]], +# ["nocache_rv32gc", ["ahb32"]], + ["noicache_rv32gc", ["ahb32"]], + ["noicache_rv64gc", ["ahb64"]], + ["nodcache_rv64gc", ["ahb64"]], + ["nocache_rv64gc", ["ahb64"]], + + ### add misaligned tests + + # fp/int divider permutations + ["div_2_1_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_2_1i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_2_2_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_2_2i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_2_4_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_2_4i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_4_1_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_4_1i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_4_2_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_4_2i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_4_4_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_4_4i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_2_1_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_2_1i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_2_2_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_2_2i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_2_4_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_2_4i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_4_1_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_4_1i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_4_2_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_4_2i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_4_4_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_4_4i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + + # fpu permutations + ["f_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma"]], + ["fh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32zfh", "arch32zfh_divsqrt"]], + ["fdh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]], + ["fdq_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32i"]], + ["fdqh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt", "arch32i"]], + ["f_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma"]], + ["fh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64zfh", "arch64zfh_divsqrt"]], + ["fdh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]], + ["fdq_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64i"]], + ["fdqh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt", "arch64i", "wally64q"]], + ] + +bpredtests = [ + ["bpred_TWOBIT_6_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + ["bpred_TWOBIT_8_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + ["bpred_TWOBIT_10_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + ["bpred_TWOBIT_12_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + ["bpred_TWOBIT_14_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + ["bpred_TWOBIT_16_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + ["bpred_TWOBIT_6_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + ["bpred_TWOBIT_8_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + ["bpred_TWOBIT_10_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + ["bpred_TWOBIT_12_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + ["bpred_TWOBIT_14_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + ["bpred_TWOBIT_16_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + + ["bpred_GSHARE_6_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + ["bpred_GSHARE_6_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + ["bpred_GSHARE_8_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + ["bpred_GSHARE_8_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + ["bpred_GSHARE_12_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + ["bpred_GSHARE_12_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + ["bpred_GSHARE_14_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + ["bpred_GSHARE_14_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + ["bpred_GSHARE_16_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + ["bpred_GSHARE_16_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + + # btb + ["bpred_GSHARE_10_16_6_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_16_6_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_16_8_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_16_8_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_16_12_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_16_12_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + + # ras + ["bpred_GSHARE_10_2_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_2_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_3_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_3_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_4_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_4_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_6_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_6_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_10_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_10_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"] +] + +################################## +# Data Types & Functions +################################## + +TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr']) +# name: the name of this test configuration (used in printing human-readable +# output and picking logfile names) +# cmd: the command to run to test (should include the logfile as '{}', and +# the command needs to write to that file) +# grepstr: the string to grep through the log file for. The test succeeds iff +# grep finds that string in the logfile (is used by grep, so it may +# be any pattern grep accepts, see `man 1 grep` for more info). + +class bcolors: + HEADER = '\033[95m' + OKBLUE = '\033[94m' + OKCYAN = '\033[96m' + OKGREEN = '\033[92m' + WARNING = '\033[93m' + FAIL = '\033[91m' + ENDC = '\033[0m' + BOLD = '\033[1m' + UNDERLINE = '\033[4m' + +def addTests(tests, sim): + for test in tests: + config = test[0]; + suites = test[1]; + if (len(test) >= 3): + args = " --args " + " ".join(test[2]) + else: + args = "" + if (len(test) >= 4): + gs = test[3] + else: + gs = "All tests ran without failures" + cmdPrefix="wsim --sim " + sim + " " + config + for t in suites: + tc = TestCase( + name=t, + variant=config, + cmd=cmdPrefix + " " + t + args, + grepstr=gs) + configs.append(tc) + +def search_log_for_text(text, logfile): + """Search through the given log file for text, returning True if it is found or False if it is not""" + grepcmd = "grep -e '%s' '%s' > /dev/null" % (text, logfile) +# print(" search_log_for_text invoking %s" % grepcmd) + return os.system(grepcmd) == 0 + +def run_test_case(config): + """Run the given test case, and return 0 if the test suceeds and 1 if it fails""" + logname = WALLY + "/sim/questa/logs/"+config.variant+"_"+config.name+".log" ### *** fix hardwiring to questa log + #cmd = config.cmd + " > " + logname + if ("lint-wally" in config.cmd): + cmd = config.cmd + " | tee " + logname + else: + cmd = config.cmd + " > " + logname + os.chdir(regressionDir) +# print(" run_test_case invoking %s" % cmd) + os.system(cmd) + if search_log_for_text(config.grepstr, logname): + print(f"{bcolors.OKGREEN}%s_%s: Success{bcolors.ENDC}" % (config.variant, config.name)) + return 0 + else: + print(f"{bcolors.FAIL}%s_%s: Failures detected in output{bcolors.ENDC}" % (config.variant, config.name)) + print(" Check %s" % logname) + return 1 + +################################## +# Main body +################################## + + +WALLY = os.environ.get('WALLY') +regressionDir = WALLY + '/sim' +os.chdir(regressionDir) + +coveragesim = "questa" # Questa is required for code/functional coverage +defaultsim = "questa" # Default simulator for all other tests; change to Verilator when flow is ready + +coverage = '--coverage' in sys.argv +fp = '--fp' in sys.argv +nightly = '--nightly' in sys.argv +testfloat = '--testfloat' in sys.argv + +if (nightly): + nightMode = "--nightly"; + sims = ["questa", "verilator", "vcs"] +else: + nightMode = ""; + sims = [defaultsim] + +if (coverage): # only run RV64GC tests in coverage mode + coverStr = '--coverage' +else: + coverStr = '' + + +# Run Lint +configs = [ + TestCase( + name="lints", + variant="all", + cmd="lint-wally " + nightMode, + grepstr="lints run with no errors or warnings" + ) + ] + +if (coverage): # only run RV64GC tests on Questa in coverage mode + addTests(tests64gc_nofp, "questa") + if (fp): + addTests(tests64gc_fp, "questa") +else: + for sim in sims: + addTests(tests, sim) + addTests(tests64gc_nofp, sim) + addTests(tests64gc_fp, sim) + # run derivative configurations in nightly regression + if (nightly): + addTests(derivconfigtests, defaultsim) + +# testfloat tests +if (testfloat): + configs = [] + + testfloatconfigs = ["fdqh_ieee_rv64gc", "fdq_ieee_rv64gc", "fdh_ieee_rv64gc", "fd_ieee_rv64gc", "fh_ieee_rv64gc", "f_ieee_rv64gc", "fdqh_ieee_rv32gc", "f_ieee_rv32gc"] + for config in testfloatconfigs: + tests = ["div", "sqrt", "add", "sub", "mul", "cvtint", "cvtfp", "fma", "cmp"] + if ("f_" in config): + tests.remove("cvtfp") + for test in tests: + tc = TestCase( + name=test, + variant=config, + cmd="wsim --tb testbench_fp " + config + " " + test, + grepstr="All Tests completed with 0 errors") + configs.append(tc) + + + testfloatdivconfigs = [ + "fdh_ieee_div_2_1_rv32gc", "fdh_ieee_div_2_1_rv64gc", "fdh_ieee_div_2_2_rv32gc", + "fdh_ieee_div_2_2_rv64gc", "fdh_ieee_div_2_4_rv32gc", "fdh_ieee_div_2_4_rv64gc", + "fdh_ieee_div_4_1_rv32gc", "fdh_ieee_div_4_1_rv64gc", "fdh_ieee_div_4_2_rv32gc", + "fdh_ieee_div_4_2_rv64gc", "fdh_ieee_div_4_4_rv32gc", "fdh_ieee_div_4_4_rv64gc", + "fd_ieee_div_2_1_rv32gc", "fd_ieee_div_2_1_rv64gc", "fd_ieee_div_2_2_rv32gc", + "fd_ieee_div_2_2_rv64gc", "fd_ieee_div_2_4_rv32gc", "fd_ieee_div_2_4_rv64gc", + "fd_ieee_div_4_1_rv32gc", "fd_ieee_div_4_1_rv64gc", "fd_ieee_div_4_2_rv32gc", + "fd_ieee_div_4_2_rv64gc", "fd_ieee_div_4_4_rv32gc", "fd_ieee_div_4_4_rv64gc", + "fdqh_ieee_div_2_1_rv32gc", "fdqh_ieee_div_2_1_rv64gc", "fdqh_ieee_div_2_2_rv32gc", + "fdqh_ieee_div_2_2_rv64gc", "fdqh_ieee_div_2_4_rv32gc", "fdqh_ieee_div_2_4_rv64gc", + "fdqh_ieee_div_4_1_rv32gc", "fdqh_ieee_div_4_1_rv64gc", "fdqh_ieee_div_4_2_rv32gc", + "fdqh_ieee_div_4_2_rv64gc", "fdqh_ieee_div_4_4_rv32gc", "fdqh_ieee_div_4_4_rv64gc", + "fdq_ieee_div_2_1_rv32gc", "fdq_ieee_div_2_1_rv64gc", "fdq_ieee_div_2_2_rv32gc", + "fdq_ieee_div_2_2_rv64gc", "fdq_ieee_div_2_4_rv32gc", "fdq_ieee_div_2_4_rv64gc", + "fdq_ieee_div_4_1_rv32gc", "fdq_ieee_div_4_1_rv64gc", "fdq_ieee_div_4_2_rv32gc", + "fdq_ieee_div_4_2_rv64gc", "fdq_ieee_div_4_4_rv32gc", "fdq_ieee_div_4_4_rv64gc", + "fh_ieee_div_2_1_rv32gc", "fh_ieee_div_2_1_rv64gc", "fh_ieee_div_2_2_rv32gc", + "fh_ieee_div_2_2_rv64gc", "fh_ieee_div_2_4_rv32gc", "fh_ieee_div_2_4_rv64gc", + "fh_ieee_div_4_1_rv32gc", "fh_ieee_div_4_1_rv64gc", "fh_ieee_div_4_2_rv32gc", + "fh_ieee_div_4_2_rv64gc", "fh_ieee_div_4_4_rv32gc", "fh_ieee_div_4_4_rv64gc", + "f_ieee_div_2_1_rv32gc", "f_ieee_div_2_1_rv64gc", "f_ieee_div_2_2_rv32gc", + "f_ieee_div_2_2_rv64gc", "f_ieee_div_2_4_rv32gc", "f_ieee_div_2_4_rv64gc", + "f_ieee_div_4_1_rv32gc", "f_ieee_div_4_1_rv64gc", "f_ieee_div_4_2_rv32gc", + "f_ieee_div_4_2_rv64gc", "f_ieee_div_4_4_rv32gc", "f_ieee_div_4_4_rv64gc" + ] + for config in testfloatdivconfigs: + # div test case + tests = ["div", "sqrt"] + if ("ieee" in config): + tests.append("cvtint") + tests.append("cvtfp") + if ("f_" in config): + tests.remove("cvtfp") + for test in tests: + tc = TestCase( + name=test, + variant=config, + cmd="wsim --tb testbench_fp --sim questa " + config + " " + test, + grepstr="All Tests completed with 0 errors") + configs.append(tc) + + +def main(): + """Run the tests and count the failures""" + global configs, coverage + os.chdir(regressionDir) + for d in ["questa/logs", "questa/wkdir", "verilator/logs", "verilator/wkdir", "vcs/logs", "vcs/wkdir"]: + try: + os.mkdir(d) + except: + pass + + if '--makeTests' in sys.argv: + os.chdir(regressionDir) + os.system('./make-tests.sh | tee ./logs/make-tests.log') + + if '--all' in sys.argv: + TIMEOUT_DUR = 30*7200 # seconds + #configs.append(getBuildrootTC(boot=True)) + elif '--buildroot' in sys.argv: + TIMEOUT_DUR = 30*7200 # seconds + #configs=[getBuildrootTC(boot=True)] + elif '--coverage' in sys.argv: + TIMEOUT_DUR = 20*60 # seconds + # Presently don't run buildroot because it has a different config and can't be merged with the rv64gc coverage. + # Also it is slow to run. + # configs.append(getBuildrootTC(boot=False)) + os.system('rm -f cov/*.ucdb') + elif '--nightly' in sys.argv: + TIMEOUT_DUR = 60*1440 # 1 day + #configs.append(getBuildrootTC(boot=False)) + elif '--testfloat' in sys.argv: + TIMEOUT_DUR = 60*60 # seconds + else: + TIMEOUT_DUR = 10*60 # seconds + #configs.append(getBuildrootTC(boot=False)) + + # Scale the number of concurrent processes to the number of test cases, but + # max out at a limited number of concurrent processes to not overwhelm the system + with Pool(processes=min(len(configs),multiprocessing.cpu_count())) as pool: + num_fail = 0 + results = {} + for config in configs: + results[config] = pool.apply_async(run_test_case,(config,)) + for (config,result) in results.items(): + try: + num_fail+=result.get(timeout=TIMEOUT_DUR) + except TimeoutError: + num_fail+=1 + print(f"{bcolors.FAIL}%s_%s: Timeout - runtime exceeded %d seconds{bcolors.ENDC}" % (config.variant, config.name, TIMEOUT_DUR)) + + # Coverage report + if coverage: + os.system('make coverage') + # Count the number of failures + if num_fail: + print(f"{bcolors.FAIL}Regression failed with %s failed configurations{bcolors.ENDC}" % num_fail) + else: + print(f"{bcolors.OKGREEN}SUCCESS! All tests ran without failures{bcolors.ENDC}") + return num_fail + +if __name__ == '__main__': + exit(main()) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index af3789564..1810747ec 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -176,8 +176,8 @@ git clone https://github.com/riscv/sail-riscv.git cd sail-riscv # For now, use checkout that is stable for Wally #git checkout 72b2516d10d472ac77482fd959a9401ce3487f60 # not new enough for Zicboz? -make -j ${NUM_THREADS} -ARCH=RV32 make -j ${NUM_THREADS} +make -j ${NUM_THREADS} c_emulator/riscv_sim_RV64 +ARCH=RV32 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV32 sudo ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 /usr/bin/riscv_sim_RV64 sudo ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32 diff --git a/bin/wsim b/bin/wsim new file mode 100755 index 000000000..0796c51cd --- /dev/null +++ b/bin/wsim @@ -0,0 +1,72 @@ +#!/usr/bin/python3 +# +# wsim +# David_Harris@hmc.edu 5 April 2024 +# Invoke a Wally simulation for a desired configuration and test suite or ELF on the specified simulator +# usage: wsim CONFIG TESTSUITE [-s/--sim SIMULATOR] [-g/--gui] +# example: wsim rv64gc arch64i +# example: wsim rv64gc tests/riscof/work/riscv-arch-test/rv64i_m/I/src/ref/ref.elf +# example: wsim rv32i arch32i -s verilator +# example: wsim fdqh_ieee_rv64gc add -t testbench_fp # run TestFloat +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +import argparse +import os + +# Parse arguments +parser = argparse.ArgumentParser() +parser.add_argument("config", help="Configuration file") +parser.add_argument("testsuite", help="Test suite or ELF file") +parser.add_argument("--sim", "-s", help="Simulator", choices=["questa", "verilator", "vcs"], default="questa") +parser.add_argument("--tb", "-t", help="Testbench", choices=["testbench", "testbench_fp"], default="testbench") +parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true") +parser.add_argument("--coverage", "-c", help="Code & Functional Coverage", action="store_true") +parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="") +args = parser.parse_args() +print("Config=" + args.config + " tests=" + args.testsuite + " sim=" + args.sim + " gui=" + str(args.gui) + " args='" + args.args + "'") + +# Validate arguments +if (args.gui): + if (args.sim != "questa"): + print("GUI option only supported for Questa") + exit(1) + +if (args.coverage): + if (args.sim != "questa"): + print("Coverage option only available for Questa") + exit(1) + + +# create the output sub-directories. +WALLY = os.environ.get('WALLY') +regressionDir = WALLY + '/sim/' +for d in ["logs", "wkdir", "cov"]: + try: + os.mkdir(regressionDir+args.sim+"/"+d) + except: + pass + +# Launch selected simulator +cd = "cd $WALLY/sim/" +args.sim +if (args.sim == "questa"): + if (args.tb == "testbench_fp"): + args.args = " -GTEST=" + args.testsuite + " " + args.args +# cmd = "do wally.do " + args.config + " " + args.testsuite + " " + args.tb + " " + " -GTEST=" + args.testsuite + " " + args.args +# else: +# cmd = "do wally.do " + args.config + " " + args.testsuite + " " + args.tb + " " + args.args + cmd = "do wally.do " + args.config + " " + args.testsuite + " " + args.tb + " " + args.args + if (args.coverage): + cmd += " -coverage" + if (args.gui): # launch Questa with GUI; add +acc to keep variables accessible + cmd = cd + "; vsim -do \"" + cmd + " +acc\"" + else: # launch Questa in batch mode + cmd = cd + "; vsim -c -do \"" + cmd + "\"" + print("Running Questa with command: " + cmd) + os.system(cmd) +elif (args.sim == "verilator"): + # PWD=${WALLY}/sim CONFIG=rv64gc TESTSUITE=arch64i + print(f"Running Verilator on {args.config} {args.testsuite}") + os.system(f"/usr/bin/make -C {regressionDir}/verilator WALLYCONF={args.config} TEST={args.testsuite}") +elif (args.sim == "vcs"): + print("Running VCS on %s %s", args.config, args.testsuite) diff --git a/config/derivlist.txt b/config/derivlist.txt index 1c4f19fe2..3f6a869d9 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -587,6 +587,9 @@ IEEE754 1 deriv fd_ieee_rv64gc fd_rv64gc IEEE754 1 +deriv fdh_ieee_rv64gc fdh_rv64gc +IEEE754 1 + deriv fdq_ieee_rv64gc fdq_rv64gc IEEE754 1 diff --git a/fpga/zsbl/linker.x b/fpga/zsbl/linker.x new file mode 100644 index 000000000..f448109cc --- /dev/null +++ b/fpga/zsbl/linker.x @@ -0,0 +1,244 @@ +OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv", + "elf64-littleriscv") +OUTPUT_ARCH(riscv) +ENTRY(_start) +SEARCH_DIR("/opt/riscv/riscv64-unknown-elf/lib"); +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + /* init segment to ensure we get a consistent start routine*/ + . = 0x0000000000000000; + . = ALIGN(0x0); + .init : { + *(.init) + } + _start_end = .; + + PROVIDE (__executable_start = SEGMENT_START("text-segment", 0x0)); . = SEGMENT_START("text-segment", _start_end); + .interp : { *(.interp) } + .note.gnu.build-id : { *(.note.gnu.build-id) } + .hash : { *(.hash) } + .gnu.hash : { *(.gnu.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .gnu.version : { *(.gnu.version) } + .gnu.version_d : { *(.gnu.version_d) } + .gnu.version_r : { *(.gnu.version_r) } + .rela.dyn : + { + *(.rela.init) + *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) + *(.rela.fini) + *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) + *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) + *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) + *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) + *(.rela.ctors) + *(.rela.dtors) + *(.rela.got) + *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) + *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) + *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) + *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) + *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) + PROVIDE_HIDDEN (__rela_iplt_start = .); + *(.rela.iplt) + PROVIDE_HIDDEN (__rela_iplt_end = .); + } + .rela.plt : + { + *(.rela.plt) + } + .init : + { + KEEP (*(SORT_NONE(.init))) + } + .plt : { *(.plt) } + .iplt : { *(.iplt) } + .text : + { + *(.text.unlikely .text.*_unlikely .text.unlikely.*) + *(.text.exit .text.exit.*) + *(.text.startup .text.startup.*) + *(.text.hot .text.hot.*) + *(.text .stub .text.* .gnu.linkonce.t.*) + /* .gnu.warning sections are handled specially by elf64.em. */ + *(.gnu.warning) + } + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } + .rodata1 : { *(.rodata1) } + .sdata2 : + { + *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) + } + .sbss2 : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) } + .eh_frame_hdr : { *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) } + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) *(.eh_frame.*) } + .gcc_except_table : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) } + .gnu_extab : ONLY_IF_RO { *(.gnu_extab*) } + /* These sections are generated by the Sun/Oracle C++ compiler. */ + .exception_ranges : ONLY_IF_RO { *(.exception_ranges*) } + /* Adjust the address for the data segment. We want to adjust up to + the same address within the page on the next page up. */ + . = DATA_SEGMENT_ALIGN (CONSTANT (MAXPAGESIZE), CONSTANT (COMMONPAGESIZE)); + /* Exception handling */ + .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) *(.eh_frame.*) } + .gnu_extab : ONLY_IF_RW { *(.gnu_extab) } + .gcc_except_table : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) } + .exception_ranges : ONLY_IF_RW { *(.exception_ranges*) } + /* Thread Local Storage sections */ + .tdata : + { + PROVIDE_HIDDEN (__tdata_start = .); + *(.tdata .tdata.* .gnu.linkonce.td.*) + } + .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } + .jcr : { KEEP (*(.jcr)) } + .data.rel.ro : { *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro .data.rel.ro.* .gnu.linkonce.d.rel.ro.*) } + .dynamic : { *(.dynamic) } + . = DATA_SEGMENT_RELRO_END (0, .); + .data : + { + __DATA_BEGIN__ = .; + *(.data .data.* .gnu.linkonce.d.*) + SORT(CONSTRUCTORS) + } + .data1 : { *(.data1) } + .got : { *(.got.plt) *(.igot.plt) *(.got) *(.igot) } + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + .sdata : + { + __SDATA_BEGIN__ = .; + *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) + *(.sdata .sdata.* .gnu.linkonce.s.*) + } + _edata = .; PROVIDE (edata = .); + . = .; + __bss_start = .; + .sbss : + { + *(.dynsbss) + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.scommon) + } + .bss : + { + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. + FIXME: Why do we need it? When there is no .bss section, we do not + pad the .data section. */ + . = ALIGN(. != 0 ? 64 / 8 : 1); + } + . = ALIGN(64 / 8); + . = SEGMENT_START("ldata-segment", .); + . = ALIGN(64 / 8); + __BSS_END__ = .; + __global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800, + MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800)); + _end = .; PROVIDE (end = .); + . = DATA_SEGMENT_END (.); + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + /* DWARF 3 */ + .debug_pubtypes 0 : { *(.debug_pubtypes) } + .debug_ranges 0 : { *(.debug_ranges) } + /* DWARF Extension. */ + .debug_macro 0 : { *(.debug_macro) } + .debug_addr 0 : { *(.debug_addr) } + .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) } + /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) } +} diff --git a/linux/Makefile b/linux/Makefile index 46a193090..6f7b6c7fb 100644 --- a/linux/Makefile +++ b/linux/Makefile @@ -1,4 +1,3 @@ -RISCV := /opt/riscv #BUILDROOT := ${RISCV}/buildroot-test BUILDROOT := buildroot IMAGES := ${BUILDROOT}/output/images @@ -32,6 +31,8 @@ OBJDUMPS := $(foreach name, $(OBJDUMPS), $(DIS)/$(name).objdump) all: clean download Image disassemble install +all_nosudo: clean download Image disassemble install_nosudo + Image: bash -c "unset LD_LIBRARY_PATH; make -C $(BUILDROOT) --jobs;" $(MAKE) generate @@ -40,6 +41,18 @@ install: sudo rm -rf $(RISCV)/$(BUILDROOT) sudo mv $(BUILDROOT) $(RISCV)/$(BUILDROOT) +install_nosudo: + rm -rf $(RISCV)/$(BUILDROOT) + mv $(BUILDROOT) $(RISCV)/$(BUILDROOT) + +dumptvs: + sudo mkdir -p $(RISCV)/linux-testvectors + cd testvector-generation; sudo ./genInitMem.sh + +dumptvs_nosudo: + mkdir -p $(RISCV)/linux-testvectors + cd testvector-generation; ./genInitMem.sh + # Temp rule for debugging test: echo $(shell find $(BUILDROOT)/output/build -maxdepth 2 -type d -regex ".*/linux-[0-9]+\.[0-9]+\.[0-9]+$$") diff --git a/linux/buildroot-config-src/buildroot-2023.05.1/main.config b/linux/buildroot-config-src/buildroot-2023.05.1/main.config index 348922670..3ea431c02 100644 --- a/linux/buildroot-config-src/buildroot-2023.05.1/main.config +++ b/linux/buildroot-config-src/buildroot-2023.05.1/main.config @@ -134,7 +134,7 @@ BR2_GCC_VERSION_12_X=y BR2_GCC_VERSION="12.3.0" BR2_EXTRA_GCC_CONFIG_OPTIONS="" BR2_TOOLCHAIN_BUILDROOT_CXX=y -# BR2_TOOLCHAIN_BUILDROOT_FORTRAN is not set +BR2_TOOLCHAIN_BUILDROOT_FORTRAN=y # BR2_GCC_ENABLE_OPENMP is not set # BR2_GCC_ENABLE_GRAPHITE is not set BR2_PACKAGE_HOST_GDB_ARCH_SUPPORTS=y @@ -152,6 +152,7 @@ BR2_TOOLCHAIN_SUPPORTS_VARIADIC_MI_THUNK=y BR2_USE_WCHAR=y BR2_ENABLE_LOCALE=y BR2_INSTALL_LIBSTDCPP=y +BR2_TOOLCHAIN_HAS_FORTRAN=y BR2_TOOLCHAIN_HAS_THREADS=y BR2_TOOLCHAIN_HAS_THREADS_DEBUG=y BR2_TOOLCHAIN_HAS_THREADS_NPTL=y @@ -1086,10 +1087,6 @@ BR2_PACKAGE_PROVIDES_HOST_LUAINTERPRETER="host-lua" # BR2_PACKAGE_MICROPYTHON is not set # BR2_PACKAGE_MOARVM is not set BR2_PACKAGE_HOST_MONO_ARCH_SUPPORTS=y - -# -# octave needs a toolchain w/ C++ and fortran, gcc >= 4.8 -# BR2_PACKAGE_HOST_OPENJDK_BIN_ARCH_SUPPORTS=y # BR2_PACKAGE_PERL is not set BR2_PACKAGE_PHP_ARCH_SUPPORTS=y @@ -1731,10 +1728,7 @@ BR2_PACKAGE_LIBCAMERA_ARCH_SUPPORTS=y # BR2_PACKAGE_ACE is not set # BR2_PACKAGE_APR is not set # BR2_PACKAGE_APR_UTIL is not set - -# -# armadillo needs a toolchain w/ fortran, C++ -# +# BR2_PACKAGE_ARMADILLO is not set # BR2_PACKAGE_ATF is not set # BR2_PACKAGE_AVRO_C is not set # BR2_PACKAGE_BCTOOLBOX is not set @@ -1782,10 +1776,7 @@ BR2_PACKAGE_GOBJECT_INTROSPECTION_ARCH_SUPPORTS=y BR2_PACKAGE_JEMALLOC_ARCH_SUPPORTS=y # BR2_PACKAGE_JEMALLOC is not set BR2_PACKAGE_LAPACK_ARCH_SUPPORTS=y - -# -# lapack/blas needs a toolchain w/ fortran -# +# BR2_PACKAGE_LAPACK is not set BR2_PACKAGE_LIBABSEIL_CPP_ARCH_SUPPORTS=y # BR2_PACKAGE_LIBABSEIL_CPP is not set # BR2_PACKAGE_LIBARGTABLE2 is not set diff --git a/setup.sh b/setup.sh index f609c1e3d..d8063b2aa 100644 --- a/setup.sh +++ b/setup.sh @@ -27,6 +27,10 @@ export PATH=$WALLY/bin:$PATH ulimit -s 100000 # load site licenses and tool locations -source $RISCV/site-setup.sh +if [ -f ${RISCV}/site-setup.sh ]; then + source ${RISCV}/site-setup.sh +else + source ${WALLY}/site-setup.sh +fi echo "setup done" diff --git a/sim/linux-wave.do b/sim/linux-wave.do deleted file mode 100644 index 614c6ab07..000000000 --- a/sim/linux-wave.do +++ /dev/null @@ -1,357 +0,0 @@ -onerror {resume} -quietly virtual function -install /testbench/dut/core/lsu -env /testbench/dut/core/lsu/bus { &{/testbench/dut/core/lsu/LSUHTRANS[1], /testbench/dut/core/lsu/LSUHADDR }} test -quietly WaveActivateNextPane {} 0 -add wave -noupdate /testbench/clk -add wave -noupdate /testbench/reset -add wave -noupdate /testbench/dut/core/priv/priv/SATP_REGW -add wave -noupdate -group Testbench /testbench/reset_ext -add wave -noupdate -group Testbench -radix unsigned /testbench/InstrCountW -add wave -noupdate -group Testbench -radix unsigned /testbench/AttemptedInstructionCount -add wave -noupdate -group Testbench -radix decimal /testbench/interruptInstrCount -add wave -noupdate -group Testbench /testbench/interruptCauseVal -add wave -noupdate -group Testbench /testbench/interruptEpcVal -add wave -noupdate -group Testbench /testbench/interruptTVal -add wave -noupdate -group Testbench /testbench/interruptDesc -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM -add wave -noupdate -expand -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/priv/priv/InterruptM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/ExceptionM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW -add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallF -add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallD -add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallE -add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallM -add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallW -add wave -noupdate -group {instruction pipeline} /testbench/InstrFName -add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD -add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrE -add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrM -add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/PCD -add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/InstrD -add wave -noupdate -group {Decode Stage} /testbench/InstrDName -add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/InstrValidD -add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD -add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD -add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D -add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D -add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE -add wave -noupdate -group {Execution Stage} /testbench/ExpectedPCE -add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE -add wave -noupdate -group {Execution Stage} /testbench/InstrEName -add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE -add wave -noupdate -group {Execution Stage} /testbench/textE -add wave -noupdate -group {Execution Stage} -color {Cornflower Blue} /testbench/FunctionName/FunctionName -add wave -noupdate -expand -group {Memory Stage} /testbench/checkInstrM -add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM -add wave -noupdate -expand -group {Memory Stage} /testbench/ExpectedPCM -add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM -add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName -add wave -noupdate -expand -group {Memory Stage} /testbench/textM -add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM -add wave -noupdate -group {WriteBack stage} /testbench/checkInstrW -add wave -noupdate -group {WriteBack stage} /testbench/InstrValidW -add wave -noupdate -group {WriteBack stage} /testbench/PCW -add wave -noupdate -group {WriteBack stage} /testbench/ExpectedPCW -add wave -noupdate -group {WriteBack stage} /testbench/InstrW -add wave -noupdate -group {WriteBack stage} /testbench/InstrWName -add wave -noupdate -group {WriteBack stage} /testbench/textW -add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check} -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCNextF -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF -add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE -add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCE -add wave -noupdate -group PCS /testbench/dut/core/ifu/PCNextF -add wave -noupdate -group PCS /testbench/dut/core/ifu/PCD -add wave -noupdate -group PCS /testbench/dut/core/PCE -add wave -noupdate -group PCS /testbench/dut/core/PCM -add wave -noupdate -group PCS /testbench/PCW -add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF -add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF -add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F -add wave -noupdate -group RegFile -expand /testbench/dut/core/ieu/dp/regf/rf -add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a1 -add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a2 -add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a3 -add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rd1 -add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rd2 -add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/we3 -add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/wd3 -add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ReadDataW -add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/CSRReadValW -add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultSrcW -add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultW -add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/A -add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/B -add wave -noupdate -group alu -divider internals -add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1D -add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2D -add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1E -add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2E -add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdE -add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdM -add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdW -add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/MemReadE -add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RegWriteM -add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RegWriteW -add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/ForwardAE -add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/ForwardBE -add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/LoadStallD -add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE -add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE -add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE -add wave -noupdate -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState -add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF -add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr -add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCNextF -add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF -add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay -add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF -add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr -add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck -add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite -add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/ITLBMissF -add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress -add wave -noupdate -group lsu /testbench/dut/core/lsu/IEUAdrM -add wave -noupdate -group lsu /testbench/dut/core/lsu/PAdrM -add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW -add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM -add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM -add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM -add wave -noupdate -group lsu /testbench/dut/core/lsu/WriteDataM -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/BusStall -add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM -add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay} -add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr -add wave -noupdate -group lsu -expand -group dcache -expand -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr -add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty -add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty -add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr -add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/CacheableM -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM[2]} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits[2]} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits[2]} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetValid -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM -add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit -add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress -add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_D -add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_A -add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_U -add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_X -add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_W -add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_R -add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_V -add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/ImproperPrivilege -add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Misaligned -add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/dtlb/InvalidRead -add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/dtlb/InvalidWrite -add wave -noupdate -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault -add wave -noupdate -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM -add wave -noupdate -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr -add wave -noupdate -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal -add wave -noupdate -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HCLK -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESETn -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HREADY -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESP -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HADDR -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWDATA -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWRITE -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HSIZE -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK -add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite -add wave -noupdate -group itlb /testbench/dut/core/ifu/ITLBMissF -add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress -add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/PMAInstrAccessFaultF -add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr -add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr -add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIntr -add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIME -add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIMECMP -add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/SIN -add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/DSRb -add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/DCDb -add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/CTSb -add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/RIb -add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/SOUT -add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/RTSb -add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/DTRb -add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/OUT1b -add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/OUT2b -add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/INTR -add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/TXRDYb -add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/RXRDYb -add wave -noupdate -group {debug trace} -expand -group mem -color Yellow /testbench/dut/core/FlushW -add wave -noupdate -group {debug trace} -expand -group mem /testbench/checkInstrM -add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/core/PCM -add wave -noupdate -group {debug trace} -expand -group mem /testbench/ExpectedPCM -add wave -noupdate -group {debug trace} -expand -group mem /testbench/textM -add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/core/hzu/TrapM -add wave -noupdate -group {debug trace} -expand -group wb /testbench/checkInstrW -add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW -add wave -noupdate -group {debug trace} -expand -group wb /testbench/ExpectedPCW -add wave -noupdate -group {debug trace} -expand -group wb /testbench/TrapW -add wave -noupdate -group {debug trace} -expand -group wb /testbench/textW -add wave -noupdate -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]} -add wave -noupdate -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]} -add wave -noupdate -group {Performance Counters} -label {LOAD STORE HAZARD} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]} -add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP DIRECTION WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]} -add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]} -add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BTA/JTA WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]} -add wave -noupdate -group {Performance Counters} -expand -group BRP -label {JAL(R) INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]} -add wave -noupdate -group {Performance Counters} -expand -group BRP -label {RAS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]} -add wave -noupdate -group {Performance Counters} -expand -group BRP -label {RETURN INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]} -add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]} -add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {ICACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]} -add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {ICACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]} -add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]} -add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]} -add wave -noupdate /testbench/dut/core/lsu/test -add wave -noupdate {/testbench/dut/core/lsu/LSUHTRANS[1]} -add wave -noupdate /testbench/dut/core/lsu/LSUHADDR -add wave -noupdate /testbench/dut/core/lsu/LSUHTRANS -add wave -noupdate /testbench/dut/core/lsu/HRDATA -add wave -noupdate /testbench/dut/core/lsu/LSUHWDATA -add wave -noupdate /testbench/dut/core/lsu/LSUHWRITE -add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck -add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate /testbench/dut/core/priv/priv/PrivilegeModeW -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{invalid oad data} {15916799 ns} 1} {{original store} {4919493 ns} 1} {{correct load data} {165196425 ns} 0} {{Cursor 4} {165662196 ns} 1} {{Cursor 5} {165196436 ns} 1} -quietly wave cursor active 3 -configure wave -namecolwidth 250 -configure wave -valuecolwidth 314 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {165196205 ns} {165196487 ns} diff --git a/sim/GetLineNum.do b/sim/questa/GetLineNum.do similarity index 100% rename from sim/GetLineNum.do rename to sim/questa/GetLineNum.do diff --git a/sim/questa/coverage b/sim/questa/coverage new file mode 100755 index 000000000..038253911 --- /dev/null +++ b/sim/questa/coverage @@ -0,0 +1,2 @@ +# recompile coverage tests and run coverage including them +pushd $WALLY/tests/coverage; make; popd; ./regression-wally -coverage diff --git a/sim/coverage-exclusions-rv64gc.do b/sim/questa/coverage-exclusions-rv64gc.do similarity index 73% rename from sim/coverage-exclusions-rv64gc.do rename to sim/questa/coverage-exclusions-rv64gc.do index 36098d90d..3331c4574 100644 --- a/sim/coverage-exclusions-rv64gc.do +++ b/sim/questa/coverage-exclusions-rv64gc.do @@ -28,6 +28,10 @@ # This file should be a last resort. It's preferable to put # // coverage off # statements inline with the code whenever possible. + +set WALLY $::env(WALLY) +set SRC ${WALLY}/src + # a hack to describe coverage exclusions without hardcoding linenumbers: do GetLineNum.do @@ -44,13 +48,13 @@ coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtfsm -ftrans state DON # which won't happen while the divider is busy. coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtfsm -ftrans state BUSY->IDLE # All Memory-stage stalls have resolved by time fdivsqrt finishes regular operation in this configuration, so can't test StallM -coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtfsm -linerange [GetLineNum ../src/fpu/fdivsqrt/fdivsqrtfsm.sv "exclusion-tag: fdivsqrtfsm stallm"] -item b 1 -coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtfsm -linerange [GetLineNum ../src/fpu/fdivsqrt/fdivsqrtfsm.sv "exclusion-tag: fdivsqrtfsm stallm"] -item s 1 +coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtfsm -linerange [GetLineNum ${SRC}/fpu/fdivsqrt/fdivsqrtfsm.sv "exclusion-tag: fdivsqrtfsm stallm"] -item b 1 +coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtfsm -linerange [GetLineNum ${SRC}/fpu/fdivsqrt/fdivsqrtfsm.sv "exclusion-tag: fdivsqrtfsm stallm"] -item s 1 # Division by zero never sets sticky/guard/overflow/round to cause inexact or underflow result, but check out of paranoia -coverage exclude -scope /dut/core/fpu/fpu/postprocess/flags -linerange [GetLineNum ../src/fpu/postproc/flags.sv "assign FpInexact"] -item e 1 -fecexprrow 15 -coverage exclude -scope /dut/core/fpu/fpu/postprocess/flags -linerange [GetLineNum ../src/fpu/postproc/flags.sv "assign Underflow"] -item e 1 -fecexprrow 22 +coverage exclude -scope /dut/core/fpu/fpu/postprocess/flags -linerange [GetLineNum ${SRC}/fpu/postproc/flags.sv "assign FpInexact"] -item e 1 -fecexprrow 15 +coverage exclude -scope /dut/core/fpu/fpu/postprocess/flags -linerange [GetLineNum ${SRC}/fpu/postproc/flags.sv "assign Underflow"] -item e 1 -fecexprrow 22 # Convert int to fp will never underflow -coverage exclude -scope /dut/core/fpu/fpu/postprocess/cvtshiftcalc -linerange [GetLineNum ../src/fpu/postproc/cvtshiftcalc.sv "assign CvtResUf"] -item e 1 -fecexprrow 4 +coverage exclude -scope /dut/core/fpu/fpu/postprocess/cvtshiftcalc -linerange [GetLineNum ${SRC}/fpu/postproc/cvtshiftcalc.sv "assign CvtResUf"] -item e 1 -fecexprrow 4 ################## # Cache Exclusions @@ -62,89 +66,89 @@ coverage exclude -scope /dut/core/fpu/fpu/postprocess/cvtshiftcalc -linerange [G coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -fstate CurrState STATE_FLUSH STATE_FLUSH_WRITEBACK STATE_FLUSH_WRITEBACK STATE_WRITEBACK coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -ftrans CurrState STATE_WRITE_LINE->STATE_READY STATE_FETCH->STATE_READY # exclude unused transitions from case statement. Unfortunately the whole branch needs to be excluded I think. Expression coverage should still work. -coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache state-case"] -item b 1 +coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache state-case"] -item b 1 # I$ does not flush -coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache FlushCache"] -item e 1 -fecexprrow 2 +coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache FlushCache"] -item e 1 -fecexprrow 2 # exclude branch/condition coverage: LineDirty if statement -coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache FETCHStatement"] -item bc 1 -coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache FLUSHStatement"] -item bs 1 +coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache FETCHStatement"] -item bc 1 +coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache FLUSHStatement"] -item bs 1 # exclude the unreachable logic -set start [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag-start: icache case"] -set end [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag-end: icache case"] +set start [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag-start: icache case"] +set end [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag-end: icache case"] coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange $start-$end -coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache WRITEBACKStatement"] +coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache WRITEBACKStatement"] # exclude Atomic Operation logic -coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: cache AnyMiss"] -item e 1 -fecexprrow 6 -coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache storeAMO1"] -item e 1 -fecexprrow 2-4 -coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache AnyUpdateHit"] -item e 1 -fecexprrow 2 +coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: cache AnyMiss"] -item e 1 -fecexprrow 6 +coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache storeAMO1"] -item e 1 -fecexprrow 2-4 +coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache AnyUpdateHit"] -item e 1 -fecexprrow 2 # cache write logic -coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache CacheW"] -item e 1 -fecexprrow 4 +coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache CacheW"] -item e 1 -fecexprrow 4 # output signal logic -coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache StallStates"] -item e 1 -fecexprrow 8 12 14 -set start [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag-start: icache flushdirtycontrols"] -set end [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag-end: icache flushdirtycontrols"] +coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache StallStates"] -item e 1 -fecexprrow 8 12 14 +set start [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag-start: icache flushdirtycontrols"] +set end [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag-end: icache flushdirtycontrols"] coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange $start-$end -coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache CacheBusW"] -coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache SelAdrCauses"] -item e 1 -fecexprrow 4 10 -coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache SelAdrTag"] -item e 1 -fecexprrow 8 -coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache CacheBusRCauses"] -item e 1 -fecexprrow 1-2 12 +coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache CacheBusW"] +coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache SelAdrCauses"] -item e 1 -fecexprrow 4 10 +coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache SelAdrTag"] -item e 1 -fecexprrow 8 +coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache CacheBusRCauses"] -item e 1 -fecexprrow 1-2 12 # cache.sv AdrSelMuxData and AdrSelMuxTag and CacheBusAdrMux, excluding unhit Flush branch -coverage exclude -scope /dut/core/ifu/bus/icache/icache/AdrSelMuxData -linerange [GetLineNum ../src/generic/mux.sv "exclusion-tag: mux3"] -item b 1 -coverage exclude -scope /dut/core/ifu/bus/icache/icache/AdrSelMuxTag -linerange [GetLineNum ../src/generic/mux.sv "exclusion-tag: mux3"] -item b 1 -coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheBusAdrMux -linerange [GetLineNum ../src/generic/mux.sv "exclusion-tag: mux3"] -item b 1 3 +coverage exclude -scope /dut/core/ifu/bus/icache/icache/AdrSelMuxData -linerange [GetLineNum ${SRC}/generic/mux.sv "exclusion-tag: mux3"] -item b 1 +coverage exclude -scope /dut/core/ifu/bus/icache/icache/AdrSelMuxTag -linerange [GetLineNum ${SRC}/generic/mux.sv "exclusion-tag: mux3"] -item b 1 +coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheBusAdrMux -linerange [GetLineNum ${SRC}/generic/mux.sv "exclusion-tag: mux3"] -item b 1 3 # CacheWay Dirty logic. -scope does not accept wildcards. set numcacheways 4 for {set i 0} {$i < $numcacheways} {incr i} { - coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: icache SetDirtyWay"] -item e 1 - coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: icache SelectedWiteWordEn"] -item e 1 -fecexprrow 4 6 + coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "exclusion-tag: icache SetDirtyWay"] -item e 1 + coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "exclusion-tag: icache SelectedWiteWordEn"] -item e 1 -fecexprrow 4 6 # below: flushD can't go high during an icache write b/c of pipeline stall - coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache SetValidEN"] -item e 1 -fecexprrow 4 - coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache ClearValidEN"] -item e 1 -fecexprrow 4 + coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "exclusion-tag: cache SetValidEN"] -item e 1 -fecexprrow 4 + coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "exclusion-tag: cache ClearValidEN"] -item e 1 -fecexprrow 4 # No CMO to clear valid bits of I$ - coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "// exclusion-tag: icache ClearValidBits"] - coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "// exclusion-tag: icache ClearValidWay"] -item e 1 + coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "// exclusion-tag: icache ClearValidBits"] + coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "// exclusion-tag: icache ClearValidWay"] -item e 1 # No dirty ways in read-only I$ - coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "// exclusion-tag: icache DirtyWay"] -item e 1 + coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "// exclusion-tag: icache DirtyWay"] -item e 1 } # I$ buscachefsm does not perform atomics or write/writeback; HREADY is always 1 -coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicReadData"] -coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicElse"] -item s 1 -coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicPhase"] -coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicWait"] -item bs 1 -coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWriteback"] -item b 2 -coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWriteback"] -item s 1 -coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm WritebackWriteback"] -coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm WritebackWriteback2"] -item bs 1 -coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY4"] -item bs 1 -coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY6"] -item bs 1 -coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADYread"] -item c 1 -feccondrow 1 -coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWriteback"] -item c 1 -feccondrow 1,2,3,4,6 -coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY4"] -item c 1 -coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY6"] -item c 1 -coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "assign HTRANS"] -item c 1 -feccondrow 5 -coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "assign BeatCntEn"] -item e 1 -fecexprrow 4 -coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "assign CacheAccess"] -item e 1 -fecexprrow 4 -coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "assign BusStall"] -item e 1 -fecexprrow 10,12,18 -coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "assign CacheBusAck"] -item e 1 -fecexprrow 3 +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicReadData"] +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicElse"] -item s 1 +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicPhase"] +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicWait"] -item bs 1 +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWriteback"] -item b 2 +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWriteback"] -item s 1 +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm WritebackWriteback"] +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm WritebackWriteback2"] -item bs 1 +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY4"] -item bs 1 +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY6"] -item bs 1 +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADYread"] -item c 1 -feccondrow 1 +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWriteback"] -item c 1 -feccondrow 1,2,3,4,6 +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY4"] -item c 1 +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY6"] -item c 1 +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "assign HTRANS"] -item c 1 -feccondrow 5 +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "assign BeatCntEn"] -item e 1 -fecexprrow 4 +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "assign CacheAccess"] -item e 1 -fecexprrow 4 +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "assign BusStall"] -item e 1 -fecexprrow 10,12,18 +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "assign CacheBusAck"] -item e 1 -fecexprrow 3 ## D$ Exclusions. # InvalidateCache is I$ only: -coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: dcache InvalidateCheck"] -item b 2 -coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: dcache InvalidateCheck"] -item s 1 -coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: dcache CacheEn"] -item e 1 -fecexprrow 12 -coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: cache AnyMiss"] -item e 1 -fecexprrow 4 +coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: dcache InvalidateCheck"] -item b 2 +coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: dcache InvalidateCheck"] -item s 1 +coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: dcache CacheEn"] -item e 1 -fecexprrow 12 +coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: cache AnyMiss"] -item e 1 -fecexprrow 4 set numcacheways 4 for {set i 0} {$i < $numcacheways} {incr i} { - coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: dcache invalidateway"] -item bes 1 -fecexprrow 4 + coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "exclusion-tag: dcache invalidateway"] -item bes 1 -fecexprrow 4 # InvalidateCacheDelay is always 0 for D$ because it is flushed, not invalidated - coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: dcache HitWay"] -item 3 1 -fecexprrow 2 + coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "exclusion-tag: dcache HitWay"] -item 3 1 -fecexprrow 2 # FlushStage=1 will never happen when SetValidWay=1 since a pipeline stall is asserted by the cache in the fetch stage, which happens before # going into the WRITE_LINE state (and asserting SetValidWay). No TrapM can fire and since StallW is high, a stallM caused by WFIStallM would not cause a flushW. - coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache SetValidEN"] -item e 1 -fecexprrow 4 - coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache ClearValidEN"] -item e 1 -fecexprrow 4 -# Not right; other ways can get flushed and dirtied simultaneously coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache UpdateDirty"] -item c 1 -feccondrow 6 + coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "exclusion-tag: cache SetValidEN"] -item e 1 -fecexprrow 4 + coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "exclusion-tag: cache ClearValidEN"] -item e 1 -fecexprrow 4 +# Not right; other ways can get flushed and dirtied simultaneously coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "exclusion-tag: cache UpdateDirty"] -item c 1 -feccondrow 6 } # D$ writeback, flush, write_line, or flush_writeback states can't be cancelled by a flush coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -ftrans CurrState STATE_WRITEBACK->STATE_READY STATE_FLUSH->STATE_READY STATE_WRITE_LINE->STATE_READY STATE_FLUSH_WRITEBACK->STATE_READY @@ -164,16 +168,16 @@ coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/ddr4dec coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/sdcdec # PMA Regions 1, 2, and 3 (dtim, irom, ddr4) are never used in the rv64gc configuration, so exclude coverage -set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-atomic"] +set line [GetLineNum ${SRC}/mmu/pmachecker.sv "exclusion-tag: unused-atomic"] coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4 coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4 -set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-tim"] +set line [GetLineNum ${SRC}/mmu/pmachecker.sv "exclusion-tag: unused-tim"] coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4 coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4 -set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-cachable"] +set line [GetLineNum ${SRC}/mmu/pmachecker.sv "exclusion-tag: unused-cachable"] coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2 coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2 -set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-idempotent"] +set line [GetLineNum ${SRC}/mmu/pmachecker.sv "exclusion-tag: unused-idempotent"] coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4,6 coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4,6,8 @@ -183,7 +187,7 @@ coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/uncoreramdec coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/spidec # The following peripherals are always supported -set line [GetLineNum ../src/mmu/adrdec.sv "exclusion-tag: adrdecSel"] +set line [GetLineNum ${SRC}/mmu/adrdec.sv "exclusion-tag: adrdecSel"] coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/bootromdec -linerange $line-$line -item e 1 -fecexprrow 3,7 coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/gpiodec -linerange $line-$line -item e 1 -fecexprrow 3 coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/uartdec -linerange $line-$line -item e 1 -fecexprrow 3 @@ -191,104 +195,104 @@ coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/plicdec -line coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/spidec -linerange $line-$line -item e 1 -fecexprrow 3 #Excluding signals in lsu: clintdec and uncoreram accept all sizes so 'SizeValid' will never be 0 -set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"] +set line [GetLineNum ${SRC}/mmu/adrdec.sv "& SizeValid"] coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/clintdec -linerange $line-$line -item e 1 -fecexprrow 5 -set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"] +set line [GetLineNum ${SRC}/mmu/adrdec.sv "& SizeValid"] coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/uncoreramdec -linerange $line-$line -item e 1 -fecexprrow 5 -# set line [GetLineNum ../src/mmu/adrdec.sv "& Supported"] +# set line [GetLineNum ${SRC}/mmu/adrdec.sv "& Supported"] coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/dtimdec coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/iromdec coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/ddr4dec coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/sdcdec # No DTIM or IROM -coverage exclude -scope /dut/core/ifu/bus/icache/UnCachedDataMux -linerange [GetLineNum ../src/generic/mux.sv "exclusion-tag: mux3"] -item b 1 -coverage exclude -scope /dut/core/lsu/bus/dcache/UnCachedDataMux -linerange [GetLineNum ../src/generic/mux.sv "exclusion-tag: mux3"] -item b 1 +coverage exclude -scope /dut/core/ifu/bus/icache/UnCachedDataMux -linerange [GetLineNum ${SRC}/generic/mux.sv "exclusion-tag: mux3"] -item b 1 +coverage exclude -scope /dut/core/lsu/bus/dcache/UnCachedDataMux -linerange [GetLineNum ${SRC}/generic/mux.sv "exclusion-tag: mux3"] -item b 1 #################### # Unused access types due to sharing IFU and LSU logic #################### ## The lsu never executes instructions so 'ExecuteAccessF' will never be 1 -set line [GetLineNum ../src/mmu/pmachecker.sv "AccessRWXC ="] +set line [GetLineNum ${SRC}/mmu/pmachecker.sv "AccessRWXC ="] coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 6 -set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| ExecuteAccessF"] +set line [GetLineNum ${SRC}/mmu/pmachecker.sv "ReadAccessM \\| ExecuteAccessF"] coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 4 -set line [GetLineNum ../src/mmu/pmachecker.sv "ExecuteAccessF & PMAAccessFault"] +set line [GetLineNum ${SRC}/mmu/pmachecker.sv "ExecuteAccessF & PMAAccessFault"] coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2 -set line [GetLineNum ../src/mmu/mmu.sv "ExecuteAccessF \\| ReadAccessM"] +set line [GetLineNum ${SRC}/mmu/mmu.sv "ExecuteAccessF \\| ReadAccessM"] coverage exclude -scope /dut/core/lsu/dmmu/dmmu -linerange $line-$line -item e 1 -fecexprrow 2 -set line [GetLineNum ../src/mmu/mmu.sv "TLBPageFault & ExecuteAccessF"] +set line [GetLineNum ${SRC}/mmu/mmu.sv "TLBPageFault & ExecuteAccessF"] coverage exclude -scope /dut/core/lsu/dmmu/dmmu -linerange $line-$line -item e 1 -fecexprrow 1,2,4 -set line [GetLineNum ../src/mmu/mmu.sv "PMAInstrAccessFaultF \\|"] +set line [GetLineNum ${SRC}/mmu/mmu.sv "PMAInstrAccessFaultF \\|"] coverage exclude -scope /dut/core/lsu/dmmu/dmmu -linerange $line-$line -item e 1 -fecexprrow 2,4,5,6 -set line [GetLineNum ../src/mmu/pmpchecker.sv "EnforcePMP & ExecuteAccessF"] +set line [GetLineNum ${SRC}/mmu/pmpchecker.sv "EnforcePMP & ExecuteAccessF"] coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 1,2,4,5,6 -set line [GetLineNum ../src/mmu/pmpchecker.sv "EnforcePMP & ExecuteAccessF"] +set line [GetLineNum ${SRC}/mmu/pmpchecker.sv "EnforcePMP & ExecuteAccessF"] coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 3 ## The IFU has ReadAccess = WriteAccess = 0 and ExecuteAccess = 1 hardwired, so exclude alternatives -set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| WriteAccessM"] +set line [GetLineNum ${SRC}/mmu/pmachecker.sv "ReadAccessM \\| WriteAccessM"] coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2 4 -set line [GetLineNum ../src/mmu/pmachecker.sv "WriteAccessM \\| ExecuteAccessF"] +set line [GetLineNum ${SRC}/mmu/pmachecker.sv "WriteAccessM \\| ExecuteAccessF"] coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1-5 -set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| ExecuteAccessF"] +set line [GetLineNum ${SRC}/mmu/pmachecker.sv "ReadAccessM \\| ExecuteAccessF"] coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1-3 -set line [GetLineNum ../src/mmu/pmachecker.sv "ExecuteAccessF & PMAAccessFault"] +set line [GetLineNum ${SRC}/mmu/pmachecker.sv "ExecuteAccessF & PMAAccessFault"] coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1 -set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM & PMAAccessFault"] +set line [GetLineNum ${SRC}/mmu/pmachecker.sv "ReadAccessM & PMAAccessFault"] coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2-4 -set line [GetLineNum ../src/mmu/pmachecker.sv "PMAStoreAmoAccessFaultM ="] +set line [GetLineNum ${SRC}/mmu/pmachecker.sv "PMAStoreAmoAccessFaultM ="] coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -set line [GetLineNum ../src/mmu/pmachecker.sv "AccessRWXC \\| AtomicAccessM"] +set line [GetLineNum ${SRC}/mmu/pmachecker.sv "AccessRWXC \\| AtomicAccessM"] coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 3 -set line [GetLineNum ../src/mmu/mmu.sv "ExecuteAccessF \\| ReadAccessM"] +set line [GetLineNum ${SRC}/mmu/mmu.sv "ExecuteAccessF \\| ReadAccessM"] coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,3,4 -set line [GetLineNum ../src/mmu/mmu.sv "ReadAccessM & ~WriteAccessM"] +set line [GetLineNum ${SRC}/mmu/mmu.sv "ReadAccessM & ~WriteAccessM"] coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 2-4 -set line [GetLineNum ../src/mmu/mmu.sv "assign AmoAccessM"] +set line [GetLineNum ${SRC}/mmu/mmu.sv "assign AmoAccessM"] coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -set line [GetLineNum ../src/mmu/mmu.sv "assign AmoMisalignedCausesAccessFaultM"] +set line [GetLineNum ${SRC}/mmu/mmu.sv "assign AmoMisalignedCausesAccessFaultM"] coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -set line [GetLineNum ../src/mmu/mmu.sv "DataMisalignedM & WriteAccessM"] +set line [GetLineNum ${SRC}/mmu/mmu.sv "DataMisalignedM & WriteAccessM"] coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4 -set line [GetLineNum ../src/mmu/mmu.sv "TLBPageFault & ExecuteAccessF"] +set line [GetLineNum ${SRC}/mmu/mmu.sv "TLBPageFault & ExecuteAccessF"] coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 3 -set line [GetLineNum ../src/mmu/mmu.sv "TLBPageFault & ReadNoAmoAccessM"] +set line [GetLineNum ${SRC}/mmu/mmu.sv "TLBPageFault & ReadNoAmoAccessM"] coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4 -set line [GetLineNum ../src/mmu/mmu.sv "StoreAmoPageFaultM \="] +set line [GetLineNum ${SRC}/mmu/mmu.sv "StoreAmoPageFaultM \="] coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4 -set line [GetLineNum ../src/mmu/mmu.sv "DataMisalignedM & ReadNoAmoAccessM"] +set line [GetLineNum ${SRC}/mmu/mmu.sv "DataMisalignedM & ReadNoAmoAccessM"] coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4 -set line [GetLineNum ../src/mmu/pmpchecker.sv "EnforcePMP & WriteAccessM"] +set line [GetLineNum ${SRC}/mmu/pmpchecker.sv "EnforcePMP & WriteAccessM"] coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 1,2,4,5,6 -set line [GetLineNum ../src/mmu/pmpchecker.sv "EnforcePMP & ReadAccessM"] +set line [GetLineNum ${SRC}/mmu/pmpchecker.sv "EnforcePMP & ReadAccessM"] coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 1,2,4,5,6 -set line [GetLineNum ../src/mmu/mmu.sv "LoadAccessFaultM \="] +set line [GetLineNum ${SRC}/mmu/mmu.sv "LoadAccessFaultM \="] coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 2,4,5,6 -set line [GetLineNum ../src/mmu/mmu.sv "StoreAmoAccessFaultM \="] +set line [GetLineNum ${SRC}/mmu/mmu.sv "StoreAmoAccessFaultM \="] coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 2,4,5,6 -set line [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "ReadAccess \\| WriteAccess"] +set line [GetLineNum ${SRC}/mmu/tlb/tlbcontrol.sv "ReadAccess \\| WriteAccess"] coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $line-$line -item e 1 -fecexprrow 1,3,4 -set line [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "CAMHit & TLBAccess"] +set line [GetLineNum ${SRC}/mmu/tlb/tlbcontrol.sv "CAMHit & TLBAccess"] coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $line-$line -item e 1 -fecexprrow 3 -set line [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "~CAMHit & TLBAccess"] +set line [GetLineNum ${SRC}/mmu/tlb/tlbcontrol.sv "~CAMHit & TLBAccess"] coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $line-$line -item e 1 -fecexprrow 3 # IMMU only makes word-sized accesses -set line [GetLineNum ../src/mmu/mmu.sv "exclusion-tag: immu-wordaccess"] +set line [GetLineNum ${SRC}/mmu/mmu.sv "exclusion-tag: immu-wordaccess"] set line2 [expr $line + 6 ] coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item e 1 -fecexprrow 4 coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item b 1 coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item s 1 # IMMU never disables translations -coverage exclude -scope /dut/core/ifu/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "assign Translate"] -item e 1 -fecexprrow 2 -coverage exclude -scope /dut/core/ifu/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "assign UpdateDA"] -item e 1 -fecexprrow 5 +coverage exclude -scope /dut/core/ifu/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange [GetLineNum ${SRC}/mmu/tlb/tlbcontrol.sv "assign Translate"] -item e 1 -fecexprrow 2 +coverage exclude -scope /dut/core/ifu/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange [GetLineNum ${SRC}/mmu/tlb/tlbcontrol.sv "assign UpdateDA"] -item e 1 -fecexprrow 5 # never reaches this when ENVCFG_ADUE_1 because HPTW updates A bit first -coverage exclude -scope /dut/core/ifu/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "assign PrePageFault"] -item e 1 -fecexprrow 18 +coverage exclude -scope /dut/core/ifu/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange [GetLineNum ${SRC}/mmu/tlb/tlbcontrol.sv "assign PrePageFault"] -item e 1 -fecexprrow 18 @@ -298,19 +302,19 @@ coverage exclude -scope /dut/core/ifu/ifu/immu/immu/tlb/tlb/tlbcontrol -linerang ############### # RV64GC HPTW never starts at L1_ADR -set line [GetLineNum ../src/mmu/hptw.sv "InitialWalkerState == L1_ADR"] +set line [GetLineNum ${SRC}/mmu/hptw.sv "InitialWalkerState == L1_ADR"] coverage exclude -scope /dut/core/lsu/lsu/hptw/hptw -linerange $line-$line -item c 1 -feccondrow 2 # Never possible to get a page fault when neither reading nor writing -set line [GetLineNum ../src/mmu/hptw.sv "assign HPTWLoadPageFault"] +set line [GetLineNum ${SRC}/mmu/hptw.sv "assign HPTWLoadPageFault"] coverage exclude -scope /dut/core/lsu/lsu/hptw/hptw -linerange $line-$line -item e 1 -fecexprrow 7 # Never possible to get a store page fault from an ITLB walk -set line [GetLineNum ../src/mmu/hptw.sv "assign HPTWStoreAmoPageFault"] +set line [GetLineNum ${SRC}/mmu/hptw.sv "assign HPTWStoreAmoPageFault"] coverage exclude -scope /dut/core/lsu/lsu/hptw/hptw -linerange $line-$line -item e 1 -fecexprrow 3 # Never possible to get Access = 0 on a nonleaf PTE with no OtherPageFault (because InvalidRead/Write will be 1 on the nonleaf) -set line [GetLineNum ../src/mmu/hptw.sv "assign HPTWUpdateDA"] +set line [GetLineNum ${SRC}/mmu/hptw.sv "assign HPTWUpdateDA"] coverage exclude -scope /dut/core/lsu/lsu/hptw/hptw -linerange $line-$line -item e 1 -fecexprrow 3 ############### @@ -318,78 +322,78 @@ coverage exclude -scope /dut/core/lsu/lsu/hptw/hptw -linerange $line-$line -item ############### # IMMU PMP does not support CBO instructions -coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ../src/mmu/pmpchecker.sv "exclusion-tag: immu-pmpcbom"] -coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ../src/mmu/pmpchecker.sv "exclusion-tag: immu-pmpcboz"] -coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ../src/mmu/pmpchecker.sv "exclusion-tag: immu-pmpcboaccess"] +coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ${SRC}/mmu/pmpchecker.sv "exclusion-tag: immu-pmpcbom"] +coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ${SRC}/mmu/pmpchecker.sv "exclusion-tag: immu-pmpcboz"] +coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ${SRC}/mmu/pmpchecker.sv "exclusion-tag: immu-pmpcboaccess"] # No irom -set line [GetLineNum ../src/ifu/ifu.sv "~ITLBMissF & ~CacheableF & ~SelIROM"] +set line [GetLineNum ${SRC}/ifu/ifu.sv "~ITLBMissF & ~CacheableF & ~SelIROM"] coverage exclude -scope /dut/core/ifu -linerange $line-$line -item c 1 -feccondrow 6 -set line [GetLineNum ../src/ifu/ifu.sv "~ITLBMissF & CacheableF & ~SelIROM"] +set line [GetLineNum ${SRC}/ifu/ifu.sv "~ITLBMissF & CacheableF & ~SelIROM"] coverage exclude -scope /dut/core/ifu -linerange $line-$line -item c 1 -feccondrow 4 # no DTIM -set line [GetLineNum ../src/lsu/lsu.sv "assign BusRW"] +set line [GetLineNum ${SRC}/lsu/lsu.sv "assign BusRW"] coverage exclude -scope /dut/core/lsu -linerange $line-$line -item c 1 -feccondrow 4 -set line [GetLineNum ../src/lsu/lsu.sv "assign CacheRWM"] +set line [GetLineNum ${SRC}/lsu/lsu.sv "assign CacheRWM"] coverage exclude -scope /dut/core/lsu -linerange $line-$line -item c 1 -feccondrow 4 # Excluding reset and clear for impossible case in the wficountreg in privdec -set line [GetLineNum ../src/generic/flop/floprc.sv "reset \\| clear"] -coverage exclude -scope /dut/core/priv/priv/pmd/wfi/wficountreg -linerange $line-$line -item c 1 -feccondrow 2 +#set line [GetLineNum ${SRC}/generic/flop/floprc.sv "reset \\| clear"] +#coverage exclude -scope /dut/core/priv/priv/pmd/wfi/wficountreg -linerange $line-$line -item c 1 -feccondrow 2 # Exclude system reset case in ebu -set line [GetLineNum ../src/ebu/ebufsmarb.sv "BeatCounter\\("] +set line [GetLineNum ${SRC}/ebu/ebufsmarb.sv "BeatCounter\\("] coverage exclude -scope /dut/core/ebu/ebu/ebufsmarb -linerange $line-$line -item e 1 -fecexprrow 1 -set line [GetLineNum ../src/ebu/ebufsmarb.sv "FinalBeatReg\\("] +set line [GetLineNum ${SRC}/ebu/ebufsmarb.sv "FinalBeatReg\\("] coverage exclude -scope /dut/core/ebu/ebu/ebufsmarb -linerange $line-$line -item e 1 -fecexprrow 1 -set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicElse"] +set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicElse"] coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item bc 1 -set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicWait"] +set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicWait"] coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item bc 1 # The WritebackWriteback and FetchWriteback support back to back pipelined cache writebacks and fetch then # writebacks. The cache never issues these type of requests. -set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm WritebackWriteback"] +set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm WritebackWriteback"] coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item bc 2 -set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWriteback"] +set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWriteback"] coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item bc 2 # FetchWait never occurs because HREADY is never 0. -set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWait"] +set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWait"] coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item bc 1 # all of these HREADY exclusions occur because HREADY is always 1. The ram_ahb module never stalls. -set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY0"] +set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY0"] coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1 -#set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY1"] +#set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY1"] #coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1 -#set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY2"] +#set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY2"] #coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1 -set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY3"] +set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY3"] coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 4 -set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY4"] +set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY4"] coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1 coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 3 -set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY5"] +set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY5"] coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1 -set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY6"] +set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY6"] coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1 coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 5 -coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "assign CacheBusAck"] -item e 1 -fecexprrow 5 +coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "assign CacheBusAck"] -item e 1 -fecexprrow 5 -coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicElse"] -item s 1 -coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicWait"] -item s 1 +coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicElse"] -item s 1 +coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicWait"] -item s 1 # these transitions will not happen coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -ftrans CurrState DATA_PHASE->ADR_PHASE ATOMIC_READ_DATA_PHASE->ADR_PHASE ATOMIC_PHASE->ADR_PHASE @@ -399,15 +403,15 @@ coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefs coverage exclude -srcfile priorityonehot.sv # Excluding pmpadrdecs[0] coverage case for PAgePMPAdrIn being hardwired to 1 -coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker/pmp/pmpadrdecs[0] -linerange [GetLineNum ../src/mmu/pmpadrdec.sv "exclusion-tag: PAgePMPAdrIn"] -item e 1 -fecexprrow 1 -coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmp/pmpchecker/pmp/pmpadrdecs[0] -linerange [GetLineNum ../src/mmu/pmpadrdec.sv "exclusion-tag: PAgePMPAdrIn"] -item e 1 -fecexprrow 1 +coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker/pmp/pmpadrdecs[0] -linerange [GetLineNum ${SRC}/mmu/pmpadrdec.sv "exclusion-tag: PAgePMPAdrIn"] -item e 1 -fecexprrow 1 +coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmp/pmpchecker/pmp/pmpadrdecs[0] -linerange [GetLineNum ${SRC}/mmu/pmpadrdec.sv "exclusion-tag: PAgePMPAdrIn"] -item e 1 -fecexprrow 1 #################### # Privileged #################### # Instruction Misaligned never asserted because compresssed instructions are accepted -coverage exclude -scope /dut/core/priv/priv/trap -linerange [GetLineNum ../src/privileged/trap.sv "assign ExceptionM"] -item e 1 -fecexprrow 2 +coverage exclude -scope /dut/core/priv/priv/trap -linerange [GetLineNum ${SRC}/privileged/trap.sv "assign ExceptionM"] -item e 1 -fecexprrow 2 #################### # EBU diff --git a/sim/fpga-wave.do b/sim/questa/fpga-wave.do similarity index 100% rename from sim/fpga-wave.do rename to sim/questa/fpga-wave.do diff --git a/sim/run-imperas-linux.sh b/sim/questa/run-imperas-linux.sh similarity index 73% rename from sim/run-imperas-linux.sh rename to sim/questa/run-imperas-linux.sh index 86e6d1f64..7192adb81 100755 --- a/sim/run-imperas-linux.sh +++ b/sim/questa/run-imperas-linux.sh @@ -7,4 +7,4 @@ export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=100" #export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=10500000" #export OTHERFLAGS="" -vsim -do "do wally-linux-imperas.do buildroot buildroot $::env(RISCV) 0 0 0" +vsim -c -do "do questa/wally-linux-imperas.do buildroot buildroot $::env(RISCV) 0 0 0" diff --git a/sim/sim-imperas b/sim/questa/sim-imperas similarity index 100% rename from sim/sim-imperas rename to sim/questa/sim-imperas diff --git a/sim/sim-testfloat b/sim/questa/sim-testfloat similarity index 86% rename from sim/sim-testfloat rename to sim/questa/sim-testfloat index b7da7104a..ee13f17c9 100755 --- a/sim/sim-testfloat +++ b/sim/questa/sim-testfloat @@ -9,4 +9,6 @@ # sqrt - test square root # all - test everything -vsim -do "do testfloat.do fdqh_ieee_rv64gc $1" + +wsim fdqh_ieee_rv64gc $1 --tb testbench_fp --gui + diff --git a/sim/sim-testfloat-batch b/sim/questa/sim-testfloat-batch similarity index 67% rename from sim/sim-testfloat-batch rename to sim/questa/sim-testfloat-batch index 96fb0f345..52ad83c0f 100755 --- a/sim/sim-testfloat-batch +++ b/sim/questa/sim-testfloat-batch @@ -1,3 +1,4 @@ +# Run TestFloat simulation # cvtint - test integer conversion unit (fcvtint) # cvtfp - test floating-point conversion unit (fcvtfp) @@ -10,4 +11,7 @@ # sqrt - test square root # all - test everything -vsim -c -do "do testfloat.do fdqh_ieee_rv64gc $1" +#vsim -c -do "do testfloat.do fdqh_ieee_rv64gc $1" +wsim fdqh_ieee_rv64gc $1 --tb testbench_fp +#wsim fdqh_ieee_rv64gc $1 --tb testbench_fp --gui + diff --git a/sim/questa/sim-testfloat-verilator b/sim/questa/sim-testfloat-verilator new file mode 100755 index 000000000..c08484275 --- /dev/null +++ b/sim/questa/sim-testfloat-verilator @@ -0,0 +1,27 @@ +#!/usr/bin/bash + +# sim-testfloat-verilator +# David_Harris@hmc.edu 3 April 2024 +# Run Testfloat simulations with Verilator +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +# cvtint - test integer conversion unit (fcvtint) +# cvtfp - test floating-point conversion unit (fcvtfp) +# cmp - test comparison unit's LT, LE, EQ opperations (fcmp) +# add - test addition +# fma - test fma +# mul - test mult with fma +# sub - test subtraction +# div - test division +# sqrt - test square root +# all - test everything + +#vsim -c -do "do testfloat.do fdqh_ieee_rv64gc $1" + +verilator -GTEST="\"all\"" -GTEST_SIZE="\"all\"" --timescale "1ns/1ns" --timing --binary --top-module testbenchfp "-I../config/shared" "-I../config/deriv/fdqh_ieee_rv64gc" ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv --relative-includes + +#vlog +incdir+../config/deriv/$1 +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697 + +# Change TEST_SIZE to only test certain FP width +# values are QP, DP, SP, HP or all for all tests +#vsim -voptargs=+acc work.testbenchfp -GTEST=$2 -GTEST_SIZE="all" diff --git a/sim/questa/sim-wally b/sim/questa/sim-wally new file mode 100755 index 000000000..3359be0eb --- /dev/null +++ b/sim/questa/sim-wally @@ -0,0 +1,2 @@ +wsim rv64gc arch64i --gui + diff --git a/sim/questa/sim-wally-batch b/sim/questa/sim-wally-batch new file mode 100755 index 000000000..7b3c69339 --- /dev/null +++ b/sim/questa/sim-wally-batch @@ -0,0 +1 @@ +wsim rv64gc arch64i diff --git a/sim/wally-imperas-cov.do b/sim/questa/wally-imperas-cov.do similarity index 100% rename from sim/wally-imperas-cov.do rename to sim/questa/wally-imperas-cov.do diff --git a/sim/wally-imperas-no-idv.do b/sim/questa/wally-imperas-no-idv.do similarity index 100% rename from sim/wally-imperas-no-idv.do rename to sim/questa/wally-imperas-no-idv.do diff --git a/sim/wally-imperas.do b/sim/questa/wally-imperas.do similarity index 100% rename from sim/wally-imperas.do rename to sim/questa/wally-imperas.do diff --git a/sim/wally-linux-imperas.do b/sim/questa/wally-linux-imperas.do similarity index 100% rename from sim/wally-linux-imperas.do rename to sim/questa/wally-linux-imperas.do diff --git a/sim/questa/wally.do b/sim/questa/wally.do new file mode 100644 index 000000000..184da43d0 --- /dev/null +++ b/sim/questa/wally.do @@ -0,0 +1,141 @@ +# wally-batch.do +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Modification by Oklahoma State University & Harvey Mudd College +# Use with Testbench +# James Stine, 2008; David Harris 2021 +# Go Cowboys!!!!!! +# +# Takes 1:10 to run RV64IC tests using gui + +# Usage: do wally-batch.do [-coverage] [+acc] [any number of +value] [any number of -G VAR=VAL] +# Example: do wally-batch.do rv64gc arch64i testbench + +# Use this wally-batch.do file to run this example. +# Either bring up ModelSim and type the following at the "ModelSim>" prompt: +# do wally-batch.do +# or, to run from a shell, type the following at the shell prompt: +# vsim -do wally-batch.do -c +# (omit the "-c" to see the GUI while running from the shell) + +onbreak {resume} + +set CFG ${1} +set TESTSUITE ${2} +set TESTBENCH ${3} +set WKDIR wkdir/${CFG}_${TESTSUITE} +set WALLY $::env(WALLY) +set CONFIG ${WALLY}/config +set SRC ${WALLY}/src +set TB ${WALLY}/testbench + +# create library +if [file exists ${WKDIR}] { + vdel -lib ${WKDIR} -all +} +vlib ${WKDIR} +# Create directory for coverage data +mkdir -p cov + +set coverage 0 +set CoverageVoptArg "" +set CoverageVsimArg "" + +# Need to be able to pass arguments to vopt. Unforunately argv does not work because +# it takes on different values if vsim and the do file are called from the command line or +# if the do file isd called from questa sim directly. This chunk of code uses the $4 through $n +# variables and compacts into a single list for passing to vopt. +set tbArgs "" +set from 4 +set step 1 +set lst {} +set GUI 0 +set PlusArgs {} +set ParamArgs {} +set accFlag "" +for {set i 0} true {incr i} { + set x [expr {$i*$step + $from}] + if {$x > $argc} break + set arg [expr "$$x"] + lappend lst $arg +} + +if {$argc >= 3} { + if {[lindex $lst [expr { [llength $lst] -1 } ]] eq "+acc"} { + set GUI 1 + set accFlag "+acc" + set tbArgs [lrange $lst 0 end-1] + } else { + set tbArgs $lst + } + set tbArgsLst [split $lst " "] + # separate the +args from the -G parameters + foreach otherArg $tbArgsLst { + if {[string index $otherArg 0] eq "+"} { + lappend PlusArgs $otherArg + } else { + lappend ParamArgs $otherArg + } + } + #echo "PlusArgs" + #echo $PlusArgs + #echo "ParamArgs" + #echo $ParamArgs + #echo "accFlag" + #echo $accFlag + + #if {$3 eq "-coverage" || ($argc >= 7 && $7 eq "-coverage")} { + # set coverage 1 + # set CoverageVoptArg "+cover=sbecf" + # set CoverageVsimArg "-coverage" + #} elseif {$3 eq "tbArgs"} { + # set tbArgs $lst + # puts $tbArgs + #} +} + +# compile source files +# suppress spurious warnngs about +# "Extra checking for conflicts with always_comb done at vopt time" +# because vsim will run vopt + +vlog -lint -work ${WKDIR} +incdir+${CONFIG}/$1 +incdir+${CONFIG}/deriv/$1 +incdir+${CONFIG}/shared ${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 + +# start and run simulation +# remove +acc flag for faster sim during regressions if there is no need to access internal signals +vopt $accFlag wkdir/${CFG}_${TESTSUITE}.${TESTBENCH} -work ${WKDIR} ${tbArgs} -o testbenchopt ${CoverageVoptArg} +# *** tbArgs producees a warning that TEST not found in design when running sim-testfloat-batch. Need to separate -G and + arguments to pass separately to vopt and vsim +vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} ${PlusArgs} -fatal 7 -suppress 3829 ${CoverageVsimArg} + +# vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829 +# power add generates the logging necessary for said generation. +# power add -r /dut/core/* +if { ${GUI} } { + add log -recursive /* + if { ${TESTBENCH} eq "testbench_fp" } { + do wave-fpu.do + } else { + do wave.do + } +} + +run -all +# power off -r /dut/core/* + + +if {$coverage} { + set UCDB cov/${CFG}_${TESTSUITE}.ucdb + echo "Saving coverage to ${UCDB}" + do coverage-exclusions-rv64gc.do # beware: this assumes testing the rv64gc configuration + coverage save -instance /testbench/dut/core ${UCDB} +} + +# These aren't doing anything helpful +#profile report -calltree -file wally-calltree.rpt -cutoff 2 +#power report -all -bsaif power.saif + +# terminate simulation unless we need to keep the GUI running +if { ${GUI} == 0} { + quit +} + diff --git a/sim/questa/wave-fpu.do b/sim/questa/wave-fpu.do new file mode 100644 index 000000000..f4da1e8a2 --- /dev/null +++ b/sim/questa/wave-fpu.do @@ -0,0 +1,30 @@ + +add wave -noupdate /testbench_fp/clk +add wave -noupdate -radix decimal /testbench_fp/VectorNum +add wave -noupdate /testbench_fp/FrmNum +add wave -noupdate /testbench_fp/X +add wave -noupdate /testbench_fp/Y +add wave -noupdate /testbench_fp/Z +add wave -noupdate /testbench_fp/Res +add wave -noupdate /testbench_fp/Ans +add wave -noupdate /testbench_fp/reset +add wave -noupdate /testbench_fp/DivStart +add wave -noupdate /testbench_fp/FDivBusyE +add wave -noupdate /testbench_fp/CheckNow +add wave -noupdate /testbench_fp/DivDone +add wave -noupdate /testbench_fp/ResMatch +add wave -noupdate /testbench_fp/FlagMatch +add wave -noupdate /testbench_fp/CheckNow +add wave -noupdate /testbench_fp/NaNGood +add wave -group {PostProc} -noupdate /testbench_fp/postprocess/* +add wave -group {PostProc} -noupdate /testbench_fp/postprocess/specialcase/* +add wave -group {PostProc} -noupdate /testbench_fp/postprocess/flags/* +add wave -group {PostProc} -noupdate /testbench_fp/postprocess/normshift/* +add wave -group {PostProc} -noupdate /testbench_fp/postprocess/shiftcorrection/* +add wave -group {PostProc} -noupdate /testbench_fp/postprocess/resultsign/* +add wave -group {PostProc} -noupdate /testbench_fp/postprocess/round/* +add wave -group {PostProc} -noupdate /testbench_fp/postprocess/fmashiftcalc/* +add wave -group {PostProc} -noupdate /testbench_fp/postprocess/divshiftcalc/* +add wave -group {PostProc} -noupdate /testbench_fp/postprocess/cvtshiftcalc/* +add wave -group {Testbench} -noupdate /testbench_fp/* +add wave -group {Testbench} -noupdate /testbench_fp/readvectors/* diff --git a/sim/wave.do b/sim/questa/wave.do similarity index 91% rename from sim/wave.do rename to sim/questa/wave.do index 7c8eae184..bb6b1d54b 100644 --- a/sim/wave.do +++ b/sim/questa/wave.do @@ -6,43 +6,43 @@ add wave -noupdate /testbench/reset add wave -noupdate /testbench/memfilename add wave -noupdate /testbench/dut/core/SATP_REGW add wave -noupdate /testbench/dut/core/InstrValidM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM -add wave -noupdate -expand -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ieu/c/LoadStallD -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/BPWrongE -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ieu/c/MDUStallD -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/pmd/WFITimeoutM -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW -add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallF -add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallD -add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallE -add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallM -add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallW -add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/PendingIntsM -add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/InstrValidM -add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/ValidIntsM -add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/hzu/WFIInterruptedM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM +add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ieu/c/LoadStallD +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPWrongE +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ieu/c/MDUStallD +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/pmd/WFITimeoutM +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW +add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallF +add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallD +add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallE +add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallM +add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallW +add wave -noupdate -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/PendingIntsM +add wave -noupdate -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/InstrValidM +add wave -noupdate -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/ValidIntsM +add wave -noupdate -group HDU -group interrupts /testbench/dut/core/hzu/WFIInterruptedM add wave -noupdate -group {instruction pipeline} /testbench/InstrFName add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD @@ -205,7 +205,6 @@ add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/SrcAE add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/SrcBE add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ALUResultE add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ResultW -add wave -noupdate -expand -group {Memory Stage} /testbench/FunctionName/FunctionName/FunctionName add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrValidM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM @@ -407,29 +406,29 @@ add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dm add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk -add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextWalkerState -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/PBMTFaultM +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk +add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextWalkerState +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE +add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF +add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM +add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF +add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM +add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWFaultM +add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM +add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF +add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM +add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM +add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault +add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/PBMTFaultM add wave -noupdate -group {WriteBack stage} /testbench/InstrW add wave -noupdate -group {WriteBack stage} /testbench/InstrWName add wave -noupdate -group {WriteBack stage} /testbench/dut/core/priv/priv/pmd/wfiW @@ -678,4 +677,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {11566 ns} {11760 ns} +WaveRestoreZoom {0 ns} {284634 ns} diff --git a/sim/regression-wally b/sim/regression-wally deleted file mode 100755 index f58c8bdfe..000000000 --- a/sim/regression-wally +++ /dev/null @@ -1,471 +0,0 @@ -#!/usr/bin/python3 -################################## -# -# regression-wally -# David_Harris@Hmc.edu 25 January 2021 -# Modified by Jarred Allen -# -# Run a regression with multiple configurations in parallel and exit with -# non-zero status code if an error happened, as well as printing human-readable -# output. -# -################################## -import sys,os,shutil -import multiprocessing - - - -class bcolors: - HEADER = '\033[95m' - OKBLUE = '\033[94m' - OKCYAN = '\033[96m' - OKGREEN = '\033[92m' - WARNING = '\033[93m' - FAIL = '\033[91m' - ENDC = '\033[0m' - BOLD = '\033[1m' - UNDERLINE = '\033[4m' - -from collections import namedtuple -regressionDir = os.path.dirname(os.path.abspath(__file__)) -os.chdir(regressionDir) - -coverage = '-coverage' in sys.argv -fp = '-fp' in sys.argv -nightly = '-nightly' in sys.argv -softfloat = '-softfloat' in sys.argv - -TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr']) -# name: the name of this test configuration (used in printing human-readable -# output and picking logfile names) -# cmd: the command to run to test (should include the logfile as '{}', and -# the command needs to write to that file) -# grepstr: the string to grep through the log file for. The test succeeds iff -# grep finds that string in the logfile (is used by grep, so it may -# be any pattern grep accepts, see `man 1 grep` for more info). - -# edit this list to add more test cases -if (nightly): - nightMode = "-nightly"; - configs = [] -else: - nightMode = ""; - configs = [ - TestCase( - name="lints", - variant="all", - cmd="./lint-wally " + nightMode + " | tee {}", - grepstr="lints run with no errors or warnings" - ) - ] - -def getBuildrootTC(boot): - INSTR_LIMIT = 1000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM - MAX_EXPECTED = 246000000 # *** TODO: replace this with a search for the login prompt. - if boot: - name="buildrootboot" - BRcmd="vsim > {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < XLEN -# ["nodcache_rv32gc", ["ahb32"]], -# ["nocache_rv32gc", ["ahb32"]], - ["noicache_rv64gc", ["ahb64"]], - ["nodcache_rv64gc", ["ahb64"]], - ["nocache_rv64gc", ["ahb64"]], - - ### add misaligned tests - - ["div_2_1_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], - ["div_2_1i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], - ["div_2_2_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], - ["div_2_2i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], - ["div_2_4_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], - ["div_2_4i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], - ["div_4_1_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], - ["div_4_1i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], - ["div_4_2_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], - ["div_4_2i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], - ["div_4_4_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], - ["div_4_4i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], - ["div_2_1_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], - ["div_2_1i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], - ["div_2_2_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], - ["div_2_2i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], - ["div_2_4_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], - ["div_2_4i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], - ["div_4_1_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], - ["div_4_1i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], - ["div_4_2_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], - ["div_4_2i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], - ["div_4_4_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], - ["div_4_4i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], - - ### branch predictor simulation - - # ["bpred_TWOBIT_6_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - # ["bpred_TWOBIT_8_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - # ["bpred_TWOBIT_10_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - # ["bpred_TWOBIT_12_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - # ["bpred_TWOBIT_14_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - # ["bpred_TWOBIT_16_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - # ["bpred_TWOBIT_6_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - # ["bpred_TWOBIT_8_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - # ["bpred_TWOBIT_10_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - # ["bpred_TWOBIT_12_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - # ["bpred_TWOBIT_14_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - # ["bpred_TWOBIT_16_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - - # ["bpred_GSHARE_6_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - # ["bpred_GSHARE_6_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - # ["bpred_GSHARE_8_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - # ["bpred_GSHARE_8_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - # ["bpred_GSHARE_10_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - # ["bpred_GSHARE_10_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - # ["bpred_GSHARE_12_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - # ["bpred_GSHARE_12_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - # ["bpred_GSHARE_14_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - # ["bpred_GSHARE_14_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - # ["bpred_GSHARE_16_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - # ["bpred_GSHARE_16_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - - # # btb - # ["bpred_GSHARE_10_16_6_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - # ["bpred_GSHARE_10_16_6_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - # ["bpred_GSHARE_10_16_8_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - # ["bpred_GSHARE_10_16_8_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - # ["bpred_GSHARE_10_16_12_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - # ["bpred_GSHARE_10_16_12_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - - # # ras - # ["bpred_GSHARE_10_2_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - # ["bpred_GSHARE_10_2_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - # ["bpred_GSHARE_10_3_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - # ["bpred_GSHARE_10_3_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - # ["bpred_GSHARE_10_4_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - # ["bpred_GSHARE_10_4_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - # ["bpred_GSHARE_10_6_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - # ["bpred_GSHARE_10_6_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - # ["bpred_GSHARE_10_10_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - # ["bpred_GSHARE_10_10_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - -# enable floating-point tests when lint is fixed - ["f_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma"]], - ["fh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32zfh", "arch32zfh_divsqrt"]], - ["fdh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]], - ["fdq_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32i"]], - ["fdqh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt", "arch32i"]], - ["f_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma"]], - ["fh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64zfh", "arch64zfh_divsqrt"]], # hanging 1/31/24 dh; try again when lint is fixed - ["fdh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]], - ["fdq_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64i"]], - ["fdqh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt", "arch64i", "wally64q"]], - - - ] - for test in derivconfigtests: - config = test[0]; - tests = test[1]; - if(len(test) >= 4 and test[2] == "configOptions"): - configOptions = test[3] - cmdPrefix = "vsim > {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < /dev/null" % (text, logfile) - return os.system(grepcmd) == 0 - -def run_test_case(config): - """Run the given test case, and return 0 if the test suceeds and 1 if it fails""" - logname = "logs/"+config.variant+"_"+config.name+".log" - cmd = config.cmd.format(logname) -# print(cmd) - os.chdir(regressionDir) - os.system(cmd) - if search_log_for_text(config.grepstr, logname): - print(f"{bcolors.OKGREEN}%s_%s: Success{bcolors.ENDC}" % (config.variant, config.name)) - return 0 - else: - print(f"{bcolors.FAIL}%s_%s: Failures detected in output{bcolors.ENDC}" % (config.variant, config.name)) - print(" Check %s" % logname) - return 1 - -def main(): - """Run the tests and count the failures""" - global configs, coverage - try: - os.chdir(regressionDir) - os.mkdir("logs") - except: - pass - try: - shutil.rmtree("wkdir") - except: - pass - finally: - os.mkdir("wkdir") - - if '-makeTests' in sys.argv: - os.chdir(regressionDir) - os.system('./make-tests.sh | tee ./logs/make-tests.log') - - if '-all' in sys.argv: - TIMEOUT_DUR = 30*7200 # seconds - configs.append(getBuildrootTC(boot=True)) - elif '-buildroot' in sys.argv: - TIMEOUT_DUR = 30*7200 # seconds - configs=[getBuildrootTC(boot=True)] - elif '-coverage' in sys.argv: - TIMEOUT_DUR = 20*60 # seconds - # Presently don't run buildroot because it has a different config and can't be merged with the rv64gc coverage. - # Also it is slow to run. - # configs.append(getBuildrootTC(boot=False)) - os.system('rm -f cov/*.ucdb') - elif '-nightly' in sys.argv: - TIMEOUT_DUR = 60*1440 # 1 day - configs.append(getBuildrootTC(boot=False)) - elif '-softfloat' in sys.argv: - TIMEOUT_DUR = 60*60 # seconds - else: - TIMEOUT_DUR = 10*60 # seconds - configs.append(getBuildrootTC(boot=False)) - - # Scale the number of concurrent processes to the number of test cases, but - # max out at a limited number of concurrent processes to not overwhelm the system - with Pool(processes=min(len(configs),multiprocessing.cpu_count())) as pool: - num_fail = 0 - results = {} - for config in configs: - results[config] = pool.apply_async(run_test_case,(config,)) - for (config,result) in results.items(): - try: - num_fail+=result.get(timeout=TIMEOUT_DUR) - except TimeoutError: - num_fail+=1 - print(f"{bcolors.FAIL}%s_%s: Timeout - runtime exceeded %d seconds{bcolors.ENDC}" % (config.variant, config.name, TIMEOUT_DUR)) - - # Coverage report - if coverage: - os.system('make coverage') - # Count the number of failures - if num_fail: - print(f"{bcolors.FAIL}Regression failed with %s failed configurations{bcolors.ENDC}" % num_fail) - else: - print(f"{bcolors.OKGREEN}SUCCESS! All tests ran without failures{bcolors.ENDC}") - return num_fail - -if __name__ == '__main__': - exit(main()) diff --git a/sim/sim-buildroot b/sim/sim-buildroot deleted file mode 100755 index 530e33386..000000000 --- a/sim/sim-buildroot +++ /dev/null @@ -1,33 +0,0 @@ -#!/bin/bash - -# Defaults -INSTR_LIMIT=0 -INSTR_WAVEON=1 -CHECKPOINT=0 - -# Arg Parsing -for i in "$@"; do - case $i in - --INSTR_LIMIT=*) - INSTR_LIMIT="${i#*=}" - shift # past argument=value - ;; - --INSTR_WAVEON=*) - INSTR_WAVEON="${i#*=}" - shift # past argument=value - ;; - --CHECKPOINT=*) - CHECKPOINT="${i#*=}" - shift # past argument=value - ;; - *) - # unknown option - ;; - esac -done - -echo "INSTR_LIMIT = ${INSTR_LIMIT}" -echo "INSTR_WAVEON = ${INSTR_WAVEON}" -echo "CHECKPOINT = ${CHECKPOINT}" - -vsim -do "do ./wally.do buildroot buildroot $RISCV $INSTR_LIMIT $INSTR_WAVEON $CHECKPOINT" diff --git a/sim/sim-buildroot-batch b/sim/sim-buildroot-batch deleted file mode 100755 index 81a6fac1e..000000000 --- a/sim/sim-buildroot-batch +++ /dev/null @@ -1,36 +0,0 @@ -#!/bin/bash - -# Defaults -INSTR_LIMIT=0 -INSTR_WAVEON=1 -CHECKPOINT=0 - -# Arg Parsing -for i in "$@"; do - case $i in - --INSTR_LIMIT=*) - INSTR_LIMIT="${i#*=}" - shift # past argument=value - ;; - --INSTR_WAVEON=*) - INSTR_WAVEON="${i#*=}" - shift # past argument=value - ;; - --CHECKPOINT=*) - CHECKPOINT="${i#*=}" - shift # past argument=value - ;; - *) - # unknown option - ;; - esac -done - -echo "INSTR_LIMIT = ${INSTR_LIMIT}" -echo "INSTR_WAVEON = ${INSTR_WAVEON}" -echo "CHECKPOINT = ${CHECKPOINT}" - -# *** change config from buildroot to rv64gc -vsim -c < gmon_$(WALLYCONF).log + verilator_profcfunc gmon_$(WALLYCONF).log > gmon_$(WALLYCONF).log2 + mkdir -p $(WORKING_DIR)/logs_profiling + mv gmon_$(WALLYCONF)* $(WORKING_DIR)/logs_profiling + echo "Please check $(WORKING_DIR)/logs_profiling/gmon_$(WALLYCONF)* for logs and output files." + +run: obj_dir_non_profiling/Vtestbench_$(WALLYCONF) + mkdir -p $(WORKING_DIR)/logs + time $(WORKING_DIR)/obj_dir_non_profiling/Vtestbench_$(WALLYCONF) +TEST=$(TEST) 2>&1 > $(WORKING_DIR)/logs/$(WALLYCONF)_$(TEST).log + echo "Please check $(WORKING_DIR)/logs/$(WALLYCONF)_$(TEST).log for logs and output files." + +obj_dir_non_profiling/Vtestbench_$(WALLYCONF): $(SOURCE) + mkdir -p obj_dir_non_profiling + time verilator \ + --Mdir obj_dir_non_profiling -o Vtestbench_$(WALLYCONF) \ + -cc --binary \ + $(OPT) $(PARAMS) $(NONPROF) \ + --timescale "1ns/1ns" --timing --top-module testbench --relative-includes \ + "-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" \ + wrapper.c \ + ${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv + +obj_dir_profiling/Vtestbench_$(WALLYCONF): $(SOURCE) + mkdir -p obj_dir_profiling + time verilator \ + --Mdir obj_dir_profiling -o Vtestbench_$(WALLYCONF) \ + -cc --binary \ + --prof-cfuncs $(OPT) $(PARAMS) \ + --timescale "1ns/1ns" --timing --top-module testbench --relative-includes \ + wrapper.c \ + "-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" ${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv + +questa: + time vsim -c -do "do ${WALLY}/sim/wally-batch.do $(WALLYCONF) $(TEST)" + +clean: + rm -rf $(WORKING_DIR)/obj_dir_non_profiling $(WORKING_DIR)/obj_dir_profiling $(WORKING_DIR)/logs $(WORKING_DIR)/logs_profiling \ No newline at end of file diff --git a/sim/verilator/README.md b/sim/verilator/README.md new file mode 100644 index 000000000..5fd1b57b3 --- /dev/null +++ b/sim/verilator/README.md @@ -0,0 +1,32 @@ +# Simulation with Verilator + +Different executables will be built for different architecture configurations, e.g., rv64gc, rv32i. A executable can run all the test suites that it can run with `+TEST=`. + +Demand: + +- Avoid unnecessary compilation by sharing the same executable for a specific configuration + - executables are stored in `obj_dir_non_profiling` and `obj_dir_profiling` correspondingly +- Wsim should support `-s verilator` option and run simulation with Verilator. + +## Folder Structure + +This folder contains the following files that help the simulation of Wally with Verilator: + +- Makefile: simplify the usage with Verialtor +- executables + - `obj_dir_non_profiling`: non-profiling executables for different configurations + - `obj_dir_profiling`: profiling executables for different configurations +- logs in `logs` and `logs_profiling` correspondingly +- [NOT WORKING] `logs`: contains all the logs + +## Examples + +```shell +# non-profiling mode +make WALLYCONF=rv64gc TEST=arch64i run +# profiling mode +make WALLYCONF=rv64gc TEST=arch64i profile + +# remove all the temporary files, including executables and logs +make clean +``` \ No newline at end of file diff --git a/sim/verilator/wrapper.c b/sim/verilator/wrapper.c new file mode 100644 index 000000000..6589a3848 --- /dev/null +++ b/sim/verilator/wrapper.c @@ -0,0 +1,7 @@ +#include + +#include "Vtestbench__Dpi.h" + +const char *getenvval(const char *pszName) { + return ((const char *) getenv(pszName)); +} \ No newline at end of file diff --git a/sim/wally-batch.do b/sim/wally-batch.do deleted file mode 100644 index 4afe42202..000000000 --- a/sim/wally-batch.do +++ /dev/null @@ -1,92 +0,0 @@ -# wally-batch.do -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Modification by Oklahoma State University & Harvey Mudd College -# Use with Testbench -# James Stine, 2008; David Harris 2021 -# Go Cowboys!!!!!! -# -# Takes 1:10 to run RV64IC tests using gui - -# Usage: do wally-batch.do -# Example: do wally-batch.do rv32imc imperas-32i - -# Use this wally-batch.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do wally-batch.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do wally-batch.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists wkdir/work_${1}_${2}] { - vdel -lib wkdir/work_${1}_${2} -all -} -vlib wkdir/work_${1}_${2} -# Create directory for coverage data -mkdir -p cov - -set coverage 0 -set CoverageVoptArg "" -set CoverageVsimArg "" - -# Need to be able to pass arguments to vopt. Unforunately argv does not work because -# it takes on different values if vsim and the do file are called from the command line or -# if the do file isd called from questa sim directly. This chunk of code uses the $4 through $n -# variables and compacts into a single list for passing to vopt. -set configOptions "" -set from 4 -set step 1 -set lst {} -for {set i 0} true {incr i} { - set x [expr {$i*$step + $from}] - if {$x > $argc} break - set arg [expr "$$x"] - lappend lst $arg -} - -if {$argc >= 3} { - if {$3 eq "-coverage" || ($argc >= 7 && $7 eq "-coverage")} { - set coverage 1 - set CoverageVoptArg "+cover=sbecf" - set CoverageVsimArg "-coverage" - } elseif {$3 eq "configOptions"} { - set configOptions $lst - puts $configOptions - } -} - -# compile source files -# suppress spurious warnngs about -# "Extra checking for conflicts with always_comb done at vopt time" -# because vsim will run vopt - -# default to config/rv64ic, but allow this to be overridden at the command line. For example: -# do wally-pipelined-batch.do ../config/rv32imc rv32imc - -vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 - -# start and run simulation -# remove +acc flag for faster sim during regressions if there is no need to access internal signals -vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 ${configOptions} -o testbenchopt ${CoverageVoptArg} -vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829 ${CoverageVsimArg} - -# vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829 -# power add generates the logging necessary for said generation. -# power add -r /dut/core/* -run -all -# power off -r /dut/core/* - - -if {$coverage} { - echo "Saving coverage to ${1}_${2}.ucdb" - do coverage-exclusions-rv64gc.do # beware: this assumes testing the rv64gc configuration - coverage save -instance /testbench/dut/core cov/${1}_${2}.ucdb -} - -# These aren't doing anything helpful -#profile report -calltree -file wally-calltree.rpt -cutoff 2 -#power report -all -bsaif power.saif -quit diff --git a/sim/wally.do b/sim/wally.do deleted file mode 100644 index 430146d39..000000000 --- a/sim/wally.do +++ /dev/null @@ -1,120 +0,0 @@ -# wally.do -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Modification by Oklahoma State University & Harvey Mudd College -# Use with Testbench -# James Stine, 2008; David Harris 2021 -# Go Cowboys!!!!!! -# -# Takes 1:10 to run RV64IC tests using gui - -# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m" - -# Use this wally-pipelined.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do wally.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do wally.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -# suppress spurious warnngs about -# "Extra checking for conflicts with always_comb done at vopt time" -# because vsim will run vopt - -# start and run simulation -# remove +acc flag for faster sim during regressions if there is no need to access internal signals -if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { - vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 - # start and run simulation - vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G NO_SPOOFING=0 -o testbenchopt - vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7 - - #-- Run the Simulation - #run -all - add log -recursive /* - do linux-wave.do - run -all - - exec ./slack-notifier/slack-notifier.py - -} elseif {$2 eq "buildroot-no-trace"} { - vlog -lint -work work_${1}_${2} +incdir+../config/deriv/$1 +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 - # start and run simulation - vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_SPOOFING=1 -o testbenchopt - vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7 - - #-- Run the Simulation - echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" - echo "Don't forget to change DEBUG_LEVEL = 0." - echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" - #run 100 ns - #force -deposit testbench/dut/core/priv/priv/csr/csri/IE_REGW 16'h2aa - #force -deposit testbench/dut/uncore/uncore/clint/clint/MTIMECMP 64'h1000 - run 14000 ms - #add log -recursive /* - #do linux-wave.do - #run -all - - exec ./slack-notifier/slack-notifier.py - -} elseif {$2 eq "fpga"} { - echo "hello" - vlog -work work +incdir+../config/fpga +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/sdc/*.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv ../../fpga/sim/*.sv -suppress 8852,12070,3084,3829,2583,7063,13286 - vopt +acc work.testbench -G TEST=$2 -G DEBUG=0 -o workopt - vsim workopt +nowarn3829 -fatal 7 - - do fpga-wave.do - add log -r /* - run 20 ms - -} else { - vlog +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 - vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt - - vsim workopt +nowarn3829 -fatal 7 - - view wave - #-- display input and output signals as hexidecimal values - #do ./wave-dos/peripheral-waves.do - add log -recursive /* - do wave.do - #do wave-bus.do - - # power add generates the logging necessary for saif generation. - #power add -r /dut/core/* - #-- Run the Simulation - - run -all - #power off -r /dut/core/* - #power report -all -bsaif power.saif - noview ../testbench/testbench.sv - view wave -} - - - -#elseif {$2 eq "buildroot-no-trace""} { -# vlog -lint -work work_${1}_${2} +incdir+../config/deriv/$1 +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 - # start and run simulation -# vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=470350800 -G INSTR_WAVEON=470350800 -G CHECKPOINT=470350800 -G DEBUG_TRACE=0 -o testbenchopt -# vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829 - - #-- Run the Simulation -# run 100 ns -# force -deposit testbench/dut/core/priv/priv/csr/csri/IE_REGW 16'h2aa -# force -deposit testbench/dut/uncore/uncore/clint/clint/MTIMECMP 64'h1000 -# add log -recursive /* -# do linux-wave.do -# run -all - -# exec ./slack-notifier/slack-notifier.py -#} diff --git a/sim/wave-all.do b/sim/wave-all.do deleted file mode 100644 index f151680f3..000000000 --- a/sim/wave-all.do +++ /dev/null @@ -1,1606 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate /testbench/clk -add wave -noupdate /testbench/reset -add wave -noupdate /testbench/memfilename -add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/PCE -add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName -add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/InstrE -add wave -noupdate -divider -add wave -noupdate /testbench/dut/core/ebu/ebu/IReadF -add wave -noupdate /testbench/dut/core/DataStall -add wave -noupdate /testbench/dut/core/InstrStall -add wave -noupdate /testbench/dut/core/StallF -add wave -noupdate /testbench/dut/core/StallD -add wave -noupdate /testbench/dut/core/FlushD -add wave -noupdate /testbench/dut/core/FlushE -add wave -noupdate /testbench/dut/core/FlushM -add wave -noupdate /testbench/dut/core/FlushW -add wave -noupdate -divider -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCF -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrF -add wave -noupdate /testbench/InstrFName -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrD -add wave -noupdate /testbench/InstrDName -add wave -noupdate -divider -add wave -noupdate -expand -group {Decode Stage} /testbench/dut/core/ieu/InstrD -add wave -noupdate -expand -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD -add wave -noupdate -expand -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D -add wave -noupdate -expand -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D -add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/rf -add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/a1 -add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/a2 -add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/a3 -add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/rd1 -add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/rd2 -add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/wd3 -add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/we3 -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcAE -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcBE -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultE -add wave -noupdate /testbench/dut/core/ieu/dp/PCSrcE -add wave -noupdate -divider -add wave -noupdate /testbench/InstrMName -add wave -noupdate /testbench/dut/uncore/uncore/ram/memwrite -add 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/testbench/dut/core/ifu/UnalignedPCNextF -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCNextF -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/misaligned -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/BranchMisalignedFaultE -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/BranchMisalignedFaultM -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/TrapMisalignedFaultM -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/StallExceptResolveBranchesF -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PrivilegedChangePCM -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/IllegalCompInstrD -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPlusUpperF -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPlus2or4F -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCD -add wave -noupdate -radix hexadecimal /testbench/PCW -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCLinkD -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCLinkE -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCLinkM -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/CompressedF -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrRawD -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrE -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/nop -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/pcmux/d0 -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/pcmux/d1 -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/pcmux/d2 -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/pcmux/s -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/pcmux/y -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/pcreg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/pcreg/load -add wave -noupdate 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hexadecimal /testbench/dut/core/ifu/decomp/immCILUI -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/immSH -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/op -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrMisalginedReg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrMisalginedReg/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrMisalginedReg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrMisalginedReg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrMisalignedAdrReg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrMisalignedAdrReg/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrMisalignedAdrReg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrMisalignedAdrReg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrEReg/clk -add wave -noupdate -radix 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wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/InstrValidM -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/PrivilegedD -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/PrivilegedE -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/ControlsD -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/aluc3D -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/subD -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/sraD -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/sltD -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/sltuD -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/BranchTakenE -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/zeroE -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/ltE -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/ltuE -add wave -noupdate -radix hexadecimal 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/testbench/dut/core/ieu/dp/ALUControlE -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUSrcAE -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUSrcBE -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/TargetSrcE -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/PCE -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/FlagsE -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/PCTargetE -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/FlushM -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/Funct3M -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/CSRReadValW -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ReadDataW -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RetM -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/TrapM -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcAM 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/testbench/dut/core/ieu/dp/Rs2EReg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/Rs2EReg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdEReg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdEReg/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdEReg/clear -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdEReg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdEReg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/faemux/d0 -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/faemux/d1 -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/faemux/d2 -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/faemux/s -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/faemux/y -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/fbemux/d0 -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/fbemux/d1 -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/fbemux/d2 -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/fbemux/s -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/fbemux/y -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/srcamux/d0 -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/srcamux/d1 -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/srcamux/s -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/srcamux/y -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/srcbmux/d0 -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/srcbmux/d1 -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/srcbmux/s -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/srcbmux/y -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/A -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/B -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/ALUControl -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/Result -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/FlagsE -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/sh/a -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/sh/amt -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/sh/right -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/sh/arith -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/sh/w64 -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/sh/y -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/sh/genblk1/z -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/sh/genblk1/zshift -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/sh/genblk1/ylower -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/sh/genblk1/yupper -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/sh/genblk1/offset -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/sh/genblk1/amt6 -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/targetsrcmux/d0 -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/targetsrcmux/d1 -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/targetsrcmux/s -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/targetsrcmux/y -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcAMReg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcAMReg/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcAMReg/clear -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcAMReg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcAMReg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultMReg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultMReg/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultMReg/clear -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultMReg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultMReg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/WriteDataMReg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/WriteDataMReg/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/WriteDataMReg/clear -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/WriteDataMReg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/WriteDataMReg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdMEg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdMEg/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdMEg/clear -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdMEg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdMEg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultWReg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultWReg/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultWReg/clear -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultWReg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultWReg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdWEg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdWEg/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdWEg/clear -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdWEg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdWEg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/resultmux/d0 -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/resultmux/d1 -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/resultmux/d2 -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/resultmux/d3 -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/resultmux/s -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/resultmux/y -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/Rs1D -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/Rs2D -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/Rs1E -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/Rs2E -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/RdE -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/RdM -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/RdW -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/MemReadE -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/RegWriteM -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/RegWriteW -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/ForwardAE -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/ForwardBE -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/LoadStallD -add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/FlushW -add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/DataStall -add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/MemRWM -add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/MemAdrM -add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/Funct3M -add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/ReadDataM -add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/WriteDataM -add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/MemPAdrM -add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/MemRWAlignedM -add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/DataMisalignedM -add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/MemAckW -add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/ReadDataW -add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/DataAccessFaultM -add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/LoadMisalignedFaultM -add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/LoadAccessFaultM -add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/StoreAmoMisalignedFaultM -add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/StoreAmoAccessFaultM -add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/ReadDataWReg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/ReadDataWReg/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/ReadDataWReg/clear -add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/ReadDataWReg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/ReadDataWReg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/UnsignedLoadM -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/InstrPAdrF -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/IReadF -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/IRData -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/MemPAdrM -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/DReadM -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/DWriteM -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/WriteDataM -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/DSizeM -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/DRData -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HRDATA -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HREADY -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HRESP -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HCLK -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HRESETn -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HADDR -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HWDATA -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HWRITE -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HSIZE -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HBURST -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HPROT -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HTRANS -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HMASTLOCK -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/InstrAckD -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/MemAckW -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/GrantData -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/ISize -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HRDATAMasked -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/IReady -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/DReady -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/HRDATA -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/HADDR -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/UnsignedLoadM -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/HSIZE -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/HRDATAMasked -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/ByteM -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/HalfwordM -add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/genblk1/WordM -add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/PCSrcE -add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/CSRWritePendingDEM -add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/RetM -add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/TrapM -add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/LoadStallD -add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/InstrStall -add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/DataStall -add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/StallF -add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/StallD -add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/FlushD -add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/FlushE -add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/FlushM -add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/FlushW -add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/BranchFlushDE -add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/StallDCause -add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/StallFCause -add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/StallWCause -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/FlushW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/CSRWriteM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/SrcAM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/InstrM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/PCM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/CSRReadValW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/PrivilegedNextPCM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/RetM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/TrapM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/InstrValidM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/FRegWriteM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/LoadStallD -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/PrivilegedM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/InstrMisalignedFaultM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/InstrAccessFaultF -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/IllegalIEUInstrFaultD -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/LoadMisalignedFaultM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/LoadAccessFaultM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/StoreAmoMisalignedFaultM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/StoreAmoAccessFaultM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/TimerIntM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/ExtIntM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/SwIntM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/InstrMisalignedAdrM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/MemAdrM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/SetFflagsM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/FRM_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/FlushD -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/FlushE -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/FlushM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/StallD -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/NextPrivilegeModeM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/PrivilegeModeW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/CauseM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/NextFaultMtvalM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/MEPC_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/SEPC_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/UEPC_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/UTVEC_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/STVEC_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/MTVEC_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/MEDELEG_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/MIDELEG_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/SEDELEG_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/SIDELEG_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/uretM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/sretM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/mretM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/ecallM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/ebreakM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/wfiM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/sfencevmaM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/IllegalCSRAccessM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/IllegalIEUInstrFaultE -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/IllegalIEUInstrFaultM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/InstrAccessFaultD -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/InstrAccessFaultE -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/InstrAccessFaultM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/IllegalInstrFaultM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/BreakpointFaultM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/EcallFaultM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/InstrPageFaultM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/LoadPageFaultM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/StorePageFaultM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/MTrapM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/STrapM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/UTrapM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/STATUS_MPP -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/STATUS_SPP -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/STATUS_TSR -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/STATUS_MIE -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/STATUS_SIE -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/MIP_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/MIE_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/md -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/sd -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/privmodereg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/privmodereg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/privmodereg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/InstrM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/PrivilegedM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/IllegalIEUInstrFaultM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/IllegalCSRAccessM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/PrivilegeModeW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/STATUS_TSR -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/IllegalInstrFaultM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/uretM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/sretM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/mretM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/ecallM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/ebreakM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/wfiM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/sfencevmaM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/IllegalPrivilegedInstrM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/FlushW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/InstrM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/PCM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/SrcAM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRWriteM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/TrapM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/MTrapM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/STrapM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/UTrapM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/mretM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/sretM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/uretM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/TimerIntM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/ExtIntM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/SwIntM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/InstrValidM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/FRegWriteM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/LoadStallD -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/NextPrivilegeModeM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/PrivilegeModeW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CauseM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/NextFaultMtvalM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/STATUS_MPP -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/STATUS_SPP -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/STATUS_TSR -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/MEPC_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/SEPC_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/UEPC_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/UTVEC_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/STVEC_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/MTVEC_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/MEDELEG_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/MIDELEG_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/SEDELEG_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/SIDELEG_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/MIP_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/MIE_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/STATUS_MIE -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/STATUS_SIE -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/SetFflagsM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/FRM_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRReadValW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/IllegalCSRAccessM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRMReadValM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRSReadValM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRUReadValM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRNReadValM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRCReadValM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRReadValM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRSrcM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRRWM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRRSM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRRCM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRWriteValM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/MSTATUS_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/SSTATUS_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/USTATUS_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/MCOUNTINHIBIT_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/MCOUNTEREN_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/SCOUNTEREN_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/WriteMSTATUSM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/WriteSSTATUSM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/WriteUSTATUSM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRMWriteM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRSWriteM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRUWriteM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/UnalignedNextEPCM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/NextEPCM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/NextCauseM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/NextMtvalM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSCAdrM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/SIP_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/SIE_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/UIP_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/UIE_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/IllegalCSRCAccessM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/IllegalCSRMAccessM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/IllegalCSRSAccessM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/IllegalCSRUAccessM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/IllegalCSRNAccessM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/InsufficientCSRPrivilegeM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/CSRMWriteM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/CSRSWriteM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/CSCAdrM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/ExtIntM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/TimerIntM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/SwIntM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/MIDELEG_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/MIP_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/MIE_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/SIP_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/SIE_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/CSRWriteValM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/IntInM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/IP_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/IE_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/MIP_WRITE_MASK -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/SIP_WRITE_MASK -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/WriteMIPM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/WriteMIEM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/WriteSIPM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/WriteSIEM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/WriteMSTATUSM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/WriteSSTATUSM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/WriteUSTATUSM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/TrapM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/FRegWriteM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/NextPrivilegeModeM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/PrivilegeModeW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/mretM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/sretM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/uretM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/CSRWriteValM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/MSTATUS_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/SSTATUS_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/USTATUS_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_MPP -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_SPP -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_TSR -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_MIE -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_SIE -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_SD -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_TW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_TVM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_MXR -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_SUM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_SUM_INT -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_MPRV -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_MPRV_INT -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_SXL -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_UXL -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_XS -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_FS -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_FS_INT -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_MPP_NEXT -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_MPIE -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_SPIE -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_UPIE -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_UIE -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/InstrValidM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/LoadStallD -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/CSRMWriteM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/CSCAdrM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/PrivilegeModeW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/CSRWriteValM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/MCOUNTINHIBIT_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/MCOUNTEREN_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/SCOUNTEREN_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/CSRCReadValM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/IllegalCSRCAccessM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/CYCLE_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/INSTRET_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/HPMCOUNTER3_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/HPMCOUNTER4_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/CYCLEPlusM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/INSTRETPlusM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/HPMCOUNTER3PlusM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/HPMCOUNTER4PlusM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/NextCYCLEM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/NextINSTRETM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/NextHPMCOUNTER3M -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/NextHPMCOUNTER4M -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/WriteCYCLEM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/WriteINSTRETM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/WriteHPMCOUNTER3M -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/WriteHPMCOUNTER4M -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/CounterNumM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/CYCLEreg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/CYCLEreg/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/CYCLEreg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/CYCLEreg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/INSTRETreg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/INSTRETreg/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/INSTRETreg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/INSTRETreg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/HPMCOUNTER3reg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/HPMCOUNTER3reg/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/HPMCOUNTER3reg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/HPMCOUNTER3reg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/HPMCOUNTER4reg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/HPMCOUNTER4reg/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/HPMCOUNTER4reg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/HPMCOUNTER4reg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/CSRMWriteM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTrapM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/CSCAdrM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/NextEPCM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/NextCauseM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/NextMtvalM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MSTATUS_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/CSRWriteValM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/CSRMReadValM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MEPC_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVEC_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTEREN_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTINHIBIT_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MEDELEG_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MIDELEG_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MIP_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MIE_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WriteMSTATUSM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/IllegalCSRMAccessM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MISA_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MSCRATCH_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCAUSE_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVAL_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/PMPCFG01_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/PMPCFG23_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/PMPADDR0_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/zero -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/allones -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MEDELEG_MASK -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MIDELEG_MASK -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WriteMTVECM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WriteMEDELEGM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WriteMIDELEGM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WriteMSCRATCHM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WriteMEPCM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WriteMCAUSEM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WriteMTVALM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WriteMCOUNTERENM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WriteMCOUNTINHIBITM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WritePMPCFG0M -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WritePMPCFG2M -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WritePMPADDR0M -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MISAbits -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk2/PMPCFG01reg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk2/PMPCFG01reg/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk2/PMPCFG01reg/en -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk2/PMPCFG01reg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk2/PMPCFG01reg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk2/PMPCFG23reg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk2/PMPCFG23reg/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk2/PMPCFG23reg/en -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk2/PMPCFG23reg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk2/PMPCFG23reg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk1/MEDELEGreg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk1/MEDELEGreg/load -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk1/MEDELEGreg/en -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk1/MEDELEGreg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk1/MEDELEGreg/val -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk1/MEDELEGreg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk1/MIDELEGreg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk1/MIDELEGreg/load -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk1/MIDELEGreg/en -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk1/MIDELEGreg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk1/MIDELEGreg/val -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk1/MIDELEGreg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVECreg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVECreg/load -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVECreg/en -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVECreg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVECreg/val -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVECreg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MSCRATCHreg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MSCRATCHreg/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MSCRATCHreg/en -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MSCRATCHreg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MSCRATCHreg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MEPCreg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MEPCreg/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MEPCreg/en -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MEPCreg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MEPCreg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCAUSEreg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCAUSEreg/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCAUSEreg/en -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCAUSEreg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCAUSEreg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVALreg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVALreg/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVALreg/en -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVALreg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVALreg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTERENreg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTERENreg/load -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTERENreg/en -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTERENreg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTERENreg/val -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTERENreg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTINHIBITreg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTINHIBITreg/load -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTINHIBITreg/en -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTINHIBITreg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTINHIBITreg/val -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTINHIBITreg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/PMPADDR0reg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/PMPADDR0reg/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/PMPADDR0reg/en -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/PMPADDR0reg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/PMPADDR0reg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/CSRSWriteM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/STrapM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/CSCAdrM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/NextEPCM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/NextCauseM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/NextMtvalM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SSTATUS_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/CSRWriteValM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/CSRSReadValM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SEPC_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/STVEC_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SCOUNTEREN_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SEDELEG_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SIDELEG_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SIP_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SIE_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/WriteSSTATUSM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/IllegalCSRSAccessM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/zero -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/allones -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SEDELEG_MASK -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/WriteSTVECM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/WriteSEDELEGM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/WriteSIDELEGM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/WriteSSCRATCHM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/WriteSEPCM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/WriteSCAUSEM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/WriteSTVALM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/WriteSATPM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/WriteSCOUNTERENM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SSCRATCH_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCAUSE_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/STVAL_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SATP_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/STVECreg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/STVECreg/load -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/STVECreg/en -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/STVECreg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/STVECreg/val -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/STVECreg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SSCRATCHreg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SSCRATCHreg/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SSCRATCHreg/en -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SSCRATCHreg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SSCRATCHreg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SEPCreg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SEPCreg/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SEPCreg/en -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SEPCreg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SEPCreg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCAUSEreg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCAUSEreg/load -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCAUSEreg/en -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCAUSEreg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCAUSEreg/val -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCAUSEreg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/STVALreg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/STVALreg/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/STVALreg/en -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/STVALreg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/STVALreg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SATPreg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SATPreg/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SATPreg/en -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SATPreg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SATPreg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCOUNTERENreg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCOUNTERENreg/load -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCOUNTERENreg/en -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCOUNTERENreg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCOUNTERENreg/val -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCOUNTERENreg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/CSRNWriteM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/UTrapM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/CSCAdrM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/NextEPCM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/NextCauseM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/NextMtvalM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/USTATUS_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/CSRWriteValM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/CSRNReadValM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/UEPC_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/UTVEC_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/UIP_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/UIE_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/WriteUSTATUSM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/IllegalCSRNAccessM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/CSRUWriteM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/CSCAdrM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/CSRWriteValM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/CSRUReadValM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/SetFflagsM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/FRM_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/IllegalCSRUAccessM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/FFLAGS_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/WriteFFLAGSM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/WriteFRMM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/WriteFCSRM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/NextFRMM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/NextFFLAGSM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/FRMreg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/FRMreg/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/FRMreg/en -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/FRMreg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/FRMreg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/FFLAGSreg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/FFLAGSreg/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/FFLAGSreg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/FFLAGSreg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/CSRValWReg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/CSRValWReg/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/CSRValWReg/clear -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/CSRValWReg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/CSRValWReg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregD/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregD/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregD/clear -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregD/en -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregD/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregD/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregE/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregE/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregE/clear -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregE/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregE/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregM/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregM/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregM/clear -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregM/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregM/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/InstrMisalignedFaultM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/InstrAccessFaultM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/IllegalInstrFaultM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/BreakpointFaultM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/LoadMisalignedFaultM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/StoreAmoMisalignedFaultM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/LoadAccessFaultM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/StoreAmoAccessFaultM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/EcallFaultM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/InstrPageFaultM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/LoadPageFaultM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/StorePageFaultM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/mretM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/sretM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/uretM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/PrivilegeModeW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/NextPrivilegeModeM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/MEPC_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/SEPC_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/UEPC_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/UTVEC_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/STVEC_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/MTVEC_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/MIP_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/MIE_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/STATUS_MIE -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/STATUS_SIE -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/InstrMisalignedAdrM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/MemAdrM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/InstrM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/TrapM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/MTrapM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/STrapM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/UTrapM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/RetM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/PrivilegedNextPCM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/CauseM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/NextFaultMtvalM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/MIntGlobalEnM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/SIntGlobalEnM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/PendingIntsM -add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/InterruptM -add wave -noupdate -radix hexadecimal /testbench/dut/imem/AdrF -add wave -noupdate -radix hexadecimal /testbench/dut/imem/InstrF -add wave -noupdate -radix hexadecimal /testbench/dut/imem/InstrAccessFaultF -add wave -noupdate -radix hexadecimal /testbench/dut/imem/adrbits -add wave -noupdate -radix hexadecimal /testbench/dut/imem/rd -add wave -noupdate -radix hexadecimal /testbench/dut/imem/rd2 -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HCLK -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HRESETn -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HADDR -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HWDATAIN -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HWRITE -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HSIZE -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HBURST -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HPROT -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HTRANS -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HMASTLOCK -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HRDATAEXT -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADYEXT -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HRESPEXT -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HRDATA -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADY -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HRESP -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/DataAccessFaultM -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/TimerIntM -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/SwIntM -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/GPIOPinsIn -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/GPIOPinsOut -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/GPIOPinsEn -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/UARTSin -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/UARTSout -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HWDATA -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADTim -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADCLINT -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADGPIO -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADUART -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HSELTim -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HSELCLINT -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HSELGPIO -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/PreHSELUART -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HSELUART -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HRESPTim -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HRESPCLINT -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HRESPGPIO -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HRESPUART -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADYTim -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADYCLINT -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADYGPIO -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADYUART -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/MemRW -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/MemRWtim -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/MemRWclint -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/MemRWgpio -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/MemRWuart -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/UARTIntr -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/timdec/HADDR -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/timdec/Base -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/timdec/Range -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/timdec/HSEL -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/timdec/match -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clintdec/HADDR -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clintdec/Base -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clintdec/Range -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clintdec/HSEL -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clintdec/match -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpiodec/HADDR -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpiodec/Base -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpiodec/Range -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpiodec/HSEL -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpiodec/match -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uartdec/HADDR -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uartdec/Base -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uartdec/Range -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uartdec/HSEL -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uartdec/match -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/sww/HRDATA -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/sww/HADDR -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/sww/HSIZE -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/sww/HWDATAIN -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/sww/HWDATA -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/sww/ByteM -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/sww/HalfwordM -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/sww/WriteDataSubwordDuplicated -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/sww/ByteMaskM -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/HCLK -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/HRESETn -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/MemRWtim -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/HADDR -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/HWDATA -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/HSELTim -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/HREADTim -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/HRESPTim -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/HREADYTim -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/entry -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/memread -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/memwrite -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/busycount -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/HCLK -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/HRESETn -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/MemRWclint -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/HADDR -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/HWDATA -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/HREADCLINT -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/HRESPCLINT -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/HREADYCLINT -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/TimerIntM -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/SwIntM -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/MTIMECMP -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/MTIME -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/MSIP -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/entry -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/memread -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/memwrite -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/HCLK -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/HRESETn -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/MemRWgpio -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/HADDR -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/HWDATA -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/HREADGPIO -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/HRESPGPIO -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/HREADYGPIO -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/GPIOPinsIn -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/GPIOPinsOut -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/GPIOPinsEn -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/INPUT_VAL -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/INPUT_EN -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/OUTPUT_EN -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/OUTPUT_VAL -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/entry -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/memread -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/memwrite -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/HCLK -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/HRESETn -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/MemRWuart -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/HADDR -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/HWDATA -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/HREADUART -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/HRESPUART -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/HREADYUART -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/SIN -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/DSRb -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/DCDb -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/CTSb -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/RIb -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/SOUT -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/RTSb -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/DTRb -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/OUT1b -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/OUT2b -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/INTR -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/TXRDYb -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/RXRDYb -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/A -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/MEMRb -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/MEMWb -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/Din -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/Dout -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/BAUDOUTb -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/HCLK -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/HRESETn -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/A -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/Din -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/Dout -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/MEMRb -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/MEMWb -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/INTR -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/TXRDYb -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/RXRDYb -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/BAUDOUTb -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/RCLK -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/SIN -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DSRb -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DCDb -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/CTSb -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/RIb -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/SOUT -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/RTSb -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DTRb -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/OUT1b -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/OUT2b -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/RBR -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/FCR -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/LCR -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/LSR -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/SCR -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DLL -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DLM -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/IER -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/MSR -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/MCR -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/SINd -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DSRbd -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DCDbd -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/CTSbd -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/RIbd -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/SINsync -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DSRbsync -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DCDbsync -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/CTSbsync -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/RIbsync -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DSRb2 -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DCDb2 -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/CTSb2 -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/RIb2 -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/SOUTbit -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/loop -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DLAB -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/baudpulse -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txbaudpulse -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxbaudpulse -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/baudcount -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxoversampledcnt -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txoversampledcnt -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxbitsreceived -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txbitssent -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxstate -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txstate -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxshiftreg -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifohead -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifotail -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txfifohead -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txfifotail -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifotriggerlevel -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifoentries -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txfifoentries -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxbitsexpected -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txbitsexpected -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/RXBR -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxtimeoutcnt -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxcentered -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxparity -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxparitybit -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxstopbit -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxparityerr -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxoverrunerr -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxframingerr -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxbreak -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifohaserr -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxdataready -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifoempty -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifotriggered -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifotimeout -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifodmaready -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxdata9 -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxdata -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxerrbit -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfullbit -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/TXHR -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txdata -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/nexttxdata -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txsr -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txnextbit -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txhrfull -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txsrfull -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txparity -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txfifoempty -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txfifofull -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txfifodmaready -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/fifoenabled -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/fifodmamodesel -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/evenparitysel -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxlinestatusintr -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxdataavailintr -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txhremptyintr -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/modemstatusintr -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/intrpending -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/intrid -add wave -noupdate -radix hexadecimal /testbench/it/clk -add wave -noupdate -radix hexadecimal /testbench/it/reset -add wave -noupdate -radix hexadecimal /testbench/it/FlushE -add wave -noupdate -radix hexadecimal /testbench/it/InstrD -add wave -noupdate -radix hexadecimal /testbench/it/InstrE -add wave -noupdate -radix hexadecimal /testbench/it/InstrM -add wave -noupdate -radix hexadecimal /testbench/it/InstrW -add wave -noupdate -radix hexadecimal /testbench/it/InstrWReg/clk -add wave -noupdate -radix hexadecimal /testbench/it/InstrWReg/reset -add wave -noupdate -radix hexadecimal /testbench/it/InstrWReg/d -add wave -noupdate -radix hexadecimal /testbench/it/InstrWReg/q -add wave -noupdate -radix hexadecimal /testbench/it/ddec/instr -add wave -noupdate -radix hexadecimal /testbench/it/ddec/op -add wave -noupdate -radix hexadecimal /testbench/it/ddec/funct3 -add wave -noupdate -radix hexadecimal /testbench/it/ddec/funct7 -add wave -noupdate -radix hexadecimal /testbench/it/ddec/imm -add wave -noupdate -radix hexadecimal /testbench/it/edec/instr -add wave -noupdate -radix hexadecimal /testbench/it/edec/op -add wave -noupdate -radix hexadecimal /testbench/it/edec/funct3 -add wave -noupdate -radix hexadecimal /testbench/it/edec/funct7 -add wave -noupdate -radix hexadecimal /testbench/it/edec/imm -add wave -noupdate -radix hexadecimal /testbench/it/mdec/instr -add wave -noupdate -radix hexadecimal /testbench/it/mdec/op -add wave -noupdate -radix hexadecimal /testbench/it/mdec/funct3 -add wave -noupdate -radix hexadecimal /testbench/it/mdec/funct7 -add wave -noupdate -radix hexadecimal /testbench/it/mdec/imm -add wave -noupdate -radix hexadecimal /testbench/it/wdec/instr -add wave -noupdate -radix hexadecimal /testbench/it/wdec/op -add wave -noupdate -radix hexadecimal /testbench/it/wdec/funct3 -add wave -noupdate -radix hexadecimal /testbench/it/wdec/funct7 -add wave -noupdate -radix hexadecimal /testbench/it/wdec/imm -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {330314 ns} 0} {{Cursor 3} {330384 ns} 0} -quietly wave cursor active 2 -configure wave -namecolwidth 250 -configure wave -valuecolwidth 168 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {330283 ns} {330427 ns} diff --git a/sim/wave-dos/ahb-muldiv.do b/sim/wave-dos/ahb-muldiv.do deleted file mode 100644 index 3170bc969..000000000 --- a/sim/wave-dos/ahb-muldiv.do +++ /dev/null @@ -1,100 +0,0 @@ -restart -f -delete wave /* -view wave - -add wave /testbench/clk -add wave /testbench/reset -add wave -divider - -# new -#add wave /testbench/dut/core/ebu/ebu/IReadF -add wave /testbench/dut/core/DataStall -add wave /testbench/dut/core/ICacheStallF -add wave /testbench/dut/core/StallF -add wave /testbench/dut/core/StallD - -add wave /testbench/dut/core/StallE -add wave /testbench/dut/core/StallM -add wave /testbench/dut/core/StallW -add wave /testbench/dut/core/FlushD -add wave /testbench/dut/core/FlushE -add wave /testbench/dut/core/FlushM -add wave /testbench/dut/core/FlushW - -add wave -noupdate -divider -height 32 "MulDiv" -add wave -hex /testbench/dut/core/mdu/* - -add wave -noupdate -divider -height 32 "Integer Divider" -add wave -hex /testbench/dut/core/mdu/genblk1/div/fsm1/CURRENT_STATE -add wave -hex /testbench/dut/core/mdu/genblk1/div/fsm1/NEXT_STATE -add wave -hex /testbench/dut/core/mdu/genblk1/div/* - -add wave -noupdate -divider -height 32 "RF" -add wave -hex /testbench/dut/core/ieu/dp/regf/* -add wave -hex /testbench/dut/core/ieu/dp/regf/rf - -add wave -divider -add wave -hex /testbench/dut/core/ifu/PCF -add wave -hex /testbench/dut/core/ifu/PCD -add wave -hex /testbench/dut/core/ifu/InstrD -add wave /testbench/InstrDName -add wave -divider - -add wave -hex /testbench/dut/core/ifu/PCE -add wave -hex /testbench/dut/core/ifu/InstrE -add wave /testbench/InstrEName -add wave -hex /testbench/dut/core/ieu/dp/SrcAE -add wave -hex /testbench/dut/core/ieu/dp/SrcBE -add wave -hex /testbench/dut/core/ieu/dp/ALUResultE -#add wave /testbench/dut/core/ieu/dp/PCSrcE -add wave -divider - -add wave -hex /testbench/dut/core/ifu/PCM -add wave -hex /testbench/dut/core/ifu/InstrM -add wave /testbench/InstrMName -add wave /testbench/dut/uncore/uncore/ram/memwrite -add wave -hex /testbench/dut/uncore/uncore/HADDR -add wave -hex /testbench/dut/uncore/uncore/HWDATA -add wave -divider - -add wave -hex /testbench/dut/core/ebu/ebu/MemReadM -add wave -hex /testbench/dut/core/ebu/ebu/InstrReadF -add wave -hex /testbench/dut/core/ebu/ebu/BusState -add wave -hex /testbench/dut/core/ebu/ebu/NextBusState -add wave -hex /testbench/dut/core/ebu/ebu/HADDR -add wave -hex /testbench/dut/core/ebu/ebu/HREADY -add wave -hex /testbench/dut/core/ebu/ebu/HTRANS -add wave -hex /testbench/dut/core/ebu/ebu/HRDATA -add wave -hex /testbench/dut/core/ebu/ebu/HWRITE -add wave -hex /testbench/dut/core/ebu/ebu/HWDATA -add wave -hex /testbench/dut/core/ebu/ebu/HBURST -add wave -hex /testbench/dut/core/ebu/ebu/CaptureDataM -add wave -divider - -add wave -hex /testbench/dut/uncore/uncore/ram/* -add wave -divider - -add wave -hex /testbench/dut/core/ifu/PCW -add wave -hex /testbench/dut/core/ifu/InstrW -add wave /testbench/InstrWName -add wave /testbench/dut/core/ieu/dp/RegWriteW -add wave -hex /testbench/dut/core/ebu/ebu/ReadDataW -add wave -hex /testbench/dut/core/ieu/dp/ResultW -add wave -hex /testbench/dut/core/ieu/dp/RdW -add wave -divider - -add wave -hex /testbench/dut/uncore/uncore/ram/* -add wave -divider - -# appearance -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {100 ps} -configure wave -namecolwidth 350 -configure wave -valuecolwidth 250 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -set DefaultRadix hexadecimal diff --git a/sim/wave-dos/ahb-waves.do b/sim/wave-dos/ahb-waves.do deleted file mode 100644 index 37a397d04..000000000 --- a/sim/wave-dos/ahb-waves.do +++ /dev/null @@ -1,89 +0,0 @@ -# ahb-waves.do -restart -f -delete wave /* -view wave - -add wave /testbench/clk -add wave /testbench/reset -add wave -divider - -#add wave /testbench/dut/core/ebu/ebu/IReadF -add wave /testbench/dut/core/DataStall -add wave /testbench/dut/core/ICacheStallF -add wave /testbench/dut/core/StallF -add wave /testbench/dut/core/StallD -add wave /testbench/dut/core/StallE -add wave /testbench/dut/core/StallM -add wave /testbench/dut/core/StallW -add wave /testbench/dut/core/FlushD -add wave /testbench/dut/core/FlushE -add wave /testbench/dut/core/FlushM -add wave /testbench/dut/core/FlushW - -add wave -divider -add wave -hex /testbench/dut/core/ifu/PCF -add wave -hex /testbench/dut/core/ifu/PCD -add wave -hex /testbench/dut/core/ifu/InstrD -add wave /testbench/InstrDName -add wave -hex /testbench/dut/core/ifu/ic/InstrRawD -add wave -divider - -add wave -hex /testbench/dut/core/ifu/PCE -add wave -hex /testbench/dut/core/ifu/InstrE -add wave /testbench/InstrEName -add wave -hex /testbench/dut/core/ieu/dp/SrcAE -add wave -hex /testbench/dut/core/ieu/dp/SrcBE -add wave -hex /testbench/dut/core/ieu/dp/ALUResultE -#add wave /testbench/dut/core/ieu/dp/PCSrcE -add wave -divider - -add wave -hex /testbench/dut/core/ifu/PCM -add wave -hex /testbench/dut/core/ifu/InstrM -add wave /testbench/InstrMName -add wave /testbench/dut/uncore/uncore/ram/memwrite -add wave -hex /testbench/dut/uncore/uncore/HADDR -add wave -hex /testbench/dut/uncore/uncore/HWDATA -add wave -divider - -add wave -hex /testbench/dut/core/ebu/ebu/MemReadM -add wave -hex /testbench/dut/core/ebu/ebu/InstrReadF -add wave -hex /testbench/dut/core/ebu/ebu/BusState -add wave -hex /testbench/dut/core/ebu/ebu/NextBusState -add wave -hex /testbench/dut/core/ebu/ebu/HADDR -add wave -hex /testbench/dut/core/ebu/ebu/HREADY -add wave -hex /testbench/dut/core/ebu/ebu/HTRANS -add wave -hex /testbench/dut/core/ebu/ebu/HRDATA -add wave -hex /testbench/dut/core/ebu/ebu/HWRITE -add wave -hex /testbench/dut/core/ebu/ebu/HWDATA -add wave -hex /testbench/dut/core/ebu/ebu/CaptureDataM -add wave -divider - -add wave -hex /testbench/dut/uncore/uncore/ram/* -add wave -divider - -add wave -hex /testbench/dut/core/ifu/PCW -add wave -hex /testbench/dut/core/ifu/InstrW -add wave /testbench/InstrWName -add wave /testbench/dut/core/ieu/dp/RegWriteW -add wave -hex /testbench/dut/core/ebu/ebu/ReadDataW -add wave -hex /testbench/dut/core/ieu/dp/ResultW -add wave -hex /testbench/dut/core/ieu/dp/RdW -add wave -divider - -add wave -hex /testbench/dut/uncore/uncore/ram/* -add wave -divider - -add wave -hex -r /testbench/* - -# appearance -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {100 ps} -configure wave -namecolwidth 250 -configure wave -valuecolwidth 150 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -set DefaultRadix hexadecimal diff --git a/sim/wave-dos/cache-waves.do b/sim/wave-dos/cache-waves.do deleted file mode 100644 index ff6e855ec..000000000 --- a/sim/wave-dos/cache-waves.do +++ /dev/null @@ -1,76 +0,0 @@ -add wave /testbench/clk -add wave /testbench/reset -add wave -divider - -#add wave /testbench/dut/core/ebu/ebu/IReadF -add wave /testbench/dut/core/DataStall -add wave /testbench/dut/core/ICacheStallF -add wave /testbench/dut/core/StallF -add wave /testbench/dut/core/StallD -add wave /testbench/dut/core/StallE -add wave /testbench/dut/core/StallM -add wave /testbench/dut/core/StallW -add wave /testbench/dut/core/FlushD -add wave /testbench/dut/core/FlushE -add wave /testbench/dut/core/FlushM -add wave /testbench/dut/core/FlushW - -add wave -divider -add wave -hex /testbench/dut/core/ifu/PCF -add wave -hex /testbench/dut/core/ifu/PCD -add wave -hex /testbench/dut/core/ifu/InstrD - -add wave /testbench/InstrDName -add wave -divider - - -add wave -hex /testbench/dut/core/ifu/PCE -add wave -hex /testbench/dut/core/ifu/InstrE -add wave /testbench/InstrEName -add wave -hex /testbench/dut/core/ieu/dp/SrcAE -add wave -hex /testbench/dut/core/ieu/dp/SrcBE -add wave -hex /testbench/dut/core/ieu/dp/ALUResultE -#add wave /testbench/dut/core/ieu/dp/PCSrcE -add wave -divider - -add wave -hex /testbench/dut/core/ifu/PCM -add wave -hex /testbench/dut/core/ifu/InstrM -add wave /testbench/InstrMName -add wave /testbench/dut/uncore/uncore/ram/memwrite -add wave -hex /testbench/dut/uncore/uncore/HADDR -add wave -hex /testbench/dut/uncore/uncore/HWDATA -add wave -divider - -add wave -hex /testbench/dut/core/ebu/ebu/MemReadM -add wave -hex /testbench/dut/core/ebu/ebu/InstrReadF -add wave -hex /testbench/dut/core/ebu/ebu/BusState -add wave -hex /testbench/dut/core/ebu/ebu/NextBusState -add wave -hex /testbench/dut/core/ebu/ebu/HADDR -add wave -hex /testbench/dut/core/ebu/ebu/HREADY -add wave -hex /testbench/dut/core/ebu/ebu/HTRANS -add wave -hex /testbench/dut/core/ebu/ebu/HRDATA -add wave -hex /testbench/dut/core/ebu/ebu/HWRITE -add wave -hex /testbench/dut/core/ebu/ebu/HWDATA -add wave -hex /testbench/dut/core/ebu/ebu/ReadDataM -add wave -divider - -add wave /testbench/dut/core/ebu/ebu/CaptureDataM -add wave /testbench/dut/core/ebu/ebu/CapturedDataAvailable -add wave /testbench/dut/core/StallW -add wave -hex /testbench/dut/core/ebu/ebu/CapturedData -add wave -hex /testbench/dut/core/ebu/ebu/ReadDataWnext -add wave -hex /testbench/dut/core/ebu/ebu/ReadDataW -add wave -hex /testbench/dut/core/ifu/PCW -add wave -hex /testbench/dut/core/ifu/InstrW -add wave /testbench/InstrWName -add wave /testbench/dut/core/ieu/dp/RegWriteW -add wave -hex /testbench/dut/core/ebu/ebu/ReadDataW -add wave -hex /testbench/dut/core/ieu/dp/ResultW -add wave -hex /testbench/dut/core/ieu/dp/RdW -add wave -divider - -add wave -hex /testbench/dut/core/dmem/* -add wave -hex /testbench/dut/core/dmem/genblk1/* -add wave -divider - -add wave -hex -r /testbench/* diff --git a/sim/wave-dos/default-waves.do b/sim/wave-dos/default-waves.do deleted file mode 100644 index 2c7f0f755..000000000 --- a/sim/wave-dos/default-waves.do +++ /dev/null @@ -1,65 +0,0 @@ -# default-waves.do -restart -f -delete wave /* -view wave - -# Diplays All Signals recursively -add wave /testbench/clk -add wave /testbench/reset -add wave -divider -#add wave /testbench/dut/core/ebu/ebu/IReadF -#add wave /testbench/dut/core/DataStall -add wave /testbench/dut/core/ICacheStallF -add wave /testbench/dut/core/StallF -add wave /testbench/dut/core/StallD -add wave /testbench/dut/core/StallE -add wave /testbench/dut/core/StallM -add wave /testbench/dut/core/StallW -add wave /testbench/dut/core/FlushD -add wave /testbench/dut/core/FlushE -add wave /testbench/dut/core/FlushM -add wave /testbench/dut/core/FlushW - -add wave -divider -add wave -hex /testbench/dut/core/ifu/PCF -add wave -hex /testbench/dut/core/ifu/PCD -add wave -hex /testbench/dut/core/ifu/InstrD -add wave /testbench/InstrDName -add wave -divider -add wave -hex /testbench/dut/core/ifu/PCE -add wave -hex /testbench/dut/core/ifu/InstrE -add wave /testbench/InstrEName -add wave -hex /testbench/dut/core/ieu/dp/SrcAE -add wave -hex /testbench/dut/core/ieu/dp/SrcBE -add wave -hex /testbench/dut/core/ieu/dp/ALUResultE -#add wave /testbench/dut/core/ieu/dp/PCSrcE -add wave -divider -add wave -hex /testbench/dut/core/ifu/PCM -add wave -hex /testbench/dut/core/ifu/InstrM -add wave /testbench/InstrMName -add wave /testbench/dut/uncore/uncore/ram/memwrite -add wave -hex /testbench/dut/uncore/uncore/HADDR -add wave -hex /testbench/dut/uncore/uncore/HWDATA -add wave -divider -add wave -hex /testbench/PCW -add wave -hex /testbench/InstrW -add wave /testbench/InstrWName -add wave /testbench/dut/core/ieu/dp/RegWriteW -add wave -hex /testbench/dut/core/ieu/dp/ResultW -add wave -hex /testbench/dut/core/ieu/dp/RdW -add wave -divider - -add wave -hex -r /testbench/* - -# appearance -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {100 ps} -configure wave -namecolwidth 250 -configure wave -valuecolwidth 150 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -set DefaultRadix hexadecimal diff --git a/sim/wave-dos/generic.do b/sim/wave-dos/generic.do deleted file mode 100644 index 1d59f3fbe..000000000 --- a/sim/wave-dos/generic.do +++ /dev/null @@ -1,23 +0,0 @@ -# default-waves.do -restart -f -delete wave /* -view wave - -# Diplays All Signals recursively -add wave /testbench/clk -add wave /testbench/reset -add wave -divider -add wave -hex -r /testbench/* - -# appearance -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {300 ps} -configure wave -namecolwidth 350 -configure wave -valuecolwidth 150 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -set DefaultRadix hexadecimal diff --git a/sim/wave-dos/linux-waves.do b/sim/wave-dos/linux-waves.do deleted file mode 100644 index 102cfe24f..000000000 --- a/sim/wave-dos/linux-waves.do +++ /dev/null @@ -1,207 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider -add wave -noupdate /testbench/clk -add wave -noupdate /testbench/reset -add wave -noupdate -radix decimal /testbench/errorCount -add wave -noupdate -radix decimal /testbench/InstrCountW -add wave -noupdate -divider Stalls_and_Flushes -add wave -noupdate /testbench/dut/core/StallF -add wave -noupdate /testbench/dut/core/StallD -add wave -noupdate /testbench/dut/core/StallE -add wave -noupdate /testbench/dut/core/StallM -add wave -noupdate /testbench/dut/core/StallW -add wave -noupdate /testbench/dut/core/FlushD -add wave -noupdate /testbench/dut/core/FlushE -add wave -noupdate /testbench/dut/core/FlushM -add wave -noupdate /testbench/dut/core/FlushW -add wave -noupdate -divider F -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCF -add wave -noupdate -divider D -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCD -add wave -noupdate /testbench/InstrDName -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrD -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/InstrValidD -add wave -noupdate -divider E -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCE -add wave -noupdate /testbench/InstrEName -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrE -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/InstrValidE -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcAE -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcBE -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultE -add wave -noupdate -divider M -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCM -add wave -noupdate /testbench/InstrMName -add wave -noupdate /testbench/textM -add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrM -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/InstrValidM -add wave -noupdate -radix hexadecimal /testbench/dut/core/lsu.bus.dcache/MemPAdrM -add wave -noupdate -radix hexadecimal /testbench/dut/core/lsu.bus.dcache/MemRWM -add wave -noupdate /testbench/dut/core/lsu.bus.dcache/WriteDataM -add wave -noupdate -radix hexadecimal /testbench/dut/core/lsu.bus.dcache/ReadDataM -add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/DTLBWalk -add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/BasePageTablePPN -add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/CurrentPPN -add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/MemWrite -add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/Executable -add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/Writable -add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/Readable -add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/Valid -add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/Misaligned -add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/MegapageMisaligned -add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/ValidPTE -add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/LeafPTE -add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/ValidLeafPTE -add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/ValidNonLeafPTE -add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/StartWalk -add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/TLBMiss -add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/PRegEn -add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/NextPageType -add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/SvMode -add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/TranslationVAdr -add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/WalkerState -add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/NextWalkerState -add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/InitialWalkerState -add wave -noupdate -group LSU -r /testbench/dut/core/lsu/* -add wave -noupdate -group DCache -r /testbench/dut/core/lsu.bus.dcache/* -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/clk -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/reset -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/StallW -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/UnsignedLoadM -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/AtomicMaskedM -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/Funct7M -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/InstrPAdrF -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/InstrReadF -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/InstrRData -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/InstrAckF -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DCtoAHBPAdrM -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DCtoAHBReadM -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DCtoAHBWriteM -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DCtoAHBWriteData -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DCfromAHBReadData -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/MemSizeM -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DCfromAHBAck -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HRDATA -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HREADY -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HRESP -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HCLK -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HRESETn -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HADDR -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HWDATA -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HWRITE -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HSIZE -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HBURST -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HPROT -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HTRANS -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HMASTLOCK -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HADDRD -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HSIZED -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HWRITED -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/GrantData -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/AccessAddress -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/ISize -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HRDATAMasked -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/ReadDataM -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HRDATANext -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/CapturedHRDATAMasked -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/WriteData -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/IReady -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DReady -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/CaptureDataM -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/CapturedDataAvailable -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/BusState -add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/NextBusState -add wave -noupdate -divider W -add wave -noupdate -radix hexadecimal /testbench/PCW -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/InstrValidW -add wave -noupdate /testbench/textM -add wave -noupdate /testbench/dut/core/ieu/dp/ReadDataW -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ResultW -add wave -noupdate -group RF /testbench/dut/core/ieu/dp/RegWriteW -add wave -noupdate -group RF -radix unsigned /testbench/dut/core/ieu/dp/RdW -add wave -noupdate -group RF /testbench/dut/core/ieu/dp/regf/wd3 -add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[2]} -add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[3]} -add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[4]} -add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[5]} -add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[6]} -add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[7]} -add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[8]} -add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[9]} -add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[10]} -add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[11]} -add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[12]} -add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[13]} -add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[14]} -add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[15]} -add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[16]} -add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[17]} -add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[18]} -add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[19]} -add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[20]} -add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[21]} -add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[22]} -add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[23]} -add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[24]} -add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[25]} -add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[26]} -add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[27]} -add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[28]} -add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[29]} -add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[30]} -add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[31]} -add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/MSTATUS_REGW -add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/MCOUNTINHIBIT_REGW -add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/MCOUNTEREN_REGW -add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/MIDELEG_REGW -add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/MIP_REGW -add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/MIE_REGW -add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MEPC_REGW -add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVEC_REGW -add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTEREN_REGW -add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTINHIBIT_REGW -add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MEDELEG_REGW -add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MIDELEG_REGW -add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MSCRATCH_REGW -add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCAUSE_REGW -add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVAL_REGW -add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/SSTATUS_REGW -add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/SCOUNTEREN_REGW -add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/SIP_REGW -add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/SIE_REGW -add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SEPC_REGW -add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/STVEC_REGW -add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SCOUNTEREN_REGW -add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SEDELEG_REGW -add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SIDELEG_REGW -add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SATP_REGW -add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/USTATUS_REGW -add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/UEPC_REGW -add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/UTVEC_REGW -add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/UIP_REGW -add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/UIE_REGW -add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/PMPCFG_ARRAY_REGW -add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/PMPADDR_ARRAY_REGW -add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MISA_REGW -add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/FRM_REGW -add wave -noupdate -divider -add wave -hex -r /testbench/* -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 8} {42752672 ns} 1} {{Cursor 2} {42752634 ns} 0} -quietly wave cursor active 2 -configure wave -namecolwidth 250 -configure wave -valuecolwidth 297 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {42752559 ns} {42752771 ns} diff --git a/sim/wave-dos/peripheral-waves.do b/sim/wave-dos/peripheral-waves.do deleted file mode 100644 index 3f3974dc2..000000000 --- a/sim/wave-dos/peripheral-waves.do +++ /dev/null @@ -1,118 +0,0 @@ -# peripheral-waves.do - -restart -f -delete wave /* -view wave - -# general stuff -add wave /testbench/clk -add wave /testbench/reset -add wave -divider - -#add wave /testbench/dut/core/DataStall -add wave /testbench/dut/core/StallF -add wave /testbench/dut/core/StallD -add wave /testbench/dut/core/StallE -add wave /testbench/dut/core/StallM -add wave /testbench/dut/core/StallW -add wave /testbench/dut/core/FlushD -add wave /testbench/dut/core/FlushE -add wave /testbench/dut/core/FlushM -add wave /testbench/dut/core/FlushW -add wave -divider - -add wave -hex /testbench/dut/core/ifu/PCF -add wave -hex /testbench/dut/core/ifu/PCD -add wave -hex /testbench/dut/core/ifu/InstrD -add wave -hex /testbench/dut/core/ieu/c/InstrValidD -add wave /testbench/InstrDName -add wave -divider -add wave -hex /testbench/dut/core/ifu/PCE -add wave -hex /testbench/dut/core/ifu/InstrE -add wave -hex /testbench/dut/core/ieu/c/InstrValidE -add wave /testbench/InstrEName -add wave -hex /testbench/dut/core/ieu/dp/SrcAE -add wave -hex /testbench/dut/core/ieu/dp/SrcBE -add wave -hex /testbench/dut/core/ieu/dp/ALUResultE -#add wave /testbench/dut/core/ieu/dp/PCSrcE -add wave /testbench/dut/core/mdu/genblk1/div/DivStartE -add wave /testbench/dut/core/mdu/DivBusyE -add wave -hex /testbench/dut/core/mdu/genblk1/div/RemM -add wave -hex /testbench/dut/core/mdu/genblk1/div/QuotM - -add wave -divider -add wave -hex /testbench/dut/core/ifu/PCM -add wave -hex /testbench/dut/core/ifu/InstrM -add wave -hex /testbench/dut/core/ieu/c/InstrValidM -add wave /testbench/InstrMName -add wave /testbench/dut/uncore/uncore/ram/memwrite -add wave -hex /testbench/dut/core/WriteDataM -add wave -hex /testbench/dut/core/lsu.bus.dcache/MemPAdrM -add wave -hex /testbench/dut/core/lsu.bus.dcache/WriteDataM -add wave -hex /testbench/dut/core/lsu.bus.dcache/ReadDataM -add wave -divider -add wave -hex /testbench/PCW -#add wave -hex /testbench/InstrW -#add wave -hex /testbench/dut/core/ieu/c/InstrValidW -#add wave /testbench/InstrWName -add wave -hex /testbench/dut/core/ReadDataW -add wave -hex /testbench/dut/core/ieu/dp/ResultW -add wave -hex /testbench/dut/core/ieu/dp/RegWriteW -add wave -hex /testbench/dut/core/ieu/dp/WriteDataW -add wave -hex /testbench/dut/core/ieu/dp/RdW -add wave -divider -add wave -hex /testbench/dut/core/priv/csr/TrapM -add wave -hex /testbench/dut/core/priv/csr/UnalignedNextEPCM -add wave -hex /testbench/dut/core/priv/csr/genblk1/csrm/WriteMEPCM -add wave -hex /testbench/dut/core/priv/csr/genblk1/csrm/MEPC_REGW - -add wave -divider RegFile -add wave -hex /testbench/dut/core/ieu/dp/regf/rf[1] -add wave -hex /testbench/dut/core/ieu/dp/regf/rf[2] -add wave -hex /testbench/dut/core/ieu/dp/regf/rf[3] -add wave -hex /testbench/dut/core/ieu/dp/regf/rf[4] -add wave -hex /testbench/dut/core/ieu/dp/regf/rf[5] -add wave -hex /testbench/dut/core/ieu/dp/regf/rf[6] -add wave -hex /testbench/dut/core/ieu/dp/regf/rf[7] -add wave -hex /testbench/dut/core/ieu/dp/regf/rf[8] -add wave -hex /testbench/dut/core/ieu/dp/regf/rf[9] -add wave -hex /testbench/dut/core/ieu/dp/regf/rf[10] -add wave -hex /testbench/dut/core/ieu/dp/regf/rf[11] -add wave -hex /testbench/dut/core/ieu/dp/regf/rf[12] -add wave -hex /testbench/dut/core/ieu/dp/regf/rf[13] -add wave -hex /testbench/dut/core/ieu/dp/regf/rf[14] -add wave -hex /testbench/dut/core/ieu/dp/regf/rf[15] -add wave -hex /testbench/dut/core/ieu/dp/regf/rf[16] -add wave -hex /testbench/dut/core/ieu/dp/regf/rf[17] -add wave -hex /testbench/dut/core/ieu/dp/regf/rf[18] -add wave -hex /testbench/dut/core/ieu/dp/regf/rf[19] -add wave -hex /testbench/dut/core/ieu/dp/regf/rf[20] -add wave -hex /testbench/dut/core/ieu/dp/regf/rf[21] -add wave -hex /testbench/dut/core/ieu/dp/regf/rf[22] -add wave -hex /testbench/dut/core/ieu/dp/regf/rf[23] -add wave -hex /testbench/dut/core/ieu/dp/regf/rf[24] -add wave -hex /testbench/dut/core/ieu/dp/regf/rf[25] -add wave -hex /testbench/dut/core/ieu/dp/regf/rf[26] -add wave -hex /testbench/dut/core/ieu/dp/regf/rf[27] -add wave -hex /testbench/dut/core/ieu/dp/regf/rf[28] -add wave -hex /testbench/dut/core/ieu/dp/regf/rf[29] -add wave -hex /testbench/dut/core/ieu/dp/regf/rf[30] -add wave -hex /testbench/dut/core/ieu/dp/regf/rf[31] - -# peripherals -add wave -divider PLIC -add wave -hex /testbench/dut/core/priv/csr/TrapM -add wave -hex /testbench/dut/uncore/uncore/plic/plic/* -add wave -hex /testbench/dut/uncore/uncore/plic/plic/intPriority -add wave -hex /testbench/dut/uncore/uncore/plic/plic/pendingArray -add wave -divider UART -add wave -hex /testbench/dut/uncore/uncore/uart/uart/u/* -add wave -divider GPIO -add wave -hex /testbench/dut/uncore/uncore/gpio/gpio/* -#add wave -divider -#add wave -hex /testbench/dut/core/ebu/ebu/* -#add wave -divider -#add wave -divider - -# everything else -add wave -hex -r /testbench/* diff --git a/sim/wave-fpu.do b/sim/wave-fpu.do deleted file mode 100644 index 08b6b3378..000000000 --- a/sim/wave-fpu.do +++ /dev/null @@ -1,30 +0,0 @@ - -add wave -noupdate /testbenchfp/clk -add wave -noupdate -radix decimal /testbenchfp/VectorNum -add wave -noupdate /testbenchfp/FrmNum -add wave -noupdate /testbenchfp/X -add wave -noupdate /testbenchfp/Y -add wave -noupdate /testbenchfp/Z -add wave -noupdate /testbenchfp/Res -add wave -noupdate /testbenchfp/Ans -add wave -noupdate /testbenchfp/reset -add wave -noupdate /testbenchfp/DivStart -add wave -noupdate /testbenchfp/FDivBusyE -add wave -noupdate /testbenchfp/CheckNow -add wave -noupdate /testbenchfp/DivDone -add wave -noupdate /testbenchfp/ResMatch -add wave -noupdate /testbenchfp/FlagMatch -add wave -noupdate /testbenchfp/CheckNow -add wave -noupdate /testbenchfp/NaNGood -add wave -group {PostProc} -noupdate /testbenchfp/postprocess/* -add wave -group {PostProc} -noupdate /testbenchfp/postprocess/specialcase/* -add wave -group {PostProc} -noupdate /testbenchfp/postprocess/flags/* -add wave -group {PostProc} -noupdate /testbenchfp/postprocess/normshift/* -add wave -group {PostProc} -noupdate /testbenchfp/postprocess/shiftcorrection/* -add wave -group {PostProc} -noupdate /testbenchfp/postprocess/resultsign/* -add wave -group {PostProc} -noupdate /testbenchfp/postprocess/round/* -add wave -group {PostProc} -noupdate /testbenchfp/postprocess/fmashiftcalc/* -add wave -group {PostProc} -noupdate /testbenchfp/postprocess/divshiftcalc/* -add wave -group {PostProc} -noupdate /testbenchfp/postprocess/cvtshiftcalc/* -add wave -group {Testbench} -noupdate /testbenchfp/* -add wave -group {Testbench} -noupdate /testbenchfp/readvectors/* diff --git a/sim/wally.xrun b/sim/xcelium/wally.xrun similarity index 100% rename from sim/wally.xrun rename to sim/xcelium/wally.xrun diff --git a/site-setup.sh b/site-setup.sh index cf28a93f1..1ffca5fd4 100755 --- a/site-setup.sh +++ b/site-setup.sh @@ -12,11 +12,12 @@ export MGLS_LICENSE_FILE=27002@zircon.eng.hmc.edu # Change this to your Siemens license server for Questa export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server for Design Compiler export QUESTA_HOME=/cad/mentor/questa_sim-2023.4/questasim # Change this for your path to Questa, excluding bin -export SNPS_HOME=/cad/synopsys/SYN # Change this for your path to Design Compiler, excluding bin +export DC_HOME=/cad/synopsys/SYN # Change this for your path to Synopsys Design Compiler, excluding bin +export VCS_HOME=/cad/synopsys/vcs/U-2023.03-SP2-4 # Change this for your path to Synopsys VCS, exccluding bin # Tools # Questa and Synopsys -export PATH=$QUESTA_HOME/bin:$SNPS_HOME/bin:$PATH +export PATH=$QUESTA_HOME/bin:$DC_HOME/bin:$VCS_HOME/bin:$PATH # GCC export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$RISCV/riscv-gnu-toolchain/lib:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib diff --git a/src/fpu/postproc/fmashiftcalc.sv b/src/fpu/postproc/fmashiftcalc.sv index 81e7fb6d9..d6d9cec15 100644 --- a/src/fpu/postproc/fmashiftcalc.sv +++ b/src/fpu/postproc/fmashiftcalc.sv @@ -83,23 +83,23 @@ module fmashiftcalc import cvw::*; #(parameter cvw_t P) ( if (P.FPSIZES == 1) begin logic Sum0LEZ, Sum0GEFL; assign Sum0LEZ = PreNormSumExp[P.NE+1] | ~|PreNormSumExp; - assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-2)); + assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-1)); // changed from -2 dh 4/3/24 for issue 655 assign FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL & ~FmaSZero; end else if (P.FPSIZES == 2) begin logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL; assign Sum0LEZ = PreNormSumExp[P.NE+1] | ~|PreNormSumExp; - assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-2)); + assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-1)); // changed from -2 dh 4/3/24 for issue 655 assign Sum1LEZ = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.BIAS1)); - assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF1-2+P.BIAS-P.BIAS1)) | ~|PreNormSumExp; + assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF1-1+P.BIAS-P.BIAS1)) | ~|PreNormSumExp; assign FmaPreResultSubnorm = (Fmt ? Sum0LEZ : Sum1LEZ) & (Fmt ? Sum0GEFL : Sum1GEFL) & ~FmaSZero; end else if (P.FPSIZES == 3) begin logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL, Sum2LEZ, Sum2GEFL; assign Sum0LEZ = PreNormSumExp[P.NE+1] | ~|PreNormSumExp; - assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-2)); + assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-1)); assign Sum1LEZ = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.BIAS1)); - assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF1-2+P.BIAS-P.BIAS1)) | ~|PreNormSumExp; + assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF1-1+P.BIAS-P.BIAS1)) | ~|PreNormSumExp; assign Sum2LEZ = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.BIAS2)); - assign Sum2GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF2-2+P.BIAS-P.BIAS2)) | ~|PreNormSumExp; + assign Sum2GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF2-1+P.BIAS-P.BIAS2)) | ~|PreNormSumExp; always_comb begin case (Fmt) P.FMT: FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL; // & ~FmaSZero; // checking sum is not zero is harmless but turns out to be unnecessary @@ -111,13 +111,13 @@ module fmashiftcalc import cvw::*; #(parameter cvw_t P) ( end else if (P.FPSIZES == 4) begin logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL, Sum2LEZ, Sum2GEFL, Sum3LEZ, Sum3GEFL; assign Sum0LEZ = PreNormSumExp[P.NE+1] | ~|PreNormSumExp; - assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-2)); + assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-1)); assign Sum1LEZ = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.D_BIAS)); - assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.D_NF-2+P.BIAS-P.D_BIAS)) | ~|PreNormSumExp; + assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.D_NF-1+P.BIAS-P.D_BIAS)) | ~|PreNormSumExp; assign Sum2LEZ = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.S_BIAS)); - assign Sum2GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.S_NF-2+P.BIAS-P.S_BIAS)) | ~|PreNormSumExp; + assign Sum2GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.S_NF-1+P.BIAS-P.S_BIAS)) | ~|PreNormSumExp; assign Sum3LEZ = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.H_BIAS)); - assign Sum3GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.H_NF-2+P.BIAS-P.H_BIAS)) | ~|PreNormSumExp; + assign Sum3GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.H_NF-1+P.BIAS-P.H_BIAS)) | ~|PreNormSumExp; always_comb begin case (Fmt) 2'h3: FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL & ~FmaSZero; diff --git a/src/uncore/clint_apb.sv b/src/uncore/clint_apb.sv index 9122c3dab..997c1bd39 100644 --- a/src/uncore/clint_apb.sv +++ b/src/uncore/clint_apb.sv @@ -150,6 +150,7 @@ module clint_apb import cvw::*; #(parameter cvw_t P) ( endmodule +/* module timeregsync import cvw::*; #(parameter cvw_t P) ( input logic clk, resetn, input logic we0, we1, @@ -169,6 +170,7 @@ module timeregsync import cvw::*; #(parameter cvw_t P) ( else q <= q + 1; endmodule + module timereg import cvw::*; #(parameter cvw_t P) ( input logic PCLK, PRESETn, TIMECLK, input logic we0, we1, @@ -245,3 +247,4 @@ module graytobinary #(parameter N) ( assign b[i] = g[i] ^ b[i+1]; end endmodule +*/ \ No newline at end of file diff --git a/src/uncore/uart_apb.sv b/src/uncore/uart_apb.sv index eeecb7ea5..c3f8bb31c 100644 --- a/src/uncore/uart_apb.sv +++ b/src/uncore/uart_apb.sv @@ -60,7 +60,7 @@ module uart_apb import cvw::*; #(parameter cvw_t P) ( else assign PRDATA = {Dout, Dout, Dout, Dout}; logic BAUDOUTb; // loop tx clock BAUDOUTb back to rx clock RCLK - uartPC16550D #(P.UART_PRESCALE) u( + uartPC16550D #(P.UART_PRESCALE) uartPC( // Processor Interface .PCLK, .PRESETn, .A(entry), .Din, diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv index 22e0a35fc..97099d0e2 100644 --- a/src/uncore/uncore.sv +++ b/src/uncore/uncore.sv @@ -139,7 +139,7 @@ module uncore import cvw::*; #(parameter cvw_t P)( end else begin : gpio assign GPIOOUT = 0; assign GPIOEN = 0; assign GPIOIntr = 0; end - if (P.UART_SUPPORTED == 1) begin : uart + if (P.UART_SUPPORTED == 1) begin : uartgen // Hack to work around Verilator bug https://github.com/verilator/verilator/issues/4769 uart_apb #(P) uart( .PCLK, .PRESETn, .PSEL(PSEL[3]), .PADDR(PADDR[2:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, .PRDATA(PRDATA[3]), .PREADY(PREADY[3]), diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv index d82a5c0d4..8e223f858 100644 --- a/src/wally/wallypipelinedsoc.sv +++ b/src/wally/wallypipelinedsoc.sv @@ -79,7 +79,7 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P) ( ); // instantiate uncore if a bus interface exists - if (P.BUS_SUPPORTED) begin : uncore + if (P.BUS_SUPPORTED) begin : uncoregen // Hack to work around Verilator bug https://github.com/verilator/verilator/issues/4769 uncore #(P) uncore(.HCLK, .HRESETn, .TIMECLK, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, .HSELEXTSDC, diff --git a/testbench/common/loggers.sv b/testbench/common/loggers.sv index e4dd1e4fe..4104bd0ec 100644 --- a/testbench/common/loggers.sv +++ b/testbench/common/loggers.sv @@ -27,7 +27,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module loggers import cvw::*; #(parameter cvw_t P, - parameter string TEST, + parameter PrintHPMCounters, parameter I_CACHE_ADDR_LOGGER, parameter D_CACHE_ADDR_LOGGER, @@ -39,7 +39,8 @@ module loggers import cvw::*; #(parameter cvw_t P, // input logic BeginSample, // input logic StartSample, // input logic EndSample, - input string memfilename + input string memfilename, + input string TEST ); // performance counter logging @@ -79,40 +80,64 @@ module loggers import cvw::*; #(parameter cvw_t P, "Divide Cycles" }; + always_comb + if (TEST == "embench") begin + StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_trigger"; + EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_trigger"; + end else if (TEST == "coremark") begin + StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_time"; + EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_time"; + end else begin + StartSampleFirst = reset; + EndSample = DCacheFlushStart & ~DCacheFlushDone; + end + + /* if(TEST == "embench") begin // embench runs warmup then runs start_trigger // embench end with stop_trigger. - assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_trigger"; - flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed); - assign StartSample = StartSampleFirst & ~ StartSampleDelayed; + //assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_trigger"; + //flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed); + //assign StartSample = StartSampleFirst & ~ StartSampleDelayed; - assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_trigger"; + //assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_trigger"; flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed); assign EndSample = EndSampleFirst & ~ EndSampleDelayed; end else if(TEST == "coremark") begin // embench runs warmup then runs start_trigger // embench end with stop_trigger. - assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_time"; - flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed); - assign StartSample = StartSampleFirst & ~ StartSampleDelayed; + //assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_time"; + //flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed); + //assign StartSample = StartSampleFirst & ~ StartSampleDelayed; - assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_time"; + //assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_time"; flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed); assign EndSample = EndSampleFirst & ~ EndSampleDelayed; end else begin // default start condiction is reset // default end condiction is end of test (DCacheFlushDone) - assign StartSampleFirst = reset; - flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed); - assign StartSample = StartSampleFirst & ~ StartSampleDelayed; - assign EndSample = DCacheFlushStart & ~DCacheFlushDone; + //assign StartSampleFirst = reset; + //flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed); + //assign StartSample = StartSampleFirst & ~ StartSampleDelayed; + //assign EndSample = DCacheFlushStart & ~DCacheFlushDone; flop #(1) BeginReg(clk, StartSampleFirst, BeginDelayed); assign BeginSample = StartSampleFirst & ~BeginDelayed; end + + */ + + flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed); + assign StartSample = StartSampleFirst & ~StartSampleDelayed; + flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed); + assign EndSample = EndSampleFirst & ~ EndSampleDelayed; + flop #(1) BeginReg(clk, StartSampleFirst, BeginDelayed); // ** is this redundant with StartSampleReg? + assign BeginSample = StartSampleFirst & ~BeginDelayed; + + always @(negedge clk) begin if(StartSample) begin for(HPMCindex = 0; HPMCindex < 32; HPMCindex += 1) begin diff --git a/testbench/coverage/test_fencei_coverage.svh b/testbench/coverage/test_fencei_coverage.svh new file mode 100644 index 000000000..bb492b1cb --- /dev/null +++ b/testbench/coverage/test_fencei_coverage.svh @@ -0,0 +1,25 @@ +typedef RISCV_instruction #(ILEN, XLEN, FLEN, VLEN, NHART, RETIRE) test_ins_rv64i_t; + +covergroup test_fencei_cg with function sample(test_ins_rv64i_t ins); + option.per_instance = 1; + option.comment = "Fence.I"; + + cp_asm_count : coverpoint ins.ins_str == "fence.i" iff (ins.trap == 0 ) { + option.comment = "Number of times instruction is executed"; + bins count[] = {1}; + } +endgroup + +function void test_fencei_sample(int hart, int issue); + test_ins_rv64i_t ins; + + case (traceDataQ[hart][issue][0].inst_name) + "fenci" : begin + ins = new(hart, issue, traceDataQ); + test_fencei_cg.sample(ins); + end + endcase + +endfunction + + diff --git a/testbench/coverage/test_fencei_coverage_init.svh b/testbench/coverage/test_fencei_coverage_init.svh new file mode 100644 index 000000000..c07507d43 --- /dev/null +++ b/testbench/coverage/test_fencei_coverage_init.svh @@ -0,0 +1,4 @@ +test_fencei_cg = new(); test_fencei_cg.set_inst_name("obj_fencei"); + +// test_fencei_cg = new(); +//test_fencei_cg.set_inst_name("obj_fencei"); diff --git a/testbench/testbench.sv b/testbench/testbench.sv index ee725c245..e16a265ea 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -34,18 +34,20 @@ `endif import cvw::*; +`ifdef VERILATOR +import "DPI-C" function string getenvval(input string env_name); +`else +import "DPI-C" function string getenv(input string env_name); +`endif module testbench; /* verilator lint_off WIDTHTRUNC */ /* verilator lint_off WIDTHEXPAND */ parameter DEBUG=0; - parameter string TEST="arch64m"; parameter PrintHPMCounters=0; parameter BPRED_LOGGER=0; parameter I_CACHE_ADDR_LOGGER=0; parameter D_CACHE_ADDR_LOGGER=0; - parameter RISCV_DIR = "/opt/riscv"; - parameter INSTR_LIMIT = 0; `ifdef USE_IMPERAS_DV import idvPkg::*; @@ -59,6 +61,16 @@ module testbench; logic reset_ext, reset; logic ResetMem; + // Variables that can be overwritten with $value$plusargs at start of simulation + string TEST; + integer INSTR_LIMIT; +`ifdef VERILATOR + string RISCV_DIR = getenvval("RISCV"); // "/opt/riscv"; +`else + string RISCV_DIR = getenv("RISCV"); // "/opt/riscv"; +`endif + // string RISCV_DIR = "/opt/riscv"; + // DUT signals logic [P.AHBW-1:0] HRDATAEXT; logic HREADYEXT, HRESPEXT; @@ -99,9 +111,14 @@ module testbench; logic SelectTest; logic TestComplete; - // pick tests based on modes supported initial begin - $display("TEST is %s", TEST); + // look for arguments passed to simulation, or use defaults + if (!$value$plusargs("TEST=%s", TEST)) + TEST = "none"; + if (!$value$plusargs("INSTR_LIMIT=%d", INSTR_LIMIT)) + INSTR_LIMIT = 0; + + // pick tests based on modes supported //tests = '{}; if (P.XLEN == 64) begin // RV64 case (TEST) @@ -236,7 +253,7 @@ module testbench; logic ResetCntRst; logic CopyRAM; - string signame, memfilename, bootmemfilename, pathname; + string signame, memfilename, bootmemfilename, uartoutfilename, pathname, rmCmd; integer begin_signature_addr, end_signature_addr, signature_size; assign ResetThreshold = 3'd5; @@ -299,15 +316,43 @@ module testbench; // Find the test vector files and populate the PC to function label converter //////////////////////////////////////////////////////////////////////////////// logic [P.XLEN-1:0] testadr; - assign begin_signature_addr = ProgramAddrLabelArray["begin_signature"]; - assign end_signature_addr = ProgramAddrLabelArray["sig_end_canary"]; - assign signature_size = end_signature_addr - begin_signature_addr; + always_comb begin + begin_signature_addr = ProgramAddrLabelArray["begin_signature"]; + end_signature_addr = ProgramAddrLabelArray["sig_end_canary"]; + signature_size = end_signature_addr - begin_signature_addr; + end + logic EcallFaultM; + if (P.ZICSR_SUPPORTED) + assign EcallFaultM = dut.core.priv.priv.EcallFaultM; + else + assign EcallFaultM = 0; always @(posedge clk) begin + //////////////////////////////////////////////////////////////////////////////// + // Verify the test ran correctly by checking the memory against a known signature. + //////////////////////////////////////////////////////////////////////////////// + if(TestBenchReset) test = 1; + if (P.ZICSR_SUPPORTED & TEST == "coremark") + if (EcallFaultM) begin + $display("Benchmark: coremark is done."); + $stop; + end + if (P.ZICSR_SUPPORTED & dut.core.ifu.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.ieu.InstrValidM) begin + $display("Program fetched illegal instruction 0x00000000 from address 0x00000000. Might be fault with no fault handler."); + //$stop; // presently wally32/64priv tests trigger this for reasons not yet understood. + end + + // modifications 4/3/24 kunlin & harris to speed up Verilator + // For some reason, Verilator runs ~100x slower when these SelectTest and Validate codes are in the posedge clk block + //end // added + //always @(posedge SelectTest) // added if(SelectTest) begin if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"}; else if(TEST == "buildroot") begin memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"}; bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"}; + uartoutfilename = {"logs/", TEST, "_uart.out"}; + rmCmd = {"rm -f ", uartoutfilename}; + $system(rmCmd); // Delete existing UARToutfile end else memfilename = {pathname, tests[test], ".elf.memfile"}; if (riscofTest) begin @@ -325,20 +370,14 @@ module testbench; // and initialize them to zero (also initilaize them to zero at the start of the next test) updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray); end - - //////////////////////////////////////////////////////////////////////////////// - // Verify the test ran correctly by checking the memory against a known signature. - //////////////////////////////////////////////////////////////////////////////// - if(TestBenchReset) test = 1; - if (TEST == "coremark") - if (dut.core.priv.priv.EcallFaultM) begin - $display("Benchmark: coremark is done."); - $stop; - end - if (P.ZICSR_SUPPORTED & dut.core.ifu.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.ieu.InstrValidM) begin - $display("Program fetched illegal instruction 0x00000000 from address 0x00000000. Might be fault with no fault handler."); - //$stop; // presently wally32/64priv tests trigger this for reasons not yet understood. - end +`ifdef VERILATOR // this macro is defined when verilator is used + // Simulator Verilator has an issue that the validate logic below slows runtime 110x if it is + // in the posedge clk block rather than a separate posedge Validate block. + // Until it is fixed, provide a silly posedge Validate block to keep Verilator happy. + // https://github.com/verilator/verilator/issues/4967 + end // restored + always @(posedge Validate) // added +`endif if(Validate) begin if (TEST == "embench") begin // Writes contents of begin_signature to .sim.output file @@ -374,10 +413,17 @@ module testbench; if (test == tests.size()) begin if (totalerrors == 0) $display("SUCCESS! All tests ran without failures."); else $display("FAIL: %d test programs had errors", totalerrors); - $stop; // if this is changed to $finish, wally-batch.do does not go to the next step to run coverage +`ifdef VERILATOR // this macro is defined when verilator is used + $finish; // Simulator Verilator needs $finish to terminate simulation. +`else + $stop; // if this is changed to $finish for Questa, wally-batch.do does not go to the next step to run coverage, and wally.do terminates without allowing GUI debug +`endif end end - end +`ifndef VERILATOR + // Remove this when issue 4967 is resolved and the posedge Validate logic above is removed + end +`endif //////////////////////////////////////////////////////////////////////////////// @@ -397,10 +443,10 @@ module testbench; string romfilename, sdcfilename; romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"}; sdcfilename = {"../testbench/sdc/ramdisk2.hex"}; - //$readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM); + //$readmemh(romfilename, dut.uncoregen.uncore.bootrom.bootrom.memory.ROM); //$readmemh(sdcfilename, sdcard.sdcard.FLASHmem); // shorten sdc timers for simulation - //dut.uncore.uncore.sdc.SDC.LimitTimers = 1; + //dut.uncoregen.uncore.sdc.SDC.LimitTimers = 1; end end end else if (P.IROM_SUPPORTED) begin @@ -414,13 +460,13 @@ module testbench; if (LoadMem) begin if (TEST == "buildroot") begin memFile = $fopen(bootmemfilename, "rb"); - readResult = $fread(dut.uncore.uncore.bootrom.bootrom.memory.ROM, memFile); + readResult = $fread(dut.uncoregen.uncore.bootrom.bootrom.memory.ROM, memFile); $fclose(memFile); memFile = $fopen(memfilename, "rb"); - readResult = $fread(dut.uncore.uncore.ram.ram.memory.RAM, memFile); + readResult = $fread(dut.uncoregen.uncore.ram.ram.memory.RAM, memFile); $fclose(memFile); end else - $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); + $readmemh(memfilename, dut.uncoregen.uncore.ram.ram.memory.RAM); if (TEST == "embench") $display("Read memfile %s", memfilename); end if (CopyRAM) begin @@ -429,7 +475,7 @@ module testbench; EndIndex = (end_signature_addr >> LogXLEN) + 8; BaseIndex = P.UNCORE_RAM_BASE >> LogXLEN; for(ShadowIndex = StartIndex; ShadowIndex <= EndIndex; ShadowIndex++) begin - testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.uncore.uncore.ram.ram.memory.RAM[ShadowIndex - BaseIndex]; + testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.uncoregen.uncore.ram.ram.memory.RAM[ShadowIndex - BaseIndex]; end end end @@ -457,7 +503,7 @@ module testbench; always @(posedge clk) if (ResetMem) // program memory is sometimes reset (e.g. for CoreMark, which needs zeroed memory) for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) - dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = 0; + dut.uncoregen.uncore.ram.ram.memory.RAM[adrindex] = 0; //////////////////////////////////////////////////////////////////////////////// // Actual hardware @@ -469,7 +515,7 @@ module testbench; assign SPIIn = 0; if(P.EXT_MEM_SUPPORTED) begin - ram_ahb #(.BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE)) + ram_ahb #(.P(P), .BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE)) ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT), .HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY, .HWSTRB); end else begin @@ -538,8 +584,8 @@ module testbench; ramxdetector #(P.XLEN, P.LLEN) ramxdetector(clk, dut.core.lsu.MemRWM[1], dut.core.lsu.LSULoadAccessFaultM, dut.core.lsu.ReadDataM, dut.core.ifu.PCM, InstrM, dut.core.lsu.IEUAdrM, InstrMName); riscvassertions #(P) riscvassertions(); // check assertions for a legal configuration - loggers #(P, TEST, PrintHPMCounters, I_CACHE_ADDR_LOGGER, D_CACHE_ADDR_LOGGER, BPRED_LOGGER) - loggers (clk, reset, DCacheFlushStart, DCacheFlushDone, memfilename); + loggers #(P, PrintHPMCounters, I_CACHE_ADDR_LOGGER, D_CACHE_ADDR_LOGGER, BPRED_LOGGER) + loggers (clk, reset, DCacheFlushStart, DCacheFlushDone, memfilename, TEST); // track the current function or global label if (DEBUG == 1 | ((PrintHPMCounters | BPRED_LOGGER) & P.ZICNTR_SUPPORTED)) begin : FunctionName @@ -547,6 +593,18 @@ module testbench; .clk(clk), .ProgramAddrMapFile(ProgramAddrMapFile), .ProgramLabelMapFile(ProgramLabelMapFile)); end + // Append UART output to file for tests + if (P.UART_SUPPORTED) begin: uart_logger + always @(posedge clk) begin + if (TEST == "buildroot") begin + if (~dut.uncoregen.uncore.uartgen.uart.MEMWb & dut.uncoregen.uncore.uartgen.uart.uartPC.A == 3'b000 & ~dut.uncoregen.uncore.uartgen.uart.uartPC.DLAB) begin + memFile = $fopen(uartoutfilename, "ab"); + $fwrite(memFile, "%c", dut.uncoregen.uncore.uartgen.uart.uartPC.Din); + $fclose(memFile); + end + end + end + end // Termination condition // terminate on a specific ECALL after li x3,1 for old Imperas tests, *** remove this when old imperas tests are removed @@ -556,7 +614,8 @@ module testbench; logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls if (P.ZICSR_SUPPORTED) assign ecf = dut.core.priv.priv.EcallFaultM; else assign ecf = 0; - assign TestComplete = ecf & + always_comb begin + TestComplete = ecf & (dut.core.ieu.dp.regf.rf[3] == 1 | (dut.core.ieu.dp.regf.we3 & dut.core.ieu.dp.regf.a3 == 3 & @@ -564,15 +623,18 @@ module testbench; ((InstrM == 32'h6f | InstrM == 32'hfc32a423 | InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM ) | ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" ); //assign DCacheFlushStart = TestComplete; + end DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk), .reset(reset), .start(DCacheFlushStart), .done(DCacheFlushDone)); - if(P.ZICSR_SUPPORTED & INSTR_LIMIT != 0) begin + if(P.ZICSR_SUPPORTED) begin logic [P.XLEN-1:0] Minstret; assign Minstret = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]; always @(negedge clk) begin - if((Minstret != 0) && (Minstret % 'd100000 == 0)) $display("Reached %d instructions", Minstret); - if((Minstret == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $stop; $stop; end + if (INSTR_LIMIT > 0) begin + if((Minstret != 0) && (Minstret % 'd100000 == 0)) $display("Reached %d instructions", Minstret); + if((Minstret == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $stop; $stop; end + end end end @@ -756,6 +818,8 @@ end logic [P.XLEN-1:0] signature[0:SIGNATURESIZE]; string signame; logic [P.XLEN-1:0] testadr, testadrNoBase; + + //$display("Invoking CheckSignature %s %s %0t", pathname, TestName, $time); // read .signature.output file and compare to check for errors if (riscofTest) signame = {pathname, TestName, "/ref/Reference-sail_c_simulator.signature"}; @@ -804,20 +868,27 @@ end // Check errors testadr = ($unsigned(begin_signature_addr))/(P.XLEN/8); testadrNoBase = (begin_signature_addr - P.UNCORE_RAM_BASE)/(P.XLEN/8); + // logic UNCORE_RAM_SUPPORTED; + // if(P.UNCORE_RAM_SUPPORTED) + // assign UNCORE_RAM_SUPPORTED = P.UNCORE_RAM_SUPPORTED; + // else + // assign UNCORE_RAM_SUPPORTED = 0; for (i=0; i XLEN ? FLEN-XLEN : XLEN-FLEN){1'b0}}, CmpRes}; + `CVTINTUNIT: if (WriteIntVal) Res = {{(FLEN > XLEN ? FLEN-XLEN : XLEN-FLEN){1'b0}}, IntRes}; else Res = FpRes; `CVTFPUNIT: Res = FpRes; endcase @@ -859,6 +861,10 @@ module testbenchfp; DivStart = 1'b0; nextstate = S0; end + default: begin + DivStart = 1'b0; + nextstate = S0; + end endcase // case (state) end @@ -1149,22 +1155,22 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( 2'b11: begin // quad X = TestVector[12+2*(P.Q_LEN)-1:12+(P.Q_LEN)]; Y = TestVector[12+(P.Q_LEN)-1:12]; - Ans = TestVector[8]; + Ans = {{P.FLEN-1{1'b0}}, TestVector[8]}; end 2'b01: if (P.D_SUPPORTED) begin // double X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[12+2*(P.D_LEN)-1:12+(P.D_LEN)]}; Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[12+(P.D_LEN)-1:12]}; - Ans = TestVector[8]; + Ans = {{P.FLEN-1{1'b0}}, TestVector[8]}; end 2'b00: if (P.S_SUPPORTED) begin // single X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[12+2*(P.S_LEN)-1:12+(P.S_LEN)]}; Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[12+(P.S_LEN)-1:12]}; - Ans = TestVector[8]; + Ans = {{P.FLEN-1{1'b0}}, TestVector[8]}; end 2'b10: begin // half X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[12+2*(P.H_LEN)-1:12+(P.H_LEN)]}; Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[12+(P.H_LEN)-1:12]}; - Ans = TestVector[8]; + Ans = {{P.FLEN-1{1'b0}}, TestVector[8]}; end endcase `CVTFPUNIT: @@ -1254,7 +1260,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( case (Fmt) 2'b11: begin // quad // {is the integer a long, is the opperation to an integer} - casex ({OpCtrl[2:1]}) + casez ({OpCtrl[2:1]}) 2'b11: begin // long -> quad X = {P.FLEN{1'bx}}; SrcA = TestVector[8+P.Q_LEN+P.XLEN-1:8+(P.Q_LEN)]; @@ -1269,18 +1275,18 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( 2'b01: begin // quad -> long X = {TestVector[8+P.XLEN+P.Q_LEN-1:8+(P.XLEN)]}; SrcA = {P.XLEN{1'bx}}; - Ans = {TestVector[8+(P.XLEN-1):8]}; + Ans = {{(P.FLEN > 64 ? P.FLEN-64 : 0){1'b0}}, TestVector[8+(P.XLEN-1):8]}; end 2'b00: begin // quad -> int X = {TestVector[8+32+P.Q_LEN-1:8+(32)]}; SrcA = {P.XLEN{1'bx}}; - Ans = {{P.XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; + Ans = {{P.FLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; end endcase end 2'b01: if (P.D_SUPPORTED) begin // double // {Int->Fp?, is the integer a long} - casex ({OpCtrl[2:1]}) + casez ({OpCtrl[2:1]}) 2'b11: begin // long -> double X = {P.FLEN{1'bx}}; SrcA = TestVector[8+P.D_LEN+P.XLEN-1:8+(P.D_LEN)]; @@ -1295,18 +1301,18 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( 2'b01: begin // double -> long X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+P.XLEN+P.D_LEN-1:8+(P.XLEN)]}; SrcA = {P.XLEN{1'bx}}; - Ans = {TestVector[8+(P.XLEN-1):8]}; + Ans = {{(P.FLEN-64){1'b0}}, TestVector[8+(P.XLEN-1):8]}; end 2'b00: begin // double -> int X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+32+P.D_LEN-1:8+(32)]}; SrcA = {P.XLEN{1'bx}}; - Ans = {{P.XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; + Ans = {{P.FLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; end endcase end 2'b00: if (P.S_SUPPORTED) begin // single // {is the integer a long, is the opperation to an integer} - casex ({OpCtrl[2:1]}) + casez ({OpCtrl[2:1]}) 2'b11: begin // long -> single X = {P.FLEN{1'bx}}; SrcA = TestVector[8+P.S_LEN+P.XLEN-1:8+(P.S_LEN)]; @@ -1321,18 +1327,18 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( 2'b01: begin // single -> long X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.XLEN+P.S_LEN-1:8+(P.XLEN)]}; SrcA = {P.XLEN{1'bx}}; - Ans = {TestVector[8+(P.XLEN-1):8]}; + Ans = {{(P.FLEN > 64 ? P.FLEN-64 : 0){1'b0}}, TestVector[8+(P.XLEN-1):8]}; end 2'b00: begin // single -> int X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+32+P.S_LEN-1:8+(32)]}; SrcA = {P.XLEN{1'bx}}; - Ans = {{P.XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; + Ans = {{P.FLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; end endcase end 2'b10: begin // half // {is the integer a long, is the opperation to an integer} - casex ({OpCtrl[2:1]}) + casez ({OpCtrl[2:1]}) 2'b11: begin // long -> half X = {P.FLEN{1'bx}}; SrcA = TestVector[8+P.H_LEN+P.XLEN-1:8+(P.H_LEN)]; @@ -1347,12 +1353,12 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( 2'b01: begin // half -> long X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.XLEN+P.H_LEN-1:8+(P.XLEN)]}; SrcA = {P.XLEN{1'bx}}; - Ans = {TestVector[8+(P.XLEN-1):8]}; + Ans = {{(P.FLEN > 64 ? P.FLEN-64 : 0){1'b0}}, TestVector[8+(P.XLEN-1):8]}; end 2'b00: begin // half -> int X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+32+P.H_LEN-1:8+(32)]}; SrcA = {P.XLEN{1'bx}}; - Ans = {{P.XLEN-32{TestVector[8+32-1]}}, TestVector[8+(32-1):8]}; + Ans = {{P.FLEN-32{TestVector[8+32-1]}}, TestVector[8+(32-1):8]}; end endcase end diff --git a/testbench/tests.vh b/testbench/tests.vh index 6958fc50d..8dfd69415 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -35,12 +35,12 @@ string tvpaths[] = '{ "$RISCV/imperas-riscv-tests/work/", - "../tests/riscof/work/riscv-arch-test/", - "../tests/riscof/work/wally-riscv-arch-test/", - "../benchmarks/coremark/work/", - "../addins/embench-iot/", - "../tests/custom/work/", - "../tests/coverage/" + "../../tests/riscof/work/riscv-arch-test/", + "../../tests/riscof/work/wally-riscv-arch-test/", + "../../benchmarks/coremark/work/", + "../../addins/embench-iot/", + "../../tests/custom/work/", + "../../tests/coverage/" }; string coverage64gc[] = '{ diff --git a/testbench/tests-fp.vh b/testbench/tests_fp.vh similarity index 99% rename from testbench/tests-fp.vh rename to testbench/tests_fp.vh index e29cc8447..4c0e9cda5 100644 --- a/testbench/tests-fp.vh +++ b/testbench/tests_fp.vh @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// tests0fo.vh +// tests_fp.vh // // Written: Katherine Parry 2022 // Modified: @@ -24,7 +24,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`define PATH "../tests/fp/vectors/" +`define PATH "../../tests/fp/vectors/" `define ADD_OPCTRL 3'b110 `define MUL_OPCTRL 3'b100 `define SUB_OPCTRL 3'b111 diff --git a/tests/riscof/spike/spike_rv64gc_isa.yaml b/tests/riscof/spike/spike_rv64gc_isa.yaml index f7e6b8c73..b8fabebde 100644 --- a/tests/riscof/spike/spike_rv64gc_isa.yaml +++ b/tests/riscof/spike/spike_rv64gc_isa.yaml @@ -27,7 +27,7 @@ hart0: warl: dependency_fields: [] legal: - - extensions[25:0] bitmask [0x014112D, 0x0000000] + - extensions[25:0] bitmask [0x015112D, 0x0000000] wr_illegal: - Unchanged