From fa087aeb30831e376445ce41a94d0cc3f4959846 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Tue, 10 Jan 2023 11:19:28 -0600 Subject: [PATCH 01/22] Initial commit for the boot process. --- pipelined/config/fpga/wally-config.vh | 4 + .../src/uncore/newsdc/axi_sdc_controller.v | 661 ++++++++++++++++++ pipelined/src/uncore/newsdc/license.txt | 502 +++++++++++++ pipelined/src/uncore/newsdc/sd_cmd_master.v | 152 ++++ .../src/uncore/newsdc/sd_cmd_serial_host.v | 263 +++++++ pipelined/src/uncore/newsdc/sd_data_master.v | 150 ++++ .../src/uncore/newsdc/sd_data_serial_host.v | 311 ++++++++ pipelined/src/uncore/newsdc/sd_defines.h | 91 +++ pipelined/src/uncore/uncore.sv | 2 + tests/custom/boot/Makefile | 112 +++ tests/custom/boot/boot.c | 370 ++++++++++ 11 files changed, 2618 insertions(+) create mode 100644 pipelined/src/uncore/newsdc/axi_sdc_controller.v create mode 100644 pipelined/src/uncore/newsdc/license.txt create mode 100644 pipelined/src/uncore/newsdc/sd_cmd_master.v create mode 100644 pipelined/src/uncore/newsdc/sd_cmd_serial_host.v create mode 100644 pipelined/src/uncore/newsdc/sd_data_master.v create mode 100644 pipelined/src/uncore/newsdc/sd_data_serial_host.v create mode 100644 pipelined/src/uncore/newsdc/sd_defines.h create mode 100644 tests/custom/boot/Makefile create mode 100644 tests/custom/boot/boot.c diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh index c786950de..b16721d34 100644 --- a/pipelined/config/fpga/wally-config.vh +++ b/pipelined/config/fpga/wally-config.vh @@ -122,6 +122,10 @@ `define SDC_BASE 56'h00012100 `define SDC_RANGE 56'h0000001F +// Temporary Boot Process Stuff +`define SDC2_BASE 56'h00013000 +`defube SDC2_RANGE 56'h0000007F + // Bus Interface width `define AHBW 64 diff --git a/pipelined/src/uncore/newsdc/axi_sdc_controller.v b/pipelined/src/uncore/newsdc/axi_sdc_controller.v new file mode 100644 index 000000000..989c05881 --- /dev/null +++ b/pipelined/src/uncore/newsdc/axi_sdc_controller.v @@ -0,0 +1,661 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2013-2022 Authors //// +//// //// +//// Based on original work by //// +//// Adam Edvardsson (adam.edvardsson@orsoc.se) //// +//// //// +//// Copyright (C) 2009 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from https://www.gnu.org/licenses/ //// +//// //// +////////////////////////////////////////////////////////////////////// + +module sdc_controller #( + parameter dma_addr_bits = 32, + parameter fifo_addr_bits = 7, + parameter sdio_card_detect_level = 1, + parameter voltage_controll_reg = 3300, + parameter capabilies_reg = 16'b0000_0000_0000_0011 +) ( + input wire async_resetn, + + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clock CLK" *) + (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF M_AXI:S_AXI_LITE, FREQ_HZ 100000000" *) + input wire clock, + + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR" *) + (* X_INTERFACE_PARAMETER = "CLK_DOMAIN clock, ID_WIDTH 0, PROTOCOL AXI4LITE, DATA_WIDTH 32" *) + input wire [15:0] s_axi_awaddr, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID" *) + input wire s_axi_awvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY" *) + output wire s_axi_awready, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA" *) + input wire [31:0] s_axi_wdata, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID" *) + input wire s_axi_wvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY" *) + output wire s_axi_wready, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP" *) + output reg [1:0] s_axi_bresp, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID" *) + output reg s_axi_bvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY" *) + input wire s_axi_bready, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR" *) + input wire [15:0] s_axi_araddr, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID" *) + input wire s_axi_arvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY" *) + output wire s_axi_arready, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA" *) + output reg [31:0] s_axi_rdata, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP" *) + output reg [1:0] s_axi_rresp, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID" *) + output reg s_axi_rvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY" *) + input wire s_axi_rready, + + (* X_INTERFACE_PARAMETER = "CLK_DOMAIN clock, ID_WIDTH 0, PROTOCOL AXI4, DATA_WIDTH 32" *) + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) + output reg [dma_addr_bits-1:0] m_axi_awaddr, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *) + output reg [7:0] m_axi_awlen, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) + output reg m_axi_awvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) + input wire m_axi_awready, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) + output wire [31:0] m_axi_wdata, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *) + output reg m_axi_wlast, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) + output reg m_axi_wvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) + input wire m_axi_wready, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) + input wire [1:0] m_axi_bresp, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) + input wire m_axi_bvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) + output wire m_axi_bready, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) + output reg [dma_addr_bits-1:0] m_axi_araddr, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *) + output reg [7:0] m_axi_arlen, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) + output reg m_axi_arvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) + input wire m_axi_arready, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) + input wire [31:0] m_axi_rdata, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *) + input wire m_axi_rlast, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) + input wire [1:0] m_axi_rresp, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) + input wire m_axi_rvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) + output wire m_axi_rready, + + // SD BUS + inout wire sdio_cmd, + inout wire [3:0] sdio_dat, + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 sdio_clk CLK" *) + (* X_INTERFACE_PARAMETER = "FREQ_HZ 50000000" *) + output reg sdio_clk, + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 sdio_reset RST" *) + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_HIGH" *) + output reg sdio_reset, + input wire sdio_cd, + + // Interrupts + output wire interrupt +); + +`include "sd_defines.h" + +wire reset; + +wire go_idle; +reg cmd_start; +wire [1:0] cmd_setting; +wire cmd_start_tx; +wire [39:0] cmd; +wire [119:0] cmd_response; +wire cmd_crc_ok; +wire cmd_index_ok; +wire cmd_finish; + +wire d_write; +wire d_read; +wire [31:0] data_in_rx_fifo; +wire en_tx_fifo; +wire en_rx_fifo; +wire sd_data_busy; +wire data_busy; +wire data_crc_ok; +wire tx_fifo_re; +wire rx_fifo_we; + +reg data_start_rx; +reg data_start_tx; +reg data_prepare_tx; +reg cmd_int_rst; +reg data_int_rst; +reg ctrl_rst; + +// AXI accessible registers +reg [31:0] argument_reg; +reg [`CMD_REG_SIZE-1:0] command_reg; +reg [`CMD_TIMEOUT_W-1:0] cmd_timeout_reg; +reg [`DATA_TIMEOUT_W-1:0] data_timeout_reg; +reg [0:0] software_reset_reg; +wire [31:0] response_0_reg; +wire [31:0] response_1_reg; +wire [31:0] response_2_reg; +wire [31:0] response_3_reg; +reg [`BLKSIZE_W-1:0] block_size_reg; +reg [1:0] controller_setting_reg; +wire [`INT_CMD_SIZE-1:0] cmd_int_status_reg; +wire [`INT_DATA_SIZE-1:0] data_int_status_reg; +wire [`INT_DATA_SIZE-1:0] data_int_status; +reg [`INT_CMD_SIZE-1:0] cmd_int_enable_reg; +reg [`INT_DATA_SIZE-1:0] data_int_enable_reg; +reg [`BLKCNT_W-1:0] block_count_reg; +reg [dma_addr_bits-1:0] dma_addr_reg; +reg [7:0] clock_divider_reg = 124; // 400KHz + +// ------ Clocks and resets + +(* ASYNC_REG="true" *) +reg [2:0] reset_sync; +assign reset = reset_sync[2]; + +always @(posedge clock) + reset_sync <= {reset_sync[1:0], !async_resetn}; + +reg [7:0] clock_cnt; +reg clock_state; +reg clock_posedge; +reg clock_data_in; +wire fifo_almost_full; +wire fifo_almost_empty; + +always @(posedge clock) begin + if (reset) begin + clock_posedge <= 0; + clock_data_in <= 0; + clock_state <= 0; + clock_cnt <= 0; + end else if (clock_cnt < clock_divider_reg) begin + clock_posedge <= 0; + clock_data_in <= 0; + clock_cnt <= clock_cnt + 1; + end else if (clock_cnt < 124 && data_busy && en_rx_fifo && fifo_almost_full) begin + // Prevent Rx FIFO overflow + clock_posedge <= 0; + clock_data_in <= 0; + clock_cnt <= clock_cnt + 1; + end else if (clock_cnt < 124 && data_busy && en_tx_fifo && fifo_almost_empty) begin + // Prevent Tx FIFO underflow + clock_posedge <= 0; + clock_data_in <= 0; + clock_cnt <= clock_cnt + 1; + end else begin + clock_state <= !clock_state; + clock_posedge <= !clock_state; + if (clock_divider_reg == 0) + clock_data_in <= !clock_state; + else + clock_data_in <= clock_state; + clock_cnt <= 0; + end + sdio_clk <= sdio_reset || clock_state; + + if (reset) sdio_reset <= 0; + else if (clock_posedge) sdio_reset <= controller_setting_reg[1]; +end + +// ------ SD IO Buffers + +wire sd_cmd_i; +wire sd_cmd_o; +wire sd_cmd_oe; +reg sd_cmd_reg_o; +reg sd_cmd_reg_t; +wire [3:0] sd_dat_i; +wire [3:0] sd_dat_o; +wire sd_dat_oe; +reg [3:0] sd_dat_reg_o; +reg sd_dat_reg_t; + +IOBUF IOBUF_cmd (.O(sd_cmd_i), .IO(sdio_cmd), .I(sd_cmd_reg_o), .T(sd_cmd_reg_t)); +IOBUF IOBUF_dat0 (.O(sd_dat_i[0]), .IO(sdio_dat[0]), .I(sd_dat_reg_o[0]), .T(sd_dat_reg_t)); +IOBUF IOBUF_dat1 (.O(sd_dat_i[1]), .IO(sdio_dat[1]), .I(sd_dat_reg_o[1]), .T(sd_dat_reg_t)); +IOBUF IOBUF_dat2 (.O(sd_dat_i[2]), .IO(sdio_dat[2]), .I(sd_dat_reg_o[2]), .T(sd_dat_reg_t)); +IOBUF IOBUF_dat3 (.O(sd_dat_i[3]), .IO(sdio_dat[3]), .I(sd_dat_reg_o[3]), .T(sd_dat_reg_t)); + +always @(negedge clock) begin + // Output data delayed by 1/2 clock cycle (5ns) to ensure + // required hold time: default speed - min 5ns, high speed - min 2ns (actual 5ns) + if (sdio_reset) begin + sd_cmd_reg_o <= 0; + sd_dat_reg_o <= 0; + sd_cmd_reg_t <= 0; + sd_dat_reg_t <= 0; + end else begin + sd_cmd_reg_o <= sd_cmd_o; + sd_dat_reg_o <= sd_dat_o; + sd_cmd_reg_t <= !sd_cmd_oe; + sd_dat_reg_t <= !(sd_dat_oe || (cmd_start_tx && (command_reg == 0))); + end +end + +// ------ SD card detect + +reg [25:0] sd_detect_cnt; +wire sd_insert_int = sd_detect_cnt[25]; +wire sd_remove_int = !sd_detect_cnt[25]; +reg sd_insert_ie; +reg sd_remove_ie; + +always @(posedge clock) begin + if (sdio_cd != sdio_card_detect_level) begin + sd_detect_cnt <= 0; + end else if (!sd_insert_int) begin + sd_detect_cnt <= sd_detect_cnt + 1; + end +end + +// ------ AXI Slave Interface + +reg [15:0] read_addr; +reg [15:0] write_addr; +reg [31:0] write_data; +reg rd_req; +reg [1:0] wr_req; + +assign s_axi_arready = !rd_req && !s_axi_rvalid; +assign s_axi_awready = !wr_req[0] && !s_axi_bvalid; +assign s_axi_wready = !wr_req[1] && !s_axi_bvalid; + +always @(posedge clock) begin + if (reset) begin + s_axi_rdata <= 0; + s_axi_rresp <= 0; + s_axi_rvalid <= 0; + s_axi_bresp <= 0; + s_axi_bvalid <= 0; + rd_req <= 0; + wr_req <= 0; + read_addr <= 0; + write_addr <= 0; + write_data <= 0; + cmd_start <= 0; + data_int_rst <= 0; + cmd_int_rst <= 0; + ctrl_rst <= 0; + argument_reg <= 0; + command_reg <= 0; + cmd_timeout_reg <= 0; + data_timeout_reg <= 0; + block_size_reg <= `RESET_BLOCK_SIZE; + controller_setting_reg <= 0; + cmd_int_enable_reg <= 0; + data_int_enable_reg <= 0; + software_reset_reg <= 0; + clock_divider_reg <= `RESET_CLOCK_DIV; + block_count_reg <= 0; + sd_insert_ie <= 0; + sd_remove_ie <= 0; + dma_addr_reg <= 0; + end else begin + if (clock_posedge) begin + cmd_start <= 0; + data_int_rst <= 0; + cmd_int_rst <= 0; + ctrl_rst <= software_reset_reg[0]; + end + if (s_axi_arready && s_axi_arvalid) begin + read_addr <= s_axi_araddr; + rd_req <= 1; + end + if (s_axi_rvalid && s_axi_rready) begin + s_axi_rvalid <= 0; + end else if (!s_axi_rvalid && rd_req) begin + s_axi_rdata <= 0; + if (read_addr[15:8] == 0) begin + case (read_addr[7:0]) + `argument : s_axi_rdata <= argument_reg; + `command : s_axi_rdata <= command_reg; + `resp0 : s_axi_rdata <= response_0_reg; + `resp1 : s_axi_rdata <= response_1_reg; + `resp2 : s_axi_rdata <= response_2_reg; + `resp3 : s_axi_rdata <= response_3_reg; + `controller : s_axi_rdata <= controller_setting_reg; + `blksize : s_axi_rdata <= block_size_reg; + `voltage : s_axi_rdata <= voltage_controll_reg; + `capa : s_axi_rdata <= capabilies_reg | (dma_addr_bits << 8); + `clock_d : s_axi_rdata <= clock_divider_reg; + `reset : s_axi_rdata <= { cmd_start, data_int_rst, cmd_int_rst, ctrl_rst }; + `cmd_timeout : s_axi_rdata <= cmd_timeout_reg; + `data_timeout : s_axi_rdata <= data_timeout_reg; + `cmd_isr : s_axi_rdata <= cmd_int_status_reg; + `cmd_iser : s_axi_rdata <= cmd_int_enable_reg; + `data_isr : s_axi_rdata <= data_int_status_reg; + `data_iser : s_axi_rdata <= data_int_enable_reg; + `blkcnt : s_axi_rdata <= block_count_reg; + `card_detect : s_axi_rdata <= { sd_remove_int, sd_remove_ie, sd_insert_int, sd_insert_ie }; + `dst_src_addr : s_axi_rdata <= dma_addr_reg[31:0]; + `dst_src_addr_high : if (dma_addr_bits > 32) s_axi_rdata <= dma_addr_reg[dma_addr_bits-1:32]; + endcase + end + s_axi_rresp <= 0; + s_axi_rvalid <= 1; + rd_req <= 0; + end + if (s_axi_awready && s_axi_awvalid) begin + write_addr <= s_axi_awaddr; + wr_req[0] <= 1; + end + if (s_axi_wready && s_axi_wvalid) begin + write_data <= s_axi_wdata; + wr_req[1] <= 1; + end + if (s_axi_bvalid && s_axi_bready) begin + s_axi_bvalid <= 0; + end else if (!s_axi_bvalid && wr_req == 2'b11) begin + if (write_addr[15:8] == 0) begin + case (write_addr[7:0]) + `argument : begin argument_reg <= write_data; cmd_start <= 1; end + `command : command_reg <= write_data; + `reset : software_reset_reg <= write_data; + `cmd_timeout : cmd_timeout_reg <= write_data; + `data_timeout : data_timeout_reg <= write_data; + `blksize : block_size_reg <= write_data; + `controller : controller_setting_reg <= write_data; + `cmd_isr : cmd_int_rst <= 1; + `cmd_iser : cmd_int_enable_reg <= write_data; + `clock_d : clock_divider_reg <= write_data; + `data_isr : data_int_rst <= 1; + `data_iser : data_int_enable_reg <= write_data; + `blkcnt : block_count_reg <= write_data; + `card_detect : begin sd_remove_ie <= write_data[2]; sd_insert_ie <= write_data[0]; end + `dst_src_addr : dma_addr_reg[31:0] <= write_data; + `dst_src_addr_high : if (dma_addr_bits > 32) dma_addr_reg[dma_addr_bits-1:32] <= write_data; + endcase + end + s_axi_bresp <= 0; + s_axi_bvalid <= 1; + wr_req <= 0; + end + end +end + +// ------ Data FIFO + +reg [31:0] fifo_mem [(1<= (1 << fifo_addr_bits) / 2; +wire [31:0] fifo_din = en_rx_fifo ? data_in_rx_fifo : m_bus_dat_i; +wire fifo_we = en_rx_fifo ? rx_fifo_we && clock_posedge : m_axi_rready && m_axi_rvalid; +wire fifo_re = en_rx_fifo ? m_axi_wready && m_axi_wvalid : tx_fifo_re && clock_posedge; +reg [31:0] fifo_dout; + +assign fifo_almost_full = fifo_data_len > (1 << fifo_addr_bits) * 3 / 4; +assign fifo_almost_empty = fifo_free_len > (1 << fifo_addr_bits) * 3 / 4; + +wire tx_stb = en_tx_fifo && fifo_free_len >= (1 << fifo_addr_bits) / 3; +wire rx_stb = en_rx_fifo && m_axi_bresp_cnt != 3'b111 && (fifo_data_len >= (1 << fifo_addr_bits) / 3 || (!fifo_empty && !data_busy)); + +always @(posedge clock) + if (reset || ctrl_rst || !(en_rx_fifo || en_tx_fifo)) begin + fifo_inp_pos <= 0; + fifo_out_pos <= 0; + end else begin + if (fifo_we && !fifo_full) begin + fifo_mem[fifo_inp_pos] <= fifo_din; + fifo_inp_pos <= fifo_inp_nxt; + if (fifo_empty) fifo_dout <= fifo_din; + end + if (fifo_re && !fifo_empty) begin + if (fifo_we && !fifo_full && fifo_out_nxt == fifo_inp_pos) fifo_dout <= fifo_din; + else fifo_dout <= fifo_mem[fifo_out_nxt]; + fifo_out_pos <= fifo_out_nxt; + end + end + +// ------ AXI Master Interface + +// AXI transaction (DDR access) is over 80 clock cycles +// Must use burst to achive required throughput + +reg m_axi_cyc; +wire m_axi_write = en_rx_fifo; +reg [7:0] m_axi_wcnt; +reg [dma_addr_bits-1:2] m_bus_adr_o; +wire [31:0] m_bus_dat_i; +reg [2:0] m_axi_bresp_cnt; +reg m_bus_error; + +assign m_axi_bready = m_axi_bresp_cnt != 0; +assign m_axi_rready = m_axi_cyc & !m_axi_write; +assign m_bus_dat_i = {m_axi_rdata[7:0],m_axi_rdata[15:8],m_axi_rdata[23:16],m_axi_rdata[31:24]}; +assign m_axi_wdata = {fifo_dout[7:0],fifo_dout[15:8],fifo_dout[23:16],fifo_dout[31:24]}; + +// AXI burst cannot cross a 4KB boundary +wire [fifo_addr_bits-1:0] tx_burst_len; +wire [fifo_addr_bits-1:0] rx_burst_len; +assign tx_burst_len = m_bus_adr_o[11:2] + fifo_free_len >= m_bus_adr_o[11:2] ? fifo_free_len - 1 : ~m_bus_adr_o[fifo_addr_bits+1:2]; +assign rx_burst_len = m_bus_adr_o[11:2] + fifo_data_len >= m_bus_adr_o[11:2] ? fifo_data_len - 1 : ~m_bus_adr_o[fifo_addr_bits+1:2]; + +assign data_int_status_reg = { data_int_status[`INT_DATA_SIZE-1:1], + !en_rx_fifo && !en_tx_fifo && !m_axi_cyc && m_axi_bresp_cnt == 0 && data_int_status[0] }; + +always @(posedge clock) begin + if (reset | ctrl_rst) begin + m_axi_arvalid <= 0; + m_axi_awvalid <= 0; + m_axi_wvalid <= 0; + m_axi_cyc <= 0; + end else if (m_axi_cyc) begin + if (m_axi_awvalid && m_axi_awready) begin + m_axi_awvalid <= 0; + end + if (m_axi_arvalid && m_axi_arready) begin + m_axi_arvalid <= 0; + end + if (m_axi_wvalid && m_axi_wready) begin + if (m_axi_wlast) begin + m_axi_wvalid <= 0; + m_axi_cyc <= 0; + end else begin + m_axi_wlast <= m_axi_wcnt + 1 == m_axi_awlen; + m_axi_wcnt <= m_axi_wcnt + 1; + end + end + if (m_axi_rvalid && m_axi_rready && m_axi_rlast) begin + m_axi_cyc <= 0; + end + end else if (tx_stb || rx_stb) begin + m_axi_cyc <= 1; + m_axi_wcnt <= 0; + if (m_axi_write) begin + m_axi_awaddr <= { m_bus_adr_o, 2'b00 }; + m_axi_awlen <= rx_burst_len < 8'hff ? rx_burst_len : 8'hff; + m_axi_wlast <= rx_burst_len == 0; + m_axi_awvalid <= 1; + m_axi_wvalid <= 1; + end else begin + m_axi_araddr <= { m_bus_adr_o, 2'b00 }; + m_axi_arlen <= tx_burst_len < 8'hff ? tx_burst_len : 8'hff; + m_axi_arvalid <= 1; + end + end + if (reset | ctrl_rst) begin + m_bus_adr_o <= 0; + end else if ((m_axi_wready && m_axi_wvalid) || (m_axi_rready && m_axi_rvalid)) begin + m_bus_adr_o <= m_bus_adr_o + 1; + end else if (!m_axi_cyc && !en_rx_fifo && !en_tx_fifo) begin + m_bus_adr_o <= dma_addr_reg[dma_addr_bits-1:2]; + end + if (reset | ctrl_rst) begin + m_axi_bresp_cnt <= 0; + end else if ((m_axi_awvalid && m_axi_awready) && !(m_axi_bvalid && m_axi_bready)) begin + m_axi_bresp_cnt <= m_axi_bresp_cnt + 1; + end else if (!(m_axi_awvalid && m_axi_awready) && (m_axi_bvalid && m_axi_bready)) begin + m_axi_bresp_cnt <= m_axi_bresp_cnt - 1; + end + if (reset | ctrl_rst | cmd_start) begin + m_bus_error <= 0; + end else if (m_axi_bvalid && m_axi_bready && m_axi_bresp) begin + m_bus_error <= 1; + end else if (m_axi_rvalid && m_axi_rready && m_axi_rresp) begin + m_bus_error <= 1; + end + if (reset | ctrl_rst) begin + data_start_tx <= 0; + data_start_rx <= 0; + data_prepare_tx <= 0; + end else if (clock_posedge) begin + data_start_tx <= 0; + data_start_rx <= 0; + if (cmd_start) begin + data_prepare_tx <= 0; + if (command_reg[`CMD_WITH_DATA] == 2'b01) data_start_rx <= 1; + else if (command_reg[`CMD_WITH_DATA] != 2'b00) data_prepare_tx <= 1; + end else if (data_prepare_tx) begin + if (cmd_int_status_reg[`INT_CMD_CC]) begin + data_prepare_tx <= 0; + data_start_tx <= 1; + end else if (cmd_int_status_reg[`INT_CMD_EI]) begin + data_prepare_tx <= 0; + end + end + end +end + +// ------ SD Card Interface + +sd_cmd_master sd_cmd_master0( + .clock (clock), + .clock_posedge (clock_posedge), + .reset (reset | ctrl_rst), + .start (cmd_start), + .int_status_rst (cmd_int_rst), + .setting (cmd_setting), + .start_xfr (cmd_start_tx), + .go_idle (go_idle), + .cmd (cmd), + .response (cmd_response), + .crc_error (!cmd_crc_ok), + .index_ok (cmd_index_ok), + .busy (sd_data_busy), + .finish (cmd_finish), + .argument (argument_reg), + .command (command_reg), + .timeout (cmd_timeout_reg), + .int_status (cmd_int_status_reg), + .response_0 (response_0_reg), + .response_1 (response_1_reg), + .response_2 (response_2_reg), + .response_3 (response_3_reg) + ); + +sd_cmd_serial_host cmd_serial_host0( + .clock (clock), + .clock_posedge (clock_posedge), + .clock_data_in (clock_data_in), + .reset (reset | ctrl_rst | go_idle), + .setting (cmd_setting), + .cmd (cmd), + .start (cmd_start_tx), + .finish (cmd_finish), + .response (cmd_response), + .crc_ok (cmd_crc_ok), + .index_ok (cmd_index_ok), + .cmd_i (sd_cmd_i), + .cmd_o (sd_cmd_o), + .cmd_oe (sd_cmd_oe) + ); + +sd_data_master sd_data_master0( + .clock (clock), + .clock_posedge (clock_posedge), + .reset (reset | ctrl_rst), + .start_tx (data_start_tx), + .start_rx (data_start_rx), + .timeout (data_timeout_reg), + .d_write (d_write), + .d_read (d_read), + .en_tx_fifo (en_tx_fifo), + .en_rx_fifo (en_rx_fifo), + .fifo_empty (fifo_empty), + .fifo_ready (fifo_ready), + .fifo_full (fifo_full), + .bus_cycle (m_axi_cyc || m_axi_bresp_cnt != 0), + .xfr_complete (!data_busy), + .crc_error (!data_crc_ok), + .bus_error (m_bus_error), + .int_status (data_int_status), + .int_status_rst (data_int_rst) + ); + +sd_data_serial_host sd_data_serial_host0( + .clock (clock), + .clock_posedge (clock_posedge), + .clock_data_in (clock_data_in), + .reset (reset | ctrl_rst), + .data_in (fifo_dout), + .rd (tx_fifo_re), + .data_out (data_in_rx_fifo), + .we (rx_fifo_we), + .dat_oe (sd_dat_oe), + .dat_o (sd_dat_o), + .dat_i (sd_dat_i), + .blksize (block_size_reg), + .bus_4bit (controller_setting_reg[0]), + .blkcnt (block_count_reg), + .start ({d_read, d_write}), + .byte_alignment (dma_addr_reg[1:0]), + .sd_data_busy (sd_data_busy), + .busy (data_busy), + .crc_ok (data_crc_ok) + ); + +assign interrupt = + |(cmd_int_status_reg & cmd_int_enable_reg) || + |(data_int_status_reg & data_int_enable_reg) || + (sd_insert_int & sd_insert_ie) || + (sd_remove_int & sd_remove_ie); + +endmodule diff --git a/pipelined/src/uncore/newsdc/license.txt b/pipelined/src/uncore/newsdc/license.txt new file mode 100644 index 000000000..4362b4915 --- /dev/null +++ b/pipelined/src/uncore/newsdc/license.txt @@ -0,0 +1,502 @@ + GNU LESSER GENERAL PUBLIC LICENSE + Version 2.1, February 1999 + + Copyright (C) 1991, 1999 Free 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See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +Also add information on how to contact you by electronic and paper mail. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the library, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the + library `Frob' (a library for tweaking knobs) written by James Random Hacker. + + , 1 April 1990 + Ty Coon, President of Vice + +That's all there is to it! diff --git a/pipelined/src/uncore/newsdc/sd_cmd_master.v b/pipelined/src/uncore/newsdc/sd_cmd_master.v new file mode 100644 index 000000000..6b46c786d --- /dev/null +++ b/pipelined/src/uncore/newsdc/sd_cmd_master.v @@ -0,0 +1,152 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2013-2022 Authors //// +//// //// +//// Based on original work by //// +//// Adam Edvardsson (adam.edvardsson@orsoc.se) //// +//// //// +//// Copyright (C) 2009 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from https://www.gnu.org/licenses/ //// +//// //// +////////////////////////////////////////////////////////////////////// +`include "sd_defines.h" + +module sd_cmd_master( + input clock, + input clock_posedge, + input reset, + input start, + input int_status_rst, + output [1:0] setting, + output reg start_xfr, + output reg go_idle, + output reg [39:0] cmd, + input [119:0] response, + input crc_error, + input index_ok, + input finish, + input busy, // direct signal from data sd data input (data[0]) + //input card_detect, + input [31:0] argument, + input [`CMD_REG_SIZE-1:0] command, + input [`CMD_TIMEOUT_W-1:0] timeout, + output [`INT_CMD_SIZE-1:0] int_status, + output reg [31:0] response_0, + output reg [31:0] response_1, + output reg [31:0] response_2, + output reg [31:0] response_3 +); + +reg expect_response; +reg long_response; +reg [`INT_CMD_SIZE-1:0] int_status_reg; +reg [`CMD_TIMEOUT_W-1:0] watchdog; +reg watchdog_enable; + +reg [2:0] state; +parameter IDLE = 3'b001; +parameter EXECUTE = 3'b010; +parameter BUSY_CHECK = 3'b100; + +assign setting[1:0] = {long_response, expect_response}; +assign int_status = state == IDLE ? int_status_reg : 5'h0; + +always @(posedge clock) begin + if (reset) begin + response_0 <= 0; + response_1 <= 0; + response_2 <= 0; + response_3 <= 0; + int_status_reg <= 0; + expect_response <= 0; + long_response <= 0; + cmd <= 0; + start_xfr <= 0; + watchdog <= 0; + watchdog_enable <= 0; + go_idle <= 0; + state <= IDLE; + end else if (clock_posedge) begin + case (state) + IDLE: begin + go_idle <= 0; + if (command[`CMD_RESPONSE_CHECK] == 2'b10 || command[`CMD_RESPONSE_CHECK] == 2'b11) begin + expect_response <= 1; + long_response <= 1; + end else if (command[`CMD_RESPONSE_CHECK] == 2'b01) begin + expect_response <= 1; + long_response <= 0; + end else begin + expect_response <= 0; + long_response <= 0; + end + cmd[39:38] <= 2'b01; + cmd[37:32] <= command[`CMD_INDEX]; + cmd[31:0] <= argument; + watchdog <= 0; + watchdog_enable <= timeout != 0; + if (start) begin + start_xfr <= 1; + int_status_reg <= 0; + state <= EXECUTE; + end + end + EXECUTE: begin + start_xfr <= 0; + if (watchdog_enable && watchdog >= timeout) begin + int_status_reg[`INT_CMD_CTE] <= 1; + int_status_reg[`INT_CMD_EI] <= 1; + go_idle <= 1; + state <= IDLE; + end else if (finish) begin + if (command[`CMD_CRC_CHECK] && crc_error) begin + int_status_reg[`INT_CMD_CCRCE] <= 1; + int_status_reg[`INT_CMD_EI] <= 1; + end + if (command[`CMD_IDX_CHECK] && !index_ok) begin + int_status_reg[`INT_CMD_CIE] <= 1; + int_status_reg[`INT_CMD_EI] <= 1; + end + int_status_reg[`INT_CMD_CC] <= 1; + if (expect_response) begin + response_0 <= response[119:88]; + response_1 <= response[87:56]; + response_2 <= response[55:24]; + response_3 <= {response[23:0], 8'h00}; + end + if (command[`CMD_BUSY_CHECK]) state <= BUSY_CHECK; + else state <= IDLE; + end else if (watchdog_enable) begin + watchdog <= watchdog + 1; + end + end + BUSY_CHECK: begin + if (!busy) state <= IDLE; + end + endcase + if (int_status_rst) + int_status_reg <= 0; + end +end + +endmodule diff --git a/pipelined/src/uncore/newsdc/sd_cmd_serial_host.v b/pipelined/src/uncore/newsdc/sd_cmd_serial_host.v new file mode 100644 index 000000000..0cebb4f2e --- /dev/null +++ b/pipelined/src/uncore/newsdc/sd_cmd_serial_host.v @@ -0,0 +1,263 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2013-2022 Authors //// +//// //// +//// Based on original work by //// +//// Adam Edvardsson (adam.edvardsson@orsoc.se) //// +//// //// +//// Copyright (C) 2009 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from https://www.gnu.org/licenses/ //// +//// //// +////////////////////////////////////////////////////////////////////// + +module sd_cmd_serial_host ( + //---------------Input ports--------------- + input clock, + input clock_posedge, + input clock_data_in, + input reset, + input [1:0] setting, + input [39:0] cmd, + input start, + input cmd_i, + //---------------Output ports--------------- + output reg [119:0] response, + output reg finish, + output reg crc_ok, + output reg index_ok, + output reg cmd_oe, + output reg cmd_o +); + +//-------------Internal Constant------------- +parameter INIT_DELAY = 4; +parameter BITS_TO_SEND = 48; +parameter CMD_SIZE = 40; +parameter RESP_SIZE = 128; + +//---------------Internal variable----------- +reg cmd_dat_reg; +integer resp_len; +reg with_response; +reg [CMD_SIZE-1:0] cmd_buff; +reg [RESP_SIZE-1:0] resp_buff; +integer resp_idx; +//CRC +reg crc_rst; +reg [6:0]crc_in; +wire [6:0] crc_val; +reg crc_enable; +reg crc_bit; +reg crc_match; +//-Internal Counterns +integer counter; +//-State Machine +parameter + STATE_SIZE = 8, + INIT = 8'b00000001, + IDLE = 8'b00000010, + SETUP_CRC = 8'b00000100, + WRITE = 8'b00001000, + READ_WAIT = 8'b00010000, + READ = 8'b00100000, + FINISH_WR = 8'b01000000, + FINISH_WO = 8'b10000000; +reg [STATE_SIZE-1:0] state; + +//Misc +`define cmd_idx (CMD_SIZE-1-counter) + +//sd cmd input pad register +always @(posedge clock) begin + if (clock_data_in) cmd_dat_reg <= cmd_i; +end + +//------------------------------------------ +sd_crc_7 CRC_7( + crc_bit, + crc_enable & clock_posedge, + clock, + crc_rst, + crc_val); + +//------------------------------------------ + +always @(posedge clock) begin + if (reset) begin + resp_len <= 0; + with_response <= 0; + cmd_buff <= 0; + crc_enable <= 0; + resp_idx <= 0; + cmd_oe <= 1; + cmd_o <= 1; + resp_buff <= 0; + finish <= 0; + crc_rst <= 1; + crc_bit <= 0; + crc_in <= 0; + response <= 0; + index_ok <= 0; + crc_ok <= 0; + crc_match <= 0; + counter <= 0; + state <= INIT; + end else if (clock_posedge) begin + case (state) + INIT: begin + counter <= counter+1; + // Pull cmd line up + cmd_oe <= 1; + cmd_o <= 1; + if (counter >= INIT_DELAY) state <= IDLE; + end + IDLE: begin + cmd_oe <= 0; + counter <= 0; + crc_rst <= 1; + crc_enable <= 0; + response <= 0; + resp_idx <= 0; + crc_ok <= 0; + index_ok <= 0; + finish <= 0; + if (start) begin + resp_len <= setting[1] ? 127 : 39; + with_response <= setting[0]; + cmd_buff <= cmd; + state <= SETUP_CRC; + end + end + SETUP_CRC: begin + crc_rst <= 0; + crc_enable <= 1; + crc_bit <= cmd_buff[`cmd_idx]; + state <= WRITE; + end + WRITE: begin + if (counter < BITS_TO_SEND-8) begin // 1->40 CMD, (41 >= CNT && CNT <=47) CRC, 48 stop_bit + cmd_oe <= 1; + cmd_o <= cmd_buff[`cmd_idx]; + if (counter < BITS_TO_SEND-9) begin //1 step ahead + crc_bit <= cmd_buff[`cmd_idx-1]; + end else begin + crc_enable <= 0; + end + end else if (counter < BITS_TO_SEND-1) begin + cmd_oe <= 1; + crc_enable <= 0; + cmd_o <= crc_val[BITS_TO_SEND-counter-2]; + end else if (counter == BITS_TO_SEND-1) begin + cmd_oe <= 1; + cmd_o <= 1'b1; + end else begin + cmd_oe <= 0; + cmd_o <= 1'b1; + end + counter <= counter + 1; + if (counter >= BITS_TO_SEND && with_response) state <= READ_WAIT; + else if (counter >= BITS_TO_SEND) state <= FINISH_WO; + end + READ_WAIT: begin + crc_enable <= 0; + crc_rst <= 1; + counter <= 1; + cmd_oe <= 0; + resp_buff[RESP_SIZE-1] <= cmd_dat_reg; + if (!cmd_dat_reg) state <= READ; + end + FINISH_WO: begin + finish <= 1; + crc_enable <= 0; + crc_rst <= 1; + counter <= 0; + cmd_oe <= 0; + state <= IDLE; + end + READ: begin + crc_rst <= 0; + crc_enable <= (resp_len != RESP_SIZE-1 || counter > 7); + cmd_oe <= 0; + if (counter <= resp_len) begin + if (counter < 8) //1+1+6 (S,T,Index) + resp_buff[RESP_SIZE-1-counter] <= cmd_dat_reg; + else begin + resp_idx <= resp_idx + 1; + resp_buff[RESP_SIZE-9-resp_idx] <= cmd_dat_reg; + end + crc_bit <= cmd_dat_reg; + end else if (counter-resp_len <= 7) begin + crc_in[(resp_len+7)-(counter)] <= cmd_dat_reg; + crc_enable <= 0; + end else begin + crc_enable <= 0; + crc_match <= crc_in == crc_val; + end + counter <= counter + 1; + if (counter >= resp_len+8) state <= FINISH_WR; + end + FINISH_WR: begin + index_ok <= cmd_buff[37:32] == resp_buff[125:120]; + crc_ok <= crc_match; + finish <= 1; + crc_enable <= 0; + crc_rst <= 1; + counter <= 0; + cmd_oe <= 0; + response <= resp_buff[119:0]; + state <= IDLE; + end + default: + state <= INIT; + endcase + end +end + +endmodule + +module sd_crc_7( + input BITVAL, // Next input bit + input ENABLE, // Enable calculation + input BITSTRB, // Current bit valid (Clock) + input CLEAR, // Init CRC value + output reg [6:0] CRC // Current output CRC value +); + +wire inv; +assign inv = BITVAL ^ CRC[6]; + +always @(posedge BITSTRB or posedge CLEAR) begin + if (CLEAR) begin + CRC <= 0; + end else if (ENABLE == 1) begin + CRC[6] <= CRC[5]; + CRC[5] <= CRC[4]; + CRC[4] <= CRC[3]; + CRC[3] <= CRC[2] ^ inv; + CRC[2] <= CRC[1]; + CRC[1] <= CRC[0]; + CRC[0] <= inv; + end +end + +endmodule diff --git a/pipelined/src/uncore/newsdc/sd_data_master.v b/pipelined/src/uncore/newsdc/sd_data_master.v new file mode 100644 index 000000000..c85d7ea7a --- /dev/null +++ b/pipelined/src/uncore/newsdc/sd_data_master.v @@ -0,0 +1,150 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2013-2022 Authors //// +//// //// +//// Based on original work by //// +//// Adam Edvardsson (adam.edvardsson@orsoc.se) //// +//// //// +//// Copyright (C) 2009 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from https://www.gnu.org/licenses/ //// +//// //// +////////////////////////////////////////////////////////////////////// +`include "sd_defines.h" + +module sd_data_master ( + input clock, + input clock_posedge, + input reset, + input start_tx, + input start_rx, + input [`DATA_TIMEOUT_W-1:0] timeout, + // Output to SD-Host Reg + output reg d_write, + output reg d_read, + // To fifo filler + output reg en_tx_fifo, + output reg en_rx_fifo, + input fifo_empty, + input fifo_ready, + input fifo_full, + input bus_cycle, + // SD-DATA_Host + input xfr_complete, + input crc_error, + input bus_error, + // status output + output reg [`INT_DATA_SIZE-1:0] int_status, + input int_status_rst +); + +reg [3:0] state; +localparam IDLE = 4'b0001; +localparam START_TX_FIFO = 4'b0010; +localparam START_RX_FIFO = 4'b0100; +localparam DATA_TRANSFER = 4'b1000; + +reg [`DATA_TIMEOUT_W-1:0] watchdog; +reg watchdog_enable; + +always @(posedge clock) begin + if (reset) begin + en_tx_fifo <= 0; + en_rx_fifo <= 0; + d_write <= 0; + d_read <= 0; + int_status <= 0; + watchdog <= 0; + watchdog_enable <= 0; + state <= IDLE; + end else if (clock_posedge) begin + case (state) + IDLE: begin + en_tx_fifo <= 0; + en_rx_fifo <= 0; + d_write <= 0; + d_read <= 0; + watchdog <= 0; + watchdog_enable <= timeout != 0; + if (start_tx) state <= START_TX_FIFO; + else if (start_rx) state <= START_RX_FIFO; + end + START_RX_FIFO: begin + en_rx_fifo <= 1; + en_tx_fifo <= 0; + d_read <= 1; + if (!xfr_complete) state <= DATA_TRANSFER; + end + START_TX_FIFO: begin + en_rx_fifo <= 0; + en_tx_fifo <= 1; + if (fifo_ready) begin + d_write <= 1; + if (!xfr_complete) state <= DATA_TRANSFER; + end + end + DATA_TRANSFER: begin + d_read <= 0; + d_write <= 0; + if (en_tx_fifo && fifo_empty) begin + int_status[`INT_DATA_CFE] <= 1; + int_status[`INT_DATA_EI] <= 1; + state <= IDLE; + // stop sd_data_serial_host + d_write <= 1; + d_read <= 1; + end else if (en_rx_fifo && fifo_full) begin + int_status[`INT_DATA_CFE] <= 1; + int_status[`INT_DATA_EI] <= 1; + state <= IDLE; + // stop sd_data_serial_host + d_write <= 1; + d_read <= 1; + end else if (watchdog_enable && watchdog >= timeout) begin + int_status[`INT_DATA_CTE] <= 1; + int_status[`INT_DATA_EI] <= 1; + state <= IDLE; + // stop sd_data_serial_host + d_write <= 1; + d_read <= 1; + end else if (xfr_complete && !bus_cycle && (en_tx_fifo || fifo_empty)) begin + state <= IDLE; + if (crc_error) begin + int_status[`INT_DATA_CCRCE] <= 1; + int_status[`INT_DATA_EI] <= 1; + end + if (bus_error) begin + int_status[`INT_DATA_CBE] <= 1; + int_status[`INT_DATA_EI] <= 1; + end + int_status[`INT_DATA_CC] <= 1; + end else if (watchdog_enable) begin + watchdog <= watchdog + 1; + end + end + endcase + if (int_status_rst) + int_status <= 0; + end +end + +endmodule diff --git a/pipelined/src/uncore/newsdc/sd_data_serial_host.v b/pipelined/src/uncore/newsdc/sd_data_serial_host.v new file mode 100644 index 000000000..9a35e5a88 --- /dev/null +++ b/pipelined/src/uncore/newsdc/sd_data_serial_host.v @@ -0,0 +1,311 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2013-2022 Authors //// +//// //// +//// Based on original work by //// +//// Adam Edvardsson (adam.edvardsson@orsoc.se) //// +//// //// +//// Copyright (C) 2009 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from https://www.gnu.org/licenses/ //// +//// //// +////////////////////////////////////////////////////////////////////// +`include "sd_defines.h" + +module sd_data_serial_host( + input clock, + input clock_posedge, + input clock_data_in, + input reset, + // Tx Fifo + input [31:0] data_in, + output reg rd, + // Rx Fifo + output reg [31:0] data_out, + output reg we, + // tristate data + output reg dat_oe, + output reg[3:0] dat_o, + input [3:0] dat_i, + // Controll signals + input [`BLKSIZE_W-1:0] blksize, + input bus_4bit, + input [`BLKCNT_W-1:0] blkcnt, + input [1:0] start, + input [1:0] byte_alignment, + output sd_data_busy, + output busy, + output reg crc_ok +); + +reg [3:0] DAT_dat_reg; +reg bus_4bit_reg; +reg crc_en; +reg crc_rst; +wire [15:0] crc_out [3:0]; +reg [`BLKSIZE_W+4-1:0] data_cycles; +reg [`BLKSIZE_W+4-1:0] transf_cnt; +reg [3:0] drt_bit; +reg [3:0] drt_reg; +reg [`BLKCNT_W-1:0] blkcnt_reg; +reg [1:0] byte_alignment_reg; +reg [3:0] crc_bit; +reg [3:0] last_din; +reg [4:0] data_index; + +reg [6:0] state; +parameter IDLE = 7'b0000001; +parameter WRITE_DAT = 7'b0000010; +parameter WRITE_WAIT = 7'b0000100; +parameter WRITE_DRT = 7'b0001000; +parameter WRITE_BUSY = 7'b0010000; +parameter READ_WAIT = 7'b0100000; +parameter READ_DAT = 7'b1000000; + +// sd data input pad register +always @(posedge clock) begin + if (clock_data_in) DAT_dat_reg <= dat_i; +end + +genvar i; +generate + for (i=0; i<4; i=i+1) begin: CRC_16_gen + sd_crc_16 CRC_16_i (last_din[i], crc_en & clock_posedge, clock, crc_rst, crc_out[i]); + end +endgenerate + +assign busy = (state != IDLE); +assign sd_data_busy = !DAT_dat_reg[0]; + +always @(posedge clock) begin + if (reset) begin + state <= IDLE; + dat_oe <= 0; + crc_en <= 0; + crc_rst <= 1; + transf_cnt <= 0; + rd <= 0; + last_din <= 0; + crc_bit <= 0; + dat_o <= 4'b1111; + drt_bit <= 0; + drt_reg <= 0; + we <= 0; + data_out <= 0; + crc_ok <= 0; + data_index <= 0; + blkcnt_reg <= 0; + byte_alignment_reg <= 0; + data_cycles <= 0; + bus_4bit_reg <= 0; + end else if (clock_posedge) begin + case (state) + IDLE: begin + dat_oe <= 0; + dat_o <= 4'b1111; + transf_cnt <= 0; + crc_en <= 0; + crc_rst <= 1; + crc_bit <= 15; + we <= 0; + rd <= 0; + data_index <= 0; + blkcnt_reg <= blkcnt; + byte_alignment_reg <= byte_alignment; + data_cycles <= (bus_4bit ? {3'b000, blksize, 1'b0} + 2 : {1'b0, blksize, 3'b000} + 8); + bus_4bit_reg <= bus_4bit; + if (start == 2'b01) state <= WRITE_DAT; + else if (start == 2'b10) state <= READ_WAIT; + end + WRITE_DAT: begin + rd <= 0; + transf_cnt <= transf_cnt + 16'h1; + if (transf_cnt == 0) begin + crc_ok <= 0; + crc_bit <= 15; + end else if (transf_cnt == 1) begin + crc_rst <= 0; + crc_en <= 1; + if (bus_4bit_reg) begin + last_din <= { + data_in[31-(byte_alignment_reg << 3)], + data_in[30-(byte_alignment_reg << 3)], + data_in[29-(byte_alignment_reg << 3)], + data_in[28-(byte_alignment_reg << 3)] + }; + end else begin + last_din <= {3'h7, data_in[31-(byte_alignment_reg << 3)]}; + end + dat_oe <= 1; + dat_o <= bus_4bit_reg ? 4'h0 : 4'he; + data_index <= bus_4bit_reg ? {2'b00, byte_alignment_reg, 1'b1} : {byte_alignment_reg, 3'b001}; + end else if (transf_cnt <= data_cycles+1) begin + if (bus_4bit_reg) begin + last_din <= { + data_in[31-(data_index[2:0]<<2)], + data_in[30-(data_index[2:0]<<2)], + data_in[29-(data_index[2:0]<<2)], + data_in[28-(data_index[2:0]<<2)] + }; + if (data_index[2:0] == 3'h6 && transf_cnt <= data_cycles-1) rd <= 1; + end else begin + last_din <= {3'h7, data_in[31-data_index]}; + if (data_index == 30) rd <= 1; + end + data_index <= data_index + 5'h1; + dat_o <= last_din; + if (transf_cnt == data_cycles+1) crc_en <= 0; + end else if (transf_cnt <= data_cycles+17) begin + crc_en <= 0; + dat_o[0] <= crc_out[0][crc_bit]; + if (bus_4bit_reg) + dat_o[3:1] <= {crc_out[3][crc_bit], crc_out[2][crc_bit], crc_out[1][crc_bit]}; + crc_bit <= crc_bit - 1; + end else if (transf_cnt == data_cycles+18) begin + dat_o <= 4'hf; + end else if (transf_cnt == data_cycles+19) begin + dat_oe <= 0; + end else begin + state <= WRITE_WAIT; + end + end + WRITE_WAIT: begin + drt_bit <= 0; + if (!DAT_dat_reg[0]) state <= WRITE_DRT; + end + WRITE_DRT: begin + // See 7.3.3.1 Data Response Token + if (drt_bit <= 3) begin + drt_reg[drt_bit] <= DAT_dat_reg[0]; + end else if (drt_bit == 15) begin + crc_ok <= drt_reg[3:0] == 4'b1010; + state <= WRITE_BUSY; + end + drt_bit <= drt_bit + 1; + end + WRITE_BUSY: begin + if (DAT_dat_reg[0]) begin + if (blkcnt_reg != 0 && crc_ok) begin + transf_cnt <= 0; + blkcnt_reg <= blkcnt_reg - 1; + byte_alignment_reg <= byte_alignment_reg + blksize[1:0] + 2'b1; + crc_rst <= 1; + state <= WRITE_DAT; + end else begin + state <= IDLE; + end + end + end + READ_WAIT: begin + dat_oe <= 0; + crc_bit <= 15; + last_din <= 0; + transf_cnt <= 0; + data_index <= bus_4bit_reg ? (byte_alignment_reg << 1) : (byte_alignment_reg << 3); + if (!DAT_dat_reg[0]) begin + crc_rst <= 0; + crc_en <= 1; + state <= READ_DAT; + end + end + READ_DAT: begin + last_din <= DAT_dat_reg; + transf_cnt <= transf_cnt + 16'h1; + if (transf_cnt < data_cycles) begin + if (bus_4bit_reg) begin + we <= (data_index[2:0] == 7 || (transf_cnt == data_cycles-1 && !blkcnt_reg)); + data_out[31-(data_index[2:0]<<2)] <= DAT_dat_reg[3]; + data_out[30-(data_index[2:0]<<2)] <= DAT_dat_reg[2]; + data_out[29-(data_index[2:0]<<2)] <= DAT_dat_reg[1]; + data_out[28-(data_index[2:0]<<2)] <= DAT_dat_reg[0]; + end else begin + we <= (data_index == 31 || (transf_cnt == data_cycles-1 && !blkcnt_reg)); + data_out[31-data_index] <= DAT_dat_reg[0]; + end + data_index <= data_index + 5'h1; + crc_ok <= 1; + end else if (transf_cnt == data_cycles) begin + crc_en <= 0; + we <= 0; + end else if (transf_cnt <= data_cycles+16) begin + if (crc_out[0][crc_bit] != last_din[0]) crc_ok <= 0; + if (bus_4bit_reg) begin + if (crc_out[1][crc_bit] != last_din[1]) crc_ok <= 0; + if (crc_out[2][crc_bit] != last_din[2]) crc_ok <= 0; + if (crc_out[3][crc_bit] != last_din[3]) crc_ok <= 0; + end + if (crc_bit == 0) begin + byte_alignment_reg <= byte_alignment_reg + blksize[1:0] + 2'b1; + crc_rst <= 1; + end else begin + crc_bit <= crc_bit - 1; + end + end else if (blkcnt_reg != 0 && crc_ok) begin + blkcnt_reg <= blkcnt_reg - 1; + state <= READ_WAIT; + end else begin + state <= IDLE; + end + end + default: + state <= IDLE; + endcase + if (start == 2'b11) state <= IDLE; // Abort + end +end + +endmodule + +module sd_crc_16( + input BITVAL, // Next input bit + input ENABLE, // Enable calculation + input BITSTRB, // Current bit valid (Clock) + input CLEAR, // Init CRC value + output reg [15:0] CRC // Current output CRC value +); + +assign inv = BITVAL ^ CRC[15]; + +always @(posedge BITSTRB) begin + if (CLEAR) begin + CRC <= 0; + end else if (ENABLE == 1) begin + CRC[15] <= CRC[14]; + CRC[14] <= CRC[13]; + CRC[13] <= CRC[12]; + CRC[12] <= CRC[11] ^ inv; + CRC[11] <= CRC[10]; + CRC[10] <= CRC[9]; + CRC[9] <= CRC[8]; + CRC[8] <= CRC[7]; + CRC[7] <= CRC[6]; + CRC[6] <= CRC[5]; + CRC[5] <= CRC[4] ^ inv; + CRC[4] <= CRC[3]; + CRC[3] <= CRC[2]; + CRC[2] <= CRC[1]; + CRC[1] <= CRC[0]; + CRC[0] <= inv; + end +end + +endmodule diff --git a/pipelined/src/uncore/newsdc/sd_defines.h b/pipelined/src/uncore/newsdc/sd_defines.h new file mode 100644 index 000000000..9afbde475 --- /dev/null +++ b/pipelined/src/uncore/newsdc/sd_defines.h @@ -0,0 +1,91 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2013-2022 Authors //// +//// //// +//// Based on original work by //// +//// Adam Edvardsson (adam.edvardsson@orsoc.se) //// +//// //// +//// Copyright (C) 2009 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from https://www.gnu.org/licenses/ //// +//// //// +////////////////////////////////////////////////////////////////////// + +// global defines +`define BLKSIZE_W 12 +`define BLKCNT_W 16 +`define CMD_TIMEOUT_W 25 +`define DATA_TIMEOUT_W 28 + +// cmd module interrupts +`define INT_CMD_SIZE 5 +`define INT_CMD_CC 0 +`define INT_CMD_EI 1 +`define INT_CMD_CTE 2 +`define INT_CMD_CCRCE 3 +`define INT_CMD_CIE 4 + +// data module interrupts +`define INT_DATA_SIZE 6 +`define INT_DATA_CC 0 +`define INT_DATA_EI 1 +`define INT_DATA_CTE 2 // Timeout +`define INT_DATA_CCRCE 3 // CRC error +`define INT_DATA_CFE 4 // FIFO error +`define INT_DATA_CBE 5 // Bus error + +// command register defines +`define CMD_REG_SIZE 14 +`define CMD_RESPONSE_CHECK 1:0 +`define CMD_BUSY_CHECK 2 +`define CMD_CRC_CHECK 3 +`define CMD_IDX_CHECK 4 +`define CMD_WITH_DATA 6:5 +`define CMD_INDEX 13:8 + +// register addreses +`define argument 8'h00 +`define command 8'h04 +`define resp0 8'h08 +`define resp1 8'h0c +`define resp2 8'h10 +`define resp3 8'h14 +`define data_timeout 8'h18 +`define controller 8'h1c +`define cmd_timeout 8'h20 +`define clock_d 8'h24 +`define reset 8'h28 +`define voltage 8'h2c +`define capa 8'h30 +`define cmd_isr 8'h34 +`define cmd_iser 8'h38 +`define data_isr 8'h3c +`define data_iser 8'h40 +`define blksize 8'h44 +`define blkcnt 8'h48 +`define card_detect 8'h4c +`define dst_src_addr 8'h60 +`define dst_src_addr_high 8'h64 + +// register contents +`define RESET_BLOCK_SIZE 12'd511 +`define RESET_CLOCK_DIV 124 diff --git a/pipelined/src/uncore/uncore.sv b/pipelined/src/uncore/uncore.sv index 34c33426c..3cde211c5 100644 --- a/pipelined/src/uncore/uncore.sv +++ b/pipelined/src/uncore/uncore.sv @@ -31,6 +31,8 @@ `include "wally-config.vh" +// *** need idiom to map onto cache RAM with byte writes +// *** and use memread signal to reduce power when reads aren't needed module uncore ( // AHB Bus Interface input logic HCLK, HRESETn, diff --git a/tests/custom/boot/Makefile b/tests/custom/boot/Makefile new file mode 100644 index 000000000..6dec9c797 --- /dev/null +++ b/tests/custom/boot/Makefile @@ -0,0 +1,112 @@ +CEXT := c +CPPEXT := cpp +AEXT := s +SEXT := S +SRCEXT := \([$(CEXT)$(AEXT)$(SEXT)]\|$(CPPEXT)\) +OBJEXT := o +DEPEXT := d +SRCDIR := . +BUILDDIR := OBJ + +SOURCES ?= $(shell find $(SRCDIR) -type f -regex ".*\.$(SRCEXT)" | sort) +OBJECTS := $(SOURCES:.$(CEXT)=.$(OBJEXT)) +OBJECTS := $(OBJECTS:.$(AEXT)=.$(OBJEXT)) +OBJECTS := $(OBJECTS:.$(SEXT)=.$(OBJEXT)) +OBJECTS := $(OBJECTS:.$(CPPEXT)=.$(OBJEXT)) +OBJECTS := $(patsubst $(SRCDIR)/%,$(BUILDDIR)/%,$(OBJECTS)) + +TARGETDIR := bin +TARGET := $(TARGETDIR)/fpga-test-sdc +ROOT := .. +LIBRARY_DIRS := +LIBRARY_FILES := + +MARCH :=-march=rv64imfdc +MABI :=-mabi=lp64d +LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles +LINKER :=linker.x + + +AFLAGS =$(MARCH) $(MABI) -W +CFLAGS =$(MARCH) $(MABI) -mcmodel=medany -O2 +AS=riscv64-unknown-elf-as +CC=riscv64-unknown-elf-gcc +AR=riscv64-unknown-elf-ar + + +#Default Make +all: directories $(TARGET).memfile + +#Remake +remake: clean all + +#Make the Directories +directories: + @mkdir -p $(TARGETDIR) + @mkdir -p $(BUILDDIR) + +clean: + rm -rf $(BUILDDIR) $(TARGETDIR) *.memfile *.objdump + + +#Needed for building additional library projects +ifdef LIBRARY_DIRS +LIBS+=${LIBRARY_DIRS:%=-L%} ${LIBRARY_FILES:%=-l%} +INC+=${LIBRARY_DIRS:%=-I%} + +${LIBRARY_DIRS}: + make -C $@ -j 1 + +.PHONY: $(LIBRARY_DIRS) $(TARGET) +endif + + +#Pull in dependency info for *existing* .o files +-include $(OBJECTS:.$(OBJEXT)=.$(DEPEXT)) + +#Link +$(TARGET): $(OBJECTS) $(LIBRARY_DIRS) + $(CC) $(LINK_FLAGS) -g -o $(TARGET) $(OBJECTS) ${LIBS} -T ${LINKER} + + +#Compile +$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(CEXT) + @mkdir -p $(dir $@) + $(CC) $(CFLAGS) $(INC) -c -o $@ $< > $(BUILDDIR)/$*.list + @$(CC) $(CFLAGS) $(INC) -MM $(SRCDIR)/$*.$(CEXT) > $(BUILDDIR)/$*.$(DEPEXT) + @cp -f $(BUILDDIR)/$*.$(DEPEXT) $(BUILDDIR)/$*.$(DEPEXT).tmp + @sed -e 's|.*:|$(BUILDDIR)/$*.$(OBJEXT):|' < $(BUILDDIR)/$*.$(DEPEXT).tmp > $(BUILDDIR)/$*.$(DEPEXT) + @sed -e 's/.*://' -e 's/\\$$//' < $(BUILDDIR)/$*.$(DEPEXT).tmp | fmt -1 | sed -e 's/^ *//' -e 's/$$/:/' >> $(BUILDDIR)/$*.$(DEPEXT) + @rm -f $(BUILDDIR)/$*.$(DEPEXT).tmp + +# gcc won't output dependencies for assembly files for some reason +# most asm files don't have dependencies so the echo will work for now. +$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(AEXT) + @mkdir -p $(dir $@) + $(CC) $(CFLAGS) -c -o $@ $< > $(BUILDDIR)/$*.list + @echo $@: $< > $(BUILDDIR)/$*.$(DEPEXT) + +$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(SEXT) + @mkdir -p $(dir $@) + $(CC) $(CFLAGS) $(INC) -c -o $@ $< > $(BUILDDIR)/$*.list + @echo $@: $< > $(BUILDDIR)/$*.$(DEPEXT) + +# C++ +$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(CPPEXT) + @mkdir -p $(dir $@) + $(CC) $(CFLAGS) $(INC) -c -o $@ $< > $(BUILDDIR)/$*.list + @$(CC) $(CFLAGS) $(INC) -MM $(SRCDIR)/$*.$(CPPEXT) > $(BUILDDIR)/$*.$(DEPEXT) + @cp -f $(BUILDDIR)/$*.$(DEPEXT) $(BUILDDIR)/$*.$(DEPEXT).tmp + @sed -e 's|.*:|$(BUILDDIR)/$*.$(OBJEXT):|' < $(BUILDDIR)/$*.$(DEPEXT).tmp > $(BUILDDIR)/$*.$(DEPEXT) + @sed -e 's/.*://' -e 's/\\$$//' < $(BUILDDIR)/$*.$(DEPEXT).tmp | fmt -1 | sed -e 's/^ *//' -e 's/$$/:/' >> $(BUILDDIR)/$*.$(DEPEXT) + @rm -f $(BUILDDIR)/$*.$(DEPEXT).tmp + +# convert to hex +$(TARGET).memfile: $(TARGET) + @echo 'Making object dump file.' + @riscv64-unknown-elf-objdump -D $< > $<.objdump + @echo 'Making memory file' + riscv64-unknown-elf-elf2hex --bit-width 64 --input $^ --output $@ + extractFunctionRadix.sh $<.objdump + mkdir -p ../../imperas-riscv-tests/work/rv64BP/ + cp -f $(TARGETDIR)/* ../../imperas-riscv-tests/work/rv64BP/ diff --git a/tests/custom/boot/boot.c b/tests/custom/boot/boot.c new file mode 100644 index 000000000..71f22534f --- /dev/null +++ b/tests/custom/boot/boot.c @@ -0,0 +1,370 @@ + + +/* Card type flags (card_type) */ +#define CT_MMC 0x01 /* MMC ver 3 */ +#define CT_SD1 0x02 /* SD ver 1 */ +#define CT_SD2 0x04 /* SD ver 2 */ +#define CT_SDC (CT_SD1|CT_SD2) /* SD */ +#define CT_BLOCK 0x08 /* Block addressing */ + +#define CMD0 (0) /* GO_IDLE_STATE */ +#define CMD1 (1) /* SEND_OP_COND */ +#define CMD2 (2) /* SEND_CID */ +#define CMD3 (3) /* RELATIVE_ADDR */ +#define CMD4 (4) +#define CMD5 (5) /* SLEEP_WAKE (SDC) */ +#define CMD6 (6) /* SWITCH_FUNC */ +#define CMD7 (7) /* SELECT */ +#define CMD8 (8) /* SEND_IF_COND */ +#define CMD9 (9) /* SEND_CSD */ +#define CMD10 (10) /* SEND_CID */ +#define CMD11 (11) +#define CMD12 (12) /* STOP_TRANSMISSION */ +#define CMD13 (13) +#define CMD15 (15) +#define CMD16 (16) /* SET_BLOCKLEN */ +#define CMD17 (17) /* READ_SINGLE_BLOCK */ +#define CMD18 (18) /* READ_MULTIPLE_BLOCK */ +#define CMD19 (19) +#define CMD20 (20) +#define CMD23 (23) +#define CMD24 (24) +#define CMD25 (25) +#define CMD27 (27) +#define CMD28 (28) +#define CMD29 (29) +#define CMD30 (30) +#define CMD32 (32) +#define CMD33 (33) +#define CMD38 (38) +#define CMD42 (42) +#define CMD55 (55) /* APP_CMD */ +#define CMD56 (56) +#define ACMD6 (0x80+6) /* define the data bus width */ +#define ACMD41 (0x80+41) /* SEND_OP_COND (ACMD) */ + +// Capability bits +#define SDC_CAPABILITY_SD_4BIT 0x0001 +#define SDC_CAPABILITY_SD_RESET 0x0002 +#define SDC_CAPABILITY_ADDR 0xff00 + +// Control bits +#define SDC_CONTROL_SD_4BIT 0x0001 +#define SDC_CONTROL_SD_RESET 0x0002 + +// Card detect bits +#define SDC_CARD_INSERT_INT_EN 0x0001 +#define SDC_CARD_INSERT_INT_REQ 0x0002 +#define SDC_CARD_REMOVE_INT_EN 0x0004 +#define SDC_CARD_REMOVE_INT_REQ 0x0008 + +// Command status bits +#define SDC_CMD_INT_STATUS_CC 0x0001 // Command complete +#define SDC_CMD_INT_STATUS_EI 0x0002 // Any error +#define SDC_CMD_INT_STATUS_CTE 0x0004 // Timeout +#define SDC_CMD_INT_STATUS_CCRC 0x0008 // CRC error +#define SDC_CMD_INT_STATUS_CIE 0x0010 // Command code check error + +// Data status bits +#define SDC_DAT_INT_STATUS_TRS 0x0001 // Transfer complete +#define SDC_DAT_INT_STATUS_ERR 0x0002 // Any error +#define SDC_DAT_INT_STATUS_CTE 0x0004 // Timeout +#define SDC_DAT_INT_STATUS_CRC 0x0008 // CRC error +#define SDC_DAT_INT_STATUS_CFE 0x0010 // Data FIFO underrun or overrun + +#define ERR_EOF 30 +#define ERR_NOT_ELF 31 +#define ERR_ELF_BITS 32 +#define ERR_ELF_ENDIANNESS 33 +#define ERR_CMD_CRC 34 +#define ERR_CMD_CHECK 35 +#define ERR_DATA_CRC 36 +#define ERR_DATA_FIFO 37 +#define ERR_BUF_ALIGNMENT 38 + +struct sdc_regs { + volatile uint32_t argument; + volatile uint32_t command; + volatile uint32_t response1; + volatile uint32_t response2; + volatile uint32_t response3; + volatile uint32_t response4; + volatile uint32_t data_timeout; + volatile uint32_t control; + volatile uint32_t cmd_timeout; + volatile uint32_t clock_divider; + volatile uint32_t software_reset; + volatile uint32_t power_control; + volatile uint32_t capability; + volatile uint32_t cmd_int_status; + volatile uint32_t cmd_int_enable; + volatile uint32_t dat_int_status; + volatile uint32_t dat_int_enable; + volatile uint32_t block_size; + volatile uint32_t block_count; + volatile uint32_t card_detect; + volatile uint32_t res_50; + volatile uint32_t res_54; + volatile uint32_t res_58; + volatile uint32_t res_5c; + volatile uint64_t dma_addres; +}; + +static struct sdc_regs * const regs __attribute__((section(".rodata"))) = (struct sdc_regs *)0x00013100; + +static int errno __attribute__((section(".bss"))); +static DSTATUS drv_status __attribute__((section(".bss"))); +static BYTE card_type __attribute__((section(".bss"))); +static uint32_t response[4] __attribute__((section(".bss"))); +static FATFS fatfs __attribute__((section(".bss"))); +static int alt_mem __attribute__((section(".bss"))); +static FIL fd __attribute__((section(".bss"))); + +extern unsigned char _fbss[]; +extern unsigned char _ebss[]; + +static const char * errno_to_str(void) { + switch (errno) { + case FR_OK: return "No error"; + case FR_DISK_ERR: return "Disk I/O error"; + case FR_INT_ERR: return "Assertion failed"; + case FR_NOT_READY: return "Disk not ready"; + case FR_NO_FILE: return "File not found"; + case FR_NO_PATH: return "Path not found"; + case FR_INVALID_NAME: return "Invalid path"; + case FR_DENIED: return "Access denied"; + case FR_EXIST: return "Already exist"; + case FR_INVALID_OBJECT: return "The FS object is invalid"; + case FR_WRITE_PROTECTED: return "The drive is write protected"; + case FR_INVALID_DRIVE: return "The drive number is invalid"; + case FR_NOT_ENABLED: return "The volume has no work area"; + case FR_NO_FILESYSTEM: return "Not a valid FAT volume"; + case FR_MKFS_ABORTED: return "The f_mkfs() aborted"; + case FR_TIMEOUT: return "Timeout"; + case FR_LOCKED: return "Locked"; + case FR_NOT_ENOUGH_CORE: return "Not enough memory"; + case FR_TOO_MANY_OPEN_FILES: return "Too many open files"; + case ERR_EOF: return "Unexpected EOF"; + case ERR_NOT_ELF: return "Not an ELF file"; + case ERR_ELF_BITS: return "Wrong ELF word size"; + case ERR_ELF_ENDIANNESS: return "Wrong ELF endianness"; + case ERR_CMD_CRC: return "Command CRC error"; + case ERR_CMD_CHECK: return "Command code check error"; + case ERR_DATA_CRC: return "Data CRC error"; + case ERR_DATA_FIFO: return "Data FIFO error"; + case ERR_BUF_ALIGNMENT: return "Bad buffer alignment"; + } + return "Unknown error code"; +} + +static void usleep(unsigned us) { + uintptr_t cycles0; + uintptr_t cycles1; + asm volatile ("csrr %0, 0xB00" : "=r" (cycles0)); + for (;;) { + asm volatile ("csrr %0, 0xB00" : "=r" (cycles1)); + if (cycles1 - cycles0 >= us * 100) break; + } +} + +static int sdc_cmd_finish(unsigned cmd) { + while (1) { + unsigned status = regs->cmd_int_status; + if (status) { + // clear interrupts + regs->cmd_int_status = 0; + while (regs->software_reset != 0) {} + if (status == SDC_CMD_INT_STATUS_CC) { + // get response + response[0] = regs->response1; + response[1] = regs->response2; + response[2] = regs->response3; + response[3] = regs->response4; + return 0; + } + errno = FR_DISK_ERR; + if (status & SDC_CMD_INT_STATUS_CTE) errno = FR_TIMEOUT; + if (status & SDC_CMD_INT_STATUS_CCRC) errno = ERR_CMD_CRC; + if (status & SDC_CMD_INT_STATUS_CIE) errno = ERR_CMD_CHECK; + break; + } + } + return -1; +} + +static int sdc_data_finish(void) { + int status; + + while ((status = regs->dat_int_status) == 0) {} + regs->dat_int_status = 0; + while (regs->software_reset != 0) {} + + if (status == SDC_DAT_INT_STATUS_TRS) return 0; + errno = FR_DISK_ERR; + if (status & SDC_DAT_INT_STATUS_CTE) errno = FR_TIMEOUT; + if (status & SDC_DAT_INT_STATUS_CRC) errno = ERR_DATA_CRC; + if (status & SDC_DAT_INT_STATUS_CFE) errno = ERR_DATA_FIFO; + return -1; +} + +static int send_data_cmd(unsigned cmd, unsigned arg, void * buf, unsigned blocks) { + unsigned command = (cmd & 0x3f) << 8; + switch (cmd) { + case CMD0: + case CMD4: + case CMD15: + // No responce + break; + case CMD11: + case CMD13: + case CMD16: + case CMD17: + case CMD18: + case CMD19: + case CMD23: + case CMD24: + case CMD25: + case CMD27: + case CMD30: + case CMD32: + case CMD33: + case CMD42: + case CMD55: + case CMD56: + case ACMD6: + // R1 + command |= 1; // 48 bits + command |= 1 << 3; // resp CRC + command |= 1 << 4; // resp OPCODE + break; + case CMD7: + case CMD12: + case CMD20: + case CMD28: + case CMD29: + case CMD38: + // R1b + command |= 1; // 48 bits + command |= 1 << 2; // busy + command |= 1 << 3; // resp CRC + command |= 1 << 4; // resp OPCODE + break; + case CMD2: + case CMD9: + case CMD10: + // R2 + command |= 2; // 136 bits + command |= 1 << 3; // resp CRC + break; + case ACMD41: + // R3 + command |= 1; // 48 bits + break; + case CMD3: + // R6 + command |= 1; // 48 bits + command |= 1 << 2; // busy + command |= 1 << 3; // resp CRC + command |= 1 << 4; // resp OPCODE + break; + case CMD8: + // R7 + command |= 1; // 48 bits + command |= 1 << 3; // resp CRC + command |= 1 << 4; // resp OPCODE + break; + } + + if (blocks) { + command |= 1 << 5; + if ((intptr_t)buf & 3) { + errno = ERR_BUF_ALIGNMENT; + return -1; + } + regs->dma_addres = (uint64_t)(intptr_t)buf; + regs->block_size = 511; + regs->block_count = blocks - 1; + regs->data_timeout = 0xFFFFFF; + } + + regs->command = command; + regs->cmd_timeout = 0xFFFFF; + regs->argument = arg; + + if (sdc_cmd_finish(cmd) < 0) return -1; + if (blocks) return sdc_data_finish(); + + return 0; +} + +#define send_cmd(cmd, arg) send_data_cmd(cmd, arg, NULL, 0) + +static int ini_sd(void) { + unsigned rca; + + /* Reset controller */ + regs->software_reset = 1; + while ((regs->software_reset & 1) == 0) {} + regs->clock_divider = 0x7c; + regs->software_reset = 0; + while (regs->software_reset) {} + usleep(5000); + + card_type = 0; + drv_status = STA_NOINIT; + + if (regs->capability & SDC_CAPABILITY_SD_RESET) { + /* Power cycle SD card */ + regs->control |= SDC_CONTROL_SD_RESET; + usleep(1000000); + regs->control &= ~SDC_CONTROL_SD_RESET; + usleep(100000); + } + + /* Enter Idle state */ + send_cmd(CMD0, 0); + + card_type = CT_SD1; + if (send_cmd(CMD8, 0x1AA) == 0) { + if ((response[0] & 0xfff) != 0x1AA) { + errno = ERR_CMD_CHECK; + return -1; + } + card_type = CT_SD2; + } + + /* Wait for leaving idle state (ACMD41 with HCS bit) */ + while (1) { + /* ACMD41, Set Operating Conditions: Host High Capacity & 3.3V */ + if (send_cmd(CMD55, 0) < 0 || send_cmd(ACMD41, 0x40300000) < 0) return -1; + if (response[0] & (1 << 31)) { + if (response[0] & (1 << 30)) card_type |= CT_BLOCK; + break; + } + } + + /* Enter Identification state */ + if (send_cmd(CMD2, 0) < 0) return -1; + + /* Get RCA (Relative Card Address) */ + rca = 0x1234; + if (send_cmd(CMD3, rca << 16) < 0) return -1; + rca = response[0] >> 16; + + /* Select card */ + if (send_cmd(CMD7, rca << 16) < 0) return -1; + + /* Clock 25MHz */ + regs->clock_divider = 3; + usleep(10000); + + /* Bus width 1-bit */ + regs->control = 0; + if (send_cmd(CMD55, rca << 16) < 0 || send_cmd(ACMD6, 0) < 0) return -1; + + /* Set R/W block length to 512 */ + if (send_cmd(CMD16, 512) < 0) return -1; + + drv_status &= ~STA_NOINIT; + return 0; +} From e5d42774062884be860fa69f71caecca42e0a0bd Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Fri, 13 Jan 2023 13:56:01 -0600 Subject: [PATCH 02/22] Connected the axi_sdc_controller with an axi crossbar. Added an adrdec.sv to the adrdecs.sv file for the sake of the cache. Modified Uncore accordingly. --- fpga/generator/Makefile | 17 +- fpga/generator/wally.tcl | 3 + fpga/generator/xlnx_axi_crossbar.tcl | 31 + .../generator/xlnx_axi_dwidth_conv_32to64.tcl | 25 + .../generator/xlnx_axi_dwidth_conv_64to32.tcl | 27 + fpga/generator/xlnx_axi_dwidth_converter.tcl | 25 + fpga/src/fpgaTop.v | 654 ++++++++++++++++-- pipelined/src/mmu/adrdecs.sv | 7 +- pipelined/src/uncore/uncore.sv | 4 +- 9 files changed, 741 insertions(+), 52 deletions(-) create mode 100644 fpga/generator/xlnx_axi_crossbar.tcl create mode 100644 fpga/generator/xlnx_axi_dwidth_conv_32to64.tcl create mode 100644 fpga/generator/xlnx_axi_dwidth_conv_64to32.tcl create mode 100644 fpga/generator/xlnx_axi_dwidth_converter.tcl diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile index f39a9bce9..cdb748394 100644 --- a/fpga/generator/Makefile +++ b/fpga/generator/Makefile @@ -1,13 +1,13 @@ dst := IP # vcu118 -export XILINX_PART := xcvu9p-flga2104-2L-e -export XILINX_BOARD := xilinx.com:vcu118:part0:2.4 -export board := vcu118 +# export XILINX_PART := xcvu9p-flga2104-2L-e +# export XILINX_BOARD := xilinx.com:vcu118:part0:2.4 +# export board := vcu118 # vcu108 -#export XILINX_PART := xcvu095-ffva2104-2-e -#export XILINX_BOARD := xilinx.com:vcu108:part0:1.2 -#export board := vcu108 +export XILINX_PART := xcvu095-ffva2104-2-e +export XILINX_BOARD := xilinx.com:vcu108:part0:1.2 +export board := vcu108 all: FPGA @@ -18,7 +18,10 @@ FPGA: IP IP: $(dst)/xlnx_proc_sys_reset.log \ $(dst)/xlnx_ddr4-$(board).log \ $(dst)/xlnx_axi_clock_converter.log \ - $(dst)/xlnx_ahblite_axi_bridge.log + $(dst)/xlnx_ahblite_axi_bridge.log \ + $(dst)/xlnx_axi_crossbar.log \ + $(dst)/xlnx_axi_dwidth_conv_32to64.log \ + $(dst)/xlnx_axi_dwidth_conv_64to32.log $(dst)/%.log: %.tcl mkdir -p IP diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index 6afa9e66f..a032a866c 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -14,6 +14,9 @@ read_ip IP/xlnx_ahblite_axi_bridge.srcs/sources_1/ip/xlnx_ahblite_axi_bridge/xln read_ip IP/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter.xci read_ip IP/xlnx_ddr4.srcs/sources_1/ip/xlnx_ddr4/xlnx_ddr4.xci +# Added crossbar - Jacob Pease <2023-01-12 Thu> +read_ip IP/xlnx_axi_crossbar.srcs/sources_1/ip/xlnx_axi_crossbar/xlnx_axi_crossbar.xci + read_verilog -sv [glob -type f ../../pipelined/src/*/*.sv ../../pipelined/src/*/*/*.sv] read_verilog {../src/fpgaTop.v} diff --git a/fpga/generator/xlnx_axi_crossbar.tcl b/fpga/generator/xlnx_axi_crossbar.tcl new file mode 100644 index 000000000..ba867a640 --- /dev/null +++ b/fpga/generator/xlnx_axi_crossbar.tcl @@ -0,0 +1,31 @@ +set partNumber $::env(XILINX_PART) +set boardName $::env(XILINX_BOARD) + +# vcu118 board +#set partNumber xcvu9p-flga2104-2L-e +#set boardName xilinx.com:vcu118:part0:2.4 + +# kcu105 board +#set partNumber xcku040-ffva1156-2-e +#set boardName xilinx.com:kcu105:part0:1.7 + +set ipName xlnx_axi_crossbar + +create_project $ipName . -force -part $partNumber +set_property board_part $boardName [current_project] + +create_ip -name axi_crossbar -vendor xilinx.com -library ip -version 2.1 -module_name $ipName + +set_property -dict [list CONFIG.NUM_SI {2} \ + CONFIG.DATA_WIDTH {64} \ + CONFIG.ID_WIDTH {4} \ + CONFIG.M01_S01_READ_CONNECTIVITY {0} \ + CONFIG.M01_S01_WRITE_CONNECTIVITY {0} \ + CONFIG.M00_A00_BASE_ADDR {0x0000000080000000} \ + CONFIG.M01_A00_BASE_ADDR {0x0000000000013000}] [get_ips $ipName] + +generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +launch_run -jobs 8 ${ipName}_synth_1 +wait_on_run ${ipName}_synth_1 diff --git a/fpga/generator/xlnx_axi_dwidth_conv_32to64.tcl b/fpga/generator/xlnx_axi_dwidth_conv_32to64.tcl new file mode 100644 index 000000000..97edd97d9 --- /dev/null +++ b/fpga/generator/xlnx_axi_dwidth_conv_32to64.tcl @@ -0,0 +1,25 @@ +set partNumber $::env(XILINX_PART) +set boardName $::env(XILINX_BOARD) + +# vcu118 board +#set partNumber xcvu9p-flga2104-2L-e +#set boardName xilinx.com:vcu118:part0:2.4 + +# kcu105 board +#set partNumber xcku040-ffva1156-2-e +#set boardName xilinx.com:kcu105:part0:1.7 + +set ipName xlnx_axi_dwidth_conv_32to64 + +create_project $ipName . -force -part $partNumber +set_property board_part $boardName [current_project] + +create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -version 2.1 -module_name $ipName + +set_property -dict [list CONFIG.Component_Name {axi_dwidth_conv_32to64}] [get_ips $ipName] + +generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +launch_run -jobs 8 ${ipName}_synth_1 +wait_on_run ${ipName}_synth_1 diff --git a/fpga/generator/xlnx_axi_dwidth_conv_64to32.tcl b/fpga/generator/xlnx_axi_dwidth_conv_64to32.tcl new file mode 100644 index 000000000..3883a8a9d --- /dev/null +++ b/fpga/generator/xlnx_axi_dwidth_conv_64to32.tcl @@ -0,0 +1,27 @@ +set partNumber $::env(XILINX_PART) +set boardName $::env(XILINX_BOARD) + +# vcu118 board +#set partNumber xcvu9p-flga2104-2L-e +#set boardName xilinx.com:vcu118:part0:2.4 + +# kcu105 board +#set partNumber xcku040-ffva1156-2-e +#set boardName xilinx.com:kcu105:part0:1.7 + +set ipName xlnx_axi_dwidth_conv_64to32 + +create_project $ipName . -force -part $partNumber +set_property board_part $boardName [current_project] + +create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -version 2.1 -module_name $ipName + +set_property -dict [list CONFIG.Component_Name {axi_dwidth_conv_64to32} \ + CONFIG.SI_DATA_WIDTH {64} \ + CONFIG.MI_DATA_WIDTH {32}] [get_ips $ipName] + +generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +launch_run -jobs 8 ${ipName}_synth_1 +wait_on_run ${ipName}_synth_1 diff --git a/fpga/generator/xlnx_axi_dwidth_converter.tcl b/fpga/generator/xlnx_axi_dwidth_converter.tcl new file mode 100644 index 000000000..ba979bf01 --- /dev/null +++ b/fpga/generator/xlnx_axi_dwidth_converter.tcl @@ -0,0 +1,25 @@ +set partNumber $::env(XILINX_PART) +set boardName $::env(XILINX_BOARD) + +# vcu118 board +#set partNumber xcvu9p-flga2104-2L-e +#set boardName xilinx.com:vcu118:part0:2.4 + +# kcu105 board +#set partNumber xcku040-ffva1156-2-e +#set boardName xilinx.com:kcu105:part0:1.7 + +set ipName xlnx_axi_dwidth_converter + +create_project $ipName . -force -part $partNumber +set_property board_part $boardName [current_project] + +create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -version 2.1 -module_name $ipName + +set_property -dict [list CONFIG.Component_Name {axi_dwidth_converter}] [get_ips $ipName] + +generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +launch_run -jobs 8 ${ipName}_synth_1 +wait_on_run ${ipName}_synth_1 diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index 6a26be74e..48c475b4f 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -38,7 +38,7 @@ module fpgaTop input UARTSin, output UARTSout, - input [3:0] SDCDat, + inout [3:0] SDCDat, output SDCCLK, inout SDCCmd, @@ -130,11 +130,13 @@ module fpgaTop wire m_axi_rlast; wire m_axi_rready; + // Extra Bus signals wire [3:0] BUS_axi_arregion; wire [3:0] BUS_axi_arqos; wire [3:0] BUS_axi_awregion; wire [3:0] BUS_axi_awqos; + // Bus signals wire [3:0] BUS_axi_awid; wire [7:0] BUS_axi_awlen; wire [2:0] BUS_axi_awsize; @@ -170,7 +172,7 @@ module fpgaTop wire BUS_axi_rvalid; wire BUS_axi_rlast; wire BUS_axi_rready; - + wire BUSCLK; @@ -179,9 +181,198 @@ module fpgaTop wire [511 : 0] dbg_bus; wire CLK208; - - + + // Crossbar to Bus ------------------------------------------------ + + wire s00_axi_aclk; + wire s00_axi_aresetn; + wire [31:0]s00_axi_awaddr; + wire [7:0]s00_axi_awlen; + wire [2:0]s00_axi_awsize; + wire [1:0]s00_axi_awburst; + wire [0:0]s00_axi_awlock; + wire [3:0]s00_axi_awcache; + wire [2:0]s00_axi_awprot; + wire [3:0]s00_axi_awregion; + wire [3:0]s00_axi_awqos; + wire s00_axi_awvalid; + wire s00_axi_awready; + wire [63:0]s00_axi_wdata; + wire [7:0]s00_axi_wstrb; + wire s00_axi_wlast; + wire s00_axi_wvalid; + wire s00_axi_wready; + wire [1:0]s00_axi_bresp; + wire s00_axi_bvalid; + wire s00_axi_bready; + wire [31:0]s00_axi_araddr; + wire [7:0]s00_axi_arlen; + wire [2:0]s00_axi_arsize; + wire [1:0]s00_axi_arburst; + wire [0:0]s00_axi_arlock; + wire [3:0]s00_axi_arcache; + wire [2:0]s00_axi_arprot; + wire [3:0]s00_axi_arregion; + wire [3:0]s00_axi_arqos; + wire s00_axi_arvalid; + wire s00_axi_arready; + wire [63:0]s00_axi_rdata; + wire [1:0]s00_axi_rresp; + wire s00_axi_rlast; + wire s00_axi_rvalid; + wire s00_axi_rready; + + // 64to32 dwidth converter input interface------------------------- + wire s01_axi_aclk; + wire s01_axi_aresetn; + wire [31:0]s01_axi_awaddr; + wire [7:0]s01_axi_awlen; + wire [2:0]s01_axi_awsize; + wire [1:0]s01_axi_awburst; + wire [0:0]s01_axi_awlock; + wire [3:0]s01_axi_awcache; + wire [2:0]s01_axi_awprot; + wire [3:0]s01_axi_awregion; + wire [3:0]s01_axi_awqos; // qos signals need to be 0 for SDC + wire s01_axi_awvalid; + wire s01_axi_awready; + wire [63:0]s01_axi_wdata; + wire [7:0]s01_axi_wstrb; + wire s01_axi_wlast; + wire s01_axi_wvalid; + wire s01_axi_wready; + wire [1:0]s01_axi_bresp; + wire s01_axi_bvalid; + wire s01_axi_bready; + wire [31:0]s01_axi_araddr; + wire [7:0]s01_axi_arlen; + wire [2:0]s01_axi_arsize; + wire [1:0]s01_axi_arburst; + wire [0:0]s01_axi_arlock; + wire [3:0]s01_axi_arcache; + wire [2:0]s01_axi_arprot; + wire [3:0]s01_axi_arregion; + wire [3:0]s01_axi_arqos; // + wire s01_axi_arvalid; + wire s01_axi_arready; + wire [63:0]s01_axi_rdata; + wire [1:0]s01_axi_rresp; + wire s01_axi_rlast; + wire s01_axi_rvalid; + wire s01_axi_rready; + + // Output Interface + wire [31:0]SDCin_axi_awaddr; + wire [7:0]SDCin_axi_awlen; + wire [2:0]SDCin_axi_awsize; + wire [1:0]SDCin_axi_awburst; + wire [0:0]SDCin_axi_awlock; + wire [3:0]SDCin_axi_awcache; + wire [2:0]SDCin_axi_awprot; + wire [3:0]SDCin_axi_awregion; + wire [3:0]SDCin_axi_awqos; + wire SDCin_axi_awvalid; + wire SDCin_axi_awready; + wire [31:0]SDCin_axi_wdata; + wire [3:0]SDCin_axi_wstrb; + wire SDCin_axi_wlast; + wire SDCin_axi_wvalid; + wire SDCin_axi_wready; + wire [1:0]SDCin_axi_bresp; + wire SDCin_axi_bvalid; + wire SDCin_axi_bready; + wire [31:0]SDCin_axi_araddr; + wire [7:0]SDCin_axi_arlen; + wire [2:0]SDCin_axi_arsize; + wire [1:0]SDCin_axi_arburst; + wire [0:0]SDCin_axi_arlock; + wire [3:0]SDCin_axi_arcache; + wire [2:0]SDCin_axi_arprot; + wire [3:0]SDCin_axi_arregion; + wire [3:0]SDCin_axi_arqos; + wire SDCin_axi_arvalid; + wire SDCin_axi_arready; + wire [31:0]SDCin_axi_rdata; + wire [1:0]SDCin_axi_rresp; + wire SDCin_axi_rlast; + wire SDCin_axi_rvalid; + wire SDCin_axi_rready; + // ---------------------------------------------------------------- + + // 32to64 dwidth converter input interface ----------------------- + wire [31:0]SDCout_axi_awaddr; + wire [7:0]SDCout_axi_awlen; + wire [2:0]SDCout_axi_awsize; + wire [1:0]SDCout_axi_awburst; + wire [0:0]SDCout_axi_awlock; + wire [3:0]SDCout_axi_awcache; + wire [2:0]SDCout_axi_awprot; + wire [3:0]SDCout_axi_awregion; + wire [3:0]SDCout_axi_awqos; + wire SDCout_axi_awvalid; + wire SDCout_axi_awready; + wire [31:0]SDCout_axi_wdata; + wire [3:0]SDCout_axi_wstrb; + wire SDCout_axi_wlast; + wire SDCout_axi_wvalid; + wire SDCout_axi_wready; + wire [1:0]SDCout_axi_bresp; + wire SDCout_axi_bvalid; + wire SDCout_axi_bready; + wire [31:0]SDCout_axi_araddr; + wire [7:0]SDCout_axi_arlen; + wire [2:0]SDCout_axi_arsize; + wire [1:0]SDCout_axi_arburst; + wire [0:0]SDCout_axi_arlock; + wire [3:0]SDCout_axi_arcache; + wire [2:0]SDCout_axi_arprot; + wire [3:0]SDCout_axi_arregion; + wire [3:0]SDCout_axi_arqos; + wire SDCout_axi_arvalid; + wire SDCout_axi_arready; + wire [31:0]SDCout_axi_rdata; + wire [1:0]SDCout_axi_rresp; + wire SDCout_axi_rlast; + wire SDCout_axi_rvalid; + wire SDCout_axi_rready; + + // Output Interface + wire [31:0]m01_axi_awaddr; + wire [7:0]m01_axi_awlen; + wire [2:0]m01_axi_awsize; + wire [1:0]m01_axi_awburst; + wire [0:0]m01_axi_awlock; + wire [3:0]m01_axi_awcache; + wire [2:0]m01_axi_awprot; + wire [3:0]m01_axi_awregion; + wire [3:0]m01_axi_awqos; + wire m01_axi_awvalid; + wire m01_axi_awready; + wire [31:0]m01_axi_wdata; + wire [3:0]m01_axi_wstrb; + wire m01_axi_wlast; + wire m01_axi_wvalid; + wire m01_axi_wready; + wire [1:0]m01_axi_bresp; + wire m01_axi_bvalid; + wire m01_axi_bready; + wire [31:0]m01_axi_araddr; + wire [7:0]m01_axi_arlen; + wire [2:0]m01_axi_arsize; + wire [1:0]m01_axi_arburst; + wire [0:0]m01_axi_arlock; + wire [3:0]m01_axi_arcache; + wire [2:0]m01_axi_arprot; + wire [3:0]m01_axi_arregion; + wire [3:0]m01_axi_arqos; + wire m01_axi_arvalid; + wire m01_axi_arready; + wire [31:0]m01_axi_rdata; + wire [1:0]m01_axi_rresp; + wire m01_axi_rlast; + wire m01_axi_rvalid; + wire m01_axi_rready; assign GPIOPinsIn = {28'b0, GPI}; assign GPO = GPIOPinsOut[4:0]; @@ -295,49 +486,432 @@ module fpgaTop .m_axi_rvalid(m_axi_rvalid), .m_axi_rlast(m_axi_rlast), .m_axi_rready(m_axi_rready)); + + wire [3:0] s00_axi_awid; + wire [7:0] s00_axi_awlen; + wire [2:0] s00_axi_awsize; + wire [1:0] s00_axi_awburst; + wire [3:0] s00_axi_awcache; + wire [31:0] s00_axi_awaddr; + wire [2:0] s00_axi_awprot; + wire s00_axi_awvalid; + wire s00_axi_awready; + wire s00_axi_awlock; + wire [63:0] s00_axi_wdata; + wire [7:0] s00_axi_wstrb; + wire s00_axi_wlast; + wire s00_axi_wvalid; + wire s00_axi_wready; + wire [3:0] s00_axi_bid; + wire [1:0] s00_axi_bresp; + wire s00_axi_bvalid; + wire s00_axi_bready; + wire [3:0] s00_axi_arid; + wire [7:0] s00_axi_arlen; + wire [2:0] s00_axi_arsize; + wire [1:0] s00_axi_arburst; + wire [2:0] s00_axi_arprot; + wire [3:0] s00_axi_arcache; + wire s00_axi_arvalid; + wire [31:0] s00_axi_araddr; + wire s00_axi_arlock; + wire s00_axi_arready; + wire [3:0] s00_axi_rid; + wire [63:0] s00_axi_rdata; + wire [1:0] s00_axi_rresp; + wire s00_axi_rvalid; + wire s00_axi_rlast; + wire s00_axi_rready; + wire [3:0] s01_axi_awid; + wire [7:0] s01_axi_awlen; + wire [2:0] s01_axi_awsize; + wire [1:0] s01_axi_awburst; + wire [3:0] s01_axi_awcache; + wire [31:0] s01_axi_awaddr; + wire [2:0] s01_axi_awprot; + wire s01_axi_awvalid; + wire s01_axi_awready; + wire s01_axi_awlock; + wire [63:0] s01_axi_wdata; + wire [7:0] s01_axi_wstrb; + wire s01_axi_wlast; + wire s01_axi_wvalid; + wire s01_axi_wready; + wire [3:0] s01_axi_bid; + wire [1:0] s01_axi_bresp; + wire s01_axi_bvalid; + wire s01_axi_bready; + wire [3:0] s01_axi_arid; + wire [7:0] s01_axi_arlen; + wire [2:0] s01_axi_arsize; + wire [1:0] s01_axi_arburst; + wire [2:0] s01_axi_arprot; + wire [3:0] s01_axi_arcache; + wire s01_axi_arvalid; + wire [31:0] s01_axi_araddr; + wire s01_axi_arlock; + wire s01_axi_arready; + wire [3:0] s01_axi_rid; + wire [63:0] s01_axi_rdata; + wire [1:0] s01_axi_rresp; + wire s01_axi_rvalid; + wire s01_axi_rlast; + wire s01_axi_rready; + + + // AXI Crossbar for arbitrating the SDC and CPU -------------- + xlnx_axi_crossbar xlnx_axi_crossbar_0 + (.aclk(CPUCLK), + .aresetn(peripheral_aresetn), + + // Connect Masters + .s_axi_awid({m_axi_awid, m01_axi_awid}), + .s_axi_awaddr({m_axi_awaddr, m01_axi_awaddr}), + .s_axi_awlen({m_axi_awlen, m01_axi_awlen}), + .s_axi_awsize({m_axi_awsize, m01_axi_awsize}), + .s_axi_awburst({m_axi_awburst, m01_axi_awburst}), + .s_axi_awlock({m_axi_awlock, m01_axi_awlock}), + .s_axi_awcache({m_axi_awcache, m01_axi_awcache}), + .s_axi_awprot({m_axi_awprot, m01_axi_awprot}), + .s_axi_awqos(8'b0), + .s_axi_awregion(8'b0), + .s_axi_awvalid({m_axi_awvalid, m01_axi_awvalid}), + .s_axi_awready({m_axi_awready, m01_axi_awready}), + .s_axi_wdata({m_axi_wdata, m01_axi_wdata}), + .s_axi_wstrb({m_axi_wstrb, m01_axi_wstrb}), + .s_axi_wlast({m_axi_wlast, m01_axi_wlast}), + .s_axi_wvalid({m_axi_wvalid, m01_axi_wvalid}), + .s_axi_wready({m_axi_wready, m01_axi_wready}), + .s_axi_bid({m_axi_bid, m01_axi_bid}), + .s_axi_bresp({m_axi_bresp, m01_axi_bresp}), + .s_axi_bvalid({m_axi_bvalid, m01_axi_bvalid}), + .s_axi_bready({m_axi_bready, m01_axi_bready}), + .s_axi_arid({m_axi_arid, m01_axi_arid}), + .s_axi_araddr({m_axi_araddr, m01_axi_araddr}), + .s_axi_arlen({m_axi_arlen, m01_axi_arlen}), + .s_axi_arsize({m_axi_arsize, m01_axi_arsize}), + .s_axi_arburst({m_axi_arburst, m01_axi_arburst}), + .s_axi_arlock({m_axi_arlock, m01_axi_arlock}), + .s_axi_arcache({m_axi_arcache, m01_axi_arcache}), + .s_axi_arprot({m_axi_arprot, m01_axi_arprot}), + .s_axi_arqos(8'b0), + .s_axi_arregion(8'b0), + .s_axi_arvalid({m_axi_arvalid, m01_axi_arvalid}), + .s_axi_arready({m_axi_arready, m01_axi_arready}), + .s_axi_rid({m_axi_rid, m01_axi_rid}), + .s_axi_rdata({m_axi_rdata, m01_axi_rdata}), + .s_axi_rresp({m_axi_rresp, m01_axi_rresp}), + .s_axi_rlast({m_axi_rlast, m01_axi_rlast}), + .s_axi_rvalid({m_axi_rvalid, m01_axi_rvalid}), + .s_axi_rready({m_axi_rready, m01_axi_rready}), + + // Connect Slaves + .m_axi_awid({s00_axi_awid, s01_axi_awid}), + .m_axi_awlen({s00_axi_awlen, s01_axi_awlen}), + .m_axi_awsize({s00_axi_awsize, s01_axi_awsize}), + .m_axi_awburst({s00_axi_awburst, s01_axi_awburst}), + .m_axi_awcache({s00_axi_awcache, s01_axi_awcache}), + .m_axi_awaddr({s00_axi_awaddr, s01_axi_awaddr}), + .m_axi_awprot({s00_axi_awprot, s01_axi_awprot}), + .m_axi_awregion({s00_axi_awregion, s01_axi_awregion}), + .m_axi_awqos({s00_axi_awqos, s01_axi_awqos}), + .m_axi_awvalid({s00_axi_awvalid, s01_axi_awvalid}), + .m_axi_awready({s00_axi_awready, s01_axi_awready}), + .m_axi_awlock({s00_axi_awlock, s01_axi_awlock}), + .m_axi_wdata({s00_axi_wdata, s01_axi_wdata}), + .m_axi_wstrb({s00_axi_wstrb, s01_axi_wstrb}), + .m_axi_wlast({s00_axi_wlast, s01_axi_wlast}), + .m_axi_wvalid({s00_axi_wvalid, s01_axi_wvalid}), + .m_axi_wready({s00_axi_wready, s01_axi_wready}), + .m_axi_bid({s00_axi_bid, s01_axi_bid}), + .m_axi_bresp({s00_axi_bresp, s01_axi_bresp}), + .m_axi_bvalid({s00_axi_bvalid, s01_axi_bvalid}), + .m_axi_bready({s00_axi_bready, s01_axi_bready}), + .m_axi_arid({s00_axi_arid, s01_axi_arid}), + .m_axi_arlen({s00_axi_arlen, s01_axi_arlen}), + .m_axi_arsize({s00_axi_arsize, s01_axi_arsize}), + .m_axi_arburst({s00_axi_arburst, s01_axi_arburst}), + .m_axi_arprot({s00_axi_arprot, s01_axi_arprot}), + .m_axi_arregion({s00_axi_arregion, s01_axi_arregion}), + .m_axi_arqos({s00_axi_arqos, s01_axi_arqos}), + .m_axi_arcache({s00_axi_arcache, s01_axi_arcache}), + .m_axi_arvalid({s00_axi_arvalid, s01_axi_arvalid}), + .m_axi_araddr({s00_axi_araddr, s01_axi_araddr}), + .m_axi_arlock({s00_axi_arlock, s01_axi_arlock}), + .m_axi_arready({s00_axi_arready, s01_axi_arready}), + .m_axi_rid({s00_axi_rid, s01_axi_rid}), + .m_axi_rdata({s00_axi_rdata, s01_axi_rdata}), + .m_axi_rresp({s00_axi_rresp, s01_axi_rresp}), + .m_axi_rvalid({s00_axi_rvalid, s01_axi_rvalid}), + .m_axi_rlast({s00_axi_rlast, s01_axi_rlast}), + .m_axi_rready({s00_axi_rready, s01_axi_rready}) + ); + + // ----------------------------------------------------- + + // SDC Implementation ---------------------------------- + // + // The SDC peripheral from Eugene Tarassov takes in an AXI4Lite + // interface and outputs an AXI4 interface. In order to convert from + // one to the other, we use these dwidth converters to make sure the + // bit widths match the rest of the bus. + + xlnx_axi_dwidth_conv_64to32 axi_conv_down + (.s_axi_aclk(CPUCLK), + .s_axi_aresetn(peripheral_aresetn), + + // Slave interface + .s_axi_awaddr(s01_axi_awaddr), + .s_axi_awlen(s01_axi_awlen), + .s_axi_awsize(s01_axi_awsize), + .s_axi_awburst(s01_axi_awburst), + .s_axi_awlock(s01_axi_awlock), + .s_axi_awcache(s01_axi_awcache), + .s_axi_awprot(s01_axi_awprot), + .s_axi_awregion(s01_axi_awregion), + .s_axi_awqos(4'b0), + .s_axi_awvalid(s01_axi_awvalid), + .s_axi_awready(s01_axi_awready), + .s_axi_wdata(s01_axi_wdata), + .s_axi_wstrb(s01_axi_wstrb), + .s_axi_wlast(s01_axi_wlast), + .s_axi_wvalid(s01_axi_wvalid), + .s_axi_wready(s01_axi_wready), + .s_axi_bresp(s01_axi_bresp), + .s_axi_bvalid(s01_axi_bvalid), + .s_axi_bready(s01_axi_bready), + .s_axi_araddr(s01_axi_araddr), + .s_axi_arlen(s01_axi_arlen), + .s_axi_arsize(s01_axi_arsize), + .s_axi_arburst(s01_axi_arburst), + .s_axi_arlock(s01_axi_arlock), + .s_axi_arcache(s01_axi_arcache), + .s_axi_arprot(s01_axi_arprot), + .s_axi_arregion(s01_axi_arregion), + .s_axi_arqos(4'b0), + .s_axi_arvalid(s01_axi_arvalid), + .s_axi_arready(s01_axi_arready), + .s_axi_rdata(s01_axi_rdata), + .s_axi_rresp(s01_axi_rresp), + .s_axi_rlast(s01_axi_rlast), + .s_axi_rvalid(s01_axi_rvalid), + .s_axi_rready(s01_axi_rready), + + // Master interface + .m_axi_awaddr(SDCin_axi_awaddr), + .m_axi_awlen(SDCin_axi_awlen), + .m_axi_awsize(SDCin_axi_awsize), + .m_axi_awburst(SDCin_axi_awburst), + .m_axi_awlock(SDCin_axi_awlock), + .m_axi_awcache(SDCin_axi_awcache), + .m_axi_awprot(SDCin_axi_awprot), + .m_axi_awregion(SDCin_axi_awregion), + .m_axi_awqos(SDCin_axi_awqos), + .m_axi_awvalid(SDCin_axi_awvalid), + .m_axi_awready(SDCin_axi_awready), + .m_axi_wdata(SDCin_axi_wdata), + .m_axi_wstrb(SDCin_axi_wstrb), + .m_axi_wlast(SDCin_axi_wlast), + .m_axi_wvalid(SDCin_axi_wvalid), + .m_axi_wready(SDCin_axi_wready), + .m_axi_bresp(SDCin_axi_bresp), + .m_axi_bvalid(SDCin_axi_bvalid), + .m_axi_bready(SDCin_axi_bready), + .m_axi_araddr(SDCin_axi_araddr), + .m_axi_arlen(SDCin_axi_arlen), + .m_axi_arsize(SDCin_axi_arsize), + .m_axi_arburst(SDCin_axi_arburst), + .m_axi_arlock(SDCin_axi_arlock), + .m_axi_arcache(SDCin_axi_arcache), + .m_axi_arprot(SDCin_axi_arprot), + .m_axi_arregion(SDCin_axi_arregion), + .m_axi_arqos(SDCin_axi_arqos), + .m_axi_arvalid(SDCin_axi_arvalid), + .m_axi_arready(SDCin_axi_arready), + .m_axi_rdata(SDCin_axi_rdata), + .m_axi_rresp(SDCin_axi_rresp), + .m_axi_rlast(SDCin_axi_rlast), + .m_axi_rvalid(SDCin_axi_rvalid), + .m_axi_rready(SDCin_axi_rready), + ); + + axi_sdc_controller axiSDC + (.clock(CPUCLK), + .async_resetn(peripheral_aresetn), + + // Slave Interface + .s_axi_awaddr(SDCin_axi_awaddr[15:0]), + .s_axi_awvalid(SDCin_axi_awvalid), + .s_axi_awready(SDCin_axi_awready), + .s_axi_wdata(SDCin_axi_wdata), + .s_axi_wvalid(SDCin_axi_wvalid), + .s_axi_wready(SDCin_axi_wready), + .s_axi_bresp(SDCin_axi_bresp), + .s_axi_bvalid(SDCin_axi_bvalid), + .s_axi_bready(SDCin_axi_bready), + .s_axi_araddr(SDCin_axi_araddr[15:0]), + .s_axi_arvalid(SDCin_axi_arvalid), + .s_axi_arready(SDCin_axi_arready), + .s_axi_rdata(SDCin_axi_rdata), + .s_axi_rresp(SDCin_axi_rresp), + .s_axi_rvalid(SDCin_axi_rvalid), + .s_axi_rready(SDCin_axi_rready), + + // Master Interface + .m_axi_awaddr(SDCout_axi_awaddr), + .m_axi_awlen(SDCout_axi_awlen), + .m_axi_awvalid(SDCout_axi_awvalid), + .m_axi_awready(SDCout_axi_awready), + .m_axi_wdata(SDCout_axi_wdata), + .m_axi_wlast(SDCout_axi_wlast), + .m_axi_wvalid(SDCout_axi_wvalid), + .m_axi_wready(SDCout_axi_wready), + .m_axi_bresp(SDCout_axi_bresp), + .m_axi_bvalid(SDCout_axi_bvalid), + .m_axi_bready(SDCout_axi_bready), + .m_axi_araddr(SDCout_axi_araddr), + .m_axi_arlen(SDCout_axi_arlen), + .m_axi_arvalid(SDCout_axi_arvalid), + .m_axi_arready(SDCout_axi_arready), + .m_axi_rdata(SDCout_axi_rdata), + .m_axi_rlast(SDCout_axi_rlast), + .m_axi_rresp(SDCout_axi_rresp), + .m_axi_rvalid(SDCout_axi_rvalid), + .m_axi_rready(SDCout_axi_rready), + + // SDC interface + //.sdio_cmd(SDCcmd), + //.sdio_dat(SDCdat), + //.sdio_cd() + + + + ); + + xlnx_axi_dwidth_conv_32to64 axi_conv_up + (.s_axi_aclk(CPUCLK), + .s_axi_aresetn(peripheral_aresetn), + + // Slave interface + .s_axi_awaddr(SDCout_axi_awaddr), + .s_axi_awlen(SDCout_axi_awlen), + .s_axi_awsize(3'b0), + .s_axi_awburst(2'b0), + .s_axi_awlock(1'b0), + .s_axi_awcache(4'b0), + .s_axi_awprot(3'b0), + .s_axi_awregion(4'b0), + .s_axi_awqos(4'b0), + .s_axi_awvalid(SDCout_axi_awvalid), + .s_axi_awready(SDCout_axi_awready), + .s_axi_wdata(SDCout_axi_wdata), + .s_axi_wstrb(4'b0), + .s_axi_wlast(SDCout_axi_wlast), + .s_axi_wvalid(SDCout_axi_wvalid), + .s_axi_wready(SDCout_axi_wready), + .s_axi_bresp(SDCout_axi_bresp), + .s_axi_bvalid(SDCout_axi_bvalid), + .s_axi_bready(SDCout_axi_bready), + .s_axi_araddr(SDCout_axi_araddr), + .s_axi_arlen(SDCout_axi_arlen), + .s_axi_arsize(3'b0), + .s_axi_arburst(2'b0), + .s_axi_arlock(1'b0), + .s_axi_arcache(4'b0), + .s_axi_arprot(3'b0), + .s_axi_arregion(4'b0), + .s_axi_arqos(4'b0), + .s_axi_arvalid(SDCout_axi_arvalid), + .s_axi_arready(SDCout_axi_arready), + .s_axi_rdata(SDCout_axi_rdata), + //.s_axi_rresp(), + .s_axi_rlast(SDCout_axi_rlast), + .s_axi_rvalid(SDCout_axi_rvalid), + .s_axi_rready(SDCout_axi_rready), + + // Master interface + .m_axi_awaddr(m01_axi_awaddr), + .m_axi_awlen(m01_axi_awlen), + .m_axi_awsize(m01_axi_awsize), + .m_axi_awburst(m01_axi_awburst), + .m_axi_awlock(m01_axi_awlock), + .m_axi_awcache(m01_axi_awcache), + .m_axi_awprot(m01_axi_awprot), + .m_axi_awregion(m01_axi_awregion), + .m_axi_awqos(m01_axi_awqos), + .m_axi_awvalid(m01_axi_awvalid), + .m_axi_awready(m01_axi_awready), + .m_axi_wdata(m01_axi_wdata), + .m_axi_wstrb(m01_axi_wstrb), + .m_axi_wlast(m01_axi_wlast), + .m_axi_wvalid(m01_axi_wvalid), + .m_axi_wready(m01_axi_wready), + .m_axi_bresp(m01_axi_bresp), + .m_axi_bvalid(m01_axi_bvalid), + .m_axi_bready(m01_axi_bready), + .m_axi_araddr(m01_axi_araddr), + .m_axi_arlen(m01_axi_arlen), + .m_axi_arsize(m01_axi_arsize), + .m_axi_arburst(m01_axi_arburst), + .m_axi_arlock(m01_axi_arlock), + .m_axi_arcache(m01_axi_arcache), + .m_axi_arprot(m01_axi_arprot), + .m_axi_arregion(m01_axi_arregion), + .m_axi_arqos(m01_axi_arqos), + .m_axi_arvalid(m01_axi_arvalid), + .m_axi_arready(m01_axi_arready), + .m_axi_rdata(m01_axi_rdata), + .m_axi_rresp(m01_axi_rresp), + .m_axi_rlast(m01_axi_rlast), + .m_axi_rvalid(m01_axi_rvalid), + .m_axi_rready(m01_axi_rready), + ); + + // End SDC signals -------------------------------------------- + xlnx_axi_clock_converter xlnx_axi_clock_converter_0 (.s_axi_aclk(CPUCLK), .s_axi_aresetn(peripheral_aresetn), - .s_axi_awid(m_axi_awid), - .s_axi_awlen(m_axi_awlen), - .s_axi_awsize(m_axi_awsize), - .s_axi_awburst(m_axi_awburst), - .s_axi_awcache(m_axi_awcache), - .s_axi_awaddr(m_axi_awaddr[30:0]), - .s_axi_awprot(m_axi_awprot), + .s_axi_awid(s00_axi_awid), + .s_axi_awlen(s00_axi_awlen), + .s_axi_awsize(s00_axi_awsize), + .s_axi_awburst(s00_axi_awburst), + .s_axi_awcache(s00_axi_awcache), + .s_axi_awaddr(s00_axi_awaddr[30:0] ), + .s_axi_awprot(s00_axi_awprot), .s_axi_awregion(4'b0), // this could be a bug. bridge does not have these outputs .s_axi_awqos(4'b0), // this could be a bug. bridge does not have these outputs - .s_axi_awvalid(m_axi_awvalid), - .s_axi_awready(m_axi_awready), - .s_axi_awlock(m_axi_awlock), - .s_axi_wdata(m_axi_wdata), - .s_axi_wstrb(m_axi_wstrb), - .s_axi_wlast(m_axi_wlast), - .s_axi_wvalid(m_axi_wvalid), - .s_axi_wready(m_axi_wready), - .s_axi_bid(m_axi_bid), - .s_axi_bresp(m_axi_bresp), - .s_axi_bvalid(m_axi_bvalid), - .s_axi_bready(m_axi_bready), - .s_axi_arid(m_axi_arid), - .s_axi_arlen(m_axi_arlen), - .s_axi_arsize(m_axi_arsize), - .s_axi_arburst(m_axi_arburst), - .s_axi_arprot(m_axi_arprot), + .s_axi_awvalid(s00_axi_awvalid), + .s_axi_awready(s00_axi_awready), + .s_axi_awlock(s00_axi_awlock), + .s_axi_wdata(s00_axi_wdata), + .s_axi_wstrb(s00_axi_wstrb), + .s_axi_wlast(s00_axi_wlast), + .s_axi_wvalid(s00_axi_wvalid), + .s_axi_wready(s00_axi_wready), + .s_axi_bid(s00_axi_bid), + .s_axi_bresp(s00_axi_bresp), + .s_axi_bvalid(s00_axi_bvalid), + .s_axi_bready(s00_axi_bready), + .s_axi_arid(s00_axi_arid), + .s_axi_arlen(s00_axi_arlen), + .s_axi_arsize(s00_axi_arsize), + .s_axi_arburst(s00_axi_arburst), + .s_axi_arprot(s00_axi_arprot), .s_axi_arregion(4'b0), // this could be a bug. bridge does not have these outputs .s_axi_arqos(4'b0), // this could be a bug. bridge does not have these outputs - .s_axi_arcache(m_axi_arcache), - .s_axi_arvalid(m_axi_arvalid), - .s_axi_araddr(m_axi_araddr[30:0]), - .s_axi_arlock(m_axi_arlock), - .s_axi_arready(m_axi_arready), - .s_axi_rid(m_axi_rid), - .s_axi_rdata(m_axi_rdata), - .s_axi_rresp(m_axi_rresp), - .s_axi_rvalid(m_axi_rvalid), - .s_axi_rlast(m_axi_rlast), - .s_axi_rready(m_axi_rready), + .s_axi_arcache(s00_axi_arcache), + .s_axi_arvalid(s00_axi_arvalid), + .s_axi_araddr(s00_axi_araddr[30:0]), + .s_axi_arlock(s00_axi_arlock), + .s_axi_arready(s00_axi_arready), + .s_axi_rid(s00_axi_rid), + .s_axi_rdata(s00_axi_rdata), + .s_axi_rresp(s00_axi_rresp), + .s_axi_rvalid(s00_axi_rvalid), + .s_axi_rlast(s00_axi_rlast), + .s_axi_rready(s00_axi_rready), .m_axi_aclk(BUSCLK), .m_axi_aresetn(~reset), @@ -380,7 +954,7 @@ module fpgaTop .m_axi_rvalid(BUS_axi_rvalid), .m_axi_rlast(BUS_axi_rlast), .m_axi_rready(BUS_axi_rready)); - + xlnx_ddr4 xlnx_ddr4_c0 (.c0_init_calib_complete(c0_init_calib_complete), .dbg_clk(dbg_clk), // open diff --git a/pipelined/src/mmu/adrdecs.sv b/pipelined/src/mmu/adrdecs.sv index 4df5187d2..3443af1a9 100644 --- a/pipelined/src/mmu/adrdecs.sv +++ b/pipelined/src/mmu/adrdecs.sv @@ -31,7 +31,7 @@ module adrdecs ( input logic [`PA_BITS-1:0] PhysicalAddress, input logic AccessRW, AccessRX, AccessRWX, input logic [1:0] Size, - output logic [10:0] SelRegions + output logic [11:0] SelRegions ); localparam logic [3:0] SUPPORTED_SIZE = (`LLEN == 32 ? 4'b0111 : 4'b1111); @@ -46,8 +46,9 @@ module adrdecs ( adrdec uartdec(PhysicalAddress, `UART_BASE, `UART_RANGE, `UART_SUPPORTED, AccessRW, Size, 4'b0001, SelRegions[3]); adrdec plicdec(PhysicalAddress, `PLIC_BASE, `PLIC_RANGE, `PLIC_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[2]); adrdec sdcdec(PhysicalAddress, `SDC_BASE, `SDC_RANGE, `SDC_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE & 4'b1100, SelRegions[1]); - - assign SelRegions[0] = ~|(SelRegions[10:1]); // none of the regions are selected + adrdec newsdc(PhysicalAddressm `SDC2_BASE, `SDC2RANGE, 1'b1, AccessRW, Size, SUPPORTED_SIZE, SelRegions[11]); + + assign SelRegions[0] = ~|(SelRegions[11:1]); // none of the regions are selected endmodule diff --git a/pipelined/src/uncore/uncore.sv b/pipelined/src/uncore/uncore.sv index 4d1a30e2d..7ec5a922c 100644 --- a/pipelined/src/uncore/uncore.sv +++ b/pipelined/src/uncore/uncore.sv @@ -63,7 +63,7 @@ module uncore ( logic [`XLEN-1:0] HREADRam, HREADSDC; - logic [10:0] HSELRegions; + logic [11:0] HSELRegions; logic HSELDTIM, HSELIROM, HSELRam, HSELCLINT, HSELPLIC, HSELGPIO, HSELUART, HSELSDC; logic HSELDTIMD, HSELIROMD, HSELEXTD, HSELRamD, HSELCLINTD, HSELPLICD, HSELGPIOD, HSELUARTD, HSELSDCD; logic HRESPRam, HRESPSDC; @@ -197,7 +197,7 @@ module uncore ( // takes more than 1 cycle to repsond it needs to hold on to the old select until the // device is ready. Hense this register must be selectively enabled by HREADY. // However on reset None must be seleted. - flopenl #(11) hseldelayreg(HCLK, ~HRESETn, HREADY, HSELRegions, 11'b1, {HSELDTIMD, HSELIROMD, HSELEXTD, HSELBootRomD, HSELRamD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD, HSELNoneD}); + flopenl #(11) hseldelayreg(HCLK, ~HRESETn, HREADY, HSELRegions[10:0], 11'b1, {HSELDTIMD, HSELIROMD, HSELEXTD, HSELBootRomD, HSELRamD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD, HSELNoneD}); flopenr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HREADY, HSELBRIDGE, HSELBRIDGED); endmodule From dcfb68daeeed2b76d9127c3b8b8c56cec4b71312 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Fri, 13 Jan 2023 14:36:23 -0600 Subject: [PATCH 03/22] Added IPs to wally.tcl. --- fpga/generator/wally.tcl | 3 ++ fpga/src/fpgaTop.v | 73 ---------------------------------------- 2 files changed, 3 insertions(+), 73 deletions(-) diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index a032a866c..4399656b5 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -16,6 +16,9 @@ read_ip IP/xlnx_ddr4.srcs/sources_1/ip/xlnx_ddr4/xlnx_ddr4.xci # Added crossbar - Jacob Pease <2023-01-12 Thu> read_ip IP/xlnx_axi_crossbar.srcs/sources_1/ip/xlnx_axi_crossbar/xlnx_axi_crossbar.xci +read_ip IP/xlnx_axi_dwidth_conv_32to64.srcs/sources_1/ip/xlnx_axi_dwidth_conv_32to64/xlnx_axi_dwidth_conv_32to64.xci +read_ip IP/xlnx_axi_dwidth_conv_64to32.srcs/sources_1/ip/xlnx_axi_dwidth_conv_64to32/xlnx_axi_dwidth_conv_64to32.xci + read_verilog -sv [glob -type f ../../pipelined/src/*/*.sv ../../pipelined/src/*/*/*.sv] diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index 48c475b4f..300cfe801 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -486,79 +486,6 @@ module fpgaTop .m_axi_rvalid(m_axi_rvalid), .m_axi_rlast(m_axi_rlast), .m_axi_rready(m_axi_rready)); - - wire [3:0] s00_axi_awid; - wire [7:0] s00_axi_awlen; - wire [2:0] s00_axi_awsize; - wire [1:0] s00_axi_awburst; - wire [3:0] s00_axi_awcache; - wire [31:0] s00_axi_awaddr; - wire [2:0] s00_axi_awprot; - wire s00_axi_awvalid; - wire s00_axi_awready; - wire s00_axi_awlock; - wire [63:0] s00_axi_wdata; - wire [7:0] s00_axi_wstrb; - wire s00_axi_wlast; - wire s00_axi_wvalid; - wire s00_axi_wready; - wire [3:0] s00_axi_bid; - wire [1:0] s00_axi_bresp; - wire s00_axi_bvalid; - wire s00_axi_bready; - wire [3:0] s00_axi_arid; - wire [7:0] s00_axi_arlen; - wire [2:0] s00_axi_arsize; - wire [1:0] s00_axi_arburst; - wire [2:0] s00_axi_arprot; - wire [3:0] s00_axi_arcache; - wire s00_axi_arvalid; - wire [31:0] s00_axi_araddr; - wire s00_axi_arlock; - wire s00_axi_arready; - wire [3:0] s00_axi_rid; - wire [63:0] s00_axi_rdata; - wire [1:0] s00_axi_rresp; - wire s00_axi_rvalid; - wire s00_axi_rlast; - wire s00_axi_rready; - - wire [3:0] s01_axi_awid; - wire [7:0] s01_axi_awlen; - wire [2:0] s01_axi_awsize; - wire [1:0] s01_axi_awburst; - wire [3:0] s01_axi_awcache; - wire [31:0] s01_axi_awaddr; - wire [2:0] s01_axi_awprot; - wire s01_axi_awvalid; - wire s01_axi_awready; - wire s01_axi_awlock; - wire [63:0] s01_axi_wdata; - wire [7:0] s01_axi_wstrb; - wire s01_axi_wlast; - wire s01_axi_wvalid; - wire s01_axi_wready; - wire [3:0] s01_axi_bid; - wire [1:0] s01_axi_bresp; - wire s01_axi_bvalid; - wire s01_axi_bready; - wire [3:0] s01_axi_arid; - wire [7:0] s01_axi_arlen; - wire [2:0] s01_axi_arsize; - wire [1:0] s01_axi_arburst; - wire [2:0] s01_axi_arprot; - wire [3:0] s01_axi_arcache; - wire s01_axi_arvalid; - wire [31:0] s01_axi_araddr; - wire s01_axi_arlock; - wire s01_axi_arready; - wire [3:0] s01_axi_rid; - wire [63:0] s01_axi_rdata; - wire [1:0] s01_axi_rresp; - wire s01_axi_rvalid; - wire s01_axi_rlast; - wire s01_axi_rready; - // AXI Crossbar for arbitrating the SDC and CPU -------------- xlnx_axi_crossbar xlnx_axi_crossbar_0 From b6185189072b39a9b258faa9186425905fa9cbfd Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Fri, 13 Jan 2023 16:59:18 -0600 Subject: [PATCH 04/22] Fixed typos. Apparently `defube causes a weird vivado error. --- fpga/generator/wally.tcl | 2 - fpga/src/fpgaTop.v | 581 ++------------------------ pipelined/config/fpga/wally-config.vh | 3 +- pipelined/src/mmu/adrdecs.sv | 2 +- tests/custom/boot/boot.c | 8 + 5 files changed, 51 insertions(+), 545 deletions(-) diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index 4399656b5..15aa5bf7f 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -19,8 +19,6 @@ read_ip IP/xlnx_axi_crossbar.srcs/sources_1/ip/xlnx_axi_crossbar/xlnx_axi_crossb read_ip IP/xlnx_axi_dwidth_conv_32to64.srcs/sources_1/ip/xlnx_axi_dwidth_conv_32to64/xlnx_axi_dwidth_conv_32to64.xci read_ip IP/xlnx_axi_dwidth_conv_64to32.srcs/sources_1/ip/xlnx_axi_dwidth_conv_64to32/xlnx_axi_dwidth_conv_64to32.xci - - read_verilog -sv [glob -type f ../../pipelined/src/*/*.sv ../../pipelined/src/*/*/*.sv] read_verilog {../src/fpgaTop.v} diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index 300cfe801..6a26be74e 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -38,7 +38,7 @@ module fpgaTop input UARTSin, output UARTSout, - inout [3:0] SDCDat, + input [3:0] SDCDat, output SDCCLK, inout SDCCmd, @@ -130,13 +130,11 @@ module fpgaTop wire m_axi_rlast; wire m_axi_rready; - // Extra Bus signals wire [3:0] BUS_axi_arregion; wire [3:0] BUS_axi_arqos; wire [3:0] BUS_axi_awregion; wire [3:0] BUS_axi_awqos; - // Bus signals wire [3:0] BUS_axi_awid; wire [7:0] BUS_axi_awlen; wire [2:0] BUS_axi_awsize; @@ -172,7 +170,7 @@ module fpgaTop wire BUS_axi_rvalid; wire BUS_axi_rlast; wire BUS_axi_rready; - + wire BUSCLK; @@ -181,198 +179,9 @@ module fpgaTop wire [511 : 0] dbg_bus; wire CLK208; + - - // Crossbar to Bus ------------------------------------------------ - - wire s00_axi_aclk; - wire s00_axi_aresetn; - wire [31:0]s00_axi_awaddr; - wire [7:0]s00_axi_awlen; - wire [2:0]s00_axi_awsize; - wire [1:0]s00_axi_awburst; - wire [0:0]s00_axi_awlock; - wire [3:0]s00_axi_awcache; - wire [2:0]s00_axi_awprot; - wire [3:0]s00_axi_awregion; - wire [3:0]s00_axi_awqos; - wire s00_axi_awvalid; - wire s00_axi_awready; - wire [63:0]s00_axi_wdata; - wire [7:0]s00_axi_wstrb; - wire s00_axi_wlast; - wire s00_axi_wvalid; - wire s00_axi_wready; - wire [1:0]s00_axi_bresp; - wire s00_axi_bvalid; - wire s00_axi_bready; - wire [31:0]s00_axi_araddr; - wire [7:0]s00_axi_arlen; - wire [2:0]s00_axi_arsize; - wire [1:0]s00_axi_arburst; - wire [0:0]s00_axi_arlock; - wire [3:0]s00_axi_arcache; - wire [2:0]s00_axi_arprot; - wire [3:0]s00_axi_arregion; - wire [3:0]s00_axi_arqos; - wire s00_axi_arvalid; - wire s00_axi_arready; - wire [63:0]s00_axi_rdata; - wire [1:0]s00_axi_rresp; - wire s00_axi_rlast; - wire s00_axi_rvalid; - wire s00_axi_rready; - - // 64to32 dwidth converter input interface------------------------- - wire s01_axi_aclk; - wire s01_axi_aresetn; - wire [31:0]s01_axi_awaddr; - wire [7:0]s01_axi_awlen; - wire [2:0]s01_axi_awsize; - wire [1:0]s01_axi_awburst; - wire [0:0]s01_axi_awlock; - wire [3:0]s01_axi_awcache; - wire [2:0]s01_axi_awprot; - wire [3:0]s01_axi_awregion; - wire [3:0]s01_axi_awqos; // qos signals need to be 0 for SDC - wire s01_axi_awvalid; - wire s01_axi_awready; - wire [63:0]s01_axi_wdata; - wire [7:0]s01_axi_wstrb; - wire s01_axi_wlast; - wire s01_axi_wvalid; - wire s01_axi_wready; - wire [1:0]s01_axi_bresp; - wire s01_axi_bvalid; - wire s01_axi_bready; - wire [31:0]s01_axi_araddr; - wire [7:0]s01_axi_arlen; - wire [2:0]s01_axi_arsize; - wire [1:0]s01_axi_arburst; - wire [0:0]s01_axi_arlock; - wire [3:0]s01_axi_arcache; - wire [2:0]s01_axi_arprot; - wire [3:0]s01_axi_arregion; - wire [3:0]s01_axi_arqos; // - wire s01_axi_arvalid; - wire s01_axi_arready; - wire [63:0]s01_axi_rdata; - wire [1:0]s01_axi_rresp; - wire s01_axi_rlast; - wire s01_axi_rvalid; - wire s01_axi_rready; - - // Output Interface - wire [31:0]SDCin_axi_awaddr; - wire [7:0]SDCin_axi_awlen; - wire [2:0]SDCin_axi_awsize; - wire [1:0]SDCin_axi_awburst; - wire [0:0]SDCin_axi_awlock; - wire [3:0]SDCin_axi_awcache; - wire [2:0]SDCin_axi_awprot; - wire [3:0]SDCin_axi_awregion; - wire [3:0]SDCin_axi_awqos; - wire SDCin_axi_awvalid; - wire SDCin_axi_awready; - wire [31:0]SDCin_axi_wdata; - wire [3:0]SDCin_axi_wstrb; - wire SDCin_axi_wlast; - wire SDCin_axi_wvalid; - wire SDCin_axi_wready; - wire [1:0]SDCin_axi_bresp; - wire SDCin_axi_bvalid; - wire SDCin_axi_bready; - wire [31:0]SDCin_axi_araddr; - wire [7:0]SDCin_axi_arlen; - wire [2:0]SDCin_axi_arsize; - wire [1:0]SDCin_axi_arburst; - wire [0:0]SDCin_axi_arlock; - wire [3:0]SDCin_axi_arcache; - wire [2:0]SDCin_axi_arprot; - wire [3:0]SDCin_axi_arregion; - wire [3:0]SDCin_axi_arqos; - wire SDCin_axi_arvalid; - wire SDCin_axi_arready; - wire [31:0]SDCin_axi_rdata; - wire [1:0]SDCin_axi_rresp; - wire SDCin_axi_rlast; - wire SDCin_axi_rvalid; - wire SDCin_axi_rready; - // ---------------------------------------------------------------- - - // 32to64 dwidth converter input interface ----------------------- - wire [31:0]SDCout_axi_awaddr; - wire [7:0]SDCout_axi_awlen; - wire [2:0]SDCout_axi_awsize; - wire [1:0]SDCout_axi_awburst; - wire [0:0]SDCout_axi_awlock; - wire [3:0]SDCout_axi_awcache; - wire [2:0]SDCout_axi_awprot; - wire [3:0]SDCout_axi_awregion; - wire [3:0]SDCout_axi_awqos; - wire SDCout_axi_awvalid; - wire SDCout_axi_awready; - wire [31:0]SDCout_axi_wdata; - wire [3:0]SDCout_axi_wstrb; - wire SDCout_axi_wlast; - wire SDCout_axi_wvalid; - wire SDCout_axi_wready; - wire [1:0]SDCout_axi_bresp; - wire SDCout_axi_bvalid; - wire SDCout_axi_bready; - wire [31:0]SDCout_axi_araddr; - wire [7:0]SDCout_axi_arlen; - wire [2:0]SDCout_axi_arsize; - wire [1:0]SDCout_axi_arburst; - wire [0:0]SDCout_axi_arlock; - wire [3:0]SDCout_axi_arcache; - wire [2:0]SDCout_axi_arprot; - wire [3:0]SDCout_axi_arregion; - wire [3:0]SDCout_axi_arqos; - wire SDCout_axi_arvalid; - wire SDCout_axi_arready; - wire [31:0]SDCout_axi_rdata; - wire [1:0]SDCout_axi_rresp; - wire SDCout_axi_rlast; - wire SDCout_axi_rvalid; - wire SDCout_axi_rready; - - // Output Interface - wire [31:0]m01_axi_awaddr; - wire [7:0]m01_axi_awlen; - wire [2:0]m01_axi_awsize; - wire [1:0]m01_axi_awburst; - wire [0:0]m01_axi_awlock; - wire [3:0]m01_axi_awcache; - wire [2:0]m01_axi_awprot; - wire [3:0]m01_axi_awregion; - wire [3:0]m01_axi_awqos; - wire m01_axi_awvalid; - wire m01_axi_awready; - wire [31:0]m01_axi_wdata; - wire [3:0]m01_axi_wstrb; - wire m01_axi_wlast; - wire m01_axi_wvalid; - wire m01_axi_wready; - wire [1:0]m01_axi_bresp; - wire m01_axi_bvalid; - wire m01_axi_bready; - wire [31:0]m01_axi_araddr; - wire [7:0]m01_axi_arlen; - wire [2:0]m01_axi_arsize; - wire [1:0]m01_axi_arburst; - wire [0:0]m01_axi_arlock; - wire [3:0]m01_axi_arcache; - wire [2:0]m01_axi_arprot; - wire [3:0]m01_axi_arregion; - wire [3:0]m01_axi_arqos; - wire m01_axi_arvalid; - wire m01_axi_arready; - wire [31:0]m01_axi_rdata; - wire [1:0]m01_axi_rresp; - wire m01_axi_rlast; - wire m01_axi_rvalid; - wire m01_axi_rready; + assign GPIOPinsIn = {28'b0, GPI}; assign GPO = GPIOPinsOut[4:0]; @@ -487,358 +296,48 @@ module fpgaTop .m_axi_rlast(m_axi_rlast), .m_axi_rready(m_axi_rready)); - // AXI Crossbar for arbitrating the SDC and CPU -------------- - xlnx_axi_crossbar xlnx_axi_crossbar_0 - (.aclk(CPUCLK), - .aresetn(peripheral_aresetn), - - // Connect Masters - .s_axi_awid({m_axi_awid, m01_axi_awid}), - .s_axi_awaddr({m_axi_awaddr, m01_axi_awaddr}), - .s_axi_awlen({m_axi_awlen, m01_axi_awlen}), - .s_axi_awsize({m_axi_awsize, m01_axi_awsize}), - .s_axi_awburst({m_axi_awburst, m01_axi_awburst}), - .s_axi_awlock({m_axi_awlock, m01_axi_awlock}), - .s_axi_awcache({m_axi_awcache, m01_axi_awcache}), - .s_axi_awprot({m_axi_awprot, m01_axi_awprot}), - .s_axi_awqos(8'b0), - .s_axi_awregion(8'b0), - .s_axi_awvalid({m_axi_awvalid, m01_axi_awvalid}), - .s_axi_awready({m_axi_awready, m01_axi_awready}), - .s_axi_wdata({m_axi_wdata, m01_axi_wdata}), - .s_axi_wstrb({m_axi_wstrb, m01_axi_wstrb}), - .s_axi_wlast({m_axi_wlast, m01_axi_wlast}), - .s_axi_wvalid({m_axi_wvalid, m01_axi_wvalid}), - .s_axi_wready({m_axi_wready, m01_axi_wready}), - .s_axi_bid({m_axi_bid, m01_axi_bid}), - .s_axi_bresp({m_axi_bresp, m01_axi_bresp}), - .s_axi_bvalid({m_axi_bvalid, m01_axi_bvalid}), - .s_axi_bready({m_axi_bready, m01_axi_bready}), - .s_axi_arid({m_axi_arid, m01_axi_arid}), - .s_axi_araddr({m_axi_araddr, m01_axi_araddr}), - .s_axi_arlen({m_axi_arlen, m01_axi_arlen}), - .s_axi_arsize({m_axi_arsize, m01_axi_arsize}), - .s_axi_arburst({m_axi_arburst, m01_axi_arburst}), - .s_axi_arlock({m_axi_arlock, m01_axi_arlock}), - .s_axi_arcache({m_axi_arcache, m01_axi_arcache}), - .s_axi_arprot({m_axi_arprot, m01_axi_arprot}), - .s_axi_arqos(8'b0), - .s_axi_arregion(8'b0), - .s_axi_arvalid({m_axi_arvalid, m01_axi_arvalid}), - .s_axi_arready({m_axi_arready, m01_axi_arready}), - .s_axi_rid({m_axi_rid, m01_axi_rid}), - .s_axi_rdata({m_axi_rdata, m01_axi_rdata}), - .s_axi_rresp({m_axi_rresp, m01_axi_rresp}), - .s_axi_rlast({m_axi_rlast, m01_axi_rlast}), - .s_axi_rvalid({m_axi_rvalid, m01_axi_rvalid}), - .s_axi_rready({m_axi_rready, m01_axi_rready}), - - // Connect Slaves - .m_axi_awid({s00_axi_awid, s01_axi_awid}), - .m_axi_awlen({s00_axi_awlen, s01_axi_awlen}), - .m_axi_awsize({s00_axi_awsize, s01_axi_awsize}), - .m_axi_awburst({s00_axi_awburst, s01_axi_awburst}), - .m_axi_awcache({s00_axi_awcache, s01_axi_awcache}), - .m_axi_awaddr({s00_axi_awaddr, s01_axi_awaddr}), - .m_axi_awprot({s00_axi_awprot, s01_axi_awprot}), - .m_axi_awregion({s00_axi_awregion, s01_axi_awregion}), - .m_axi_awqos({s00_axi_awqos, s01_axi_awqos}), - .m_axi_awvalid({s00_axi_awvalid, s01_axi_awvalid}), - .m_axi_awready({s00_axi_awready, s01_axi_awready}), - .m_axi_awlock({s00_axi_awlock, s01_axi_awlock}), - .m_axi_wdata({s00_axi_wdata, s01_axi_wdata}), - .m_axi_wstrb({s00_axi_wstrb, s01_axi_wstrb}), - .m_axi_wlast({s00_axi_wlast, s01_axi_wlast}), - .m_axi_wvalid({s00_axi_wvalid, s01_axi_wvalid}), - .m_axi_wready({s00_axi_wready, s01_axi_wready}), - .m_axi_bid({s00_axi_bid, s01_axi_bid}), - .m_axi_bresp({s00_axi_bresp, s01_axi_bresp}), - .m_axi_bvalid({s00_axi_bvalid, s01_axi_bvalid}), - .m_axi_bready({s00_axi_bready, s01_axi_bready}), - .m_axi_arid({s00_axi_arid, s01_axi_arid}), - .m_axi_arlen({s00_axi_arlen, s01_axi_arlen}), - .m_axi_arsize({s00_axi_arsize, s01_axi_arsize}), - .m_axi_arburst({s00_axi_arburst, s01_axi_arburst}), - .m_axi_arprot({s00_axi_arprot, s01_axi_arprot}), - .m_axi_arregion({s00_axi_arregion, s01_axi_arregion}), - .m_axi_arqos({s00_axi_arqos, s01_axi_arqos}), - .m_axi_arcache({s00_axi_arcache, s01_axi_arcache}), - .m_axi_arvalid({s00_axi_arvalid, s01_axi_arvalid}), - .m_axi_araddr({s00_axi_araddr, s01_axi_araddr}), - .m_axi_arlock({s00_axi_arlock, s01_axi_arlock}), - .m_axi_arready({s00_axi_arready, s01_axi_arready}), - .m_axi_rid({s00_axi_rid, s01_axi_rid}), - .m_axi_rdata({s00_axi_rdata, s01_axi_rdata}), - .m_axi_rresp({s00_axi_rresp, s01_axi_rresp}), - .m_axi_rvalid({s00_axi_rvalid, s01_axi_rvalid}), - .m_axi_rlast({s00_axi_rlast, s01_axi_rlast}), - .m_axi_rready({s00_axi_rready, s01_axi_rready}) - ); - - // ----------------------------------------------------- - - // SDC Implementation ---------------------------------- - // - // The SDC peripheral from Eugene Tarassov takes in an AXI4Lite - // interface and outputs an AXI4 interface. In order to convert from - // one to the other, we use these dwidth converters to make sure the - // bit widths match the rest of the bus. - - xlnx_axi_dwidth_conv_64to32 axi_conv_down - (.s_axi_aclk(CPUCLK), - .s_axi_aresetn(peripheral_aresetn), - - // Slave interface - .s_axi_awaddr(s01_axi_awaddr), - .s_axi_awlen(s01_axi_awlen), - .s_axi_awsize(s01_axi_awsize), - .s_axi_awburst(s01_axi_awburst), - .s_axi_awlock(s01_axi_awlock), - .s_axi_awcache(s01_axi_awcache), - .s_axi_awprot(s01_axi_awprot), - .s_axi_awregion(s01_axi_awregion), - .s_axi_awqos(4'b0), - .s_axi_awvalid(s01_axi_awvalid), - .s_axi_awready(s01_axi_awready), - .s_axi_wdata(s01_axi_wdata), - .s_axi_wstrb(s01_axi_wstrb), - .s_axi_wlast(s01_axi_wlast), - .s_axi_wvalid(s01_axi_wvalid), - .s_axi_wready(s01_axi_wready), - .s_axi_bresp(s01_axi_bresp), - .s_axi_bvalid(s01_axi_bvalid), - .s_axi_bready(s01_axi_bready), - .s_axi_araddr(s01_axi_araddr), - .s_axi_arlen(s01_axi_arlen), - .s_axi_arsize(s01_axi_arsize), - .s_axi_arburst(s01_axi_arburst), - .s_axi_arlock(s01_axi_arlock), - .s_axi_arcache(s01_axi_arcache), - .s_axi_arprot(s01_axi_arprot), - .s_axi_arregion(s01_axi_arregion), - .s_axi_arqos(4'b0), - .s_axi_arvalid(s01_axi_arvalid), - .s_axi_arready(s01_axi_arready), - .s_axi_rdata(s01_axi_rdata), - .s_axi_rresp(s01_axi_rresp), - .s_axi_rlast(s01_axi_rlast), - .s_axi_rvalid(s01_axi_rvalid), - .s_axi_rready(s01_axi_rready), - - // Master interface - .m_axi_awaddr(SDCin_axi_awaddr), - .m_axi_awlen(SDCin_axi_awlen), - .m_axi_awsize(SDCin_axi_awsize), - .m_axi_awburst(SDCin_axi_awburst), - .m_axi_awlock(SDCin_axi_awlock), - .m_axi_awcache(SDCin_axi_awcache), - .m_axi_awprot(SDCin_axi_awprot), - .m_axi_awregion(SDCin_axi_awregion), - .m_axi_awqos(SDCin_axi_awqos), - .m_axi_awvalid(SDCin_axi_awvalid), - .m_axi_awready(SDCin_axi_awready), - .m_axi_wdata(SDCin_axi_wdata), - .m_axi_wstrb(SDCin_axi_wstrb), - .m_axi_wlast(SDCin_axi_wlast), - .m_axi_wvalid(SDCin_axi_wvalid), - .m_axi_wready(SDCin_axi_wready), - .m_axi_bresp(SDCin_axi_bresp), - .m_axi_bvalid(SDCin_axi_bvalid), - .m_axi_bready(SDCin_axi_bready), - .m_axi_araddr(SDCin_axi_araddr), - .m_axi_arlen(SDCin_axi_arlen), - .m_axi_arsize(SDCin_axi_arsize), - .m_axi_arburst(SDCin_axi_arburst), - .m_axi_arlock(SDCin_axi_arlock), - .m_axi_arcache(SDCin_axi_arcache), - .m_axi_arprot(SDCin_axi_arprot), - .m_axi_arregion(SDCin_axi_arregion), - .m_axi_arqos(SDCin_axi_arqos), - .m_axi_arvalid(SDCin_axi_arvalid), - .m_axi_arready(SDCin_axi_arready), - .m_axi_rdata(SDCin_axi_rdata), - .m_axi_rresp(SDCin_axi_rresp), - .m_axi_rlast(SDCin_axi_rlast), - .m_axi_rvalid(SDCin_axi_rvalid), - .m_axi_rready(SDCin_axi_rready), - ); - - axi_sdc_controller axiSDC - (.clock(CPUCLK), - .async_resetn(peripheral_aresetn), - - // Slave Interface - .s_axi_awaddr(SDCin_axi_awaddr[15:0]), - .s_axi_awvalid(SDCin_axi_awvalid), - .s_axi_awready(SDCin_axi_awready), - .s_axi_wdata(SDCin_axi_wdata), - .s_axi_wvalid(SDCin_axi_wvalid), - .s_axi_wready(SDCin_axi_wready), - .s_axi_bresp(SDCin_axi_bresp), - .s_axi_bvalid(SDCin_axi_bvalid), - .s_axi_bready(SDCin_axi_bready), - .s_axi_araddr(SDCin_axi_araddr[15:0]), - .s_axi_arvalid(SDCin_axi_arvalid), - .s_axi_arready(SDCin_axi_arready), - .s_axi_rdata(SDCin_axi_rdata), - .s_axi_rresp(SDCin_axi_rresp), - .s_axi_rvalid(SDCin_axi_rvalid), - .s_axi_rready(SDCin_axi_rready), - - // Master Interface - .m_axi_awaddr(SDCout_axi_awaddr), - .m_axi_awlen(SDCout_axi_awlen), - .m_axi_awvalid(SDCout_axi_awvalid), - .m_axi_awready(SDCout_axi_awready), - .m_axi_wdata(SDCout_axi_wdata), - .m_axi_wlast(SDCout_axi_wlast), - .m_axi_wvalid(SDCout_axi_wvalid), - .m_axi_wready(SDCout_axi_wready), - .m_axi_bresp(SDCout_axi_bresp), - .m_axi_bvalid(SDCout_axi_bvalid), - .m_axi_bready(SDCout_axi_bready), - .m_axi_araddr(SDCout_axi_araddr), - .m_axi_arlen(SDCout_axi_arlen), - .m_axi_arvalid(SDCout_axi_arvalid), - .m_axi_arready(SDCout_axi_arready), - .m_axi_rdata(SDCout_axi_rdata), - .m_axi_rlast(SDCout_axi_rlast), - .m_axi_rresp(SDCout_axi_rresp), - .m_axi_rvalid(SDCout_axi_rvalid), - .m_axi_rready(SDCout_axi_rready), - - // SDC interface - //.sdio_cmd(SDCcmd), - //.sdio_dat(SDCdat), - //.sdio_cd() - - - - ); - - xlnx_axi_dwidth_conv_32to64 axi_conv_up - (.s_axi_aclk(CPUCLK), - .s_axi_aresetn(peripheral_aresetn), - - // Slave interface - .s_axi_awaddr(SDCout_axi_awaddr), - .s_axi_awlen(SDCout_axi_awlen), - .s_axi_awsize(3'b0), - .s_axi_awburst(2'b0), - .s_axi_awlock(1'b0), - .s_axi_awcache(4'b0), - .s_axi_awprot(3'b0), - .s_axi_awregion(4'b0), - .s_axi_awqos(4'b0), - .s_axi_awvalid(SDCout_axi_awvalid), - .s_axi_awready(SDCout_axi_awready), - .s_axi_wdata(SDCout_axi_wdata), - .s_axi_wstrb(4'b0), - .s_axi_wlast(SDCout_axi_wlast), - .s_axi_wvalid(SDCout_axi_wvalid), - .s_axi_wready(SDCout_axi_wready), - .s_axi_bresp(SDCout_axi_bresp), - .s_axi_bvalid(SDCout_axi_bvalid), - .s_axi_bready(SDCout_axi_bready), - .s_axi_araddr(SDCout_axi_araddr), - .s_axi_arlen(SDCout_axi_arlen), - .s_axi_arsize(3'b0), - .s_axi_arburst(2'b0), - .s_axi_arlock(1'b0), - .s_axi_arcache(4'b0), - .s_axi_arprot(3'b0), - .s_axi_arregion(4'b0), - .s_axi_arqos(4'b0), - .s_axi_arvalid(SDCout_axi_arvalid), - .s_axi_arready(SDCout_axi_arready), - .s_axi_rdata(SDCout_axi_rdata), - //.s_axi_rresp(), - .s_axi_rlast(SDCout_axi_rlast), - .s_axi_rvalid(SDCout_axi_rvalid), - .s_axi_rready(SDCout_axi_rready), - - // Master interface - .m_axi_awaddr(m01_axi_awaddr), - .m_axi_awlen(m01_axi_awlen), - .m_axi_awsize(m01_axi_awsize), - .m_axi_awburst(m01_axi_awburst), - .m_axi_awlock(m01_axi_awlock), - .m_axi_awcache(m01_axi_awcache), - .m_axi_awprot(m01_axi_awprot), - .m_axi_awregion(m01_axi_awregion), - .m_axi_awqos(m01_axi_awqos), - .m_axi_awvalid(m01_axi_awvalid), - .m_axi_awready(m01_axi_awready), - .m_axi_wdata(m01_axi_wdata), - .m_axi_wstrb(m01_axi_wstrb), - .m_axi_wlast(m01_axi_wlast), - .m_axi_wvalid(m01_axi_wvalid), - .m_axi_wready(m01_axi_wready), - .m_axi_bresp(m01_axi_bresp), - .m_axi_bvalid(m01_axi_bvalid), - .m_axi_bready(m01_axi_bready), - .m_axi_araddr(m01_axi_araddr), - .m_axi_arlen(m01_axi_arlen), - .m_axi_arsize(m01_axi_arsize), - .m_axi_arburst(m01_axi_arburst), - .m_axi_arlock(m01_axi_arlock), - .m_axi_arcache(m01_axi_arcache), - .m_axi_arprot(m01_axi_arprot), - .m_axi_arregion(m01_axi_arregion), - .m_axi_arqos(m01_axi_arqos), - .m_axi_arvalid(m01_axi_arvalid), - .m_axi_arready(m01_axi_arready), - .m_axi_rdata(m01_axi_rdata), - .m_axi_rresp(m01_axi_rresp), - .m_axi_rlast(m01_axi_rlast), - .m_axi_rvalid(m01_axi_rvalid), - .m_axi_rready(m01_axi_rready), - ); - - // End SDC signals -------------------------------------------- - xlnx_axi_clock_converter xlnx_axi_clock_converter_0 (.s_axi_aclk(CPUCLK), .s_axi_aresetn(peripheral_aresetn), - .s_axi_awid(s00_axi_awid), - .s_axi_awlen(s00_axi_awlen), - .s_axi_awsize(s00_axi_awsize), - .s_axi_awburst(s00_axi_awburst), - .s_axi_awcache(s00_axi_awcache), - .s_axi_awaddr(s00_axi_awaddr[30:0] ), - .s_axi_awprot(s00_axi_awprot), + .s_axi_awid(m_axi_awid), + .s_axi_awlen(m_axi_awlen), + .s_axi_awsize(m_axi_awsize), + .s_axi_awburst(m_axi_awburst), + .s_axi_awcache(m_axi_awcache), + .s_axi_awaddr(m_axi_awaddr[30:0]), + .s_axi_awprot(m_axi_awprot), .s_axi_awregion(4'b0), // this could be a bug. bridge does not have these outputs .s_axi_awqos(4'b0), // this could be a bug. bridge does not have these outputs - .s_axi_awvalid(s00_axi_awvalid), - .s_axi_awready(s00_axi_awready), - .s_axi_awlock(s00_axi_awlock), - .s_axi_wdata(s00_axi_wdata), - .s_axi_wstrb(s00_axi_wstrb), - .s_axi_wlast(s00_axi_wlast), - .s_axi_wvalid(s00_axi_wvalid), - .s_axi_wready(s00_axi_wready), - .s_axi_bid(s00_axi_bid), - .s_axi_bresp(s00_axi_bresp), - .s_axi_bvalid(s00_axi_bvalid), - .s_axi_bready(s00_axi_bready), - .s_axi_arid(s00_axi_arid), - .s_axi_arlen(s00_axi_arlen), - .s_axi_arsize(s00_axi_arsize), - .s_axi_arburst(s00_axi_arburst), - .s_axi_arprot(s00_axi_arprot), + .s_axi_awvalid(m_axi_awvalid), + .s_axi_awready(m_axi_awready), + .s_axi_awlock(m_axi_awlock), + .s_axi_wdata(m_axi_wdata), + .s_axi_wstrb(m_axi_wstrb), + .s_axi_wlast(m_axi_wlast), + .s_axi_wvalid(m_axi_wvalid), + .s_axi_wready(m_axi_wready), + .s_axi_bid(m_axi_bid), + .s_axi_bresp(m_axi_bresp), + .s_axi_bvalid(m_axi_bvalid), + .s_axi_bready(m_axi_bready), + .s_axi_arid(m_axi_arid), + .s_axi_arlen(m_axi_arlen), + .s_axi_arsize(m_axi_arsize), + .s_axi_arburst(m_axi_arburst), + .s_axi_arprot(m_axi_arprot), .s_axi_arregion(4'b0), // this could be a bug. bridge does not have these outputs .s_axi_arqos(4'b0), // this could be a bug. bridge does not have these outputs - .s_axi_arcache(s00_axi_arcache), - .s_axi_arvalid(s00_axi_arvalid), - .s_axi_araddr(s00_axi_araddr[30:0]), - .s_axi_arlock(s00_axi_arlock), - .s_axi_arready(s00_axi_arready), - .s_axi_rid(s00_axi_rid), - .s_axi_rdata(s00_axi_rdata), - .s_axi_rresp(s00_axi_rresp), - .s_axi_rvalid(s00_axi_rvalid), - .s_axi_rlast(s00_axi_rlast), - .s_axi_rready(s00_axi_rready), + .s_axi_arcache(m_axi_arcache), + .s_axi_arvalid(m_axi_arvalid), + .s_axi_araddr(m_axi_araddr[30:0]), + .s_axi_arlock(m_axi_arlock), + .s_axi_arready(m_axi_arready), + .s_axi_rid(m_axi_rid), + .s_axi_rdata(m_axi_rdata), + .s_axi_rresp(m_axi_rresp), + .s_axi_rvalid(m_axi_rvalid), + .s_axi_rlast(m_axi_rlast), + .s_axi_rready(m_axi_rready), .m_axi_aclk(BUSCLK), .m_axi_aresetn(~reset), @@ -881,7 +380,7 @@ module fpgaTop .m_axi_rvalid(BUS_axi_rvalid), .m_axi_rlast(BUS_axi_rlast), .m_axi_rready(BUS_axi_rready)); - + xlnx_ddr4 xlnx_ddr4_c0 (.c0_init_calib_complete(c0_init_calib_complete), .dbg_clk(dbg_clk), // open diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh index b2c91b557..c8bf4a797 100644 --- a/pipelined/config/fpga/wally-config.vh +++ b/pipelined/config/fpga/wally-config.vh @@ -123,8 +123,9 @@ `define SDC_RANGE 56'h0000001F // Temporary Boot Process Stuff +`define SDC2_SUPPORTED 1'b1 `define SDC2_BASE 56'h00013000 -`defube SDC2_RANGE 56'h0000007F +`define SDC2_RANGE 56'h0000007F // Bus Interface width `define AHBW 64 diff --git a/pipelined/src/mmu/adrdecs.sv b/pipelined/src/mmu/adrdecs.sv index 3443af1a9..498f20ecf 100644 --- a/pipelined/src/mmu/adrdecs.sv +++ b/pipelined/src/mmu/adrdecs.sv @@ -46,7 +46,7 @@ module adrdecs ( adrdec uartdec(PhysicalAddress, `UART_BASE, `UART_RANGE, `UART_SUPPORTED, AccessRW, Size, 4'b0001, SelRegions[3]); adrdec plicdec(PhysicalAddress, `PLIC_BASE, `PLIC_RANGE, `PLIC_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[2]); adrdec sdcdec(PhysicalAddress, `SDC_BASE, `SDC_RANGE, `SDC_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE & 4'b1100, SelRegions[1]); - adrdec newsdc(PhysicalAddressm `SDC2_BASE, `SDC2RANGE, 1'b1, AccessRW, Size, SUPPORTED_SIZE, SelRegions[11]); + adrdec newsdc(PhysicalAddress, `SDC2_BASE, `SDC2_RANGE, `SDC2_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE, SelRegions[11]); assign SelRegions[0] = ~|(SelRegions[11:1]); // none of the regions are selected diff --git a/tests/custom/boot/boot.c b/tests/custom/boot/boot.c index 71f22534f..b79802ef3 100644 --- a/tests/custom/boot/boot.c +++ b/tests/custom/boot/boot.c @@ -368,3 +368,11 @@ static int ini_sd(void) { drv_status &= ~STA_NOINIT; return 0; } + +int main() { + ini_sd(); + + + + return 0; +} From ee3a9537a8d6c2ee5ee69aeaf6b3d5b48995f8f4 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Tue, 17 Jan 2023 16:46:00 -0600 Subject: [PATCH 05/22] Fixed errors in uncore and included newsdc stuff in wally.tcl --- fpga/generator/wally.tcl | 1 + fpga/src/fpgaTop.v | 579 ++++++++++++++++++++++++++++++--- pipelined/src/uncore/uncore.sv | 1 + 3 files changed, 541 insertions(+), 40 deletions(-) diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index 15aa5bf7f..fd47a892f 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -20,6 +20,7 @@ read_ip IP/xlnx_axi_dwidth_conv_32to64.srcs/sources_1/ip/xlnx_axi_dwidth_conv_32 read_ip IP/xlnx_axi_dwidth_conv_64to32.srcs/sources_1/ip/xlnx_axi_dwidth_conv_64to32/xlnx_axi_dwidth_conv_64to32.xci read_verilog -sv [glob -type f ../../pipelined/src/*/*.sv ../../pipelined/src/*/*/*.sv] +read_verilog [glob -type f ../../pipelined/src/uncore/newsdc/*.v] read_verilog {../src/fpgaTop.v} set_property include_dirs {../../pipelined/config/fpga ../../pipelined/config/shared} [current_fileset] diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index 6a26be74e..3f72c5ec0 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -38,7 +38,7 @@ module fpgaTop input UARTSin, output UARTSout, - input [3:0] SDCDat, + inout [3:0] SDCDat, output SDCCLK, inout SDCCmd, @@ -130,11 +130,13 @@ module fpgaTop wire m_axi_rlast; wire m_axi_rready; + // Extra Bus signals wire [3:0] BUS_axi_arregion; wire [3:0] BUS_axi_arqos; wire [3:0] BUS_axi_awregion; wire [3:0] BUS_axi_awqos; + // Bus signals wire [3:0] BUS_axi_awid; wire [7:0] BUS_axi_awlen; wire [2:0] BUS_axi_awsize; @@ -170,7 +172,7 @@ module fpgaTop wire BUS_axi_rvalid; wire BUS_axi_rlast; wire BUS_axi_rready; - + wire BUSCLK; @@ -179,9 +181,198 @@ module fpgaTop wire [511 : 0] dbg_bus; wire CLK208; - - + + // Crossbar to Bus ------------------------------------------------ + + wire s00_axi_aclk; + wire s00_axi_aresetn; + wire [31:0]s00_axi_awaddr; + wire [7:0]s00_axi_awlen; + wire [2:0]s00_axi_awsize; + wire [1:0]s00_axi_awburst; + wire [0:0]s00_axi_awlock; + wire [3:0]s00_axi_awcache; + wire [2:0]s00_axi_awprot; + wire [3:0]s00_axi_awregion; + wire [3:0]s00_axi_awqos; + wire s00_axi_awvalid; + wire s00_axi_awready; + wire [63:0]s00_axi_wdata; + wire [7:0]s00_axi_wstrb; + wire s00_axi_wlast; + wire s00_axi_wvalid; + wire s00_axi_wready; + wire [1:0]s00_axi_bresp; + wire s00_axi_bvalid; + wire s00_axi_bready; + wire [31:0]s00_axi_araddr; + wire [7:0]s00_axi_arlen; + wire [2:0]s00_axi_arsize; + wire [1:0]s00_axi_arburst; + wire [0:0]s00_axi_arlock; + wire [3:0]s00_axi_arcache; + wire [2:0]s00_axi_arprot; + wire [3:0]s00_axi_arregion; + wire [3:0]s00_axi_arqos; + wire s00_axi_arvalid; + wire s00_axi_arready; + wire [63:0]s00_axi_rdata; + wire [1:0]s00_axi_rresp; + wire s00_axi_rlast; + wire s00_axi_rvalid; + wire s00_axi_rready; + + // 64to32 dwidth converter input interface------------------------- + wire s01_axi_aclk; + wire s01_axi_aresetn; + wire [31:0]s01_axi_awaddr; + wire [7:0]s01_axi_awlen; + wire [2:0]s01_axi_awsize; + wire [1:0]s01_axi_awburst; + wire [0:0]s01_axi_awlock; + wire [3:0]s01_axi_awcache; + wire [2:0]s01_axi_awprot; + wire [3:0]s01_axi_awregion; + wire [3:0]s01_axi_awqos; // qos signals need to be 0 for SDC + wire s01_axi_awvalid; + wire s01_axi_awready; + wire [63:0]s01_axi_wdata; + wire [7:0]s01_axi_wstrb; + wire s01_axi_wlast; + wire s01_axi_wvalid; + wire s01_axi_wready; + wire [1:0]s01_axi_bresp; + wire s01_axi_bvalid; + wire s01_axi_bready; + wire [31:0]s01_axi_araddr; + wire [7:0]s01_axi_arlen; + wire [2:0]s01_axi_arsize; + wire [1:0]s01_axi_arburst; + wire [0:0]s01_axi_arlock; + wire [3:0]s01_axi_arcache; + wire [2:0]s01_axi_arprot; + wire [3:0]s01_axi_arregion; + wire [3:0]s01_axi_arqos; // + wire s01_axi_arvalid; + wire s01_axi_arready; + wire [63:0]s01_axi_rdata; + wire [1:0]s01_axi_rresp; + wire s01_axi_rlast; + wire s01_axi_rvalid; + wire s01_axi_rready; + + // Output Interface + wire [31:0]SDCin_axi_awaddr; + wire [7:0]SDCin_axi_awlen; + wire [2:0]SDCin_axi_awsize; + wire [1:0]SDCin_axi_awburst; + wire [0:0]SDCin_axi_awlock; + wire [3:0]SDCin_axi_awcache; + wire [2:0]SDCin_axi_awprot; + wire [3:0]SDCin_axi_awregion; + wire [3:0]SDCin_axi_awqos; + wire SDCin_axi_awvalid; + wire SDCin_axi_awready; + wire [31:0]SDCin_axi_wdata; + wire [3:0]SDCin_axi_wstrb; + wire SDCin_axi_wlast; + wire SDCin_axi_wvalid; + wire SDCin_axi_wready; + wire [1:0]SDCin_axi_bresp; + wire SDCin_axi_bvalid; + wire SDCin_axi_bready; + wire [31:0]SDCin_axi_araddr; + wire [7:0]SDCin_axi_arlen; + wire [2:0]SDCin_axi_arsize; + wire [1:0]SDCin_axi_arburst; + wire [0:0]SDCin_axi_arlock; + wire [3:0]SDCin_axi_arcache; + wire [2:0]SDCin_axi_arprot; + wire [3:0]SDCin_axi_arregion; + wire [3:0]SDCin_axi_arqos; + wire SDCin_axi_arvalid; + wire SDCin_axi_arready; + wire [31:0]SDCin_axi_rdata; + wire [1:0]SDCin_axi_rresp; + wire SDCin_axi_rlast; + wire SDCin_axi_rvalid; + wire SDCin_axi_rready; + // ---------------------------------------------------------------- + + // 32to64 dwidth converter input interface ----------------------- + wire [31:0]SDCout_axi_awaddr; + wire [7:0]SDCout_axi_awlen; + wire [2:0]SDCout_axi_awsize; + wire [1:0]SDCout_axi_awburst; + wire [0:0]SDCout_axi_awlock; + wire [3:0]SDCout_axi_awcache; + wire [2:0]SDCout_axi_awprot; + wire [3:0]SDCout_axi_awregion; + wire [3:0]SDCout_axi_awqos; + wire SDCout_axi_awvalid; + wire SDCout_axi_awready; + wire [31:0]SDCout_axi_wdata; + wire [3:0]SDCout_axi_wstrb; + wire SDCout_axi_wlast; + wire SDCout_axi_wvalid; + wire SDCout_axi_wready; + wire [1:0]SDCout_axi_bresp; + wire SDCout_axi_bvalid; + wire SDCout_axi_bready; + wire [31:0]SDCout_axi_araddr; + wire [7:0]SDCout_axi_arlen; + wire [2:0]SDCout_axi_arsize; + wire [1:0]SDCout_axi_arburst; + wire [0:0]SDCout_axi_arlock; + wire [3:0]SDCout_axi_arcache; + wire [2:0]SDCout_axi_arprot; + wire [3:0]SDCout_axi_arregion; + wire [3:0]SDCout_axi_arqos; + wire SDCout_axi_arvalid; + wire SDCout_axi_arready; + wire [31:0]SDCout_axi_rdata; + wire [1:0]SDCout_axi_rresp; + wire SDCout_axi_rlast; + wire SDCout_axi_rvalid; + wire SDCout_axi_rready; + + // Output Interface + wire [31:0]m01_axi_awaddr; + wire [7:0]m01_axi_awlen; + wire [2:0]m01_axi_awsize; + wire [1:0]m01_axi_awburst; + wire [0:0]m01_axi_awlock; + wire [3:0]m01_axi_awcache; + wire [2:0]m01_axi_awprot; + wire [3:0]m01_axi_awregion; + wire [3:0]m01_axi_awqos; + wire m01_axi_awvalid; + wire m01_axi_awready; + wire [31:0]m01_axi_wdata; + wire [3:0]m01_axi_wstrb; + wire m01_axi_wlast; + wire m01_axi_wvalid; + wire m01_axi_wready; + wire [1:0]m01_axi_bresp; + wire m01_axi_bvalid; + wire m01_axi_bready; + wire [31:0]m01_axi_araddr; + wire [7:0]m01_axi_arlen; + wire [2:0]m01_axi_arsize; + wire [1:0]m01_axi_arburst; + wire [0:0]m01_axi_arlock; + wire [3:0]m01_axi_arcache; + wire [2:0]m01_axi_arprot; + wire [3:0]m01_axi_arregion; + wire [3:0]m01_axi_arqos; + wire m01_axi_arvalid; + wire m01_axi_arready; + wire [31:0]m01_axi_rdata; + wire [1:0]m01_axi_rresp; + wire m01_axi_rlast; + wire m01_axi_rvalid; + wire m01_axi_rready; assign GPIOPinsIn = {28'b0, GPI}; assign GPO = GPIOPinsOut[4:0]; @@ -296,48 +487,356 @@ module fpgaTop .m_axi_rlast(m_axi_rlast), .m_axi_rready(m_axi_rready)); + // AXI Crossbar for arbitrating the SDC and CPU -------------- + xlnx_axi_crossbar xlnx_axi_crossbar_0 + (.aclk(CPUCLK), + .aresetn(peripheral_aresetn), + + // Connect Masters + .s_axi_awid({m_axi_awid, m01_axi_awid}), + .s_axi_awaddr({m_axi_awaddr, m01_axi_awaddr}), + .s_axi_awlen({m_axi_awlen, m01_axi_awlen}), + .s_axi_awsize({m_axi_awsize, m01_axi_awsize}), + .s_axi_awburst({m_axi_awburst, m01_axi_awburst}), + .s_axi_awlock({m_axi_awlock, m01_axi_awlock}), + .s_axi_awcache({m_axi_awcache, m01_axi_awcache}), + .s_axi_awprot({m_axi_awprot, m01_axi_awprot}), + .s_axi_awqos(8'b0), + .s_axi_awvalid({m_axi_awvalid, m01_axi_awvalid}), + .s_axi_awready({m_axi_awready, m01_axi_awready}), + .s_axi_wdata({m_axi_wdata, m01_axi_wdata}), + .s_axi_wstrb({m_axi_wstrb, m01_axi_wstrb}), + .s_axi_wlast({m_axi_wlast, m01_axi_wlast}), + .s_axi_wvalid({m_axi_wvalid, m01_axi_wvalid}), + .s_axi_wready({m_axi_wready, m01_axi_wready}), + .s_axi_bid({m_axi_bid, m01_axi_bid}), + .s_axi_bresp({m_axi_bresp, m01_axi_bresp}), + .s_axi_bvalid({m_axi_bvalid, m01_axi_bvalid}), + .s_axi_bready({m_axi_bready, m01_axi_bready}), + .s_axi_arid({m_axi_arid, m01_axi_arid}), + .s_axi_araddr({m_axi_araddr, m01_axi_araddr}), + .s_axi_arlen({m_axi_arlen, m01_axi_arlen}), + .s_axi_arsize({m_axi_arsize, m01_axi_arsize}), + .s_axi_arburst({m_axi_arburst, m01_axi_arburst}), + .s_axi_arlock({m_axi_arlock, m01_axi_arlock}), + .s_axi_arcache({m_axi_arcache, m01_axi_arcache}), + .s_axi_arprot({m_axi_arprot, m01_axi_arprot}), + .s_axi_arqos(8'b0), + .s_axi_arvalid({m_axi_arvalid, m01_axi_arvalid}), + .s_axi_arready({m_axi_arready, m01_axi_arready}), + .s_axi_rid({m_axi_rid, m01_axi_rid}), + .s_axi_rdata({m_axi_rdata, m01_axi_rdata}), + .s_axi_rresp({m_axi_rresp, m01_axi_rresp}), + .s_axi_rlast({m_axi_rlast, m01_axi_rlast}), + .s_axi_rvalid({m_axi_rvalid, m01_axi_rvalid}), + .s_axi_rready({m_axi_rready, m01_axi_rready}), + + // Connect Slaves + .m_axi_awid({s00_axi_awid, s01_axi_awid}), + .m_axi_awlen({s00_axi_awlen, s01_axi_awlen}), + .m_axi_awsize({s00_axi_awsize, s01_axi_awsize}), + .m_axi_awburst({s00_axi_awburst, s01_axi_awburst}), + .m_axi_awcache({s00_axi_awcache, s01_axi_awcache}), + .m_axi_awaddr({s00_axi_awaddr, s01_axi_awaddr}), + .m_axi_awprot({s00_axi_awprot, s01_axi_awprot}), + .m_axi_awregion({s00_axi_awregion, s01_axi_awregion}), + .m_axi_awqos({s00_axi_awqos, s01_axi_awqos}), + .m_axi_awvalid({s00_axi_awvalid, s01_axi_awvalid}), + .m_axi_awready({s00_axi_awready, s01_axi_awready}), + .m_axi_awlock({s00_axi_awlock, s01_axi_awlock}), + .m_axi_wdata({s00_axi_wdata, s01_axi_wdata}), + .m_axi_wstrb({s00_axi_wstrb, s01_axi_wstrb}), + .m_axi_wlast({s00_axi_wlast, s01_axi_wlast}), + .m_axi_wvalid({s00_axi_wvalid, s01_axi_wvalid}), + .m_axi_wready({s00_axi_wready, s01_axi_wready}), + .m_axi_bid({s00_axi_bid, s01_axi_bid}), + .m_axi_bresp({s00_axi_bresp, s01_axi_bresp}), + .m_axi_bvalid({s00_axi_bvalid, s01_axi_bvalid}), + .m_axi_bready({s00_axi_bready, s01_axi_bready}), + .m_axi_arid({s00_axi_arid, s01_axi_arid}), + .m_axi_arlen({s00_axi_arlen, s01_axi_arlen}), + .m_axi_arsize({s00_axi_arsize, s01_axi_arsize}), + .m_axi_arburst({s00_axi_arburst, s01_axi_arburst}), + .m_axi_arprot({s00_axi_arprot, s01_axi_arprot}), + .m_axi_arregion({s00_axi_arregion, s01_axi_arregion}), + .m_axi_arqos({s00_axi_arqos, s01_axi_arqos}), + .m_axi_arcache({s00_axi_arcache, s01_axi_arcache}), + .m_axi_arvalid({s00_axi_arvalid, s01_axi_arvalid}), + .m_axi_araddr({s00_axi_araddr, s01_axi_araddr}), + .m_axi_arlock({s00_axi_arlock, s01_axi_arlock}), + .m_axi_arready({s00_axi_arready, s01_axi_arready}), + .m_axi_rid({s00_axi_rid, s01_axi_rid}), + .m_axi_rdata({s00_axi_rdata, s01_axi_rdata}), + .m_axi_rresp({s00_axi_rresp, s01_axi_rresp}), + .m_axi_rvalid({s00_axi_rvalid, s01_axi_rvalid}), + .m_axi_rlast({s00_axi_rlast, s01_axi_rlast}), + .m_axi_rready({s00_axi_rready, s01_axi_rready}) + ); + + // ----------------------------------------------------- + + // SDC Implementation ---------------------------------- + // + // The SDC peripheral from Eugene Tarassov takes in an AXI4Lite + // interface and outputs an AXI4 interface. In order to convert from + // one to the other, we use these dwidth converters to make sure the + // bit widths match the rest of the bus. + + xlnx_axi_dwidth_conv_64to32 axi_conv_down + (.s_axi_aclk(CPUCLK), + .s_axi_aresetn(peripheral_aresetn), + + // Slave interface + .s_axi_awaddr(s01_axi_awaddr), + .s_axi_awlen(s01_axi_awlen), + .s_axi_awsize(s01_axi_awsize), + .s_axi_awburst(s01_axi_awburst), + .s_axi_awlock(s01_axi_awlock), + .s_axi_awcache(s01_axi_awcache), + .s_axi_awprot(s01_axi_awprot), + .s_axi_awregion(s01_axi_awregion), + .s_axi_awqos(4'b0), + .s_axi_awvalid(s01_axi_awvalid), + .s_axi_awready(s01_axi_awready), + .s_axi_wdata(s01_axi_wdata), + .s_axi_wstrb(s01_axi_wstrb), + .s_axi_wlast(s01_axi_wlast), + .s_axi_wvalid(s01_axi_wvalid), + .s_axi_wready(s01_axi_wready), + .s_axi_bresp(s01_axi_bresp), + .s_axi_bvalid(s01_axi_bvalid), + .s_axi_bready(s01_axi_bready), + .s_axi_araddr(s01_axi_araddr), + .s_axi_arlen(s01_axi_arlen), + .s_axi_arsize(s01_axi_arsize), + .s_axi_arburst(s01_axi_arburst), + .s_axi_arlock(s01_axi_arlock), + .s_axi_arcache(s01_axi_arcache), + .s_axi_arprot(s01_axi_arprot), + .s_axi_arregion(s01_axi_arregion), + .s_axi_arqos(4'b0), + .s_axi_arvalid(s01_axi_arvalid), + .s_axi_arready(s01_axi_arready), + .s_axi_rdata(s01_axi_rdata), + .s_axi_rresp(s01_axi_rresp), + .s_axi_rlast(s01_axi_rlast), + .s_axi_rvalid(s01_axi_rvalid), + .s_axi_rready(s01_axi_rready), + + // Master interface + .m_axi_awaddr(SDCin_axi_awaddr), + .m_axi_awlen(SDCin_axi_awlen), + .m_axi_awsize(SDCin_axi_awsize), + .m_axi_awburst(SDCin_axi_awburst), + .m_axi_awlock(SDCin_axi_awlock), + .m_axi_awcache(SDCin_axi_awcache), + .m_axi_awprot(SDCin_axi_awprot), + .m_axi_awregion(SDCin_axi_awregion), + .m_axi_awqos(SDCin_axi_awqos), + .m_axi_awvalid(SDCin_axi_awvalid), + .m_axi_awready(SDCin_axi_awready), + .m_axi_wdata(SDCin_axi_wdata), + .m_axi_wstrb(SDCin_axi_wstrb), + .m_axi_wlast(SDCin_axi_wlast), + .m_axi_wvalid(SDCin_axi_wvalid), + .m_axi_wready(SDCin_axi_wready), + .m_axi_bresp(SDCin_axi_bresp), + .m_axi_bvalid(SDCin_axi_bvalid), + .m_axi_bready(SDCin_axi_bready), + .m_axi_araddr(SDCin_axi_araddr), + .m_axi_arlen(SDCin_axi_arlen), + .m_axi_arsize(SDCin_axi_arsize), + .m_axi_arburst(SDCin_axi_arburst), + .m_axi_arlock(SDCin_axi_arlock), + .m_axi_arcache(SDCin_axi_arcache), + .m_axi_arprot(SDCin_axi_arprot), + .m_axi_arregion(SDCin_axi_arregion), + .m_axi_arqos(SDCin_axi_arqos), + .m_axi_arvalid(SDCin_axi_arvalid), + .m_axi_arready(SDCin_axi_arready), + .m_axi_rdata(SDCin_axi_rdata), + .m_axi_rresp(SDCin_axi_rresp), + .m_axi_rlast(SDCin_axi_rlast), + .m_axi_rvalid(SDCin_axi_rvalid), + .m_axi_rready(SDCin_axi_rready) + ); + + sdc_controller axiSDC + (.clock(CPUCLK), + .async_resetn(peripheral_aresetn), + + // Slave Interface + .s_axi_awaddr(SDCin_axi_awaddr[15:0]), + .s_axi_awvalid(SDCin_axi_awvalid), + .s_axi_awready(SDCin_axi_awready), + .s_axi_wdata(SDCin_axi_wdata), + .s_axi_wvalid(SDCin_axi_wvalid), + .s_axi_wready(SDCin_axi_wready), + .s_axi_bresp(SDCin_axi_bresp), + .s_axi_bvalid(SDCin_axi_bvalid), + .s_axi_bready(SDCin_axi_bready), + .s_axi_araddr(SDCin_axi_araddr[15:0]), + .s_axi_arvalid(SDCin_axi_arvalid), + .s_axi_arready(SDCin_axi_arready), + .s_axi_rdata(SDCin_axi_rdata), + .s_axi_rresp(SDCin_axi_rresp), + .s_axi_rvalid(SDCin_axi_rvalid), + .s_axi_rready(SDCin_axi_rready), + + // Master Interface + .m_axi_awaddr(SDCout_axi_awaddr), + .m_axi_awlen(SDCout_axi_awlen), + .m_axi_awvalid(SDCout_axi_awvalid), + .m_axi_awready(SDCout_axi_awready), + .m_axi_wdata(SDCout_axi_wdata), + .m_axi_wlast(SDCout_axi_wlast), + .m_axi_wvalid(SDCout_axi_wvalid), + .m_axi_wready(SDCout_axi_wready), + .m_axi_bresp(SDCout_axi_bresp), + .m_axi_bvalid(SDCout_axi_bvalid), + .m_axi_bready(SDCout_axi_bready), + .m_axi_araddr(SDCout_axi_araddr), + .m_axi_arlen(SDCout_axi_arlen), + .m_axi_arvalid(SDCout_axi_arvalid), + .m_axi_arready(SDCout_axi_arready), + .m_axi_rdata(SDCout_axi_rdata), + .m_axi_rlast(SDCout_axi_rlast), + .m_axi_rresp(SDCout_axi_rresp), + .m_axi_rvalid(SDCout_axi_rvalid), + .m_axi_rready(SDCout_axi_rready) + + // SDC interface + //.sdio_cmd(SDCcmd), + //.sdio_dat(SDCdat), + //.sdio_cd() + + + + ); + + xlnx_axi_dwidth_conv_32to64 axi_conv_up + (.s_axi_aclk(CPUCLK), + .s_axi_aresetn(peripheral_aresetn), + + // Slave interface + .s_axi_awaddr(SDCout_axi_awaddr), + .s_axi_awlen(SDCout_axi_awlen), + .s_axi_awsize(3'b0), + .s_axi_awburst(2'b0), + .s_axi_awlock(1'b0), + .s_axi_awcache(4'b0), + .s_axi_awprot(3'b0), + .s_axi_awregion(4'b0), + .s_axi_awqos(4'b0), + .s_axi_awvalid(SDCout_axi_awvalid), + .s_axi_awready(SDCout_axi_awready), + .s_axi_wdata(SDCout_axi_wdata), + .s_axi_wstrb(4'b0), + .s_axi_wlast(SDCout_axi_wlast), + .s_axi_wvalid(SDCout_axi_wvalid), + .s_axi_wready(SDCout_axi_wready), + .s_axi_bresp(SDCout_axi_bresp), + .s_axi_bvalid(SDCout_axi_bvalid), + .s_axi_bready(SDCout_axi_bready), + .s_axi_araddr(SDCout_axi_araddr), + .s_axi_arlen(SDCout_axi_arlen), + .s_axi_arsize(3'b0), + .s_axi_arburst(2'b0), + .s_axi_arlock(1'b0), + .s_axi_arcache(4'b0), + .s_axi_arprot(3'b0), + .s_axi_arregion(4'b0), + .s_axi_arqos(4'b0), + .s_axi_arvalid(SDCout_axi_arvalid), + .s_axi_arready(SDCout_axi_arready), + .s_axi_rdata(SDCout_axi_rdata), + //.s_axi_rresp(), + .s_axi_rlast(SDCout_axi_rlast), + .s_axi_rvalid(SDCout_axi_rvalid), + .s_axi_rready(SDCout_axi_rready), + + // Master interface + .m_axi_awaddr(m01_axi_awaddr), + .m_axi_awlen(m01_axi_awlen), + .m_axi_awsize(m01_axi_awsize), + .m_axi_awburst(m01_axi_awburst), + .m_axi_awlock(m01_axi_awlock), + .m_axi_awcache(m01_axi_awcache), + .m_axi_awprot(m01_axi_awprot), + .m_axi_awregion(m01_axi_awregion), + .m_axi_awqos(m01_axi_awqos), + .m_axi_awvalid(m01_axi_awvalid), + .m_axi_awready(m01_axi_awready), + .m_axi_wdata(m01_axi_wdata), + .m_axi_wstrb(m01_axi_wstrb), + .m_axi_wlast(m01_axi_wlast), + .m_axi_wvalid(m01_axi_wvalid), + .m_axi_wready(m01_axi_wready), + .m_axi_bresp(m01_axi_bresp), + .m_axi_bvalid(m01_axi_bvalid), + .m_axi_bready(m01_axi_bready), + .m_axi_araddr(m01_axi_araddr), + .m_axi_arlen(m01_axi_arlen), + .m_axi_arsize(m01_axi_arsize), + .m_axi_arburst(m01_axi_arburst), + .m_axi_arlock(m01_axi_arlock), + .m_axi_arcache(m01_axi_arcache), + .m_axi_arprot(m01_axi_arprot), + .m_axi_arregion(m01_axi_arregion), + .m_axi_arqos(m01_axi_arqos), + .m_axi_arvalid(m01_axi_arvalid), + .m_axi_arready(m01_axi_arready), + .m_axi_rdata(m01_axi_rdata), + .m_axi_rresp(m01_axi_rresp), + .m_axi_rlast(m01_axi_rlast), + .m_axi_rvalid(m01_axi_rvalid), + .m_axi_rready(m01_axi_rready) + ); + + // End SDC signals -------------------------------------------- + xlnx_axi_clock_converter xlnx_axi_clock_converter_0 (.s_axi_aclk(CPUCLK), .s_axi_aresetn(peripheral_aresetn), - .s_axi_awid(m_axi_awid), - .s_axi_awlen(m_axi_awlen), - .s_axi_awsize(m_axi_awsize), - .s_axi_awburst(m_axi_awburst), - .s_axi_awcache(m_axi_awcache), - .s_axi_awaddr(m_axi_awaddr[30:0]), - .s_axi_awprot(m_axi_awprot), + .s_axi_awid(s00_axi_awid), + .s_axi_awlen(s00_axi_awlen), + .s_axi_awsize(s00_axi_awsize), + .s_axi_awburst(s00_axi_awburst), + .s_axi_awcache(s00_axi_awcache), + .s_axi_awaddr(s00_axi_awaddr[30:0] ), + .s_axi_awprot(s00_axi_awprot), .s_axi_awregion(4'b0), // this could be a bug. bridge does not have these outputs .s_axi_awqos(4'b0), // this could be a bug. bridge does not have these outputs - .s_axi_awvalid(m_axi_awvalid), - .s_axi_awready(m_axi_awready), - .s_axi_awlock(m_axi_awlock), - .s_axi_wdata(m_axi_wdata), - .s_axi_wstrb(m_axi_wstrb), - .s_axi_wlast(m_axi_wlast), - .s_axi_wvalid(m_axi_wvalid), - .s_axi_wready(m_axi_wready), - .s_axi_bid(m_axi_bid), - .s_axi_bresp(m_axi_bresp), - .s_axi_bvalid(m_axi_bvalid), - .s_axi_bready(m_axi_bready), - .s_axi_arid(m_axi_arid), - .s_axi_arlen(m_axi_arlen), - .s_axi_arsize(m_axi_arsize), - .s_axi_arburst(m_axi_arburst), - .s_axi_arprot(m_axi_arprot), + .s_axi_awvalid(s00_axi_awvalid), + .s_axi_awready(s00_axi_awready), + .s_axi_awlock(s00_axi_awlock), + .s_axi_wdata(s00_axi_wdata), + .s_axi_wstrb(s00_axi_wstrb), + .s_axi_wlast(s00_axi_wlast), + .s_axi_wvalid(s00_axi_wvalid), + .s_axi_wready(s00_axi_wready), + .s_axi_bid(s00_axi_bid), + .s_axi_bresp(s00_axi_bresp), + .s_axi_bvalid(s00_axi_bvalid), + .s_axi_bready(s00_axi_bready), + .s_axi_arid(s00_axi_arid), + .s_axi_arlen(s00_axi_arlen), + .s_axi_arsize(s00_axi_arsize), + .s_axi_arburst(s00_axi_arburst), + .s_axi_arprot(s00_axi_arprot), .s_axi_arregion(4'b0), // this could be a bug. bridge does not have these outputs .s_axi_arqos(4'b0), // this could be a bug. bridge does not have these outputs - .s_axi_arcache(m_axi_arcache), - .s_axi_arvalid(m_axi_arvalid), - .s_axi_araddr(m_axi_araddr[30:0]), - .s_axi_arlock(m_axi_arlock), - .s_axi_arready(m_axi_arready), - .s_axi_rid(m_axi_rid), - .s_axi_rdata(m_axi_rdata), - .s_axi_rresp(m_axi_rresp), - .s_axi_rvalid(m_axi_rvalid), - .s_axi_rlast(m_axi_rlast), - .s_axi_rready(m_axi_rready), + .s_axi_arcache(s00_axi_arcache), + .s_axi_arvalid(s00_axi_arvalid), + .s_axi_araddr(s00_axi_araddr[30:0]), + .s_axi_arlock(s00_axi_arlock), + .s_axi_arready(s00_axi_arready), + .s_axi_rid(s00_axi_rid), + .s_axi_rdata(s00_axi_rdata), + .s_axi_rresp(s00_axi_rresp), + .s_axi_rvalid(s00_axi_rvalid), + .s_axi_rlast(s00_axi_rlast), + .s_axi_rready(s00_axi_rready), .m_axi_aclk(BUSCLK), .m_axi_aresetn(~reset), @@ -380,7 +879,7 @@ module fpgaTop .m_axi_rvalid(BUS_axi_rvalid), .m_axi_rlast(BUS_axi_rlast), .m_axi_rready(BUS_axi_rready)); - + xlnx_ddr4 xlnx_ddr4_c0 (.c0_init_calib_complete(c0_init_calib_complete), .dbg_clk(dbg_clk), // open diff --git a/pipelined/src/uncore/uncore.sv b/pipelined/src/uncore/uncore.sv index 8474d6d8c..532efe069 100644 --- a/pipelined/src/uncore/uncore.sv +++ b/pipelined/src/uncore/uncore.sv @@ -70,6 +70,7 @@ module uncore ( logic HSELDTIM, HSELIROM, HSELRam, HSELCLINT, HSELPLIC, HSELGPIO, HSELUART, HSELSDC; logic HSELDTIMD, HSELIROMD, HSELEXTD, HSELRamD, HSELCLINTD, HSELPLICD, HSELGPIOD, HSELUARTD, HSELSDCD; logic HRESPRam, HRESPSDC; + logic HREADYRam, HRESPSDCD; logic [`XLEN-1:0] HREADBootRom; logic HSELBootRom, HSELBootRomD, HRESPBootRom, HREADYBootRom, HREADYSDC; From 12b379ebd85d146fb0a7a86f43ca575421935fd3 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Thu, 19 Jan 2023 16:57:43 -0600 Subject: [PATCH 06/22] Added IOBUFs to SDCDat. Edited debug2.xdc. Dwidth converter error. --- fpga/constraints/debug2.xdc | 8 ++++---- fpga/src/fpgaTop.v | 15 ++++++++++++++- pipelined/regression/lint-wally | 2 +- 3 files changed, 19 insertions(+), 6 deletions(-) diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index bdc073ee1..e69b63795 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -82,12 +82,12 @@ connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsoc/core/lsu/b create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe15] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15] -connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[63]} ]] +connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[63]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe16] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] -connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[63]} ]] +connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[63]} ]] create_debug_port u_ila_0 probe @@ -109,7 +109,7 @@ connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsoc/core/ieu/d create_debug_port u_ila_0 probe set_property port_width 63 [get_debug_ports u_ila_0/probe20] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20] -connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[63]} ]] +connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[63]} ]] create_debug_port u_ila_0 probe @@ -674,7 +674,7 @@ connect_debug_port u_ila_0/probe129 [get_nets [list {wallypipelinedsoc/core/ieu/ create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe130] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe130] -connect_debug_port u_ila_0/probe130 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[63]} ]] +connect_debug_port u_ila_0/probe130 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[63]} ]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe131] diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index 3f72c5ec0..2bcef6adf 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -374,6 +374,8 @@ module fpgaTop wire m01_axi_rvalid; wire m01_axi_rready; + wire [3:0] SDCDatIn; + assign GPIOPinsIn = {28'b0, GPI}; assign GPO = GPIOPinsOut[4:0]; assign ahblite_resetn = peripheral_aresetn; @@ -387,6 +389,17 @@ module fpgaTop .O(SDCCmdIn), .IO(SDCCmd)); + + genvar i; + generate + for (i = 0; i < 4; i = i + 1) begin + IOBUF iobufSDCDat(.T(1'b1), + .I(1'b0), + .O(SDCDatIn[i]), + .IO(SDCDat[i])); + end + endgenerate + // reset controller XILINX IP xlnx_proc_sys_reset xlnx_proc_sys_reset_0 (.slowest_sync_clk(CPUCLK), @@ -429,7 +442,7 @@ module fpgaTop .UARTSin(UARTSin), .UARTSout(UARTSout), // SD Card - .SDCDatIn(SDCDat), + .SDCDatIn(SDCDatIn), .SDCCmdIn(SDCCmdIn), .SDCCmdOut(SDCCmdOut), .SDCCmdOE(SDCCmdOE), diff --git a/pipelined/regression/lint-wally b/pipelined/regression/lint-wally index 000b63402..1c2246384 100755 --- a/pipelined/regression/lint-wally +++ b/pipelined/regression/lint-wally @@ -5,7 +5,7 @@ export PATH=$PATH:/usr/local/bin/ verilator=`which verilator` basepath=$(dirname $0)/.. -for config in rv32e rv64gc rv32gc rv32ic rv32i rv64i rv64fpquad; do +for config in fpga rv32e rv64gc rv32gc rv32ic rv32i rv64i rv64fpquad; do #for config in rv64gc; do echo "$config linting..." if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then From 293cc88bd9467b42d63f86d9da7a6005c4fc82f2 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Mon, 23 Jan 2023 17:00:24 -0600 Subject: [PATCH 07/22] Added extra core signal to mark_debug.txt. Modified wally.tcl --- fpga/constraints/marked_debug.txt | 1 + fpga/generator/wally.tcl | 5 ++++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/fpga/constraints/marked_debug.txt b/fpga/constraints/marked_debug.txt index 97ac1ead3..ff0fb325c 100644 --- a/fpga/constraints/marked_debug.txt +++ b/fpga/constraints/marked_debug.txt @@ -30,6 +30,7 @@ wally/wallypipelinedcore.sv: logic MemRWM wally/wallypipelinedcore.sv: logic InstrValidM wally/wallypipelinedcore.sv: logic WriteDataM wally/wallypipelinedcore.sv: logic IEUAdrM +wally/wallypipelinedcore.sv: logic HRDATA ifu/spill.sv: statetype CurrState ifu/ifu.sv: logic IFUStallF ifu/ifu.sv: logic IFUHADDR diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index 5cac00f5a..e0de591b7 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -19,7 +19,7 @@ read_ip IP/xlnx_axi_crossbar.srcs/sources_1/ip/xlnx_axi_crossbar/xlnx_axi_crossb read_ip IP/xlnx_axi_dwidth_conv_32to64.srcs/sources_1/ip/xlnx_axi_dwidth_conv_32to64/xlnx_axi_dwidth_conv_32to64.xci read_ip IP/xlnx_axi_dwidth_conv_64to32.srcs/sources_1/ip/xlnx_axi_dwidth_conv_64to32/xlnx_axi_dwidth_conv_64to32.xci -read_verilog -sv [glob -type f ../../pipelined/src/*/*.sv ../../pipelined/src/*/*/*.sv] +# read_verilog -sv [glob -type f ../../pipelined/src/*/*.sv ../../pipelined/src/*/*/*.sv] read_verilog -sv [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv] read_verilog [glob -type f ../../pipelined/src/uncore/newsdc/*.v] read_verilog {../src/fpgaTop.v} @@ -47,6 +47,9 @@ synth_design -rtl -name rtl_1 report_clocks -file reports/clocks.rpt +# Temp +set_param messaging.defaultLimit 100000 + # this does synthesis? wtf? launch_runs synth_1 -jobs 4 From c8d487b9e62633ae535d9efb3a2cb4d949ceb9b9 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Mon, 23 Jan 2023 19:02:01 -0600 Subject: [PATCH 08/22] Created missing wires for axi interfaces in fpgaTop.v. --- fpga/src/fpgaTop.v | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index 2bcef6adf..95f4582fa 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -226,6 +226,7 @@ module fpgaTop // 64to32 dwidth converter input interface------------------------- wire s01_axi_aclk; wire s01_axi_aresetn; + wire [3:0]s01_axi_awid; wire [31:0]s01_axi_awaddr; wire [7:0]s01_axi_awlen; wire [2:0]s01_axi_awsize; @@ -242,9 +243,11 @@ module fpgaTop wire s01_axi_wlast; wire s01_axi_wvalid; wire s01_axi_wready; + wire [3:0]m01_axi_bid; wire [1:0]s01_axi_bresp; wire s01_axi_bvalid; wire s01_axi_bready; + wire [3:0]m01_axi_bid; wire [31:0]s01_axi_araddr; wire [7:0]s01_axi_arlen; wire [2:0]s01_axi_arsize; @@ -256,6 +259,7 @@ module fpgaTop wire [3:0]s01_axi_arqos; // wire s01_axi_arvalid; wire s01_axi_arready; + wire [3:0]m01_axi_rid; wire [63:0]s01_axi_rdata; wire [1:0]s01_axi_rresp; wire s01_axi_rlast; @@ -338,6 +342,7 @@ module fpgaTop wire SDCout_axi_rready; // Output Interface + wire [3:0]m01_axi_awid; wire [31:0]m01_axi_awaddr; wire [7:0]m01_axi_awlen; wire [2:0]m01_axi_awsize; @@ -354,9 +359,11 @@ module fpgaTop wire m01_axi_wlast; wire m01_axi_wvalid; wire m01_axi_wready; + wire [3:0] m01_axi_bid; wire [1:0]m01_axi_bresp; wire m01_axi_bvalid; wire m01_axi_bready; + wire [3:0] m01_axi_arid; wire [31:0]m01_axi_araddr; wire [7:0]m01_axi_arlen; wire [2:0]m01_axi_arsize; @@ -368,6 +375,7 @@ module fpgaTop wire [3:0]m01_axi_arqos; wire m01_axi_arvalid; wire m01_axi_arready; + wire [3:0] m01_axi_rid; wire [31:0]m01_axi_rdata; wire [1:0]m01_axi_rresp; wire m01_axi_rlast; From 07e279b5b5d7da29c92d9dbda56b10bad1e4dac1 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Mon, 23 Jan 2023 19:30:29 -0600 Subject: [PATCH 09/22] Modified makefile. Added axi protocol converter IP. --- fpga/generator/Makefile | 5 +++-- fpga/generator/wally.tcl | 1 + fpga/generator/xlnx_axi_prtcl_conv.tcl | 23 +++++++++++++++++++++++ 3 files changed, 27 insertions(+), 2 deletions(-) create mode 100644 fpga/generator/xlnx_axi_prtcl_conv.tcl diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile index 8efd9f6d1..b200a22de 100644 --- a/fpga/generator/Makefile +++ b/fpga/generator/Makefile @@ -1,5 +1,5 @@ dst := IP -sdc_src := ~/repos/sdc.tar.gz +sdc_src := ../../../sdc.tar.gz # vcu118 #export XILINX_PART := xcvu9p-flga2104-2L-e #export XILINX_BOARD := xilinx.com:vcu118:part0:2.4 @@ -22,7 +22,8 @@ IP: $(dst)/xlnx_proc_sys_reset.log \ $(dst)/xlnx_ahblite_axi_bridge.log \ $(dst)/xlnx_axi_crossbar.log \ $(dst)/xlnx_axi_dwidth_conv_32to64.log \ - $(dst)/xlnx_axi_dwidth_conv_64to32.log + $(dst)/xlnx_axi_dwidth_conv_64to32.log \ + $(dst)/xlnx_axi_prtcl_conv.log SDC: cp $(sdc_src) ../src/ diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index e0de591b7..55f65b31b 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -18,6 +18,7 @@ read_ip IP/xlnx_ddr4.srcs/sources_1/ip/xlnx_ddr4/xlnx_ddr4.xci read_ip IP/xlnx_axi_crossbar.srcs/sources_1/ip/xlnx_axi_crossbar/xlnx_axi_crossbar.xci read_ip IP/xlnx_axi_dwidth_conv_32to64.srcs/sources_1/ip/xlnx_axi_dwidth_conv_32to64/xlnx_axi_dwidth_conv_32to64.xci read_ip IP/xlnx_axi_dwidth_conv_64to32.srcs/sources_1/ip/xlnx_axi_dwidth_conv_64to32/xlnx_axi_dwidth_conv_64to32.xci +read_ip IP/xlnx_axi_prtcl_conv.srcs/sources_1/ip/xlnx_axi_prtcl_conv/xlnx_axi_prtcl_conv.xci # read_verilog -sv [glob -type f ../../pipelined/src/*/*.sv ../../pipelined/src/*/*/*.sv] read_verilog -sv [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv] diff --git a/fpga/generator/xlnx_axi_prtcl_conv.tcl b/fpga/generator/xlnx_axi_prtcl_conv.tcl new file mode 100644 index 000000000..76b6fc6cd --- /dev/null +++ b/fpga/generator/xlnx_axi_prtcl_conv.tcl @@ -0,0 +1,23 @@ +set partNumber $::env(XILINX_PART) +set boardName $::env(XILINX_BOARD) + +# vcu118 board +#set partNumber xcvu9p-flga2104-2L-e +#set boardName xilinx.com:vcu118:part0:2.4 + +# kcu105 board +#set partNumber xcku040-ffva1156-2-e +#set boardName xilinx.com:kcu105:part0:1.7 + +set ipName xlnx_axi_prtcl_conv + +create_project $ipName . -force -part $partNumber +set_property board_part $boardName [current_project] + +create_ip -name axi_protocol_converter -vendor xilinx.com -library ip -version 2.1 -module_name $ipName + +generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +launch_run -jobs 8 ${ipName}_synth_1 +wait_on_run ${ipName}_synth_1 From 264f0ba0da0a0b2215984756c9afbe0f82d3aaf4 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Fri, 27 Jan 2023 14:35:34 -0600 Subject: [PATCH 10/22] Removed IOBUF's from sdc_controller. --- fpga/src/fpgaTop.v | 216 +++++++++++++----- .../src/uncore/newsdc/axi_sdc_controller.v | 118 +++++----- tests/custom/boot/boot.c | 40 ++++ 3 files changed, 259 insertions(+), 115 deletions(-) diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index 95f4582fa..bd7d95638 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -267,39 +267,60 @@ module fpgaTop wire s01_axi_rready; // Output Interface + wire [31:0]axi4in_axi_awaddr; + wire [7:0]axi4in_axi_awlen; + wire [2:0]axi4in_axi_awsize; + wire [1:0]axi4in_axi_awburst; + wire [0:0]axi4in_axi_awlock; + wire [3:0]axi4in_axi_awcache; + wire [2:0]axi4in_axi_awprot; + wire [3:0]axi4in_axi_awregion; + wire [3:0]axi4in_axi_awqos; + wire axi4in_axi_awvalid; + wire axi4in_axi_awready; + wire [31:0]axi4in_axi_wdata; + wire [3:0]axi4in_axi_wstrb; + wire axi4in_axi_wlast; + wire axi4in_axi_wvalid; + wire axi4in_axi_wready; + wire [1:0]axi4in_axi_bresp; + wire axi4in_axi_bvalid; + wire axi4in_axi_bready; + wire [31:0]axi4in_axi_araddr; + wire [7:0]axi4in_axi_arlen; + wire [2:0]axi4in_axi_arsize; + wire [1:0]axi4in_axi_arburst; + wire [0:0]axi4in_axi_arlock; + wire [3:0]axi4in_axi_arcache; + wire [2:0]axi4in_axi_arprot; + wire [3:0]axi4in_axi_arregion; + wire [3:0]axi4in_axi_arqos; + wire axi4in_axi_arvalid; + wire axi4in_axi_arready; + wire [31:0]axi4in_axi_rdata; + wire [1:0]axi4in_axi_rresp; + wire axi4in_axi_rlast; + wire axi4in_axi_rvalid; + wire axi4in_axi_rready; + + // AXI4 to AXI4-Lite Protocol converter output wire [31:0]SDCin_axi_awaddr; - wire [7:0]SDCin_axi_awlen; - wire [2:0]SDCin_axi_awsize; - wire [1:0]SDCin_axi_awburst; - wire [0:0]SDCin_axi_awlock; - wire [3:0]SDCin_axi_awcache; wire [2:0]SDCin_axi_awprot; - wire [3:0]SDCin_axi_awregion; - wire [3:0]SDCin_axi_awqos; wire SDCin_axi_awvalid; wire SDCin_axi_awready; wire [31:0]SDCin_axi_wdata; wire [3:0]SDCin_axi_wstrb; - wire SDCin_axi_wlast; wire SDCin_axi_wvalid; wire SDCin_axi_wready; wire [1:0]SDCin_axi_bresp; wire SDCin_axi_bvalid; wire SDCin_axi_bready; wire [31:0]SDCin_axi_araddr; - wire [7:0]SDCin_axi_arlen; - wire [2:0]SDCin_axi_arsize; - wire [1:0]SDCin_axi_arburst; - wire [0:0]SDCin_axi_arlock; - wire [3:0]SDCin_axi_arcache; wire [2:0]SDCin_axi_arprot; - wire [3:0]SDCin_axi_arregion; - wire [3:0]SDCin_axi_arqos; wire SDCin_axi_arvalid; wire SDCin_axi_arready; wire [31:0]SDCin_axi_rdata; wire [1:0]SDCin_axi_rresp; - wire SDCin_axi_rlast; wire SDCin_axi_rvalid; wire SDCin_axi_rready; // ---------------------------------------------------------------- @@ -408,6 +429,14 @@ module fpgaTop end endgenerate + // IOBUF IOBUF_cmd (.O(sd_cmd_i), .IO(sdio_cmd), .I(sd_cmd_reg_o), .T(sd_cmd_reg_t)); + // IOBUF IOBUF_dat0 (.O(sd_dat_i[0]), .IO(sdio_dat[0]), .I(sd_dat_reg_o[0]), .T(sd_dat_reg_t)); + // IOBUF IOBUF_dat1 (.O(sd_dat_i[1]), .IO(sdio_dat[1]), .I(sd_dat_reg_o[1]), .T(sd_dat_reg_t)); + // IOBUF IOBUF_dat2 (.O(sd_dat_i[2]), .IO(sdio_dat[2]), .I(sd_dat_reg_o[2]), .T(sd_dat_reg_t)); + // IOBUF IOBUF_dat3 (.O(sd_dat_i[3]), .IO(sdio_dat[3]), .I(sd_dat_reg_o[3]), .T(sd_dat_reg_t)); + + + // reset controller XILINX IP xlnx_proc_sys_reset xlnx_proc_sys_reset_0 (.slowest_sync_clk(CPUCLK), @@ -514,7 +543,7 @@ module fpgaTop .aresetn(peripheral_aresetn), // Connect Masters - .s_axi_awid({m_axi_awid, m01_axi_awid}), + .s_axi_awid({m_axi_awid, 8'b0}), .s_axi_awaddr({m_axi_awaddr, m01_axi_awaddr}), .s_axi_awlen({m_axi_awlen, m01_axi_awlen}), .s_axi_awsize({m_axi_awsize, m01_axi_awsize}), @@ -534,7 +563,7 @@ module fpgaTop .s_axi_bresp({m_axi_bresp, m01_axi_bresp}), .s_axi_bvalid({m_axi_bvalid, m01_axi_bvalid}), .s_axi_bready({m_axi_bready, m01_axi_bready}), - .s_axi_arid({m_axi_arid, m01_axi_arid}), + .s_axi_arid({m_axi_arid, 8'b0}), .s_axi_araddr({m_axi_araddr, m01_axi_araddr}), .s_axi_arlen({m_axi_arlen, m01_axi_arlen}), .s_axi_arsize({m_axi_arsize, m01_axi_arsize}), @@ -570,7 +599,7 @@ module fpgaTop .m_axi_wlast({s00_axi_wlast, s01_axi_wlast}), .m_axi_wvalid({s00_axi_wvalid, s01_axi_wvalid}), .m_axi_wready({s00_axi_wready, s01_axi_wready}), - .m_axi_bid({s00_axi_bid, s01_axi_bid}), + .m_axi_bid({s00_axi_bid, 8'b0}), .m_axi_bresp({s00_axi_bresp, s01_axi_bresp}), .m_axi_bvalid({s00_axi_bvalid, s01_axi_bvalid}), .m_axi_bready({s00_axi_bready, s01_axi_bready}), @@ -586,7 +615,7 @@ module fpgaTop .m_axi_araddr({s00_axi_araddr, s01_axi_araddr}), .m_axi_arlock({s00_axi_arlock, s01_axi_arlock}), .m_axi_arready({s00_axi_arready, s01_axi_arready}), - .m_axi_rid({s00_axi_rid, s01_axi_rid}), + .m_axi_rid({s00_axi_rid, 8'b0}), .m_axi_rdata({s00_axi_rdata, s01_axi_rdata}), .m_axi_rresp({s00_axi_rresp, s01_axi_rresp}), .m_axi_rvalid({s00_axi_rvalid, s01_axi_rvalid}), @@ -645,42 +674,107 @@ module fpgaTop .s_axi_rready(s01_axi_rready), // Master interface - .m_axi_awaddr(SDCin_axi_awaddr), - .m_axi_awlen(SDCin_axi_awlen), - .m_axi_awsize(SDCin_axi_awsize), - .m_axi_awburst(SDCin_axi_awburst), - .m_axi_awlock(SDCin_axi_awlock), - .m_axi_awcache(SDCin_axi_awcache), - .m_axi_awprot(SDCin_axi_awprot), - .m_axi_awregion(SDCin_axi_awregion), - .m_axi_awqos(SDCin_axi_awqos), - .m_axi_awvalid(SDCin_axi_awvalid), - .m_axi_awready(SDCin_axi_awready), - .m_axi_wdata(SDCin_axi_wdata), - .m_axi_wstrb(SDCin_axi_wstrb), - .m_axi_wlast(SDCin_axi_wlast), - .m_axi_wvalid(SDCin_axi_wvalid), - .m_axi_wready(SDCin_axi_wready), - .m_axi_bresp(SDCin_axi_bresp), - .m_axi_bvalid(SDCin_axi_bvalid), - .m_axi_bready(SDCin_axi_bready), - .m_axi_araddr(SDCin_axi_araddr), - .m_axi_arlen(SDCin_axi_arlen), - .m_axi_arsize(SDCin_axi_arsize), - .m_axi_arburst(SDCin_axi_arburst), - .m_axi_arlock(SDCin_axi_arlock), - .m_axi_arcache(SDCin_axi_arcache), - .m_axi_arprot(SDCin_axi_arprot), - .m_axi_arregion(SDCin_axi_arregion), - .m_axi_arqos(SDCin_axi_arqos), - .m_axi_arvalid(SDCin_axi_arvalid), - .m_axi_arready(SDCin_axi_arready), - .m_axi_rdata(SDCin_axi_rdata), - .m_axi_rresp(SDCin_axi_rresp), - .m_axi_rlast(SDCin_axi_rlast), - .m_axi_rvalid(SDCin_axi_rvalid), - .m_axi_rready(SDCin_axi_rready) + .m_axi_awaddr(axi4in_axi_awaddr), + .m_axi_awlen(axi4in_axi_awlen), + .m_axi_awsize(axi4in_axi_awsize), + .m_axi_awburst(axi4in_axi_awburst), + .m_axi_awlock(axi4in_axi_awlock), + .m_axi_awcache(axi4in_axi_awcache), + .m_axi_awprot(axi4in_axi_awprot), + .m_axi_awregion(axi4in_axi_awregion), + .m_axi_awqos(axi4in_axi_awqos), + .m_axi_awvalid(axi4in_axi_awvalid), + .m_axi_awready(axi4in_axi_awready), + .m_axi_wdata(axi4in_axi_wdata), + .m_axi_wstrb(axi4in_axi_wstrb), + .m_axi_wlast(axi4in_axi_wlast), + .m_axi_wvalid(axi4in_axi_wvalid), + .m_axi_wready(axi4in_axi_wready), + .m_axi_bresp(axi4in_axi_bresp), + .m_axi_bvalid(axi4in_axi_bvalid), + .m_axi_bready(axi4in_axi_bready), + .m_axi_araddr(axi4in_axi_araddr), + .m_axi_arlen(axi4in_axi_arlen), + .m_axi_arsize(axi4in_axi_arsize), + .m_axi_arburst(axi4in_axi_arburst), + .m_axi_arlock(axi4in_axi_arlock), + .m_axi_arcache(axi4in_axi_arcache), + .m_axi_arprot(axi4in_axi_arprot), + .m_axi_arregion(axi4in_axi_arregion), + .m_axi_arqos(axi4in_axi_arqos), + .m_axi_arvalid(axi4in_axi_arvalid), + .m_axi_arready(axi4in_axi_arready), + .m_axi_rdata(axi4in_axi_rdata), + .m_axi_rresp(axi4in_axi_rresp), + .m_axi_rlast(axi4in_axi_rlast), + .m_axi_rvalid(axi4in_axi_rvalid), + .m_axi_rready(axi4in_axi_rready) ); + + xlnx_axi_prtcl_conv axi4tolite + (.aclk(CPUCLK), + .aresetn(peripheral_aresetn), + + // AXI4 In + .s_axi_awaddr(axi4in_axi_awaddr), + .s_axi_awlen(axi4in_axi_awlen), + .s_axi_awsize(axi4in_axi_awsize), + .s_axi_awburst(axi4in_axi_awburst), + .s_axi_awlock(axi4in_axi_awlock), + .s_axi_awcache(axi4in_axi_awcache), + .s_axi_awprot(axi4in_axi_awprot), + .s_axi_awregion(axi4in_axi_awregion), + .s_axi_awqos(axi4in_axi_awqos), + .s_axi_awvalid(axi4in_axi_awvalid), + .s_axi_awready(axi4in_axi_awready), + .s_axi_wdata(axi4in_axi_wdata), + .s_axi_wstrb(axi4in_axi_wstrb), + .s_axi_wlast(axi4in_axi_wlast), + .s_axi_wvalid(axi4in_axi_wvalid), + .s_axi_wready(axi4in_axi_wready), + .s_axi_bresp(axi4in_axi_bresp), + .s_axi_bvalid(axi4in_axi_bvalid), + .s_axi_bready(axi4in_axi_bready), + .s_axi_araddr(axi4in_axi_araddr), + .s_axi_arlen(axi4in_axi_arlen), + .s_axi_arsize(axi4in_axi_arsize), + .s_axi_arburst(axi4in_axi_arburst), + .s_axi_arlock(axi4in_axi_arlock), + .s_axi_arcache(axi4in_axi_arcache), + .s_axi_arprot(axi4in_axi_arprot), + .s_axi_arregion(axi4in_axi_arregion), + .s_axi_arqos(axi4in_axi_arqos), + .s_axi_arvalid(axi4in_axi_arvalid), + .s_axi_arready(axi4in_axi_arready), + .s_axi_rdata(axi4in_axi_rdata), + .s_axi_rresp(axi4in_axi_rresp), + .s_axi_rlast(axi4in_axi_rlast), + .s_axi_rvalid(axi4in_axi_rvalid), + .s_axi_rready(axi4in_axi_rready), + + // AXI4Lite Out + .m_axi_awaddr(SDCin_axi_awaddr), + .m_axi_awprot(SDCin_axi_awprot), + .m_axi_awvalid(SDCin_axi_awvalid), + .m_axi_awready(SDCin_axi_awready), + .m_axi_wdata(SDCin_axi_wdata), + .m_axi_wstrb(SDCin_axi_wstrb), + .m_axi_wvalid(SDCin_axi_wvalid), + .m_axi_wready(SDCin_axi_wready), + .m_axi_bresp(SDCin_axi_bresp), + .m_axi_bvalid(SDCin_axi_bvalid), + .m_axi_bready(SDCin_axi_bready), + .m_axi_araddr(SDCin_axi_araddr), + .m_axi_arprot(SDCin_axi_arprot), + .m_axi_arvalid(SDCin_axi_arvalid), + .m_axi_arready(SDCin_axi_arready), + .m_axi_rdata(SDCin_axi_rdata), + .m_axi_rresp(SDCin_axi_rresp), + .m_axi_rvalid(SDCin_axi_rvalid), + .m_axi_rready(SDCin_axi_rready) + + ); + sdc_controller axiSDC (.clock(CPUCLK), @@ -724,13 +818,15 @@ module fpgaTop .m_axi_rlast(SDCout_axi_rlast), .m_axi_rresp(SDCout_axi_rresp), .m_axi_rvalid(SDCout_axi_rvalid), - .m_axi_rready(SDCout_axi_rready) + .m_axi_rready(SDCout_axi_rready), // SDC interface - //.sdio_cmd(SDCcmd), - //.sdio_dat(SDCdat), - //.sdio_cd() + //.sdio_cmd(1'b0), + //.sdio_dat(4'b0), + //.sdio_cd(1'b0) + .sd_dat_i(4'b0), + .sd_cmd_i(1'b0) ); @@ -771,7 +867,7 @@ module fpgaTop .s_axi_arvalid(SDCout_axi_arvalid), .s_axi_arready(SDCout_axi_arready), .s_axi_rdata(SDCout_axi_rdata), - //.s_axi_rresp(), + .s_axi_rresp(SDCout_axi_rresp), .s_axi_rlast(SDCout_axi_rlast), .s_axi_rvalid(SDCout_axi_rvalid), .s_axi_rready(SDCout_axi_rready), diff --git a/pipelined/src/uncore/newsdc/axi_sdc_controller.v b/pipelined/src/uncore/newsdc/axi_sdc_controller.v index 989c05881..d900ddbbd 100644 --- a/pipelined/src/uncore/newsdc/axi_sdc_controller.v +++ b/pipelined/src/uncore/newsdc/axi_sdc_controller.v @@ -37,101 +37,109 @@ module sdc_controller #( parameter voltage_controll_reg = 3300, parameter capabilies_reg = 16'b0000_0000_0000_0011 ) ( - input wire async_resetn, + input wire async_resetn, (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clock CLK" *) (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF M_AXI:S_AXI_LITE, FREQ_HZ 100000000" *) - input wire clock, + input wire clock, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR" *) (* X_INTERFACE_PARAMETER = "CLK_DOMAIN clock, ID_WIDTH 0, PROTOCOL AXI4LITE, DATA_WIDTH 32" *) - input wire [15:0] s_axi_awaddr, + input wire [15:0] s_axi_awaddr, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID" *) - input wire s_axi_awvalid, + input wire s_axi_awvalid, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY" *) - output wire s_axi_awready, + output wire s_axi_awready, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA" *) - input wire [31:0] s_axi_wdata, + input wire [31:0] s_axi_wdata, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID" *) - input wire s_axi_wvalid, + input wire s_axi_wvalid, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY" *) - output wire s_axi_wready, + output wire s_axi_wready, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP" *) - output reg [1:0] s_axi_bresp, + output reg [1:0] s_axi_bresp, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID" *) - output reg s_axi_bvalid, + output reg s_axi_bvalid, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY" *) - input wire s_axi_bready, + input wire s_axi_bready, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR" *) - input wire [15:0] s_axi_araddr, + input wire [15:0] s_axi_araddr, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID" *) - input wire s_axi_arvalid, + input wire s_axi_arvalid, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY" *) - output wire s_axi_arready, + output wire s_axi_arready, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA" *) - output reg [31:0] s_axi_rdata, + output reg [31:0] s_axi_rdata, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP" *) - output reg [1:0] s_axi_rresp, + output reg [1:0] s_axi_rresp, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID" *) - output reg s_axi_rvalid, + output reg s_axi_rvalid, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY" *) - input wire s_axi_rready, + input wire s_axi_rready, (* X_INTERFACE_PARAMETER = "CLK_DOMAIN clock, ID_WIDTH 0, PROTOCOL AXI4, DATA_WIDTH 32" *) (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) - output reg [dma_addr_bits-1:0] m_axi_awaddr, + output reg [dma_addr_bits-1:0] m_axi_awaddr, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *) - output reg [7:0] m_axi_awlen, + output reg [7:0] m_axi_awlen, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) - output reg m_axi_awvalid, + output reg m_axi_awvalid, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) - input wire m_axi_awready, + input wire m_axi_awready, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) - output wire [31:0] m_axi_wdata, + output wire [31:0] m_axi_wdata, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *) - output reg m_axi_wlast, + output reg m_axi_wlast, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) - output reg m_axi_wvalid, + output reg m_axi_wvalid, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) - input wire m_axi_wready, + input wire m_axi_wready, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) - input wire [1:0] m_axi_bresp, + input wire [1:0] m_axi_bresp, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) - input wire m_axi_bvalid, + input wire m_axi_bvalid, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) - output wire m_axi_bready, + output wire m_axi_bready, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) - output reg [dma_addr_bits-1:0] m_axi_araddr, + output reg [dma_addr_bits-1:0] m_axi_araddr, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *) - output reg [7:0] m_axi_arlen, + output reg [7:0] m_axi_arlen, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) - output reg m_axi_arvalid, + output reg m_axi_arvalid, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) - input wire m_axi_arready, + input wire m_axi_arready, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) - input wire [31:0] m_axi_rdata, + input wire [31:0] m_axi_rdata, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *) - input wire m_axi_rlast, + input wire m_axi_rlast, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) - input wire [1:0] m_axi_rresp, + input wire [1:0] m_axi_rresp, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) - input wire m_axi_rvalid, + input wire m_axi_rvalid, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) - output wire m_axi_rready, + output wire m_axi_rready, // SD BUS - inout wire sdio_cmd, - inout wire [3:0] sdio_dat, + //inout wire sdio_cmd, + //inout wire [3:0] sdio_dat, (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 sdio_clk CLK" *) (* X_INTERFACE_PARAMETER = "FREQ_HZ 50000000" *) - output reg sdio_clk, + output reg sdio_clk, (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 sdio_reset RST" *) (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_HIGH" *) - output reg sdio_reset, - input wire sdio_cd, + output reg sdio_reset, + input wire sdio_cd, + + output reg sd_dat_reg_t, + output reg [3:0] sd_dat_reg_o, + input wire [3:0] sd_dat_i, + + output reg sd_cmd_reg_t, + output reg sd_cmd_reg_o, + input wire sd_cmd_i, // Interrupts - output wire interrupt + output wire interrupt ); `include "sd_defines.h" @@ -240,22 +248,22 @@ end // ------ SD IO Buffers -wire sd_cmd_i; +// wire sd_cmd_i; wire sd_cmd_o; wire sd_cmd_oe; -reg sd_cmd_reg_o; -reg sd_cmd_reg_t; -wire [3:0] sd_dat_i; +// reg sd_cmd_reg_o; +// reg sd_cmd_reg_t; +// wire [3:0] sd_dat_i; wire [3:0] sd_dat_o; wire sd_dat_oe; -reg [3:0] sd_dat_reg_o; -reg sd_dat_reg_t; +// reg [3:0] sd_dat_reg_o; +// reg sd_dat_reg_t; -IOBUF IOBUF_cmd (.O(sd_cmd_i), .IO(sdio_cmd), .I(sd_cmd_reg_o), .T(sd_cmd_reg_t)); -IOBUF IOBUF_dat0 (.O(sd_dat_i[0]), .IO(sdio_dat[0]), .I(sd_dat_reg_o[0]), .T(sd_dat_reg_t)); -IOBUF IOBUF_dat1 (.O(sd_dat_i[1]), .IO(sdio_dat[1]), .I(sd_dat_reg_o[1]), .T(sd_dat_reg_t)); -IOBUF IOBUF_dat2 (.O(sd_dat_i[2]), .IO(sdio_dat[2]), .I(sd_dat_reg_o[2]), .T(sd_dat_reg_t)); -IOBUF IOBUF_dat3 (.O(sd_dat_i[3]), .IO(sdio_dat[3]), .I(sd_dat_reg_o[3]), .T(sd_dat_reg_t)); +// IOBUF IOBUF_cmd (.O(sd_cmd_i), .IO(sdio_cmd), .I(sd_cmd_reg_o), .T(sd_cmd_reg_t)); +// IOBUF IOBUF_dat0 (.O(sd_dat_i[0]), .IO(sdio_dat[0]), .I(sd_dat_reg_o[0]), .T(sd_dat_reg_t)); +// IOBUF IOBUF_dat1 (.O(sd_dat_i[1]), .IO(sdio_dat[1]), .I(sd_dat_reg_o[1]), .T(sd_dat_reg_t)); +// IOBUF IOBUF_dat2 (.O(sd_dat_i[2]), .IO(sdio_dat[2]), .I(sd_dat_reg_o[2]), .T(sd_dat_reg_t)); +// IOBUF IOBUF_dat3 (.O(sd_dat_i[3]), .IO(sdio_dat[3]), .I(sd_dat_reg_o[3]), .T(sd_dat_reg_t)); always @(negedge clock) begin // Output data delayed by 1/2 clock cycle (5ns) to ensure diff --git a/tests/custom/boot/boot.c b/tests/custom/boot/boot.c index b79802ef3..8546861f9 100644 --- a/tests/custom/boot/boot.c +++ b/tests/custom/boot/boot.c @@ -369,6 +369,46 @@ static int ini_sd(void) { return 0; } +DRESULT disk_read(BYTE drv, BYTE * buf, LBA_t sector, UINT count) { + + if (!count) return RES_PARERR; + if (drv_status & STA_NOINIT) return RES_NOTRDY; + + /* Convert LBA to byte address if needed */ + if (!(card_type & CT_BLOCK)) sector *= 512; + while (count > 0) { + UINT bcnt = count > MAX_BLOCK_CNT ? MAX_BLOCK_CNT : count; + unsigned bytes = bcnt * 512; + if (send_data_cmd(bcnt == 1 ? CMD17 : CMD18, sector, buf, bcnt) < 0) return RES_ERROR; + if (bcnt > 1 && send_cmd(CMD12, 0) < 0) return RES_ERROR; + sector += (card_type & CT_BLOCK) ? bcnt : bytes; + count -= bcnt; + buf += bytes; + } + + return RES_OK; +} + +void disk_read(BYTE drv, BYTE * buf, LBA_t sector, UINT count) { + + if (!count) return RES_PARERR; + if (drv_status & STA_NOINIT) return RES_NOTRDY; + + /* Convert LBA to byte address if needed */ + if (!(card_type & CT_BLOCK)) sector *= 512; + while (count > 0) { + UINT bcnt = count > MAX_BLOCK_CNT ? MAX_BLOCK_CNT : count; + unsigned bytes = bcnt * 512; + if (send_data_cmd(bcnt == 1 ? CMD17 : CMD18, sector, buf, bcnt) < 0) return RES_ERROR; + if (bcnt > 1 && send_cmd(CMD12, 0) < 0) return RES_ERROR; + sector += (card_type & CT_BLOCK) ? bcnt : bytes; + count -= bcnt; + buf += bytes; + } + + return RES_OK; +} + int main() { ini_sd(); From c36d32f850477ce1ab884c8cd8c4e27147c7e126 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Fri, 27 Jan 2023 14:57:36 -0600 Subject: [PATCH 11/22] Flipped crossbar inputs and outputs to correctly place masters. --- fpga/src/fpgaTop.v | 148 ++++++++++++++++++++++----------------------- 1 file changed, 74 insertions(+), 74 deletions(-) diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index bd7d95638..bf910257d 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -543,84 +543,84 @@ module fpgaTop .aresetn(peripheral_aresetn), // Connect Masters - .s_axi_awid({m_axi_awid, 8'b0}), - .s_axi_awaddr({m_axi_awaddr, m01_axi_awaddr}), - .s_axi_awlen({m_axi_awlen, m01_axi_awlen}), - .s_axi_awsize({m_axi_awsize, m01_axi_awsize}), - .s_axi_awburst({m_axi_awburst, m01_axi_awburst}), - .s_axi_awlock({m_axi_awlock, m01_axi_awlock}), - .s_axi_awcache({m_axi_awcache, m01_axi_awcache}), - .s_axi_awprot({m_axi_awprot, m01_axi_awprot}), + .s_axi_awid({8'b0, m_axi_awid}), + .s_axi_awaddr({m01_axi_awaddr, m_axi_awaddr}), + .s_axi_awlen({m01_axi_awlen, m_axi_awlen}), + .s_axi_awsize({m01_axi_awsize, m_axi_awsize}), + .s_axi_awburst({m01_axi_awburst, m_axi_awburst}), + .s_axi_awlock({m01_axi_awlock, m_axi_awlock}), + .s_axi_awcache({m01_axi_awcache, m_axi_awcache}), + .s_axi_awprot({m01_axi_awprot, m_axi_awprot}), .s_axi_awqos(8'b0), - .s_axi_awvalid({m_axi_awvalid, m01_axi_awvalid}), - .s_axi_awready({m_axi_awready, m01_axi_awready}), - .s_axi_wdata({m_axi_wdata, m01_axi_wdata}), - .s_axi_wstrb({m_axi_wstrb, m01_axi_wstrb}), - .s_axi_wlast({m_axi_wlast, m01_axi_wlast}), - .s_axi_wvalid({m_axi_wvalid, m01_axi_wvalid}), - .s_axi_wready({m_axi_wready, m01_axi_wready}), - .s_axi_bid({m_axi_bid, m01_axi_bid}), - .s_axi_bresp({m_axi_bresp, m01_axi_bresp}), - .s_axi_bvalid({m_axi_bvalid, m01_axi_bvalid}), - .s_axi_bready({m_axi_bready, m01_axi_bready}), - .s_axi_arid({m_axi_arid, 8'b0}), - .s_axi_araddr({m_axi_araddr, m01_axi_araddr}), - .s_axi_arlen({m_axi_arlen, m01_axi_arlen}), - .s_axi_arsize({m_axi_arsize, m01_axi_arsize}), - .s_axi_arburst({m_axi_arburst, m01_axi_arburst}), - .s_axi_arlock({m_axi_arlock, m01_axi_arlock}), - .s_axi_arcache({m_axi_arcache, m01_axi_arcache}), - .s_axi_arprot({m_axi_arprot, m01_axi_arprot}), + .s_axi_awvalid({m01_axi_awvalid, m_axi_awvalid}), + .s_axi_awready({m01_axi_awready, m_axi_awready}), + .s_axi_wdata({m01_axi_wdata, m_axi_wdata}), + .s_axi_wstrb({m01_axi_wstrb, m_axi_wstrb}), + .s_axi_wlast({m01_axi_wlast, m_axi_wlast}), + .s_axi_wvalid({m01_axi_wvalid, m_axi_wvalid}), + .s_axi_wready({m01_axi_wready, m_axi_wready}), + .s_axi_bid({m01_axi_bid, m_axi_bid}), + .s_axi_bresp({m01_axi_bresp, m_axi_bresp}), + .s_axi_bvalid({m01_axi_bvalid, m_axi_bvalid}), + .s_axi_bready({m01_axi_bready, m_axi_bready}), + .s_axi_arid({8'b0, m_axi_arid}), + .s_axi_araddr({m01_axi_araddr, m_axi_araddr}), + .s_axi_arlen({m01_axi_arlen, m_axi_arlen}), + .s_axi_arsize({m01_axi_arsize, m_axi_arsize}), + .s_axi_arburst({m01_axi_arburst, m_axi_arburst}), + .s_axi_arlock({m01_axi_arlock, m_axi_arlock}), + .s_axi_arcache({m01_axi_arcache, m_axi_arcache}), + .s_axi_arprot({m01_axi_arprot, m_axi_arprot}), .s_axi_arqos(8'b0), - .s_axi_arvalid({m_axi_arvalid, m01_axi_arvalid}), - .s_axi_arready({m_axi_arready, m01_axi_arready}), - .s_axi_rid({m_axi_rid, m01_axi_rid}), - .s_axi_rdata({m_axi_rdata, m01_axi_rdata}), - .s_axi_rresp({m_axi_rresp, m01_axi_rresp}), - .s_axi_rlast({m_axi_rlast, m01_axi_rlast}), - .s_axi_rvalid({m_axi_rvalid, m01_axi_rvalid}), - .s_axi_rready({m_axi_rready, m01_axi_rready}), + .s_axi_arvalid({m01_axi_arvalid, m_axi_arvalid}), + .s_axi_arready({m01_axi_arready, m_axi_arready}), + .s_axi_rid({m01_axi_rid, m_axi_rid}), + .s_axi_rdata({m01_axi_rdata, m_axi_rdata}), + .s_axi_rresp({m01_axi_rresp, m_axi_rresp}), + .s_axi_rlast({m01_axi_rlast, m_axi_rlast}), + .s_axi_rvalid({m01_axi_rvalid, m_axi_rvalid}), + .s_axi_rready({m01_axi_rready, m_axi_rready}), // Connect Slaves - .m_axi_awid({s00_axi_awid, s01_axi_awid}), - .m_axi_awlen({s00_axi_awlen, s01_axi_awlen}), - .m_axi_awsize({s00_axi_awsize, s01_axi_awsize}), - .m_axi_awburst({s00_axi_awburst, s01_axi_awburst}), - .m_axi_awcache({s00_axi_awcache, s01_axi_awcache}), - .m_axi_awaddr({s00_axi_awaddr, s01_axi_awaddr}), - .m_axi_awprot({s00_axi_awprot, s01_axi_awprot}), - .m_axi_awregion({s00_axi_awregion, s01_axi_awregion}), - .m_axi_awqos({s00_axi_awqos, s01_axi_awqos}), - .m_axi_awvalid({s00_axi_awvalid, s01_axi_awvalid}), - .m_axi_awready({s00_axi_awready, s01_axi_awready}), - .m_axi_awlock({s00_axi_awlock, s01_axi_awlock}), - .m_axi_wdata({s00_axi_wdata, s01_axi_wdata}), - .m_axi_wstrb({s00_axi_wstrb, s01_axi_wstrb}), - .m_axi_wlast({s00_axi_wlast, s01_axi_wlast}), - .m_axi_wvalid({s00_axi_wvalid, s01_axi_wvalid}), - .m_axi_wready({s00_axi_wready, s01_axi_wready}), - .m_axi_bid({s00_axi_bid, 8'b0}), - .m_axi_bresp({s00_axi_bresp, s01_axi_bresp}), - .m_axi_bvalid({s00_axi_bvalid, s01_axi_bvalid}), - .m_axi_bready({s00_axi_bready, s01_axi_bready}), - .m_axi_arid({s00_axi_arid, s01_axi_arid}), - .m_axi_arlen({s00_axi_arlen, s01_axi_arlen}), - .m_axi_arsize({s00_axi_arsize, s01_axi_arsize}), - .m_axi_arburst({s00_axi_arburst, s01_axi_arburst}), - .m_axi_arprot({s00_axi_arprot, s01_axi_arprot}), - .m_axi_arregion({s00_axi_arregion, s01_axi_arregion}), - .m_axi_arqos({s00_axi_arqos, s01_axi_arqos}), - .m_axi_arcache({s00_axi_arcache, s01_axi_arcache}), - .m_axi_arvalid({s00_axi_arvalid, s01_axi_arvalid}), - .m_axi_araddr({s00_axi_araddr, s01_axi_araddr}), - .m_axi_arlock({s00_axi_arlock, s01_axi_arlock}), - .m_axi_arready({s00_axi_arready, s01_axi_arready}), - .m_axi_rid({s00_axi_rid, 8'b0}), - .m_axi_rdata({s00_axi_rdata, s01_axi_rdata}), - .m_axi_rresp({s00_axi_rresp, s01_axi_rresp}), - .m_axi_rvalid({s00_axi_rvalid, s01_axi_rvalid}), - .m_axi_rlast({s00_axi_rlast, s01_axi_rlast}), - .m_axi_rready({s00_axi_rready, s01_axi_rready}) + .m_axi_awid({s01_axi_awid, s00_axi_awid}), + .m_axi_awlen({s01_axi_awlen, s00_axi_awlen}), + .m_axi_awsize({s01_axi_awsize, s00_axi_awsize}), + .m_axi_awburst({s01_axi_awburst, s00_axi_awburst}), + .m_axi_awcache({s01_axi_awcache, s00_axi_awcache}), + .m_axi_awaddr({s01_axi_awaddr, s00_axi_awaddr}), + .m_axi_awprot({s01_axi_awprot, s00_axi_awprot}), + .m_axi_awregion({s01_axi_awregion, s00_axi_awregion}), + .m_axi_awqos({s01_axi_awqos, s00_axi_awqos}), + .m_axi_awvalid({s01_axi_awvalid, s00_axi_awvalid}), + .m_axi_awready({s01_axi_awready, s00_axi_awready}), + .m_axi_awlock({s01_axi_awlock, s00_axi_awlock}), + .m_axi_wdata({s01_axi_wdata, s00_axi_wdata}), + .m_axi_wstrb({s01_axi_wstrb, s00_axi_wstrb}), + .m_axi_wlast({s01_axi_wlast, s00_axi_wlast}), + .m_axi_wvalid({s01_axi_wvalid, s00_axi_wvalid}), + .m_axi_wready({s01_axi_wready, s00_axi_wready}), + .m_axi_bid({8'b0, s00_axi_bid}), + .m_axi_bresp({s01_axi_bresp, s00_axi_bresp}), + .m_axi_bvalid({s01_axi_bvalid, s00_axi_bvalid}), + .m_axi_bready({s01_axi_bready, s00_axi_bready}), + .m_axi_arid({s01_axi_arid, s00_axi_arid}), + .m_axi_arlen({s01_axi_arlen, s00_axi_arlen}), + .m_axi_arsize({s01_axi_arsize, s00_axi_arsize}), + .m_axi_arburst({s01_axi_arburst, s00_axi_arburst}), + .m_axi_arprot({s01_axi_arprot, s00_axi_arprot}), + .m_axi_arregion({s01_axi_arregion, s00_axi_arregion}), + .m_axi_arqos({s01_axi_arqos, s00_axi_arqos}), + .m_axi_arcache({s01_axi_arcache, s00_axi_arcache}), + .m_axi_arvalid({s01_axi_arvalid, s00_axi_arvalid}), + .m_axi_araddr({s01_axi_araddr, s00_axi_araddr}), + .m_axi_arlock({s01_axi_arlock, s00_axi_arlock}), + .m_axi_arready({s01_axi_arready, s00_axi_arready}), + .m_axi_rid({8'b0, s00_axi_rid}), + .m_axi_rdata({s01_axi_rdata, s00_axi_rdata}), + .m_axi_rresp({s01_axi_rresp, s00_axi_rresp}), + .m_axi_rvalid({s01_axi_rvalid, s00_axi_rvalid}), + .m_axi_rlast({s01_axi_rlast, s00_axi_rlast}), + .m_axi_rready({s01_axi_rready, s00_axi_rready}) ); // ----------------------------------------------------- From f2e4274c9cea73f2e4e75cd76d7e796e345c5b93 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Thu, 16 Feb 2023 17:33:21 -0600 Subject: [PATCH 12/22] Fixed debug signal names. Builds on the fpga. Bug in the crossbar. --- bin/wally-tool-chain-install.sh | 2 +- fpga/constraints/debug2.xdc | 2 +- fpga/constraints/marked_debug.txt | 1 - 3 files changed, 2 insertions(+), 3 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 2b45d8e77..08d63554f 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -31,7 +31,7 @@ export PATH=$PATH:$RISCV/bin set -e # break on error -NUM_THREADS=1 # for low memory machines > 16GiB +NUM_THREADS=32 # for low memory machines > 16GiB #NUM_THREADS=8 # for >= 32GiB #NUM_THREADS=16 # for >= 64GiB diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 8b0b7c448..ecb3b8e73 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -281,7 +281,7 @@ connect_debug_port u_ila_0/probe53 [get_nets [list wallypipelinedsoc/core/hzu/Re create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe54] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54] -connect_debug_port u_ila_0/probe54 [get_nets [list wallypipelinedsoc/core/hzu/TrapM ]] +connect_debug_port u_ila_0/probe54 [get_nets [list wallypipelinedsoc/core/hzu/StallFCause ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe55] diff --git a/fpga/constraints/marked_debug.txt b/fpga/constraints/marked_debug.txt index ff0fb325c..9e51d15ad 100644 --- a/fpga/constraints/marked_debug.txt +++ b/fpga/constraints/marked_debug.txt @@ -14,7 +14,6 @@ ieu/regfile.sv: logic rf ieu/datapath.sv: logic RegWriteW hazard/hazard.sv: logic BPPredWrongE hazard/hazard.sv: logic LoadStallD -hazard/hazard.sv: logic LSUStallM hazard/hazard.sv: logic FCvtIntStallD hazard/hazard.sv: logic DivBusyE hazard/hazard.sv: logic EcallFaultM From 85d789a7e06b9155319f50af89b75fcee7efb9b9 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Wed, 22 Feb 2023 15:13:16 -0600 Subject: [PATCH 13/22] AXI Crossbar is working. Fixed address width in generator script. --- fpga/constraints/debug2.xdc | 407 +++++++++++++-------------- fpga/generator/xlnx_axi_crossbar.tcl | 3 +- fpga/src/fpgaTop.v | 155 +++++----- 3 files changed, 283 insertions(+), 282 deletions(-) diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index ecb3b8e73..71e45611e 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -717,430 +717,421 @@ set_property port_width 64 [get_debug_ports u_ila_0/probe138] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe138] connect_debug_port u_ila_0/probe138 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]] -# UART Signals ------------------------------------------------------- - create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe139] +set_property port_width 4 [get_debug_ports u_ila_0/probe139] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe139] -connect_debug_port u_ila_0/probe139 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[7]}]] +connect_debug_port u_ila_0/probe139 [get_nets [list {m_axi_awid[0]} {m_axi_awid[1]} {m_axi_awid[2]} {m_axi_awid[3]} ]] + create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe140] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe140] -connect_debug_port u_ila_0/probe140 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[7]}]] +connect_debug_port u_ila_0/probe140 [get_nets [list {m_axi_awlen[0]} {m_axi_awlen[1]} {m_axi_awlen[2]} {m_axi_awlen[3]} {m_axi_awlen[4]} {m_axi_awlen[5]} {m_axi_awlen[6]} {m_axi_awlen[7]} ]] + create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe141] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe141] -connect_debug_port u_ila_0/probe141 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/A[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/A[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/A[2]}]] +connect_debug_port u_ila_0/probe141 [get_nets [list {m_axi_awsize[0]} {m_axi_awsize[1]} {m_axi_awsize[2]} ]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe142] +set_property port_width 2 [get_debug_ports u_ila_0/probe142] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe142] -connect_debug_port u_ila_0/probe142 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/MEMWb}]] +connect_debug_port u_ila_0/probe142 [get_nets [list {m_axi_awburst[0]} {m_axi_awburst[1]} ]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe143] +set_property port_width 4 [get_debug_ports u_ila_0/probe143] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe143] -connect_debug_port u_ila_0/probe143 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/SIN}]] +connect_debug_port u_ila_0/probe143 [get_nets [list {m_axi_awcache[0]} {m_axi_awcache[1]} {m_axi_awcache[2]} {m_axi_awcache[3]} ]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe144] +set_property port_width 31 [get_debug_ports u_ila_0/probe144] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe144] -connect_debug_port u_ila_0/probe144 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/SOUT}]] +connect_debug_port u_ila_0/probe144 [get_nets [list {m_axi_awaddr[0]} {m_axi_awaddr[1]} {m_axi_awaddr[2]} {m_axi_awaddr[3]} {m_axi_awaddr[4]} {m_axi_awaddr[5]} {m_axi_awaddr[6]} {m_axi_awaddr[7]} {m_axi_awaddr[8]} {m_axi_awaddr[9]} {m_axi_awaddr[10]} {m_axi_awaddr[11]} {m_axi_awaddr[12]} {m_axi_awaddr[13]} {m_axi_awaddr[14]} {m_axi_awaddr[15]} {m_axi_awaddr[16]} {m_axi_awaddr[17]} {m_axi_awaddr[18]} {m_axi_awaddr[19]} {m_axi_awaddr[20]} {m_axi_awaddr[21]} {m_axi_awaddr[22]} {m_axi_awaddr[23]} {m_axi_awaddr[24]} {m_axi_awaddr[25]} {m_axi_awaddr[26]} {m_axi_awaddr[27]} {m_axi_awaddr[28]} {m_axi_awaddr[29]} {m_axi_awaddr[30]} ]] + create_debug_port u_ila_0 probe -set_property port_width 2 [get_debug_ports u_ila_0/probe145] +set_property port_width 3 [get_debug_ports u_ila_0/probe145] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe145] -connect_debug_port u_ila_0/probe145 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[1]}]] +connect_debug_port u_ila_0/probe145 [get_nets [list {m_axi_awprot[0]} {m_axi_awprot[1]} {m_axi_awprot[2]} ]] + create_debug_port u_ila_0 probe -set_property port_width 2 [get_debug_ports u_ila_0/probe146] +set_property port_width 1 [get_debug_ports u_ila_0/probe146] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe146] -connect_debug_port u_ila_0/probe146 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[1]}]] +connect_debug_port u_ila_0/probe146 [get_nets [list {m_axi_awvalid}]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe147] +set_property port_width 1 [get_debug_ports u_ila_0/probe147] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe147] -connect_debug_port u_ila_0/probe147 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[7]}]] +connect_debug_port u_ila_0/probe147 [get_nets [list {m_axi_awready}]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe148] +set_property port_width 1 [get_debug_ports u_ila_0/probe148] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe148] -connect_debug_port u_ila_0/probe148 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[7]}]] +connect_debug_port u_ila_0/probe148 [get_nets [list {m_axi_awlock}]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe149] +set_property port_width 64 [get_debug_ports u_ila_0/probe149] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe149] -connect_debug_port u_ila_0/probe149 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[7]}]] +connect_debug_port u_ila_0/probe149 [get_nets [list {m_axi_wdata[0]} {m_axi_wdata[1]} {m_axi_wdata[2]} {m_axi_wdata[3]} {m_axi_wdata[4]} {m_axi_wdata[5]} {m_axi_wdata[6]} {m_axi_wdata[7]} {m_axi_wdata[8]} {m_axi_wdata[9]} {m_axi_wdata[10]} {m_axi_wdata[11]} {m_axi_wdata[12]} {m_axi_wdata[13]} {m_axi_wdata[14]} {m_axi_wdata[15]} {m_axi_wdata[16]} {m_axi_wdata[17]} {m_axi_wdata[18]} {m_axi_wdata[19]} {m_axi_wdata[20]} {m_axi_wdata[21]} {m_axi_wdata[22]} {m_axi_wdata[23]} {m_axi_wdata[24]} {m_axi_wdata[25]} {m_axi_wdata[26]} {m_axi_wdata[27]} {m_axi_wdata[28]} {m_axi_wdata[29]} {m_axi_wdata[30]} {m_axi_wdata[31]} {m_axi_wdata[32]} {m_axi_wdata[33]} {m_axi_wdata[34]} {m_axi_wdata[35]} {m_axi_wdata[36]} {m_axi_wdata[37]} {m_axi_wdata[38]} {m_axi_wdata[39]} {m_axi_wdata[40]} {m_axi_wdata[41]} {m_axi_wdata[42]} {m_axi_wdata[43]} {m_axi_wdata[44]} {m_axi_wdata[45]} {m_axi_wdata[46]} {m_axi_wdata[47]} {m_axi_wdata[48]} {m_axi_wdata[49]} {m_axi_wdata[50]} {m_axi_wdata[51]} {m_axi_wdata[52]} {m_axi_wdata[53]} {m_axi_wdata[54]} {m_axi_wdata[55]} {m_axi_wdata[56]} {m_axi_wdata[57]} {m_axi_wdata[58]} {m_axi_wdata[59]} {m_axi_wdata[60]} {m_axi_wdata[61]} {m_axi_wdata[62]} {m_axi_wdata[63]} ]] + create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe150] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe150] -connect_debug_port u_ila_0/probe150 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[7]}]] +connect_debug_port u_ila_0/probe150 [get_nets [list {m_axi_wstrb[0]} {m_axi_wstrb[1]} {m_axi_wstrb[2]} {m_axi_wstrb[3]} {m_axi_wstrb[4]} {m_axi_wstrb[5]} {m_axi_wstrb[6]} {m_axi_wstrb[7]} ]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe151] +set_property port_width 1 [get_debug_ports u_ila_0/probe151] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe151] -connect_debug_port u_ila_0/probe151 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[7]}]] +connect_debug_port u_ila_0/probe151 [get_nets [list {m_axi_wlast}]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe152] +set_property port_width 1 [get_debug_ports u_ila_0/probe152] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe152] -connect_debug_port u_ila_0/probe152 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[7]}]] +connect_debug_port u_ila_0/probe152 [get_nets [list {m_axi_wvalid}]] + create_debug_port u_ila_0 probe -set_property port_width 11 [get_debug_ports u_ila_0/probe153] +set_property port_width 1 [get_debug_ports u_ila_0/probe153] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe153] -connect_debug_port u_ila_0/probe153 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[10]}]] +connect_debug_port u_ila_0/probe153 [get_nets [list {m_axi_wready}]] + create_debug_port u_ila_0 probe set_property port_width 4 [get_debug_ports u_ila_0/probe154] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe154] -connect_debug_port u_ila_0/probe154 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[3]}]] +connect_debug_port u_ila_0/probe154 [get_nets [list {m_axi_bid[0]} {m_axi_bid[1]} {m_axi_bid[2]} {m_axi_bid[3]} ]] + create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe155] +set_property port_width 2 [get_debug_ports u_ila_0/probe155] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe155] -connect_debug_port u_ila_0/probe155 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[3]}]] +connect_debug_port u_ila_0/probe155 [get_nets [list {m_axi_bresp[0]} {m_axi_bresp[1]} ]] + create_debug_port u_ila_0 probe -set_property port_width 5 [get_debug_ports u_ila_0/probe156] +set_property port_width 1 [get_debug_ports u_ila_0/probe156] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe156] -connect_debug_port u_ila_0/probe156 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[4]}]] +connect_debug_port u_ila_0/probe156 [get_nets [list {m_axi_bvalid}]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe157] +set_property port_width 1 [get_debug_ports u_ila_0/probe157] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe157] -connect_debug_port u_ila_0/probe157 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][7]}]] +connect_debug_port u_ila_0/probe157 [get_nets [list {m_axi_bready}]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe158] +set_property port_width 4 [get_debug_ports u_ila_0/probe158] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe158] -connect_debug_port u_ila_0/probe158 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][7]}]] +connect_debug_port u_ila_0/probe158 [get_nets [list {m_axi_arid[0]} {m_axi_arid[1]} {m_axi_arid[2]} {m_axi_arid[3]} ]] + create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe159] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe159] -connect_debug_port u_ila_0/probe159 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][7]}]] +connect_debug_port u_ila_0/probe159 [get_nets [list {m_axi_arlen[0]} {m_axi_arlen[1]} {m_axi_arlen[2]} {m_axi_arlen[3]} {m_axi_arlen[4]} {m_axi_arlen[5]} {m_axi_arlen[6]} {m_axi_arlen[7]} ]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe160] +set_property port_width 3 [get_debug_ports u_ila_0/probe160] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe160] -connect_debug_port u_ila_0/probe160 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][7]}]] +connect_debug_port u_ila_0/probe160 [get_nets [list {m_axi_arsize[0]} {m_axi_arsize[1]} {m_axi_arsize[2]} ]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe161] +set_property port_width 2 [get_debug_ports u_ila_0/probe161] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe161] -connect_debug_port u_ila_0/probe161 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][7]}]] +connect_debug_port u_ila_0/probe161 [get_nets [list {m_axi_arburst[0]} {m_axi_arburst[1]} ]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe162] +set_property port_width 3 [get_debug_ports u_ila_0/probe162] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe162] -connect_debug_port u_ila_0/probe162 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][7]}]] +connect_debug_port u_ila_0/probe162 [get_nets [list {m_axi_arprot[0]} {m_axi_arprot[1]} {m_axi_arprot[2]} ]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe163] +set_property port_width 4 [get_debug_ports u_ila_0/probe163] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe163] -connect_debug_port u_ila_0/probe163 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][7]}]] +connect_debug_port u_ila_0/probe163 [get_nets [list {m_axi_arcache[0]} {m_axi_arcache[1]} {m_axi_arcache[2]} {m_axi_arcache[3]} ]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe164] +set_property port_width 1 [get_debug_ports u_ila_0/probe164] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe164] -connect_debug_port u_ila_0/probe164 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][7]}]] +connect_debug_port u_ila_0/probe164 [get_nets [list {m_axi_arvalid}]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe165] +set_property port_width 31 [get_debug_ports u_ila_0/probe165] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe165] -connect_debug_port u_ila_0/probe165 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][7]}]] +connect_debug_port u_ila_0/probe165 [get_nets [list {m_axi_araddr[0]} {m_axi_araddr[1]} {m_axi_araddr[2]} {m_axi_araddr[3]} {m_axi_araddr[4]} {m_axi_araddr[5]} {m_axi_araddr[6]} {m_axi_araddr[7]} {m_axi_araddr[8]} {m_axi_araddr[9]} {m_axi_araddr[10]} {m_axi_araddr[11]} {m_axi_araddr[12]} {m_axi_araddr[13]} {m_axi_araddr[14]} {m_axi_araddr[15]} {m_axi_araddr[16]} {m_axi_araddr[17]} {m_axi_araddr[18]} {m_axi_araddr[19]} {m_axi_araddr[20]} {m_axi_araddr[21]} {m_axi_araddr[22]} {m_axi_araddr[23]} {m_axi_araddr[24]} {m_axi_araddr[25]} {m_axi_araddr[26]} {m_axi_araddr[27]} {m_axi_araddr[28]} {m_axi_araddr[29]} {m_axi_araddr[30]} ]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe166] +set_property port_width 1 [get_debug_ports u_ila_0/probe166] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe166] -connect_debug_port u_ila_0/probe166 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][7]}]] +connect_debug_port u_ila_0/probe166 [get_nets [list {m_axi_arlock}]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe167] +set_property port_width 1 [get_debug_ports u_ila_0/probe167] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe167] -connect_debug_port u_ila_0/probe167 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][7]}]] +connect_debug_port u_ila_0/probe167 [get_nets [list {m_axi_arready}]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe168] +set_property port_width 4 [get_debug_ports u_ila_0/probe168] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe168] -connect_debug_port u_ila_0/probe168 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][7]}]] +connect_debug_port u_ila_0/probe168 [get_nets [list {m_axi_rid[0]} {m_axi_rid[1]} {m_axi_rid[2]} {m_axi_rid[3]} ]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe169] +set_property port_width 64 [get_debug_ports u_ila_0/probe169] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe169] -connect_debug_port u_ila_0/probe169 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][7]}]] +connect_debug_port u_ila_0/probe169 [get_nets [list {m_axi_rdata[0]} {m_axi_rdata[1]} {m_axi_rdata[2]} {m_axi_rdata[3]} {m_axi_rdata[4]} {m_axi_rdata[5]} {m_axi_rdata[6]} {m_axi_rdata[7]} {m_axi_rdata[8]} {m_axi_rdata[9]} {m_axi_rdata[10]} {m_axi_rdata[11]} {m_axi_rdata[12]} {m_axi_rdata[13]} {m_axi_rdata[14]} {m_axi_rdata[15]} {m_axi_rdata[16]} {m_axi_rdata[17]} {m_axi_rdata[18]} {m_axi_rdata[19]} {m_axi_rdata[20]} {m_axi_rdata[21]} {m_axi_rdata[22]} {m_axi_rdata[23]} {m_axi_rdata[24]} {m_axi_rdata[25]} {m_axi_rdata[26]} {m_axi_rdata[27]} {m_axi_rdata[28]} {m_axi_rdata[29]} {m_axi_rdata[30]} {m_axi_rdata[31]} {m_axi_rdata[32]} {m_axi_rdata[33]} {m_axi_rdata[34]} {m_axi_rdata[35]} {m_axi_rdata[36]} {m_axi_rdata[37]} {m_axi_rdata[38]} {m_axi_rdata[39]} {m_axi_rdata[40]} {m_axi_rdata[41]} {m_axi_rdata[42]} {m_axi_rdata[43]} {m_axi_rdata[44]} {m_axi_rdata[45]} {m_axi_rdata[46]} {m_axi_rdata[47]} {m_axi_rdata[48]} {m_axi_rdata[49]} {m_axi_rdata[50]} {m_axi_rdata[51]} {m_axi_rdata[52]} {m_axi_rdata[53]} {m_axi_rdata[54]} {m_axi_rdata[55]} {m_axi_rdata[56]} {m_axi_rdata[57]} {m_axi_rdata[58]} {m_axi_rdata[59]} {m_axi_rdata[60]} {m_axi_rdata[61]} {m_axi_rdata[62]} {m_axi_rdata[63]} ]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe170] +set_property port_width 2 [get_debug_ports u_ila_0/probe170] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe170] -connect_debug_port u_ila_0/probe170 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][7]}]] +connect_debug_port u_ila_0/probe170 [get_nets [list {m_axi_rresp[0]} {m_axi_rresp[1]} ]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe171] +set_property port_width 1 [get_debug_ports u_ila_0/probe171] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe171] -connect_debug_port u_ila_0/probe171 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][7]}]] +connect_debug_port u_ila_0/probe171 [get_nets [list {m_axi_rvalid}]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe172] +set_property port_width 1 [get_debug_ports u_ila_0/probe172] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe172] -connect_debug_port u_ila_0/probe172 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][7]}]] +connect_debug_port u_ila_0/probe172 [get_nets [list {m_axi_rlast}]] + create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe173] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe173] -connect_debug_port u_ila_0/probe173 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsrfull}]] +connect_debug_port u_ila_0/probe173 [get_nets [list {m_axi_rready}]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe174] +set_property port_width 4 [get_debug_ports u_ila_0/probe174] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe174] -connect_debug_port u_ila_0/probe174 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txhrfull}]] +connect_debug_port u_ila_0/probe174 [get_nets [list {BUS_axi_awid[0]} {BUS_axi_awid[1]} {BUS_axi_awid[2]} {BUS_axi_awid[3]} ]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe175] +set_property port_width 8 [get_debug_ports u_ila_0/probe175] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe175] -connect_debug_port u_ila_0/probe175 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifofull}]] +connect_debug_port u_ila_0/probe175 [get_nets [list {BUS_axi_awlen[0]} {BUS_axi_awlen[1]} {BUS_axi_awlen[2]} {BUS_axi_awlen[3]} {BUS_axi_awlen[4]} {BUS_axi_awlen[5]} {BUS_axi_awlen[6]} {BUS_axi_awlen[7]} ]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe176] +set_property port_width 3 [get_debug_ports u_ila_0/probe176] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe176] -connect_debug_port u_ila_0/probe176 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifoempty}]] +connect_debug_port u_ila_0/probe176 [get_nets [list {BUS_axi_awsize[0]} {BUS_axi_awsize[1]} {BUS_axi_awsize[2]} ]] + create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe177] +set_property port_width 2 [get_debug_ports u_ila_0/probe177] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe177] -connect_debug_port u_ila_0/probe177 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifotail[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifotail[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifotail[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifotail[3]}]] +connect_debug_port u_ila_0/probe177 [get_nets [list {BUS_axi_awburst[0]} {BUS_axi_awburst[1]} ]] + create_debug_port u_ila_0 probe set_property port_width 4 [get_debug_ports u_ila_0/probe178] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe178] -connect_debug_port u_ila_0/probe178 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifohead[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifohead[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifohead[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifohead[3]}]] +connect_debug_port u_ila_0/probe178 [get_nets [list {BUS_axi_awcache[0]} {BUS_axi_awcache[1]} {BUS_axi_awcache[2]} {BUS_axi_awcache[3]} ]] + create_debug_port u_ila_0 probe -set_property port_width 12 [get_debug_ports u_ila_0/probe179] +set_property port_width 31 [get_debug_ports u_ila_0/probe179] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe179] -connect_debug_port u_ila_0/probe179 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[10]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[11]}]] +connect_debug_port u_ila_0/probe179 [get_nets [list {BUS_axi_awaddr[0]} {BUS_axi_awaddr[1]} {BUS_axi_awaddr[2]} {BUS_axi_awaddr[3]} {BUS_axi_awaddr[4]} {BUS_axi_awaddr[5]} {BUS_axi_awaddr[6]} {BUS_axi_awaddr[7]} {BUS_axi_awaddr[8]} {BUS_axi_awaddr[9]} {BUS_axi_awaddr[10]} {BUS_axi_awaddr[11]} {BUS_axi_awaddr[12]} {BUS_axi_awaddr[13]} {BUS_axi_awaddr[14]} {BUS_axi_awaddr[15]} {BUS_axi_awaddr[16]} {BUS_axi_awaddr[17]} {BUS_axi_awaddr[18]} {BUS_axi_awaddr[19]} {BUS_axi_awaddr[20]} {BUS_axi_awaddr[21]} {BUS_axi_awaddr[22]} {BUS_axi_awaddr[23]} {BUS_axi_awaddr[24]} {BUS_axi_awaddr[25]} {BUS_axi_awaddr[26]} {BUS_axi_awaddr[27]} {BUS_axi_awaddr[28]} {BUS_axi_awaddr[29]} {BUS_axi_awaddr[30]} ]] + create_debug_port u_ila_0 probe -set_property port_width 7 [get_debug_ports u_ila_0/probe180] +set_property port_width 3 [get_debug_ports u_ila_0/probe180] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe180] -connect_debug_port u_ila_0/probe180 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[6]}]] +connect_debug_port u_ila_0/probe180 [get_nets [list {BUS_axi_awprot[0]} {BUS_axi_awprot[1]} {BUS_axi_awprot[2]} ]] + create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe181] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe181] -connect_debug_port u_ila_0/probe181 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotimeout}]] +connect_debug_port u_ila_0/probe181 [get_nets [list {BUS_axi_awvalid}]] + create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe182] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe182] -connect_debug_port u_ila_0/probe182 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoempty}]] +connect_debug_port u_ila_0/probe182 [get_nets [list {BUS_axi_awready}]] + create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe183] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe183] -connect_debug_port u_ila_0/probe183 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotriggered}]] +connect_debug_port u_ila_0/probe183 [get_nets [list {BUS_axi_awlock}]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe184] +set_property port_width 64 [get_debug_ports u_ila_0/probe184] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe184] -connect_debug_port u_ila_0/probe184 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxbaudpulse}]] +connect_debug_port u_ila_0/probe184 [get_nets [list {BUS_axi_wdata[0]} {BUS_axi_wdata[1]} {BUS_axi_wdata[2]} {BUS_axi_wdata[3]} {BUS_axi_wdata[4]} {BUS_axi_wdata[5]} {BUS_axi_wdata[6]} {BUS_axi_wdata[7]} {BUS_axi_wdata[8]} {BUS_axi_wdata[9]} {BUS_axi_wdata[10]} {BUS_axi_wdata[11]} {BUS_axi_wdata[12]} {BUS_axi_wdata[13]} {BUS_axi_wdata[14]} {BUS_axi_wdata[15]} {BUS_axi_wdata[16]} {BUS_axi_wdata[17]} {BUS_axi_wdata[18]} {BUS_axi_wdata[19]} {BUS_axi_wdata[20]} {BUS_axi_wdata[21]} {BUS_axi_wdata[22]} {BUS_axi_wdata[23]} {BUS_axi_wdata[24]} {BUS_axi_wdata[25]} {BUS_axi_wdata[26]} {BUS_axi_wdata[27]} {BUS_axi_wdata[28]} {BUS_axi_wdata[29]} {BUS_axi_wdata[30]} {BUS_axi_wdata[31]} {BUS_axi_wdata[32]} {BUS_axi_wdata[33]} {BUS_axi_wdata[34]} {BUS_axi_wdata[35]} {BUS_axi_wdata[36]} {BUS_axi_wdata[37]} {BUS_axi_wdata[38]} {BUS_axi_wdata[39]} {BUS_axi_wdata[40]} {BUS_axi_wdata[41]} {BUS_axi_wdata[42]} {BUS_axi_wdata[43]} {BUS_axi_wdata[44]} {BUS_axi_wdata[45]} {BUS_axi_wdata[46]} {BUS_axi_wdata[47]} {BUS_axi_wdata[48]} {BUS_axi_wdata[49]} {BUS_axi_wdata[50]} {BUS_axi_wdata[51]} {BUS_axi_wdata[52]} {BUS_axi_wdata[53]} {BUS_axi_wdata[54]} {BUS_axi_wdata[55]} {BUS_axi_wdata[56]} {BUS_axi_wdata[57]} {BUS_axi_wdata[58]} {BUS_axi_wdata[59]} {BUS_axi_wdata[60]} {BUS_axi_wdata[61]} {BUS_axi_wdata[62]} {BUS_axi_wdata[63]} ]] + create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe185] +set_property port_width 8 [get_debug_ports u_ila_0/probe185] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe185] -connect_debug_port u_ila_0/probe185 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohead[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohead[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohead[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohead[3]}]] +connect_debug_port u_ila_0/probe185 [get_nets [list {BUS_axi_wstrb[0]} {BUS_axi_wstrb[1]} {BUS_axi_wstrb[2]} {BUS_axi_wstrb[3]} {BUS_axi_wstrb[4]} {BUS_axi_wstrb[5]} {BUS_axi_wstrb[6]} {BUS_axi_wstrb[7]} ]] + create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe186] +set_property port_width 1 [get_debug_ports u_ila_0/probe186] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe186] -connect_debug_port u_ila_0/probe186 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotail[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotail[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotail[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotail[3]}]] +connect_debug_port u_ila_0/probe186 [get_nets [list {BUS_axi_wlast}]] + create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe187] +set_property port_width 1 [get_debug_ports u_ila_0/probe187] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe187] -connect_debug_port u_ila_0/probe187 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[3]}]] +connect_debug_port u_ila_0/probe187 [get_nets [list {BUS_axi_wvalid}]] + create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe188] +set_property port_width 1 [get_debug_ports u_ila_0/probe188] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe188] -connect_debug_port u_ila_0/probe188 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[2]}]] +connect_debug_port u_ila_0/probe188 [get_nets [list {BUS_axi_wready}]] + create_debug_port u_ila_0 probe -set_property port_width 31 [get_debug_ports u_ila_0/probe189] +set_property port_width 4 [get_debug_ports u_ila_0/probe189] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe189] -connect_debug_port u_ila_0/probe189 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[10]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[11]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[12]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[13]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[14]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[15]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[16]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[17]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[18]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[19]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[20]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[21]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[22]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[23]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[24]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[25]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[26]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[27]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[28]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[29]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[30]}]] +connect_debug_port u_ila_0/probe189 [get_nets [list {BUS_axi_bid[0]} {BUS_axi_bid[1]} {BUS_axi_bid[2]} {BUS_axi_bid[3]} ]] + create_debug_port u_ila_0 probe -set_property port_width 16 [get_debug_ports u_ila_0/probe190] +set_property port_width 2 [get_debug_ports u_ila_0/probe190] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe190] -connect_debug_port u_ila_0/probe190 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[10]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[11]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[12]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[13]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[14]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[15]}]] +connect_debug_port u_ila_0/probe190 [get_nets [list {BUS_axi_bresp[0]} {BUS_axi_bresp[1]} ]] + create_debug_port u_ila_0 probe -set_property port_width 16 [get_debug_ports u_ila_0/probe191] +set_property port_width 1 [get_debug_ports u_ila_0/probe191] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe191] -connect_debug_port u_ila_0/probe191 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[10]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[11]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[12]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[13]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[14]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[15]}]] +connect_debug_port u_ila_0/probe191 [get_nets [list {BUS_axi_bvalid}]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe192] +set_property port_width 1 [get_debug_ports u_ila_0/probe192] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe192] -connect_debug_port u_ila_0/probe192 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[7]}]] +connect_debug_port u_ila_0/probe192 [get_nets [list {BUS_axi_bready}]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe193] +set_property port_width 4 [get_debug_ports u_ila_0/probe193] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe193] -connect_debug_port u_ila_0/probe193 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohaserr}]] +connect_debug_port u_ila_0/probe193 [get_nets [list {BUS_axi_arid[0]} {BUS_axi_arid[1]} {BUS_axi_arid[2]} {BUS_axi_arid[3]} ]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe194] +set_property port_width 8 [get_debug_ports u_ila_0/probe194] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe194] -connect_debug_port u_ila_0/probe194 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohaserr}]] +connect_debug_port u_ila_0/probe194 [get_nets [list {BUS_axi_arlen[0]} {BUS_axi_arlen[1]} {BUS_axi_arlen[2]} {BUS_axi_arlen[3]} {BUS_axi_arlen[4]} {BUS_axi_arlen[5]} {BUS_axi_arlen[6]} {BUS_axi_arlen[7]} ]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe195] +set_property port_width 3 [get_debug_ports u_ila_0/probe195] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe195] -connect_debug_port u_ila_0/probe195 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxoverrunerr}]] +connect_debug_port u_ila_0/probe195 [get_nets [list {BUS_axi_arsize[0]} {BUS_axi_arsize[1]} {BUS_axi_arsize[2]} ]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe196] +set_property port_width 2 [get_debug_ports u_ila_0/probe196] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe196] -connect_debug_port u_ila_0/probe196 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxframingerr}]] +connect_debug_port u_ila_0/probe196 [get_nets [list {BUS_axi_arburst[0]} {BUS_axi_arburst[1]} ]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe197] +set_property port_width 3 [get_debug_ports u_ila_0/probe197] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe197] -connect_debug_port u_ila_0/probe197 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxparityerr}]] +connect_debug_port u_ila_0/probe197 [get_nets [list {BUS_axi_arprot[0]} {BUS_axi_arprot[1]} {BUS_axi_arprot[2]} ]] + create_debug_port u_ila_0 probe -set_property port_width 11 [get_debug_ports u_ila_0/probe198] +set_property port_width 4 [get_debug_ports u_ila_0/probe198] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe198] -connect_debug_port u_ila_0/probe198 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[10]}]] +connect_debug_port u_ila_0/probe198 [get_nets [list {BUS_axi_arcache[0]} {BUS_axi_arcache[1]} {BUS_axi_arcache[2]} {BUS_axi_arcache[3]} ]] + create_debug_port u_ila_0 probe -set_property port_width 11 [get_debug_ports u_ila_0/probe199] +set_property port_width 1 [get_debug_ports u_ila_0/probe199] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe199] -connect_debug_port u_ila_0/probe199 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[10]}]] +connect_debug_port u_ila_0/probe199 [get_nets [list {BUS_axi_arvalid}]] + create_debug_port u_ila_0 probe -set_property port_width 11 [get_debug_ports u_ila_0/probe200] +set_property port_width 31 [get_debug_ports u_ila_0/probe200] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe200] -connect_debug_port u_ila_0/probe200 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[10]}]] +connect_debug_port u_ila_0/probe200 [get_nets [list {BUS_axi_araddr[0]} {BUS_axi_araddr[1]} {BUS_axi_araddr[2]} {BUS_axi_araddr[3]} {BUS_axi_araddr[4]} {BUS_axi_araddr[5]} {BUS_axi_araddr[6]} {BUS_axi_araddr[7]} {BUS_axi_araddr[8]} {BUS_axi_araddr[9]} {BUS_axi_araddr[10]} {BUS_axi_araddr[11]} {BUS_axi_araddr[12]} {BUS_axi_araddr[13]} {BUS_axi_araddr[14]} {BUS_axi_araddr[15]} {BUS_axi_araddr[16]} {BUS_axi_araddr[17]} {BUS_axi_araddr[18]} {BUS_axi_araddr[19]} {BUS_axi_araddr[20]} {BUS_axi_araddr[21]} {BUS_axi_araddr[22]} {BUS_axi_araddr[23]} {BUS_axi_araddr[24]} {BUS_axi_araddr[25]} {BUS_axi_araddr[26]} {BUS_axi_araddr[27]} {BUS_axi_araddr[28]} {BUS_axi_araddr[29]} {BUS_axi_araddr[30]} ]] + create_debug_port u_ila_0 probe -set_property port_width 11 [get_debug_ports u_ila_0/probe201] +set_property port_width 1 [get_debug_ports u_ila_0/probe201] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe201] -connect_debug_port u_ila_0/probe201 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[10]}]] +connect_debug_port u_ila_0/probe201 [get_nets [list {BUS_axi_arlock}]] + create_debug_port u_ila_0 probe -set_property port_width 11 [get_debug_ports u_ila_0/probe202] +set_property port_width 1 [get_debug_ports u_ila_0/probe202] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe202] -connect_debug_port u_ila_0/probe202 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[10]}]] +connect_debug_port u_ila_0/probe202 [get_nets [list {BUS_axi_arready}]] + create_debug_port u_ila_0 probe -set_property port_width 11 [get_debug_ports u_ila_0/probe203] +set_property port_width 4 [get_debug_ports u_ila_0/probe203] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe203] -connect_debug_port u_ila_0/probe203 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[10]}]] +connect_debug_port u_ila_0/probe203 [get_nets [list {BUS_axi_rid[0]} {BUS_axi_rid[1]} {BUS_axi_rid[2]} {BUS_axi_rid[3]} ]] + create_debug_port u_ila_0 probe -set_property port_width 11 [get_debug_ports u_ila_0/probe204] +set_property port_width 64 [get_debug_ports u_ila_0/probe204] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe204] -connect_debug_port u_ila_0/probe204 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[10]}]] +connect_debug_port u_ila_0/probe204 [get_nets [list {BUS_axi_rdata[0]} {BUS_axi_rdata[1]} {BUS_axi_rdata[2]} {BUS_axi_rdata[3]} {BUS_axi_rdata[4]} {BUS_axi_rdata[5]} {BUS_axi_rdata[6]} {BUS_axi_rdata[7]} {BUS_axi_rdata[8]} {BUS_axi_rdata[9]} {BUS_axi_rdata[10]} {BUS_axi_rdata[11]} {BUS_axi_rdata[12]} {BUS_axi_rdata[13]} {BUS_axi_rdata[14]} {BUS_axi_rdata[15]} {BUS_axi_rdata[16]} {BUS_axi_rdata[17]} {BUS_axi_rdata[18]} {BUS_axi_rdata[19]} {BUS_axi_rdata[20]} {BUS_axi_rdata[21]} {BUS_axi_rdata[22]} {BUS_axi_rdata[23]} {BUS_axi_rdata[24]} {BUS_axi_rdata[25]} {BUS_axi_rdata[26]} {BUS_axi_rdata[27]} {BUS_axi_rdata[28]} {BUS_axi_rdata[29]} {BUS_axi_rdata[30]} {BUS_axi_rdata[31]} {BUS_axi_rdata[32]} {BUS_axi_rdata[33]} {BUS_axi_rdata[34]} {BUS_axi_rdata[35]} {BUS_axi_rdata[36]} {BUS_axi_rdata[37]} {BUS_axi_rdata[38]} {BUS_axi_rdata[39]} {BUS_axi_rdata[40]} {BUS_axi_rdata[41]} {BUS_axi_rdata[42]} {BUS_axi_rdata[43]} {BUS_axi_rdata[44]} {BUS_axi_rdata[45]} {BUS_axi_rdata[46]} {BUS_axi_rdata[47]} {BUS_axi_rdata[48]} {BUS_axi_rdata[49]} {BUS_axi_rdata[50]} {BUS_axi_rdata[51]} {BUS_axi_rdata[52]} {BUS_axi_rdata[53]} {BUS_axi_rdata[54]} {BUS_axi_rdata[55]} {BUS_axi_rdata[56]} {BUS_axi_rdata[57]} {BUS_axi_rdata[58]} {BUS_axi_rdata[59]} {BUS_axi_rdata[60]} {BUS_axi_rdata[61]} {BUS_axi_rdata[62]} {BUS_axi_rdata[63]} ]] + create_debug_port u_ila_0 probe -set_property port_width 11 [get_debug_ports u_ila_0/probe205] +set_property port_width 2 [get_debug_ports u_ila_0/probe205] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe205] -connect_debug_port u_ila_0/probe205 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[10]}]] +connect_debug_port u_ila_0/probe205 [get_nets [list {BUS_axi_rresp[0]} {BUS_axi_rresp[1]} ]] + create_debug_port u_ila_0 probe -set_property port_width 11 [get_debug_ports u_ila_0/probe206] +set_property port_width 1 [get_debug_ports u_ila_0/probe206] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe206] -connect_debug_port u_ila_0/probe206 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[10]}]] +connect_debug_port u_ila_0/probe206 [get_nets [list {BUS_axi_rvalid}]] + create_debug_port u_ila_0 probe -set_property port_width 11 [get_debug_ports u_ila_0/probe207] +set_property port_width 1 [get_debug_ports u_ila_0/probe207] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe207] -connect_debug_port u_ila_0/probe207 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[10]}]] +connect_debug_port u_ila_0/probe207 [get_nets [list {BUS_axi_rlast}]] + create_debug_port u_ila_0 probe -set_property port_width 11 [get_debug_ports u_ila_0/probe208] +set_property port_width 1 [get_debug_ports u_ila_0/probe208] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe208] -connect_debug_port u_ila_0/probe208 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[10]}]] - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe209] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe209] -connect_debug_port u_ila_0/probe209 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/MEMRb}]] - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe210] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe210] -connect_debug_port u_ila_0/probe210 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXRDYb}]] - -create_debug_port u_ila_0 probe -set_property port_width 12 [get_debug_ports u_ila_0/probe211] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe211] -connect_debug_port u_ila_0/probe211 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/requests[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[2]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[3]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[4]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[5]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[6]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[7]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[8]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[9]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[10]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[11]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[12]}]] - -create_debug_port u_ila_0 probe -set_property port_width 12 [get_debug_ports u_ila_0/probe212] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe212] -connect_debug_port u_ila_0/probe212 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[2]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[3]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[4]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[5]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[6]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[7]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[8]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[9]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[10]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[11]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[12]}]] - -create_debug_port u_ila_0 probe -set_property port_width 12 [get_debug_ports u_ila_0/probe213] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe213] -connect_debug_port u_ila_0/probe213 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[2]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[3]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[4]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[5]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[6]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[7]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[8]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[9]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[10]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[11]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[12]}]] - -create_debug_port u_ila_0 probe -set_property port_width 70 [get_debug_ports u_ila_0/probe214] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe214] -connect_debug_port u_ila_0/probe214 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][10]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe215] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe215] -connect_debug_port u_ila_0/probe215 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intPriority[10][0]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPriority[10][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPriority[10][2]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 10 [get_debug_ports u_ila_0/probe216] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe216] -connect_debug_port u_ila_0/probe216 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[2]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[3]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[4]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[5]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[6]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[7]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[8]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[9]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[10]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 6 [get_debug_ports u_ila_0/probe217] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe217] -connect_debug_port u_ila_0/probe217 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][0]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][5]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 6 [get_debug_ports u_ila_0/probe218] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe218] -connect_debug_port u_ila_0/probe218 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][0]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][5]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 7 [get_debug_ports u_ila_0/probe219] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe219] -connect_debug_port u_ila_0/probe219 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][7]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 7 [get_debug_ports u_ila_0/probe220] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe220] -connect_debug_port u_ila_0/probe220 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][7]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe221] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe221] -connect_debug_port u_ila_0/probe221 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0]__0[0]} {wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0]__0[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0]__0[2]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe222] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe222] -connect_debug_port u_ila_0/probe222 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1]__0[0]} {wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1]__0[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1]__0[2]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 53 [get_debug_ports u_ila_0/probe223] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe223] -connect_debug_port u_ila_0/probe223 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][11]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][12]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][13]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][14]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][15]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][16]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][17]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][18]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][19]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][20]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][21]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][22]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][23]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][24]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][25]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][26]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][27]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][28]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][29]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][30]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][31]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][32]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][33]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][34]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][35]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][36]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][37]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][38]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][39]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][40]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][41]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][42]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][43]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][44]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][45]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][46]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][47]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][48]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][49]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][50]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][51]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][52]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][53]} ]] - +connect_debug_port u_ila_0/probe208 [get_nets [list {BUS_axi_rready}]] diff --git a/fpga/generator/xlnx_axi_crossbar.tcl b/fpga/generator/xlnx_axi_crossbar.tcl index ba867a640..1d9eb4e78 100644 --- a/fpga/generator/xlnx_axi_crossbar.tcl +++ b/fpga/generator/xlnx_axi_crossbar.tcl @@ -22,7 +22,8 @@ set_property -dict [list CONFIG.NUM_SI {2} \ CONFIG.M01_S01_READ_CONNECTIVITY {0} \ CONFIG.M01_S01_WRITE_CONNECTIVITY {0} \ CONFIG.M00_A00_BASE_ADDR {0x0000000080000000} \ - CONFIG.M01_A00_BASE_ADDR {0x0000000000013000}] [get_ips $ipName] + CONFIG.M01_A00_BASE_ADDR {0x0000000000013000} \ + CONFIG.M00_A00_ADDR_WIDTH {31}] [get_ips $ipName] generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index bf910257d..4e5958875 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -94,41 +94,41 @@ module fpgaTop wire SDCCmdOE; wire SDCCmdOut; - wire [3:0] m_axi_awid; - wire [7:0] m_axi_awlen; - wire [2:0] m_axi_awsize; - wire [1:0] m_axi_awburst; - wire [3:0] m_axi_awcache; - wire [31:0] m_axi_awaddr; - wire [2:0] m_axi_awprot; - wire m_axi_awvalid; - wire m_axi_awready; - wire m_axi_awlock; - wire [63:0] m_axi_wdata; - wire [7:0] m_axi_wstrb; - wire m_axi_wlast; - wire m_axi_wvalid; - wire m_axi_wready; - wire [3:0] m_axi_bid; - wire [1:0] m_axi_bresp; - wire m_axi_bvalid; - wire m_axi_bready; - wire [3:0] m_axi_arid; - wire [7:0] m_axi_arlen; - wire [2:0] m_axi_arsize; - wire [1:0] m_axi_arburst; - wire [2:0] m_axi_arprot; - wire [3:0] m_axi_arcache; - wire m_axi_arvalid; - wire [31:0] m_axi_araddr; - wire m_axi_arlock; - wire m_axi_arready; - wire [3:0] m_axi_rid; - wire [63:0] m_axi_rdata; - wire [1:0] m_axi_rresp; - wire m_axi_rvalid; - wire m_axi_rlast; - wire m_axi_rready; + (* mark_debug = "true" *) wire [3:0] m_axi_awid; + (* mark_debug = "true" *) wire [7:0] m_axi_awlen; + (* mark_debug = "true" *) wire [2:0] m_axi_awsize; + (* mark_debug = "true" *) wire [1:0] m_axi_awburst; + (* mark_debug = "true" *) wire [3:0] m_axi_awcache; + (* mark_debug = "true" *) wire [31:0] m_axi_awaddr; + (* mark_debug = "true" *) wire [2:0] m_axi_awprot; + (* mark_debug = "true" *) wire m_axi_awvalid; + (* mark_debug = "true" *) wire m_axi_awready; + (* mark_debug = "true" *) wire m_axi_awlock; + (* mark_debug = "true" *) wire [63:0] m_axi_wdata; + (* mark_debug = "true" *) wire [7:0] m_axi_wstrb; + (* mark_debug = "true" *) wire m_axi_wlast; + (* mark_debug = "true" *) wire m_axi_wvalid; + (* mark_debug = "true" *) wire m_axi_wready; + (* mark_debug = "true" *) wire [3:0] m_axi_bid; + (* mark_debug = "true" *) wire [1:0] m_axi_bresp; + (* mark_debug = "true" *) wire m_axi_bvalid; + (* mark_debug = "true" *) wire m_axi_bready; + (* mark_debug = "true" *) wire [3:0] m_axi_arid; + (* mark_debug = "true" *) wire [7:0] m_axi_arlen; + (* mark_debug = "true" *) wire [2:0] m_axi_arsize; + (* mark_debug = "true" *) wire [1:0] m_axi_arburst; + (* mark_debug = "true" *) wire [2:0] m_axi_arprot; + (* mark_debug = "true" *) wire [3:0] m_axi_arcache; + (* mark_debug = "true" *) wire m_axi_arvalid; + (* mark_debug = "true" *) wire [31:0] m_axi_araddr; + (* mark_debug = "true" *) wire m_axi_arlock; + (* mark_debug = "true" *) wire m_axi_arready; + (* mark_debug = "true" *) wire [3:0] m_axi_rid; + (* mark_debug = "true" *) wire [63:0] m_axi_rdata; + (* mark_debug = "true" *) wire [1:0] m_axi_rresp; + (* mark_debug = "true" *) wire m_axi_rvalid; + (* mark_debug = "true" *) wire m_axi_rlast; + (* mark_debug = "true" *) wire m_axi_rready; // Extra Bus signals wire [3:0] BUS_axi_arregion; @@ -137,41 +137,41 @@ module fpgaTop wire [3:0] BUS_axi_awqos; // Bus signals - wire [3:0] BUS_axi_awid; - wire [7:0] BUS_axi_awlen; - wire [2:0] BUS_axi_awsize; - wire [1:0] BUS_axi_awburst; - wire [3:0] BUS_axi_awcache; - wire [30:0] BUS_axi_awaddr; - wire [2:0] BUS_axi_awprot; - wire BUS_axi_awvalid; - wire BUS_axi_awready; - wire BUS_axi_awlock; - wire [63:0] BUS_axi_wdata; - wire [7:0] BUS_axi_wstrb; - wire BUS_axi_wlast; - wire BUS_axi_wvalid; - wire BUS_axi_wready; - wire [3:0] BUS_axi_bid; - wire [1:0] BUS_axi_bresp; - wire BUS_axi_bvalid; - wire BUS_axi_bready; - wire [3:0] BUS_axi_arid; - wire [7:0] BUS_axi_arlen; - wire [2:0] BUS_axi_arsize; - wire [1:0] BUS_axi_arburst; - wire [2:0] BUS_axi_arprot; - wire [3:0] BUS_axi_arcache; - wire BUS_axi_arvalid; - wire [30:0] BUS_axi_araddr; - wire BUS_axi_arlock; - wire BUS_axi_arready; - wire [3:0] BUS_axi_rid; - wire [63:0] BUS_axi_rdata; - wire [1:0] BUS_axi_rresp; - wire BUS_axi_rvalid; - wire BUS_axi_rlast; - wire BUS_axi_rready; + (* mark_debug = "true" *) wire [3:0] BUS_axi_awid; + (* mark_debug = "true" *) wire [7:0] BUS_axi_awlen; + (* mark_debug = "true" *) wire [2:0] BUS_axi_awsize; + (* mark_debug = "true" *) wire [1:0] BUS_axi_awburst; + (* mark_debug = "true" *) wire [3:0] BUS_axi_awcache; + (* mark_debug = "true" *) wire [30:0] BUS_axi_awaddr; + (* mark_debug = "true" *) wire [2:0] BUS_axi_awprot; + (* mark_debug = "true" *) wire BUS_axi_awvalid; + (* mark_debug = "true" *) wire BUS_axi_awready; + (* mark_debug = "true" *) wire BUS_axi_awlock; + (* mark_debug = "true" *) wire [63:0] BUS_axi_wdata; + (* mark_debug = "true" *) wire [7:0] BUS_axi_wstrb; + (* mark_debug = "true" *) wire BUS_axi_wlast; + (* mark_debug = "true" *) wire BUS_axi_wvalid; + (* mark_debug = "true" *) wire BUS_axi_wready; + (* mark_debug = "true" *) wire [3:0] BUS_axi_bid; + (* mark_debug = "true" *) wire [1:0] BUS_axi_bresp; + (* mark_debug = "true" *) wire BUS_axi_bvalid; + (* mark_debug = "true" *) wire BUS_axi_bready; + (* mark_debug = "true" *) wire [3:0] BUS_axi_arid; + (* mark_debug = "true" *) wire [7:0] BUS_axi_arlen; + (* mark_debug = "true" *) wire [2:0] BUS_axi_arsize; + (* mark_debug = "true" *) wire [1:0] BUS_axi_arburst; + (* mark_debug = "true" *) wire [2:0] BUS_axi_arprot; + (* mark_debug = "true" *) wire [3:0] BUS_axi_arcache; + (* mark_debug = "true" *) wire BUS_axi_arvalid; + (* mark_debug = "true" *) wire [30:0] BUS_axi_araddr; + (* mark_debug = "true" *) wire BUS_axi_arlock; + (* mark_debug = "true" *) wire BUS_axi_arready; + (* mark_debug = "true" *) wire [3:0] BUS_axi_rid; + (* mark_debug = "true" *) wire [63:0] BUS_axi_rdata; + (* mark_debug = "true" *) wire [1:0] BUS_axi_rresp; + (* mark_debug = "true" *) wire BUS_axi_rvalid; + (* mark_debug = "true" *) wire BUS_axi_rlast; + (* mark_debug = "true" *) wire BUS_axi_rready; wire BUSCLK; @@ -404,14 +404,19 @@ module fpgaTop wire m01_axi_rready; wire [3:0] SDCDatIn; - + + reg sd_cmd_reg_o; + reg sd_cmd_reg_t; + wire [3:0] sd_dat_i; + assign GPIOPinsIn = {28'b0, GPI}; assign GPO = GPIOPinsOut[4:0]; assign ahblite_resetn = peripheral_aresetn; assign cpu_reset = bus_struct_reset; assign calib = c0_init_calib_complete; - + + // SD Card Tristate IOBUF iobufSDCMD(.T(~SDCCmdOE), // iobuf's T is active low .I(SDCCmdOut), @@ -825,10 +830,14 @@ module fpgaTop //.sdio_dat(4'b0), //.sdio_cd(1'b0) + //.sd_dat_reg_t(), + //.sd_dat_reg_o(), .sd_dat_i(4'b0), + + //.sd_cmd_reg_t(), + //.sd_cmd_reg_o(), .sd_cmd_i(1'b0) - ); xlnx_axi_dwidth_conv_32to64 axi_conv_up From b7571a349d17d88ad30188ea4f704340e39c4c83 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Sat, 25 Feb 2023 16:32:20 -0600 Subject: [PATCH 14/22] Preliminary work on new bootloader using new SD peripheral. Rewrote copyflash to take advantage of the new peripheral. The new peripheral has the neat ability to use CMD18 in the SD card specification, allowing us to load multiple blocks in succession, ending the chain of CMD18 commands with a CMD17. --- tests/custom/boot/boot.c | 50 ++++++++++++++++++---------------------- tests/custom/boot/boot.h | 12 ++++++++++ 2 files changed, 34 insertions(+), 28 deletions(-) create mode 100644 tests/custom/boot/boot.h diff --git a/tests/custom/boot/boot.c b/tests/custom/boot/boot.c index 8546861f9..7f04c1514 100644 --- a/tests/custom/boot/boot.c +++ b/tests/custom/boot/boot.c @@ -1,4 +1,4 @@ - +#include "boot.h" /* Card type flags (card_type) */ #define CT_MMC 0x01 /* MMC ver 3 */ @@ -72,6 +72,7 @@ #define SDC_DAT_INT_STATUS_CRC 0x0008 // CRC error #define SDC_DAT_INT_STATUS_CFE 0x0010 // Data FIFO underrun or overrun + #define ERR_EOF 30 #define ERR_NOT_ELF 31 #define ERR_ELF_BITS 32 @@ -116,12 +117,7 @@ static int errno __attribute__((section(".bss"))); static DSTATUS drv_status __attribute__((section(".bss"))); static BYTE card_type __attribute__((section(".bss"))); static uint32_t response[4] __attribute__((section(".bss"))); -static FATFS fatfs __attribute__((section(".bss"))); static int alt_mem __attribute__((section(".bss"))); -static FIL fd __attribute__((section(".bss"))); - -extern unsigned char _fbss[]; -extern unsigned char _ebss[]; static const char * errno_to_str(void) { switch (errno) { @@ -252,7 +248,7 @@ static int send_data_cmd(unsigned cmd, unsigned arg, void * buf, unsigned blocks case CMD2: case CMD9: case CMD10: - // R2 + // R2 command |= 2; // 136 bits command |= 1 << 3; // resp CRC break; @@ -305,6 +301,9 @@ static int ini_sd(void) { /* Reset controller */ regs->software_reset = 1; while ((regs->software_reset & 1) == 0) {} + + // This clock divider is meant to initialize the card at + // 400kHz regs->clock_divider = 0x7c; regs->software_reset = 0; while (regs->software_reset) {} @@ -369,10 +368,16 @@ static int ini_sd(void) { return 0; } -DRESULT disk_read(BYTE drv, BYTE * buf, LBA_t sector, UINT count) { +int disk_read(BYTE * buf, LBA_t sector, UINT count) { - if (!count) return RES_PARERR; - if (drv_status & STA_NOINIT) return RES_NOTRDY; + /* This is not needed. This has everything to do with the FAT + filesystem stuff that I'm not including. All I need to do is + initialize the SD card and read from it. Anything in here that is + checking for potential errors, I'm going to have to temporarily + do without. + */ + // if (!count) return RES_PARERR; + /* if (drv_status & STA_NOINIT) return RES_NOTRDY; */ /* Convert LBA to byte address if needed */ if (!(card_type & CT_BLOCK)) sector *= 512; @@ -389,30 +394,19 @@ DRESULT disk_read(BYTE drv, BYTE * buf, LBA_t sector, UINT count) { return RES_OK; } -void disk_read(BYTE drv, BYTE * buf, LBA_t sector, UINT count) { +void copyFlash(QWORD address, QWORD * Dst, DWORD numBlocks) { + ini_sd(); - if (!count) return RES_PARERR; - if (drv_status & STA_NOINIT) return RES_NOTRDY; - - /* Convert LBA to byte address if needed */ - if (!(card_type & CT_BLOCK)) sector *= 512; - while (count > 0) { - UINT bcnt = count > MAX_BLOCK_CNT ? MAX_BLOCK_CNT : count; - unsigned bytes = bcnt * 512; - if (send_data_cmd(bcnt == 1 ? CMD17 : CMD18, sector, buf, bcnt) < 0) return RES_ERROR; - if (bcnt > 1 && send_cmd(CMD12, 0) < 0) return RES_ERROR; - sector += (card_type & CT_BLOCK) ? bcnt : bytes; - count -= bcnt; - buf += bytes; - } - - return RES_OK; + BYTE * buf = (BYTE *)Dst; + + if (disk_read(buf, (LBA_t)address, (UINT)numBlocks) < 0) /* UART Print function?*/; } +/* int main() { ini_sd(); - return 0; } +*/ diff --git a/tests/custom/boot/boot.h b/tests/custom/boot/boot.h new file mode 100644 index 000000000..ef620cda0 --- /dev/null +++ b/tests/custom/boot/boot.h @@ -0,0 +1,12 @@ +#ifndef WALLYBOOT +#define WALLYBOOT 10000 + +#include +typedef unsigned int UINT; /* int must be 16-bit or 32-bit */ +typedef unsigned char BYTE; /* char must be 8-bit */ +typedef uint16_t WORD; /* 16-bit unsigned integer */ +typedef uint32_t DWORD; /* 32-bit unsigned integer */ +typedef uint64_t QWORD; /* 64-bit unsigned integer */ +typedef WORD WCHAR; + +#endif // WALLYBOOT From a7b547008a5dc6d0f75bfe96dae40ae968d9bac9 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Tue, 28 Feb 2023 12:18:13 -0600 Subject: [PATCH 15/22] Commented out some fat filesystem error checks. --- tests/custom/boot/boot.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/tests/custom/boot/boot.c b/tests/custom/boot/boot.c index 7f04c1514..9f4eaa6f9 100644 --- a/tests/custom/boot/boot.c +++ b/tests/custom/boot/boot.c @@ -114,7 +114,7 @@ struct sdc_regs { static struct sdc_regs * const regs __attribute__((section(".rodata"))) = (struct sdc_regs *)0x00013100; static int errno __attribute__((section(".bss"))); -static DSTATUS drv_status __attribute__((section(".bss"))); +// static DSTATUS drv_status __attribute__((section(".bss"))); static BYTE card_type __attribute__((section(".bss"))); static uint32_t response[4] __attribute__((section(".bss"))); static int alt_mem __attribute__((section(".bss"))); @@ -310,7 +310,7 @@ static int ini_sd(void) { usleep(5000); card_type = 0; - drv_status = STA_NOINIT; + // drv_status = STA_NOINIT; if (regs->capability & SDC_CAPABILITY_SD_RESET) { /* Power cycle SD card */ @@ -364,7 +364,7 @@ static int ini_sd(void) { /* Set R/W block length to 512 */ if (send_cmd(CMD16, 512) < 0) return -1; - drv_status &= ~STA_NOINIT; + // drv_status &= ~STA_NOINIT; return 0; } @@ -385,13 +385,13 @@ int disk_read(BYTE * buf, LBA_t sector, UINT count) { UINT bcnt = count > MAX_BLOCK_CNT ? MAX_BLOCK_CNT : count; unsigned bytes = bcnt * 512; if (send_data_cmd(bcnt == 1 ? CMD17 : CMD18, sector, buf, bcnt) < 0) return RES_ERROR; - if (bcnt > 1 && send_cmd(CMD12, 0) < 0) return RES_ERROR; + if (bcnt > 1 && send_cmd(CMD12, 0) < 0) return 1; sector += (card_type & CT_BLOCK) ? bcnt : bytes; count -= bcnt; buf += bytes; } - return RES_OK; + return 0;; } void copyFlash(QWORD address, QWORD * Dst, DWORD numBlocks) { From 449b835fcd2499609e30603fbdeaca8860212a47 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Tue, 28 Feb 2023 12:20:46 -0600 Subject: [PATCH 16/22] Disabled old SD card and attached IOBUF's to new SD peripheral. --- config/fpga/wally-config.vh | 2 +- fpga/src/fpgaTop.v | 47 ++++++++++++++++++++++++++----------- 2 files changed, 34 insertions(+), 15 deletions(-) diff --git a/config/fpga/wally-config.vh b/config/fpga/wally-config.vh index de25e1b43..007562a17 100644 --- a/config/fpga/wally-config.vh +++ b/config/fpga/wally-config.vh @@ -117,7 +117,7 @@ `define PLIC_SUPPORTED 1'b1 `define PLIC_BASE 56'h0C000000 `define PLIC_RANGE 56'h03FFFFFF -`define SDC_SUPPORTED 1'b1 +`define SDC_SUPPORTED 1'b0 `define SDC_BASE 56'h00012100 `define SDC_RANGE 56'h0000001F diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index 4e5958875..13f61c03f 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -90,9 +90,10 @@ module fpgaTop wire [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn; - wire SDCCmdIn; - wire SDCCmdOE; - wire SDCCmdOut; + // Old SDC connections + // wire SDCCmdIn; + // wire SDCCmdOE; + // wire SDCCmdOut; (* mark_debug = "true" *) wire [3:0] m_axi_awid; (* mark_debug = "true" *) wire [7:0] m_axi_awlen; @@ -403,11 +404,18 @@ module fpgaTop wire m01_axi_rvalid; wire m01_axi_rready; - wire [3:0] SDCDatIn; + // Old SDC input + // wire [3:0] SDCDatIn; + // New SDC Command IOBUF connections + wire sd_cmd_i; reg sd_cmd_reg_o; reg sd_cmd_reg_t; + + // New SDC Data IOBUF connections wire [3:0] sd_dat_i; + reg [3:0] sd_dat_reg_o; + reg sd_dat_reg_t; assign GPIOPinsIn = {28'b0, GPI}; assign GPO = GPIOPinsOut[4:0]; @@ -418,12 +426,12 @@ module fpgaTop // SD Card Tristate + /* IOBUF iobufSDCMD(.T(~SDCCmdOE), // iobuf's T is active low .I(SDCCmdOut), .O(SDCCmdIn), .IO(SDCCmd)); - genvar i; generate for (i = 0; i < 4; i = i + 1) begin @@ -433,8 +441,20 @@ module fpgaTop .IO(SDCDat[i])); end endgenerate - - // IOBUF IOBUF_cmd (.O(sd_cmd_i), .IO(sdio_cmd), .I(sd_cmd_reg_o), .T(sd_cmd_reg_t)); + */ + + // IOBUFS for new SDC peripheral + IOBUF IOBUF_cmd (.O(sd_cmd_i), .IO(SDCcmd), .I(sd_cmd_reg_o), .T(sd_cmd_reg_t)); + genvar i; + generate + for (i = 0; i < 4; i = i + 1) begin + IOBUF iobufSDCDat(.T(sd_dat_reg_t), + .I(sd_dat_reg_o[i]), + .O(sd_dat_i[i]), + .IO(SDCDat[i]) ); + end + endgenerate + // IOBUF IOBUF_dat0 (.O(sd_dat_i[0]), .IO(sdio_dat[0]), .I(sd_dat_reg_o[0]), .T(sd_dat_reg_t)); // IOBUF IOBUF_dat1 (.O(sd_dat_i[1]), .IO(sdio_dat[1]), .I(sd_dat_reg_o[1]), .T(sd_dat_reg_t)); // IOBUF IOBUF_dat2 (.O(sd_dat_i[2]), .IO(sdio_dat[2]), .I(sd_dat_reg_o[2]), .T(sd_dat_reg_t)); @@ -830,14 +850,13 @@ module fpgaTop //.sdio_dat(4'b0), //.sdio_cd(1'b0) - //.sd_dat_reg_t(), - //.sd_dat_reg_o(), - .sd_dat_i(4'b0), + .sd_dat_reg_t(sd_dat_reg_t), + .sd_dat_reg_o(sd_dat_reg_o), + .sd_dat_i(sd_dat_i), - //.sd_cmd_reg_t(), - //.sd_cmd_reg_o(), - .sd_cmd_i(1'b0) - + .sd_cmd_reg_t(sd_cmd_reg_t), + .sd_cmd_reg_o(sd_cmd_reg_o), + .sd_cmd_i(sd_cmd_i) ); xlnx_axi_dwidth_conv_32to64 axi_conv_up From 2d0199a35475ad8254bdeb6c2825e6dbb5c593e8 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Fri, 24 Mar 2023 17:01:27 -0500 Subject: [PATCH 17/22] Added sdio_cd to vcu108 constraints. Removed SDC signals from uncore --- fpga/constraints/constraints-vcu108.xdc | 48 ++++++----- fpga/src/fpgaTop.v | 66 ++++++++-------- src/uncore/uncore.sv | 8 +- src/wally/wallypipelinedsoc.sv | 6 +- tests/custom/boot/bios.s | 101 ++++++++++++++++++++++++ tests/custom/boot/boot.c | 19 ----- 6 files changed, 171 insertions(+), 77 deletions(-) create mode 100644 tests/custom/boot/bios.s diff --git a/fpga/constraints/constraints-vcu108.xdc b/fpga/constraints/constraints-vcu108.xdc index cbb70db92..8d59509be 100644 --- a/fpga/constraints/constraints-vcu108.xdc +++ b/fpga/constraints/constraints-vcu108.xdc @@ -3,7 +3,8 @@ # mmcm_clkout0 is the clock output of the DDR4 memory interface / 4. # This clock is not used by wally or the AHBLite Bus. However it is used by the AXI BUS on the DD4 IP. -create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O] +# create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O] +create_generated_clock -name CLKDiv64_Gen -source [get_pins xlnx_ddr4_c0/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins axiSDC/clock_posedge_reg/Q] ##### GPI #### set_property PACKAGE_PIN E34 [get_ports {GPI[0]}] @@ -16,7 +17,7 @@ set_property IOSTANDARD LVCMOS12 [get_ports {GPI[1]}] set_property IOSTANDARD LVCMOS12 [get_ports {GPI[0]}] set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports {GPI[*]}] set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports {GPI[*]}] -set_max_delay -from [get_ports {GPI[*]}] 10.000 +set_max_delay -from [get_ports {GPI[*]}] 10.000n ##### GPO #### set_property PACKAGE_PIN AT32 [get_ports {GPO[0]}] @@ -92,23 +93,32 @@ set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_port ##### SD Card I/O ##### -set_property PACKAGE_PIN BC14 [get_ports {SDCDat[3]}] -set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[3]}] -set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[2]}] -set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[1]}] -set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[0]}] -set_property PACKAGE_PIN BF7 [get_ports {SDCDat[2]}] -set_property PACKAGE_PIN BC13 [get_ports {SDCDat[1]}] -set_property PACKAGE_PIN AW16 [get_ports {SDCDat[0]}] -set_property IOSTANDARD LVCMOS18 [get_ports SDCCLK] -set_property IOSTANDARD LVCMOS18 [get_ports {SDCCmd}] -set_property PACKAGE_PIN BB16 [get_ports SDCCLK] -set_property PACKAGE_PIN BA10 [get_ports {SDCCmd}] -set_property PULLUP true [get_ports {SDCDat[3]}] -set_property PULLUP true [get_ports {SDCDat[2]}] -set_property PULLUP true [get_ports {SDCDat[1]}] -set_property PULLUP true [get_ports {SDCDat[0]}] -set_property PULLUP true [get_ports {SDCCmd}] + +# set_property PACKAGE_PIN BC14 [get_ports {SDCDat[3]}] +# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[3]}] +# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[2]}] +# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[1]}] +# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[0]}] +# set_property PACKAGE_PIN BF7 [get_ports {SDCDat[2]}] +# set_property PACKAGE_PIN BC13 [get_ports {SDCDat[1]}] +# set_property PACKAGE_PIN AW16 [get_ports {SDCDat[0]}] +# set_property IOSTANDARD LVCMOS18 [get_ports SDCCLK] +# set_property IOSTANDARD LVCMOS18 [get_ports {SDCCmd}] +# set_property PACKAGE_PIN BB16 [get_ports SDCCLK] +# set_property PACKAGE_PIN BA10 [get_ports {SDCCmd}] +# set_property PULLUP true [get_ports {SDCDat[3]}] +# set_property PULLUP true [get_ports {SDCDat[2]}] +# set_property PULLUP true [get_ports {SDCDat[1]}] +# set_property PULLUP true [get_ports {SDCDat[0]}] +# set_property PULLUP true [get_ports {SDCCmd}] + +set_property -dict {PACKAGE_PIN BC14 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[3]}] +set_property -dict {PACKAGE_PIN BF7 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[2]}] +set_property -dict {PACKAGE_PIN BC13 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[1]}] +set_property -dict {PACKAGE_PIN AW16 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[0]}] +set_property -dict {PACKAGE_PIN BA10 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCmd}] +set_property -dict {PACKAGE_PIN AW12 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCD}] +set_property -dict {PACKAGE_PIN BB16 IOSTANDARD LVCMOS18} [get_ports SDCCLK] set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCDat[*]}] diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index 13f61c03f..e2eb8441e 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -28,23 +28,24 @@ module fpgaTop (input default_250mhz_clk1_0_n, - input default_250mhz_clk1_0_p, - input reset, - input south_rst, + input default_250mhz_clk1_0_p, + input reset, + input south_rst, - input [3:0] GPI, + input [3:0] GPI, output [4:0] GPO, - input UARTSin, - output UARTSout, + input UARTSin, + output UARTSout, - inout [3:0] SDCDat, - output SDCCLK, - inout SDCCmd, + inout [3:0] SDCDat, + output SDCCLK, + inout SDCCmd, + input SDCCD, - output calib, - output cpu_reset, - output ahblite_resetn, + output calib, + output cpu_reset, + output ahblite_resetn, output [16 : 0] c0_ddr4_adr, output [1 : 0] c0_ddr4_ba, @@ -56,8 +57,8 @@ module fpgaTop inout [7 : 0] c0_ddr4_dqs_t, output [0 : 0] c0_ddr4_odt, output [0 : 0] c0_ddr4_bg, - output c0_ddr4_reset_n, - output c0_ddr4_act_n, + output c0_ddr4_reset_n, + output c0_ddr4_act_n, output [0 : 0] c0_ddr4_ck_c, output [0 : 0] c0_ddr4_ck_t ); @@ -188,6 +189,7 @@ module fpgaTop wire s00_axi_aclk; wire s00_axi_aresetn; + wire [3:0] s00_axi_awid; wire [31:0]s00_axi_awaddr; wire [7:0]s00_axi_awlen; wire [2:0]s00_axi_awsize; @@ -244,11 +246,9 @@ module fpgaTop wire s01_axi_wlast; wire s01_axi_wvalid; wire s01_axi_wready; - wire [3:0]m01_axi_bid; wire [1:0]s01_axi_bresp; wire s01_axi_bvalid; wire s01_axi_bready; - wire [3:0]m01_axi_bid; wire [31:0]s01_axi_araddr; wire [7:0]s01_axi_arlen; wire [2:0]s01_axi_arsize; @@ -260,7 +260,6 @@ module fpgaTop wire [3:0]s01_axi_arqos; // wire s01_axi_arvalid; wire s01_axi_arready; - wire [3:0]m01_axi_rid; wire [63:0]s01_axi_rdata; wire [1:0]s01_axi_rresp; wire s01_axi_rlast; @@ -376,7 +375,7 @@ module fpgaTop wire [3:0]m01_axi_awqos; wire m01_axi_awvalid; wire m01_axi_awready; - wire [31:0]m01_axi_wdata; + wire [63:0]m01_axi_wdata; wire [3:0]m01_axi_wstrb; wire m01_axi_wlast; wire m01_axi_wvalid; @@ -398,7 +397,7 @@ module fpgaTop wire m01_axi_arvalid; wire m01_axi_arready; wire [3:0] m01_axi_rid; - wire [31:0]m01_axi_rdata; + wire [63:0]m01_axi_rdata; wire [1:0]m01_axi_rresp; wire m01_axi_rlast; wire m01_axi_rvalid; @@ -409,13 +408,13 @@ module fpgaTop // New SDC Command IOBUF connections wire sd_cmd_i; - reg sd_cmd_reg_o; - reg sd_cmd_reg_t; + wire sd_cmd_reg_o; + wire sd_cmd_reg_t; // New SDC Data IOBUF connections wire [3:0] sd_dat_i; - reg [3:0] sd_dat_reg_o; - reg sd_dat_reg_t; + wire [3:0] sd_dat_reg_o; + wire sd_dat_reg_t; assign GPIOPinsIn = {28'b0, GPI}; assign GPO = GPIOPinsOut[4:0]; @@ -444,7 +443,7 @@ module fpgaTop */ // IOBUFS for new SDC peripheral - IOBUF IOBUF_cmd (.O(sd_cmd_i), .IO(SDCcmd), .I(sd_cmd_reg_o), .T(sd_cmd_reg_t)); + IOBUF IOBUF_cmd (.O(sd_cmd_i), .IO(SDCCmd), .I(sd_cmd_reg_o), .T(sd_cmd_reg_t)); genvar i; generate for (i = 0; i < 4; i = i + 1) begin @@ -502,13 +501,13 @@ module fpgaTop .GPIOPinsEn(GPIOPinsEn), // UART .UARTSin(UARTSin), - .UARTSout(UARTSout), + .UARTSout(UARTSout) // SD Card - .SDCDatIn(SDCDatIn), + /*.SDCDatIn(SDCDatIn), .SDCCmdIn(SDCCmdIn), .SDCCmdOut(SDCCmdOut), .SDCCmdOE(SDCCmdOE), - .SDCCLK(SDCCLK)); + .SDCCLK(SDCCLK));*/ // ahb lite to axi bridge xlnx_ahblite_axi_bridge xlnx_ahblite_axi_bridge_0 @@ -568,7 +567,7 @@ module fpgaTop .aresetn(peripheral_aresetn), // Connect Masters - .s_axi_awid({8'b0, m_axi_awid}), + .s_axi_awid({4'b0, m_axi_awid}), .s_axi_awaddr({m01_axi_awaddr, m_axi_awaddr}), .s_axi_awlen({m01_axi_awlen, m_axi_awlen}), .s_axi_awsize({m01_axi_awsize, m_axi_awsize}), @@ -588,7 +587,7 @@ module fpgaTop .s_axi_bresp({m01_axi_bresp, m_axi_bresp}), .s_axi_bvalid({m01_axi_bvalid, m_axi_bvalid}), .s_axi_bready({m01_axi_bready, m_axi_bready}), - .s_axi_arid({8'b0, m_axi_arid}), + .s_axi_arid({4'b0, m_axi_arid}), .s_axi_araddr({m01_axi_araddr, m_axi_araddr}), .s_axi_arlen({m01_axi_arlen, m_axi_arlen}), .s_axi_arsize({m01_axi_arsize, m_axi_arsize}), @@ -624,7 +623,7 @@ module fpgaTop .m_axi_wlast({s01_axi_wlast, s00_axi_wlast}), .m_axi_wvalid({s01_axi_wvalid, s00_axi_wvalid}), .m_axi_wready({s01_axi_wready, s00_axi_wready}), - .m_axi_bid({8'b0, s00_axi_bid}), + .m_axi_bid({4'b0, s00_axi_bid}), .m_axi_bresp({s01_axi_bresp, s00_axi_bresp}), .m_axi_bvalid({s01_axi_bvalid, s00_axi_bvalid}), .m_axi_bready({s01_axi_bready, s00_axi_bready}), @@ -640,7 +639,7 @@ module fpgaTop .m_axi_araddr({s01_axi_araddr, s00_axi_araddr}), .m_axi_arlock({s01_axi_arlock, s00_axi_arlock}), .m_axi_arready({s01_axi_arready, s00_axi_arready}), - .m_axi_rid({8'b0, s00_axi_rid}), + .m_axi_rid({4'b0, s00_axi_rid}), .m_axi_rdata({s01_axi_rdata, s00_axi_rdata}), .m_axi_rresp({s01_axi_rresp, s00_axi_rresp}), .m_axi_rvalid({s01_axi_rvalid, s00_axi_rvalid}), @@ -856,7 +855,10 @@ module fpgaTop .sd_cmd_reg_t(sd_cmd_reg_t), .sd_cmd_reg_o(sd_cmd_reg_o), - .sd_cmd_i(sd_cmd_i) + .sd_cmd_i(sd_cmd_i), + + .sdio_clk(SDCCLK), + .sdio_cd(SDCCD) ); xlnx_axi_dwidth_conv_32to64 axi_conv_up diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv index 532efe069..845a96c14 100644 --- a/src/uncore/uncore.sv +++ b/src/uncore/uncore.sv @@ -57,11 +57,11 @@ module uncore ( output logic [31:0] GPIOPinsOut, GPIOPinsEn, // GPIO pin output value and enable input logic UARTSin, // UART serial input output logic UARTSout, // UART serial output - output logic SDCCmdOut, // SD Card command output + /*output logic SDCCmdOut, // SD Card command output output logic SDCCmdOE, // SD Card command output enable input logic SDCCmdIn, // SD Card command input input logic [3:0] SDCDatIn, // SD Card data input - output logic SDCCLK // SD Card clock + output logic SDCCLK // SD Card clock*/ ); logic [`XLEN-1:0] HREADRam, HREADSDC; @@ -158,10 +158,10 @@ module uncore ( // interrupt to PLIC .SDCIntM ); - end else begin : sdc + /*end else begin : sdc assign SDCCLK = 0; assign SDCCmdOut = 0; - assign SDCCmdOE = 0; + assign SDCCmdOE = 0;*/ end // AHB Read Multiplexer diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv index e4c461571..92dded7ad 100644 --- a/src/wally/wallypipelinedsoc.sv +++ b/src/wally/wallypipelinedsoc.sv @@ -56,11 +56,11 @@ module wallypipelinedsoc ( output logic [31:0] GPIOPinsEn, // output enables for GPIO input logic UARTSin, // UART serial data input output logic UARTSout, // UART serial data output - input logic SDCCmdIn, // SDC Command input + /*input logic SDCCmdIn, // SDC Command input output logic SDCCmdOut, // SDC Command output output logic SDCCmdOE, // SDC Command output enable input logic [3:0] SDCDatIn, // SDC data input - output logic SDCCLK // SDC clock + output logic SDCCLK // SDC clock*/ ); // Uncore signals @@ -87,7 +87,7 @@ module wallypipelinedsoc ( .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT, - .SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK); + /*.SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK*/); end endmodule diff --git a/tests/custom/boot/bios.s b/tests/custom/boot/bios.s new file mode 100644 index 000000000..8057a277d --- /dev/null +++ b/tests/custom/boot/bios.s @@ -0,0 +1,101 @@ +PERIOD = 11000000 +#PERIOD = 20 + +.section .init +.global _start +.type _start, @function + + +_start: + # Initialize global pointer + .option push + .option norelax + 1:auipc gp, %pcrel_hi(__global_pointer$) + addi gp, gp, %pcrel_lo(1b) + .option pop + + li x1, 0 + li x2, 0 + li x4, 0 + li x5, 0 + li x6, 0 + li x7, 0 + li x8, 0 + li x9, 0 + li x10, 0 + li x11, 0 + li x12, 0 + li x13, 0 + li x14, 0 + li x15, 0 + li x16, 0 + li x17, 0 + li x18, 0 + li x19, 0 + li x20, 0 + li x21, 0 + li x22, 0 + li x23, 0 + li x24, 0 + li x25, 0 + li x26, 0 + li x27, 0 + li x28, 0 + li x29, 0 + li x30, 0 + li x31, 0 + + + # set the stack pointer to the top of memory - 8 bytes (pointer size) + li sp, 0x87FFFFF8 + + li a0, 0x00000000 + li a1, 0x80000000 + #li a2, 128*1024*1024/512 # copy 128MB + li a2, 127*1024*1024/512 # copy 127MB upper 1MB contains the return address (ra) + #li a2, 800 # copy 400KB + jal ra, copyFlash + + fence.i + # now toggle led so we know the copy completed. + + # write to gpio + li t2, 0xFF + la t3, 0x1006000C + li t4, 5 + +loop: + + # delay + li t0, PERIOD/2 +delay1: + addi t0, t0, -1 + bge t0, x0, delay1 + sw t2, 0x0(t3) + + li t0, PERIOD/2 +delay2: + addi t0, t0, -1 + bge t0, x0, delay2 + sw x0, 0x0(t3) + + addi t4, t4, -1 + bgt t4, x0, loop + + + # now that the card is copied and the led toggled we + # jump to the copied contents of the sd card. + +jumpToLinux: + csrrs a0, 0xF14, x0 # copy hard ID to a0 + li a1, 0x87000000 # end of memory? not 100% sure on this but it's 112MB + la a2, end_of_bios + li t0, 0x80000000 # start of code + + jalr x0, t0, 0 + +end_of_bios: + + + + diff --git a/tests/custom/boot/boot.c b/tests/custom/boot/boot.c index 9f4eaa6f9..f9fa2c0fe 100644 --- a/tests/custom/boot/boot.c +++ b/tests/custom/boot/boot.c @@ -121,25 +121,6 @@ static int alt_mem __attribute__((section(".bss"))); static const char * errno_to_str(void) { switch (errno) { - case FR_OK: return "No error"; - case FR_DISK_ERR: return "Disk I/O error"; - case FR_INT_ERR: return "Assertion failed"; - case FR_NOT_READY: return "Disk not ready"; - case FR_NO_FILE: return "File not found"; - case FR_NO_PATH: return "Path not found"; - case FR_INVALID_NAME: return "Invalid path"; - case FR_DENIED: return "Access denied"; - case FR_EXIST: return "Already exist"; - case FR_INVALID_OBJECT: return "The FS object is invalid"; - case FR_WRITE_PROTECTED: return "The drive is write protected"; - case FR_INVALID_DRIVE: return "The drive number is invalid"; - case FR_NOT_ENABLED: return "The volume has no work area"; - case FR_NO_FILESYSTEM: return "Not a valid FAT volume"; - case FR_MKFS_ABORTED: return "The f_mkfs() aborted"; - case FR_TIMEOUT: return "Timeout"; - case FR_LOCKED: return "Locked"; - case FR_NOT_ENOUGH_CORE: return "Not enough memory"; - case FR_TOO_MANY_OPEN_FILES: return "Too many open files"; case ERR_EOF: return "Unexpected EOF"; case ERR_NOT_ELF: return "Not an ELF file"; case ERR_ELF_BITS: return "Wrong ELF word size"; From b796b1b4929786558a1ae3e58108ea7f1c9004b9 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Thu, 6 Apr 2023 16:01:58 -0500 Subject: [PATCH 18/22] Build doesn't work. AXI Crossbar has problems. --- fpga/constraints/debug2.xdc | 193 +----- fpga/src/fpgaTop.v | 84 +-- .../src/uncore/newsdc/axi_sdc_controller.v | 40 +- src/generic/mem/rom1p1r.sv | 646 +++++++++++++++++- src/uncore/uncore.sv | 10 +- src/wally/wallypipelinedsoc.sv | 4 +- tests/custom/boot/Makefile | 4 +- tests/custom/boot/boot.c | 18 +- tests/custom/boot/boot.h | 5 +- 9 files changed, 773 insertions(+), 231 deletions(-) diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 71e45611e..13733e579 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -926,212 +926,93 @@ set_property port_width 1 [get_debug_ports u_ila_0/probe173] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe173] connect_debug_port u_ila_0/probe173 [get_nets [list {m_axi_rready}]] - +# ============== AXI SDC STUFF ================ create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe174] +set_property port_width 1 [get_debug_ports u_ila_0/probe174] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe174] -connect_debug_port u_ila_0/probe174 [get_nets [list {BUS_axi_awid[0]} {BUS_axi_awid[1]} {BUS_axi_awid[2]} {BUS_axi_awid[3]} ]] - +connect_debug_port u_ila_0/probe174 [get_nets [list {axiSDC/clock_posedge}]] create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe175] +set_property port_width 32 [get_debug_ports u_ila_0/probe175] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe175] -connect_debug_port u_ila_0/probe175 [get_nets [list {BUS_axi_awlen[0]} {BUS_axi_awlen[1]} {BUS_axi_awlen[2]} {BUS_axi_awlen[3]} {BUS_axi_awlen[4]} {BUS_axi_awlen[5]} {BUS_axi_awlen[6]} {BUS_axi_awlen[7]} ]] - +connect_debug_port u_ila_0/probe175 [get_nets [list {axiSDC/argument_reg[0]} {axiSDC/argument_reg[1]} {axiSDC/argument_reg[2]} {axiSDC/argument_reg[3]} {axiSDC/argument_reg[4]} {axiSDC/argument_reg[5]} {axiSDC/argument_reg[6]} {axiSDC/argument_reg[7]} {axiSDC/argument_reg[8]} {axiSDC/argument_reg[9]} {axiSDC/argument_reg[10]} {axiSDC/argument_reg[11]} {axiSDC/argument_reg[12]} {axiSDC/argument_reg[13]} {axiSDC/argument_reg[14]} {axiSDC/argument_reg[15]} {axiSDC/argument_reg[16]} {axiSDC/argument_reg[17]} {axiSDC/argument_reg[18]} {axiSDC/argument_reg[19]} {axiSDC/argument_reg[20]} {axiSDC/argument_reg[21]} {axiSDC/argument_reg[22]} {axiSDC/argument_reg[23]} {axiSDC/argument_reg[24]} {axiSDC/argument_reg[25]} {axiSDC/argument_reg[26]} {axiSDC/argument_reg[27]} {axiSDC/argument_reg[28]} {axiSDC/argument_reg[29]} {axiSDC/argument_reg[30]} {axiSDC/argument_reg[31]} ]] create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe176] +set_property port_width 25 [get_debug_ports u_ila_0/probe176] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe176] -connect_debug_port u_ila_0/probe176 [get_nets [list {BUS_axi_awsize[0]} {BUS_axi_awsize[1]} {BUS_axi_awsize[2]} ]] - +connect_debug_port u_ila_0/probe176 [get_nets [list {axiSDC/cmd_timeout_reg[0]} {axiSDC/cmd_timeout_reg[1]} {axiSDC/cmd_timeout_reg[2]} {axiSDC/cmd_timeout_reg[3]} {axiSDC/cmd_timeout_reg[4]} {axiSDC/cmd_timeout_reg[5]} {axiSDC/cmd_timeout_reg[6]} {axiSDC/cmd_timeout_reg[7]} {axiSDC/cmd_timeout_reg[8]} {axiSDC/cmd_timeout_reg[9]} {axiSDC/cmd_timeout_reg[10]} {axiSDC/cmd_timeout_reg[11]} {axiSDC/cmd_timeout_reg[12]} {axiSDC/cmd_timeout_reg[13]} {axiSDC/cmd_timeout_reg[14]} {axiSDC/cmd_timeout_reg[15]} {axiSDC/cmd_timeout_reg[16]} {axiSDC/cmd_timeout_reg[17]} {axiSDC/cmd_timeout_reg[18]} {axiSDC/cmd_timeout_reg[19]} {axiSDC/cmd_timeout_reg[20]} {axiSDC/cmd_timeout_reg[21]} {axiSDC/cmd_timeout_reg[22]} {axiSDC/cmd_timeout_reg[23]} {axiSDC/cmd_timeout_reg[24]} ]] create_debug_port u_ila_0 probe -set_property port_width 2 [get_debug_ports u_ila_0/probe177] +set_property port_width 28 [get_debug_ports u_ila_0/probe177] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe177] -connect_debug_port u_ila_0/probe177 [get_nets [list {BUS_axi_awburst[0]} {BUS_axi_awburst[1]} ]] - +connect_debug_port u_ila_0/probe177 [get_nets [list {axiSDC/data_timeout_reg[0]} {axiSDC/data_timeout_reg[1]} {axiSDC/data_timeout_reg[2]} {axiSDC/data_timeout_reg[3]} {axiSDC/data_timeout_reg[4]} {axiSDC/data_timeout_reg[5]} {axiSDC/data_timeout_reg[6]} {axiSDC/data_timeout_reg[7]} {axiSDC/data_timeout_reg[8]} {axiSDC/data_timeout_reg[9]} {axiSDC/data_timeout_reg[10]} {axiSDC/data_timeout_reg[11]} {axiSDC/data_timeout_reg[12]} {axiSDC/data_timeout_reg[13]} {axiSDC/data_timeout_reg[14]} {axiSDC/data_timeout_reg[15]} {axiSDC/data_timeout_reg[16]} {axiSDC/data_timeout_reg[17]} {axiSDC/data_timeout_reg[18]} {axiSDC/data_timeout_reg[19]} {axiSDC/data_timeout_reg[20]} {axiSDC/data_timeout_reg[21]} {axiSDC/data_timeout_reg[22]} {axiSDC/data_timeout_reg[23]} {axiSDC/data_timeout_reg[24]} {axiSDC/data_timeout_reg[25]} {axiSDC/data_timeout_reg[26]} {axiSDC/data_timeout_reg[27]} ]] create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe178] +set_property port_width 1 [get_debug_ports u_ila_0/probe178] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe178] -connect_debug_port u_ila_0/probe178 [get_nets [list {BUS_axi_awcache[0]} {BUS_axi_awcache[1]} {BUS_axi_awcache[2]} {BUS_axi_awcache[3]} ]] - +connect_debug_port u_ila_0/probe178 [get_nets [list {axiSDC/software_reset_reg}]] create_debug_port u_ila_0 probe -set_property port_width 31 [get_debug_ports u_ila_0/probe179] +set_property port_width 32 [get_debug_ports u_ila_0/probe179] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe179] -connect_debug_port u_ila_0/probe179 [get_nets [list {BUS_axi_awaddr[0]} {BUS_axi_awaddr[1]} {BUS_axi_awaddr[2]} {BUS_axi_awaddr[3]} {BUS_axi_awaddr[4]} {BUS_axi_awaddr[5]} {BUS_axi_awaddr[6]} {BUS_axi_awaddr[7]} {BUS_axi_awaddr[8]} {BUS_axi_awaddr[9]} {BUS_axi_awaddr[10]} {BUS_axi_awaddr[11]} {BUS_axi_awaddr[12]} {BUS_axi_awaddr[13]} {BUS_axi_awaddr[14]} {BUS_axi_awaddr[15]} {BUS_axi_awaddr[16]} {BUS_axi_awaddr[17]} {BUS_axi_awaddr[18]} {BUS_axi_awaddr[19]} {BUS_axi_awaddr[20]} {BUS_axi_awaddr[21]} {BUS_axi_awaddr[22]} {BUS_axi_awaddr[23]} {BUS_axi_awaddr[24]} {BUS_axi_awaddr[25]} {BUS_axi_awaddr[26]} {BUS_axi_awaddr[27]} {BUS_axi_awaddr[28]} {BUS_axi_awaddr[29]} {BUS_axi_awaddr[30]} ]] - +connect_debug_port u_ila_0/probe179 [get_nets [list {axiSDC/response_0_reg[0]} {axiSDC/response_0_reg[1]} {axiSDC/response_0_reg[2]} {axiSDC/response_0_reg[3]} {axiSDC/response_0_reg[4]} {axiSDC/response_0_reg[5]} {axiSDC/response_0_reg[6]} {axiSDC/response_0_reg[7]} {axiSDC/response_0_reg[8]} {axiSDC/response_0_reg[9]} {axiSDC/response_0_reg[10]} {axiSDC/response_0_reg[11]} {axiSDC/response_0_reg[12]} {axiSDC/response_0_reg[13]} {axiSDC/response_0_reg[14]} {axiSDC/response_0_reg[15]} {axiSDC/response_0_reg[16]} {axiSDC/response_0_reg[17]} {axiSDC/response_0_reg[18]} {axiSDC/response_0_reg[19]} {axiSDC/response_0_reg[20]} {axiSDC/response_0_reg[21]} {axiSDC/response_0_reg[22]} {axiSDC/response_0_reg[23]} {axiSDC/response_0_reg[24]} {axiSDC/response_0_reg[25]} {axiSDC/response_0_reg[26]} {axiSDC/response_0_reg[27]} {axiSDC/response_0_reg[28]} {axiSDC/response_0_reg[29]} {axiSDC/response_0_reg[30]} {axiSDC/response_0_reg[31]} ]] create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe180] +set_property port_width 32 [get_debug_ports u_ila_0/probe180] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe180] -connect_debug_port u_ila_0/probe180 [get_nets [list {BUS_axi_awprot[0]} {BUS_axi_awprot[1]} {BUS_axi_awprot[2]} ]] - +connect_debug_port u_ila_0/probe180 [get_nets [list {axiSDC/response_1_reg[0]} {axiSDC/response_1_reg[1]} {axiSDC/response_1_reg[2]} {axiSDC/response_1_reg[3]} {axiSDC/response_1_reg[4]} {axiSDC/response_1_reg[5]} {axiSDC/response_1_reg[6]} {axiSDC/response_1_reg[7]} {axiSDC/response_1_reg[8]} {axiSDC/response_1_reg[9]} {axiSDC/response_1_reg[10]} {axiSDC/response_1_reg[11]} {axiSDC/response_1_reg[12]} {axiSDC/response_1_reg[13]} {axiSDC/response_1_reg[14]} {axiSDC/response_1_reg[15]} {axiSDC/response_1_reg[16]} {axiSDC/response_1_reg[17]} {axiSDC/response_1_reg[18]} {axiSDC/response_1_reg[19]} {axiSDC/response_1_reg[20]} {axiSDC/response_1_reg[21]} {axiSDC/response_1_reg[22]} {axiSDC/response_1_reg[23]} {axiSDC/response_1_reg[24]} {axiSDC/response_1_reg[25]} {axiSDC/response_1_reg[26]} {axiSDC/response_1_reg[27]} {axiSDC/response_1_reg[28]} {axiSDC/response_1_reg[29]} {axiSDC/response_1_reg[30]} {axiSDC/response_1_reg[31]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe181] +set_property port_width 32 [get_debug_ports u_ila_0/probe181] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe181] -connect_debug_port u_ila_0/probe181 [get_nets [list {BUS_axi_awvalid}]] - +connect_debug_port u_ila_0/probe181 [get_nets [list {axiSDC/response_2_reg[0]} {axiSDC/response_2_reg[1]} {axiSDC/response_2_reg[2]} {axiSDC/response_2_reg[3]} {axiSDC/response_2_reg[4]} {axiSDC/response_2_reg[5]} {axiSDC/response_2_reg[6]} {axiSDC/response_2_reg[7]} {axiSDC/response_2_reg[8]} {axiSDC/response_2_reg[9]} {axiSDC/response_2_reg[10]} {axiSDC/response_2_reg[11]} {axiSDC/response_2_reg[12]} {axiSDC/response_2_reg[13]} {axiSDC/response_2_reg[14]} {axiSDC/response_2_reg[15]} {axiSDC/response_2_reg[16]} {axiSDC/response_2_reg[17]} {axiSDC/response_2_reg[18]} {axiSDC/response_2_reg[19]} {axiSDC/response_2_reg[20]} {axiSDC/response_2_reg[21]} {axiSDC/response_2_reg[22]} {axiSDC/response_2_reg[23]} {axiSDC/response_2_reg[24]} {axiSDC/response_2_reg[25]} {axiSDC/response_2_reg[26]} {axiSDC/response_2_reg[27]} {axiSDC/response_2_reg[28]} {axiSDC/response_2_reg[29]} {axiSDC/response_2_reg[30]} {axiSDC/response_2_reg[31]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe182] +set_property port_width 32 [get_debug_ports u_ila_0/probe182] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe182] -connect_debug_port u_ila_0/probe182 [get_nets [list {BUS_axi_awready}]] - +connect_debug_port u_ila_0/probe182 [get_nets [list {axiSDC/dma_addr_reg[0]} {axiSDC/dma_addr_reg[1]} {axiSDC/dma_addr_reg[2]} {axiSDC/dma_addr_reg[3]} {axiSDC/dma_addr_reg[4]} {axiSDC/dma_addr_reg[5]} {axiSDC/dma_addr_reg[6]} {axiSDC/dma_addr_reg[7]} {axiSDC/dma_addr_reg[8]} {axiSDC/dma_addr_reg[9]} {axiSDC/dma_addr_reg[10]} {axiSDC/dma_addr_reg[11]} {axiSDC/dma_addr_reg[12]} {axiSDC/dma_addr_reg[13]} {axiSDC/dma_addr_reg[14]} {axiSDC/dma_addr_reg[15]} {axiSDC/dma_addr_reg[16]} {axiSDC/dma_addr_reg[17]} {axiSDC/dma_addr_reg[18]} {axiSDC/dma_addr_reg[19]} {axiSDC/dma_addr_reg[20]} {axiSDC/dma_addr_reg[21]} {axiSDC/dma_addr_reg[22]} {axiSDC/dma_addr_reg[23]} {axiSDC/dma_addr_reg[24]} {axiSDC/dma_addr_reg[25]} {axiSDC/dma_addr_reg[26]} {axiSDC/dma_addr_reg[27]} {axiSDC/dma_addr_reg[28]} {axiSDC/dma_addr_reg[29]} {axiSDC/dma_addr_reg[30]} {axiSDC/dma_addr_reg[31]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe183] +set_property port_width 12 [get_debug_ports u_ila_0/probe183] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe183] -connect_debug_port u_ila_0/probe183 [get_nets [list {BUS_axi_awlock}]] - +connect_debug_port u_ila_0/probe183 [get_nets [list {axiSDC/block_size_reg[0]} {axiSDC/block_size_reg[1]} {axiSDC/block_size_reg[2]} {axiSDC/block_size_reg[3]} {axiSDC/block_size_reg[4]} {axiSDC/block_size_reg[5]} {axiSDC/block_size_reg[6]} {axiSDC/block_size_reg[7]} {axiSDC/block_size_reg[8]} {axiSDC/block_size_reg[9]} {axiSDC/block_size_reg[10]} {axiSDC/block_size_reg[11]} ]] create_debug_port u_ila_0 probe -set_property port_width 64 [get_debug_ports u_ila_0/probe184] +set_property port_width 2 [get_debug_ports u_ila_0/probe184] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe184] -connect_debug_port u_ila_0/probe184 [get_nets [list {BUS_axi_wdata[0]} {BUS_axi_wdata[1]} {BUS_axi_wdata[2]} {BUS_axi_wdata[3]} {BUS_axi_wdata[4]} {BUS_axi_wdata[5]} {BUS_axi_wdata[6]} {BUS_axi_wdata[7]} {BUS_axi_wdata[8]} {BUS_axi_wdata[9]} {BUS_axi_wdata[10]} {BUS_axi_wdata[11]} {BUS_axi_wdata[12]} {BUS_axi_wdata[13]} {BUS_axi_wdata[14]} {BUS_axi_wdata[15]} {BUS_axi_wdata[16]} {BUS_axi_wdata[17]} {BUS_axi_wdata[18]} {BUS_axi_wdata[19]} {BUS_axi_wdata[20]} {BUS_axi_wdata[21]} {BUS_axi_wdata[22]} {BUS_axi_wdata[23]} {BUS_axi_wdata[24]} {BUS_axi_wdata[25]} {BUS_axi_wdata[26]} {BUS_axi_wdata[27]} {BUS_axi_wdata[28]} {BUS_axi_wdata[29]} {BUS_axi_wdata[30]} {BUS_axi_wdata[31]} {BUS_axi_wdata[32]} {BUS_axi_wdata[33]} {BUS_axi_wdata[34]} {BUS_axi_wdata[35]} {BUS_axi_wdata[36]} {BUS_axi_wdata[37]} {BUS_axi_wdata[38]} {BUS_axi_wdata[39]} {BUS_axi_wdata[40]} {BUS_axi_wdata[41]} {BUS_axi_wdata[42]} {BUS_axi_wdata[43]} {BUS_axi_wdata[44]} {BUS_axi_wdata[45]} {BUS_axi_wdata[46]} {BUS_axi_wdata[47]} {BUS_axi_wdata[48]} {BUS_axi_wdata[49]} {BUS_axi_wdata[50]} {BUS_axi_wdata[51]} {BUS_axi_wdata[52]} {BUS_axi_wdata[53]} {BUS_axi_wdata[54]} {BUS_axi_wdata[55]} {BUS_axi_wdata[56]} {BUS_axi_wdata[57]} {BUS_axi_wdata[58]} {BUS_axi_wdata[59]} {BUS_axi_wdata[60]} {BUS_axi_wdata[61]} {BUS_axi_wdata[62]} {BUS_axi_wdata[63]} ]] - +connect_debug_port u_ila_0/probe184 [get_nets [list {axiSDC/controller_setting_reg[0]} {axiSDC/controller_setting_reg[1]} ]] create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe185] +set_property port_width 5 [get_debug_ports u_ila_0/probe185] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe185] -connect_debug_port u_ila_0/probe185 [get_nets [list {BUS_axi_wstrb[0]} {BUS_axi_wstrb[1]} {BUS_axi_wstrb[2]} {BUS_axi_wstrb[3]} {BUS_axi_wstrb[4]} {BUS_axi_wstrb[5]} {BUS_axi_wstrb[6]} {BUS_axi_wstrb[7]} ]] - +connect_debug_port u_ila_0/probe185 [get_nets [list {axiSDC/cmd_int_status_reg[0]} {axiSDC/cmd_int_status_reg[1]} {axiSDC/cmd_int_status_reg[2]} {axiSDC/cmd_int_status_reg[3]} {axiSDC/cmd_int_status_reg[4]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe186] +set_property port_width 6 [get_debug_ports u_ila_0/probe186] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe186] -connect_debug_port u_ila_0/probe186 [get_nets [list {BUS_axi_wlast}]] - +connect_debug_port u_ila_0/probe186 [get_nets [list {axiSDC/data_int_status_reg[0]} {axiSDC/data_int_status_reg[1]} {axiSDC/data_int_status_reg[2]} {axiSDC/data_int_status_reg[3]} {axiSDC/data_int_status_reg[4]} {axiSDC/data_int_status_reg[5]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe187] +set_property port_width 6 [get_debug_ports u_ila_0/probe187] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe187] -connect_debug_port u_ila_0/probe187 [get_nets [list {BUS_axi_wvalid}]] - +connect_debug_port u_ila_0/probe187 [get_nets [list {axiSDC/data_int_status[0]} {axiSDC/data_int_status[1]} {axiSDC/data_int_status[2]} {axiSDC/data_int_status[3]} {axiSDC/data_int_status[4]} {axiSDC/data_int_status[5]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe188] +set_property port_width 5 [get_debug_ports u_ila_0/probe188] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe188] -connect_debug_port u_ila_0/probe188 [get_nets [list {BUS_axi_wready}]] - +connect_debug_port u_ila_0/probe188 [get_nets [list {axiSDC/cmd_int_enable_reg[0]} {axiSDC/cmd_int_enable_reg[1]} {axiSDC/cmd_int_enable_reg[2]} {axiSDC/cmd_int_enable_reg[3]} {axiSDC/cmd_int_enable_reg[4]} ]] create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe189] +set_property port_width 6 [get_debug_ports u_ila_0/probe189] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe189] -connect_debug_port u_ila_0/probe189 [get_nets [list {BUS_axi_bid[0]} {BUS_axi_bid[1]} {BUS_axi_bid[2]} {BUS_axi_bid[3]} ]] - +connect_debug_port u_ila_0/probe189 [get_nets [list {axiSDC/data_int_enable_reg[0]} {axiSDC/data_int_enable_reg[1]} {axiSDC/data_int_enable_reg[2]} {axiSDC/data_int_enable_reg[3]} {axiSDC/data_int_enable_reg[4]} {axiSDC/data_int_enable_reg[5]} ]] create_debug_port u_ila_0 probe -set_property port_width 2 [get_debug_ports u_ila_0/probe190] +set_property port_width 16 [get_debug_ports u_ila_0/probe190] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe190] -connect_debug_port u_ila_0/probe190 [get_nets [list {BUS_axi_bresp[0]} {BUS_axi_bresp[1]} ]] - +connect_debug_port u_ila_0/probe190 [get_nets [list {axiSDC/block_count_reg[0]} {axiSDC/block_count_reg[1]} {axiSDC/block_count_reg[2]} {axiSDC/block_count_reg[3]} {axiSDC/block_count_reg[4]} {axiSDC/block_count_reg[5]} {axiSDC/block_count_reg[6]} {axiSDC/block_count_reg[7]} {axiSDC/block_count_reg[8]} {axiSDC/block_count_reg[9]} {axiSDC/block_count_reg[10]} {axiSDC/block_count_reg[11]} {axiSDC/block_count_reg[12]} {axiSDC/block_count_reg[13]} {axiSDC/block_count_reg[14]} {axiSDC/block_count_reg[15]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe191] +set_property port_width 8 [get_debug_ports u_ila_0/probe191] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe191] -connect_debug_port u_ila_0/probe191 [get_nets [list {BUS_axi_bvalid}]] - - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe192] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe192] -connect_debug_port u_ila_0/probe192 [get_nets [list {BUS_axi_bready}]] - - -create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe193] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe193] -connect_debug_port u_ila_0/probe193 [get_nets [list {BUS_axi_arid[0]} {BUS_axi_arid[1]} {BUS_axi_arid[2]} {BUS_axi_arid[3]} ]] - - -create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe194] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe194] -connect_debug_port u_ila_0/probe194 [get_nets [list {BUS_axi_arlen[0]} {BUS_axi_arlen[1]} {BUS_axi_arlen[2]} {BUS_axi_arlen[3]} {BUS_axi_arlen[4]} {BUS_axi_arlen[5]} {BUS_axi_arlen[6]} {BUS_axi_arlen[7]} ]] - - -create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe195] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe195] -connect_debug_port u_ila_0/probe195 [get_nets [list {BUS_axi_arsize[0]} {BUS_axi_arsize[1]} {BUS_axi_arsize[2]} ]] - - -create_debug_port u_ila_0 probe -set_property port_width 2 [get_debug_ports u_ila_0/probe196] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe196] -connect_debug_port u_ila_0/probe196 [get_nets [list {BUS_axi_arburst[0]} {BUS_axi_arburst[1]} ]] - - -create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe197] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe197] -connect_debug_port u_ila_0/probe197 [get_nets [list {BUS_axi_arprot[0]} {BUS_axi_arprot[1]} {BUS_axi_arprot[2]} ]] - - -create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe198] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe198] -connect_debug_port u_ila_0/probe198 [get_nets [list {BUS_axi_arcache[0]} {BUS_axi_arcache[1]} {BUS_axi_arcache[2]} {BUS_axi_arcache[3]} ]] - - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe199] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe199] -connect_debug_port u_ila_0/probe199 [get_nets [list {BUS_axi_arvalid}]] - - -create_debug_port u_ila_0 probe -set_property port_width 31 [get_debug_ports u_ila_0/probe200] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe200] -connect_debug_port u_ila_0/probe200 [get_nets [list {BUS_axi_araddr[0]} {BUS_axi_araddr[1]} {BUS_axi_araddr[2]} {BUS_axi_araddr[3]} {BUS_axi_araddr[4]} {BUS_axi_araddr[5]} {BUS_axi_araddr[6]} {BUS_axi_araddr[7]} {BUS_axi_araddr[8]} {BUS_axi_araddr[9]} {BUS_axi_araddr[10]} {BUS_axi_araddr[11]} {BUS_axi_araddr[12]} {BUS_axi_araddr[13]} {BUS_axi_araddr[14]} {BUS_axi_araddr[15]} {BUS_axi_araddr[16]} {BUS_axi_araddr[17]} {BUS_axi_araddr[18]} {BUS_axi_araddr[19]} {BUS_axi_araddr[20]} {BUS_axi_araddr[21]} {BUS_axi_araddr[22]} {BUS_axi_araddr[23]} {BUS_axi_araddr[24]} {BUS_axi_araddr[25]} {BUS_axi_araddr[26]} {BUS_axi_araddr[27]} {BUS_axi_araddr[28]} {BUS_axi_araddr[29]} {BUS_axi_araddr[30]} ]] - - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe201] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe201] -connect_debug_port u_ila_0/probe201 [get_nets [list {BUS_axi_arlock}]] - - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe202] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe202] -connect_debug_port u_ila_0/probe202 [get_nets [list {BUS_axi_arready}]] - - -create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe203] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe203] -connect_debug_port u_ila_0/probe203 [get_nets [list {BUS_axi_rid[0]} {BUS_axi_rid[1]} {BUS_axi_rid[2]} {BUS_axi_rid[3]} ]] - - -create_debug_port u_ila_0 probe -set_property port_width 64 [get_debug_ports u_ila_0/probe204] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe204] -connect_debug_port u_ila_0/probe204 [get_nets [list {BUS_axi_rdata[0]} {BUS_axi_rdata[1]} {BUS_axi_rdata[2]} {BUS_axi_rdata[3]} {BUS_axi_rdata[4]} {BUS_axi_rdata[5]} {BUS_axi_rdata[6]} {BUS_axi_rdata[7]} {BUS_axi_rdata[8]} {BUS_axi_rdata[9]} {BUS_axi_rdata[10]} {BUS_axi_rdata[11]} {BUS_axi_rdata[12]} {BUS_axi_rdata[13]} {BUS_axi_rdata[14]} {BUS_axi_rdata[15]} {BUS_axi_rdata[16]} {BUS_axi_rdata[17]} {BUS_axi_rdata[18]} {BUS_axi_rdata[19]} {BUS_axi_rdata[20]} {BUS_axi_rdata[21]} {BUS_axi_rdata[22]} {BUS_axi_rdata[23]} {BUS_axi_rdata[24]} {BUS_axi_rdata[25]} {BUS_axi_rdata[26]} {BUS_axi_rdata[27]} {BUS_axi_rdata[28]} {BUS_axi_rdata[29]} {BUS_axi_rdata[30]} {BUS_axi_rdata[31]} {BUS_axi_rdata[32]} {BUS_axi_rdata[33]} {BUS_axi_rdata[34]} {BUS_axi_rdata[35]} {BUS_axi_rdata[36]} {BUS_axi_rdata[37]} {BUS_axi_rdata[38]} {BUS_axi_rdata[39]} {BUS_axi_rdata[40]} {BUS_axi_rdata[41]} {BUS_axi_rdata[42]} {BUS_axi_rdata[43]} {BUS_axi_rdata[44]} {BUS_axi_rdata[45]} {BUS_axi_rdata[46]} {BUS_axi_rdata[47]} {BUS_axi_rdata[48]} {BUS_axi_rdata[49]} {BUS_axi_rdata[50]} {BUS_axi_rdata[51]} {BUS_axi_rdata[52]} {BUS_axi_rdata[53]} {BUS_axi_rdata[54]} {BUS_axi_rdata[55]} {BUS_axi_rdata[56]} {BUS_axi_rdata[57]} {BUS_axi_rdata[58]} {BUS_axi_rdata[59]} {BUS_axi_rdata[60]} {BUS_axi_rdata[61]} {BUS_axi_rdata[62]} {BUS_axi_rdata[63]} ]] - - -create_debug_port u_ila_0 probe -set_property port_width 2 [get_debug_ports u_ila_0/probe205] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe205] -connect_debug_port u_ila_0/probe205 [get_nets [list {BUS_axi_rresp[0]} {BUS_axi_rresp[1]} ]] - - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe206] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe206] -connect_debug_port u_ila_0/probe206 [get_nets [list {BUS_axi_rvalid}]] - - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe207] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe207] -connect_debug_port u_ila_0/probe207 [get_nets [list {BUS_axi_rlast}]] - - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe208] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe208] -connect_debug_port u_ila_0/probe208 [get_nets [list {BUS_axi_rready}]] +connect_debug_port u_ila_0/probe191 [get_nets [list {axiSDC/clock_divider_reg[0]} {axiSDC/clock_divider_reg[1]} {axiSDC/clock_divider_reg[2]} {axiSDC/clock_divider_reg[3]} {axiSDC/clock_divider_reg[4]} {axiSDC/clock_divider_reg[5]} {axiSDC/clock_divider_reg[6]} {axiSDC/clock_divider_reg[7]} ]] diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index e2eb8441e..03758249e 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -139,41 +139,41 @@ module fpgaTop wire [3:0] BUS_axi_awqos; // Bus signals - (* mark_debug = "true" *) wire [3:0] BUS_axi_awid; - (* mark_debug = "true" *) wire [7:0] BUS_axi_awlen; - (* mark_debug = "true" *) wire [2:0] BUS_axi_awsize; - (* mark_debug = "true" *) wire [1:0] BUS_axi_awburst; - (* mark_debug = "true" *) wire [3:0] BUS_axi_awcache; - (* mark_debug = "true" *) wire [30:0] BUS_axi_awaddr; - (* mark_debug = "true" *) wire [2:0] BUS_axi_awprot; - (* mark_debug = "true" *) wire BUS_axi_awvalid; - (* mark_debug = "true" *) wire BUS_axi_awready; - (* mark_debug = "true" *) wire BUS_axi_awlock; - (* mark_debug = "true" *) wire [63:0] BUS_axi_wdata; - (* mark_debug = "true" *) wire [7:0] BUS_axi_wstrb; - (* mark_debug = "true" *) wire BUS_axi_wlast; - (* mark_debug = "true" *) wire BUS_axi_wvalid; - (* mark_debug = "true" *) wire BUS_axi_wready; - (* mark_debug = "true" *) wire [3:0] BUS_axi_bid; - (* mark_debug = "true" *) wire [1:0] BUS_axi_bresp; - (* mark_debug = "true" *) wire BUS_axi_bvalid; - (* mark_debug = "true" *) wire BUS_axi_bready; - (* mark_debug = "true" *) wire [3:0] BUS_axi_arid; - (* mark_debug = "true" *) wire [7:0] BUS_axi_arlen; - (* mark_debug = "true" *) wire [2:0] BUS_axi_arsize; - (* mark_debug = "true" *) wire [1:0] BUS_axi_arburst; - (* mark_debug = "true" *) wire [2:0] BUS_axi_arprot; - (* mark_debug = "true" *) wire [3:0] BUS_axi_arcache; - (* mark_debug = "true" *) wire BUS_axi_arvalid; - (* mark_debug = "true" *) wire [30:0] BUS_axi_araddr; - (* mark_debug = "true" *) wire BUS_axi_arlock; - (* mark_debug = "true" *) wire BUS_axi_arready; - (* mark_debug = "true" *) wire [3:0] BUS_axi_rid; - (* mark_debug = "true" *) wire [63:0] BUS_axi_rdata; - (* mark_debug = "true" *) wire [1:0] BUS_axi_rresp; - (* mark_debug = "true" *) wire BUS_axi_rvalid; - (* mark_debug = "true" *) wire BUS_axi_rlast; - (* mark_debug = "true" *) wire BUS_axi_rready; + wire [3:0] BUS_axi_awid; + wire [7:0] BUS_axi_awlen; + wire [2:0] BUS_axi_awsize; + wire [1:0] BUS_axi_awburst; + wire [3:0] BUS_axi_awcache; + wire [30:0] BUS_axi_awaddr; + wire [2:0] BUS_axi_awprot; + wire BUS_axi_awvalid; + wire BUS_axi_awready; + wire BUS_axi_awlock; + wire [63:0] BUS_axi_wdata; + wire [7:0] BUS_axi_wstrb; + wire BUS_axi_wlast; + wire BUS_axi_wvalid; + wire BUS_axi_wready; + wire [3:0] BUS_axi_bid; + wire [1:0] BUS_axi_bresp; + wire BUS_axi_bvalid; + wire BUS_axi_bready; + wire [3:0] BUS_axi_arid; + wire [7:0] BUS_axi_arlen; + wire [2:0] BUS_axi_arsize; + wire [1:0] BUS_axi_arburst; + wire [2:0] BUS_axi_arprot; + wire [3:0] BUS_axi_arcache; + wire BUS_axi_arvalid; + wire [30:0] BUS_axi_araddr; + wire BUS_axi_arlock; + wire BUS_axi_arready; + wire [3:0] BUS_axi_rid; + wire [63:0] BUS_axi_rdata; + wire [1:0] BUS_axi_rresp; + wire BUS_axi_rvalid; + wire BUS_axi_rlast; + wire BUS_axi_rready; wire BUSCLK; @@ -225,6 +225,9 @@ module fpgaTop wire s00_axi_rlast; wire s00_axi_rvalid; wire s00_axi_rready; + + wire [3:0] s00_axi_bid; + wire [3:0] s00_axi_rid; // 64to32 dwidth converter input interface------------------------- wire s01_axi_aclk; @@ -508,7 +511,8 @@ module fpgaTop .SDCCmdOut(SDCCmdOut), .SDCCmdOE(SDCCmdOE), .SDCCLK(SDCCLK));*/ - + ); + // ahb lite to axi bridge xlnx_ahblite_axi_bridge xlnx_ahblite_axi_bridge_0 (.s_ahb_hclk(CPUCLK), @@ -567,7 +571,7 @@ module fpgaTop .aresetn(peripheral_aresetn), // Connect Masters - .s_axi_awid({4'b0, m_axi_awid}), + .s_axi_awid({4'b0001, m_axi_awid}), .s_axi_awaddr({m01_axi_awaddr, m_axi_awaddr}), .s_axi_awlen({m01_axi_awlen, m_axi_awlen}), .s_axi_awsize({m01_axi_awsize, m_axi_awsize}), @@ -587,7 +591,7 @@ module fpgaTop .s_axi_bresp({m01_axi_bresp, m_axi_bresp}), .s_axi_bvalid({m01_axi_bvalid, m_axi_bvalid}), .s_axi_bready({m01_axi_bready, m_axi_bready}), - .s_axi_arid({4'b0, m_axi_arid}), + .s_axi_arid({4'b0001, m_axi_arid}), .s_axi_araddr({m01_axi_araddr, m_axi_araddr}), .s_axi_arlen({m01_axi_arlen, m_axi_arlen}), .s_axi_arsize({m01_axi_arsize, m_axi_arsize}), @@ -623,7 +627,7 @@ module fpgaTop .m_axi_wlast({s01_axi_wlast, s00_axi_wlast}), .m_axi_wvalid({s01_axi_wvalid, s00_axi_wvalid}), .m_axi_wready({s01_axi_wready, s00_axi_wready}), - .m_axi_bid({4'b0, s00_axi_bid}), + .m_axi_bid({4'b0001, s00_axi_bid}), .m_axi_bresp({s01_axi_bresp, s00_axi_bresp}), .m_axi_bvalid({s01_axi_bvalid, s00_axi_bvalid}), .m_axi_bready({s01_axi_bready, s00_axi_bready}), @@ -878,7 +882,7 @@ module fpgaTop .s_axi_awvalid(SDCout_axi_awvalid), .s_axi_awready(SDCout_axi_awready), .s_axi_wdata(SDCout_axi_wdata), - .s_axi_wstrb(4'b0), + .s_axi_wstrb(8'b0), .s_axi_wlast(SDCout_axi_wlast), .s_axi_wvalid(SDCout_axi_wvalid), .s_axi_wready(SDCout_axi_wready), diff --git a/pipelined/src/uncore/newsdc/axi_sdc_controller.v b/pipelined/src/uncore/newsdc/axi_sdc_controller.v index d900ddbbd..7e206c676 100644 --- a/pipelined/src/uncore/newsdc/axi_sdc_controller.v +++ b/pipelined/src/uncore/newsdc/axi_sdc_controller.v @@ -175,25 +175,25 @@ reg data_int_rst; reg ctrl_rst; // AXI accessible registers -reg [31:0] argument_reg; -reg [`CMD_REG_SIZE-1:0] command_reg; -reg [`CMD_TIMEOUT_W-1:0] cmd_timeout_reg; -reg [`DATA_TIMEOUT_W-1:0] data_timeout_reg; -reg [0:0] software_reset_reg; -wire [31:0] response_0_reg; -wire [31:0] response_1_reg; -wire [31:0] response_2_reg; -wire [31:0] response_3_reg; -reg [`BLKSIZE_W-1:0] block_size_reg; -reg [1:0] controller_setting_reg; -wire [`INT_CMD_SIZE-1:0] cmd_int_status_reg; -wire [`INT_DATA_SIZE-1:0] data_int_status_reg; -wire [`INT_DATA_SIZE-1:0] data_int_status; -reg [`INT_CMD_SIZE-1:0] cmd_int_enable_reg; -reg [`INT_DATA_SIZE-1:0] data_int_enable_reg; -reg [`BLKCNT_W-1:0] block_count_reg; -reg [dma_addr_bits-1:0] dma_addr_reg; -reg [7:0] clock_divider_reg = 124; // 400KHz +(* mark_debug = "true" *) reg [31:0] argument_reg; +(* mark_debug = "true" *) reg [`CMD_REG_SIZE-1:0] command_reg; +(* mark_debug = "true" *) reg [`CMD_TIMEOUT_W-1:0] cmd_timeout_reg; +(* mark_debug = "true" *) reg [`DATA_TIMEOUT_W-1:0] data_timeout_reg; +(* mark_debug = "true" *) reg [0:0] software_reset_reg; +(* mark_debug = "true" *) wire [31:0] response_0_reg; +(* mark_debug = "true" *) wire [31:0] response_1_reg; +(* mark_debug = "true" *) wire [31:0] response_2_reg; +(* mark_debug = "true" *) wire [31:0] response_3_reg; +(* mark_debug = "true" *) reg [`BLKSIZE_W-1:0] block_size_reg; +(* mark_debug = "true" *) reg [1:0] controller_setting_reg; +(* mark_debug = "true" *) wire [`INT_CMD_SIZE-1:0] cmd_int_status_reg; +(* mark_debug = "true" *) wire [`INT_DATA_SIZE-1:0] data_int_status_reg; +(* mark_debug = "true" *) wire [`INT_DATA_SIZE-1:0] data_int_status; +(* mark_debug = "true" *) reg [`INT_CMD_SIZE-1:0] cmd_int_enable_reg; +(* mark_debug = "true" *) reg [`INT_DATA_SIZE-1:0] data_int_enable_reg; +(* mark_debug = "true" *) reg [`BLKCNT_W-1:0] block_count_reg; +(* mark_debug = "true" *) reg [dma_addr_bits-1:0] dma_addr_reg; +(* mark_debug = "true" *) reg [7:0] clock_divider_reg = 124; // 400KHz // ------ Clocks and resets @@ -206,7 +206,7 @@ always @(posedge clock) reg [7:0] clock_cnt; reg clock_state; -reg clock_posedge; +(* mark_debug = "true" *) reg clock_posedge; reg clock_data_in; wire fifo_almost_full; wire fifo_almost_empty; diff --git a/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv index 64cb9224b..927462c78 100644 --- a/src/generic/mem/rom1p1r.sv +++ b/src/generic/mem/rom1p1r.sv @@ -52,7 +52,7 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, // for FPGA, initialize with zero-stage bootloader if(PRELOAD_ENABLED) begin initial begin - ROM[0] = 64'h9581819300002197; + /*ROM[0] = 64'h9581819300002197; ROM[1] = 64'h4281420141014081; ROM[2] = 64'h4481440143814301; ROM[3] = 64'h4681460145814501; @@ -94,7 +94,649 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, ROM[39] = 64'h1047278367498082; ROM[40] = 64'h47858082dfed8b85; ROM[41] = 64'h40a7853b4015551b; - ROM[42] = 64'h808210a7a02367c9; + ROM[42] = 64'h808210a7a02367c9;*/ + + ROM[0] = 64'hc001819300002197; + ROM[1] = 64'h4281420141014081; + ROM[2] = 64'h4481440143814301; + ROM[3] = 64'h4681460145814501; + ROM[4] = 64'h4881480147814701; + ROM[5] = 64'h4a814a0149814901; + ROM[6] = 64'h4c814c014b814b01; + ROM[7] = 64'h4e814e014d814d01; + ROM[8] = 64'h0110011b4f814f01; + ROM[9] = 64'h059b45011161016e; + ROM[10] = 64'h0004063705fe0010; + ROM[11] = 64'h1ee000ef8006061b; + ROM[12] = 64'h0ff003930000100f; + ROM[13] = 64'h4e952e3110060e37; + ROM[14] = 64'hc602829b0053f2b7; + ROM[15] = 64'h2023fe02dfe312fd; + ROM[16] = 64'h829b0053f2b7007e; + ROM[17] = 64'hfe02dfe312fdc602; + ROM[18] = 64'h4de31efd000e2023; + ROM[19] = 64'h059bf1402573fdd0; + ROM[20] = 64'h0000061705e20870; + ROM[21] = 64'h0010029b01260613; + ROM[22] = 64'h67110002806702fe; + ROM[23] = 64'h0085179bf0070713; + ROM[24] = 64'h2781038007138ff9; + ROM[25] = 64'h7563470508a76a63; + ROM[26] = 64'h00a71733357902a7; + ROM[27] = 64'h3285350300001517; + ROM[28] = 64'h40301537e9598d79; + ROM[29] = 64'h8d7942250513051a; + ROM[30] = 64'he35d18177713e149; + ROM[31] = 64'he79300367713c295; + ROM[32] = 64'hf330674de3450207; + ROM[33] = 64'h861bc3701ff00613; + ROM[34] = 64'h01000637c730fff6; + ROM[35] = 64'hc35c674dcf10167d; + ROM[36] = 64'hd31c17fd001007b7; + ROM[37] = 64'h0007861b5b5cc30c; + ROM[38] = 64'h674d02072a23dfed; + ROM[39] = 64'h12634785fffd571c; + ROM[40] = 64'h80818793471006f6; + ROM[41] = 64'h4b10474cc3904501; + ROM[42] = 64'hc7d8c790c3cc4b58; + ROM[43] = 64'h086007138082e29d; + ROM[44] = 64'h0a90071300e50c63; + ROM[45] = 64'h0017e793f8e518e3; + ROM[46] = 64'hb74901d7e793b761; + ROM[47] = 64'h674dbfb50197e793; + ROM[48] = 64'h02072e23dffd5f5c; + ROM[49] = 64'h8513ff7d569866cd; + ROM[50] = 64'h053300a03533fff7; + ROM[51] = 64'h00a7e793808240a0; + ROM[52] = 64'h71398082557dbfa1; + ROM[53] = 64'hf8228181ca03e852; + ROM[54] = 64'hf426fc06ec4ef04a; + ROM[55] = 64'h008a7a13e05ae456; + ROM[56] = 64'h1463843289ae892a; + ROM[57] = 64'h4a8500959993000a; + ROM[58] = 64'h4549864ac4296b05; + ROM[59] = 64'h055402630009859b; + ROM[60] = 64'h008b73630004049b; + ROM[61] = 64'hecbff0ef86a66485; + ROM[62] = 64'h45814601468187aa; + ROM[63] = 64'h0207c8639c054531; + ROM[64] = 64'h0094979beb7ff0ef; + ROM[65] = 64'h0205406393811782; + ROM[66] = 64'h99ba020a1863873e; + ROM[67] = 64'ha8014501fc4d993e; + ROM[68] = 64'he93ff0ef45454685; + ROM[69] = 64'h70e24505fe055ae3; + ROM[70] = 64'h69e2790274a27442; + ROM[71] = 64'h61216b026aa26a42; + ROM[72] = 64'h9301020497138082; + ROM[73] = 64'hec26f0227179b7f9; + ROM[74] = 64'he44ef4064705e84a; + ROM[75] = 64'h842e84aad79867cd; + ROM[76] = 64'h8b85571c674d8932; + ROM[77] = 64'hd35c03600793dff5; + ROM[78] = 64'h571c674d02072423; + ROM[79] = 64'ha737b00026f3fffd; + ROM[80] = 64'h27f311f707130007; + ROM[81] = 64'hfef77de38f95b000; + ROM[82] = 64'h80018c235b1c674d; + ROM[83] = 64'he7934f5ccf9d8b89; + ROM[84] = 64'hb00026f3cf5c0027; + ROM[85] = 64'h0ff7071305f5e737; + ROM[86] = 64'h7de38f95b00027f3; + ROM[87] = 64'h9bf54f5c674dfef7; + ROM[88] = 64'h9737b00026f3cf5c; + ROM[89] = 64'h27f367f707130098; + ROM[90] = 64'hfef77de38f95b000; + ROM[91] = 64'h4501458146014681; + ROM[92] = 64'h80818993dd7ff0ef; + ROM[93] = 64'h0593460146814789; + ROM[94] = 64'h00f9882345211aa0; + ROM[95] = 64'ha783e50ddbfff0ef; + ROM[96] = 64'h17d21aa007130009; + ROM[97] = 64'h479102e79e6393d1; + ROM[98] = 64'hf0efa80900f98823; + ROM[99] = 64'ha78302054663da1f; + ROM[100]= 64'h46810207cc630009; + ROM[101]= 64'h0370051345814601; + ROM[102]= 64'h468187aad87ff0ef; + ROM[103]= 64'h0513403005b74601; + ROM[104]= 64'h8522fc07dae30a90; + ROM[105]= 64'h864a69a270a27402; + ROM[106]= 64'h614564e2694285a6; + ROM[107]= 64'hebd18b8583f9b5b9; + ROM[108]= 64'h4509458146014681; + ROM[109]= 64'hfc054de3d4fff0ef; + ROM[110]= 64'h123405b746014681; + ROM[111]= 64'h44e3d3dff0ef450d; + ROM[112]= 64'h77c10009a983fc05; + ROM[113]= 64'h460100f9f9b34681; + ROM[114]= 64'hd23ff0ef451d85ce; + ROM[115]= 64'h470567cdfa0547e3; + ROM[116]= 64'h4737b00026f3d3d8; + ROM[117]= 64'h27f323f70713000f; + ROM[118]= 64'hfef77de38f95b000; + ROM[119]= 64'h46810007ae2367cd; + ROM[120]= 64'h0370051385ce4601; + ROM[121]= 64'hf6054de3cefff0ef; + ROM[122]= 64'h0513458146014681; + ROM[123]= 64'h44e3cddff0ef0860; + ROM[124]= 64'h059346014681f605; + ROM[125]= 64'hccbff0ef45412000; + ROM[126]= 64'he7930109c783bf99; + ROM[127]= 64'hb78d00f988230087; + ROM[128]= 64'h0000000000000000; + ROM[129]= 64'h0000000000000000; + ROM[130]= 64'h0000000000000000; + ROM[131]= 64'h0000000000000000; + ROM[132]= 64'h0000000000000000; + ROM[133]= 64'h0000000000000000; + ROM[134]= 64'h0000000000000000; + ROM[135]= 64'h0000000000000000; + ROM[136]= 64'h0000000000000000; + ROM[137]= 64'h0000000000000000; + ROM[138]= 64'h0000000000000000; + ROM[139]= 64'h0000000000000000; + ROM[140]= 64'h0000000000000000; + ROM[141]= 64'h0000000000000000; + ROM[142]= 64'h0000000000000000; + ROM[143]= 64'h0000000000000000; + ROM[144]= 64'h0000000000000000; + ROM[145]= 64'h0000000000000000; + ROM[146]= 64'h0000000000000000; + ROM[147]= 64'h0000000000000000; + ROM[148]= 64'h0000000000000000; + ROM[149]= 64'h0000000000000000; + ROM[150]= 64'h0000000000000000; + ROM[151]= 64'h0000000000000000; + ROM[152]= 64'h0000000000000000; + ROM[153]= 64'h0000000000000000; + ROM[154]= 64'h0000000000000000; + ROM[155]= 64'h0000000000000000; + ROM[156]= 64'h0000000000000000; + ROM[157]= 64'h0000000000000000; + ROM[158]= 64'h0000000000000000; + ROM[159]= 64'h0000000000000000; + ROM[160]= 64'h0000000000000000; + ROM[161]= 64'h0000000000000000; + ROM[162]= 64'h0000000000000000; + ROM[163]= 64'h0000000000000000; + ROM[164]= 64'h0000000000000000; + ROM[165]= 64'h0000000000000000; + ROM[166]= 64'h0000000000000000; + ROM[167]= 64'h0000000000000000; + ROM[168]= 64'h0000000000000000; + ROM[169]= 64'h0000000000000000; + ROM[170]= 64'h0000000000000000; + ROM[171]= 64'h0000000000000000; + ROM[172]= 64'h0000000000000000; + ROM[173]= 64'h0000000000000000; + ROM[174]= 64'h0000000000000000; + ROM[175]= 64'h0000000000000000; + ROM[176]= 64'h0000000000000000; + ROM[177]= 64'h0000000000000000; + ROM[178]= 64'h0000000000000000; + ROM[179]= 64'h0000000000000000; + ROM[180]= 64'h0000000000000000; + ROM[181]= 64'h0000000000000000; + ROM[182]= 64'h0000000000000000; + ROM[183]= 64'h0000000000000000; + ROM[184]= 64'h0000000000000000; + ROM[185]= 64'h0000000000000000; + ROM[186]= 64'h0000000000000000; + ROM[187]= 64'h0000000000000000; + ROM[188]= 64'h0000000000000000; + ROM[189]= 64'h0000000000000000; + ROM[190]= 64'h0000000000000000; + ROM[191]= 64'h0000000000000000; + ROM[192]= 64'h0000000000000000; + ROM[193]= 64'h0000000000000000; + ROM[194]= 64'h0000000000000000; + ROM[195]= 64'h0000000000000000; + ROM[196]= 64'h0000000000000000; + ROM[197]= 64'h0000000000000000; + ROM[198]= 64'h0000000000000000; + ROM[199]= 64'h0000000000000000; + ROM[200]= 64'h0000000000000000; + ROM[201]= 64'h0000000000000000; + ROM[202]= 64'h0000000000000000; + ROM[203]= 64'h0000000000000000; + ROM[204]= 64'h0000000000000000; + ROM[205]= 64'h0000000000000000; + ROM[206]= 64'h0000000000000000; + ROM[207]= 64'h0000000000000000; + ROM[208]= 64'h0000000000000000; + ROM[209]= 64'h0000000000000000; + ROM[210]= 64'h0000000000000000; + ROM[211]= 64'h0000000000000000; + ROM[212]= 64'h0000000000000000; + ROM[213]= 64'h0000000000000000; + ROM[214]= 64'h0000000000000000; + ROM[215]= 64'h0000000000000000; + ROM[216]= 64'h0000000000000000; + ROM[217]= 64'h0000000000000000; + ROM[218]= 64'h0000000000000000; + ROM[219]= 64'h0000000000000000; + ROM[220]= 64'h0000000000000000; + ROM[221]= 64'h0000000000000000; + ROM[222]= 64'h0000000000000000; + ROM[223]= 64'h0000000000000000; + ROM[224]= 64'h0000000000000000; + ROM[225]= 64'h0000000000000000; + ROM[226]= 64'h0000000000000000; + ROM[227]= 64'h0000000000000000; + ROM[228]= 64'h0000000000000000; + ROM[229]= 64'h0000000000000000; + ROM[230]= 64'h0000000000000000; + ROM[231]= 64'h0000000000000000; + ROM[232]= 64'h0000000000000000; + ROM[233]= 64'h0000000000000000; + ROM[234]= 64'h0000000000000000; + ROM[235]= 64'h0000000000000000; + ROM[236]= 64'h0000000000000000; + ROM[237]= 64'h0000000000000000; + ROM[238]= 64'h0000000000000000; + ROM[239]= 64'h0000000000000000; + ROM[240]= 64'h0000000000000000; + ROM[241]= 64'h0000000000000000; + ROM[242]= 64'h0000000000000000; + ROM[243]= 64'h0000000000000000; + ROM[244]= 64'h0000000000000000; + ROM[245]= 64'h0000000000000000; + ROM[246]= 64'h0000000000000000; + ROM[247]= 64'h0000000000000000; + ROM[248]= 64'h0000000000000000; + ROM[249]= 64'h0000000000000000; + ROM[250]= 64'h0000000000000000; + ROM[251]= 64'h0000000000000000; + ROM[252]= 64'h0000000000000000; + ROM[253]= 64'h0000000000000000; + ROM[254]= 64'h0000000000000000; + ROM[255]= 64'h0000000000000000; + ROM[256]= 64'h0000000000000000; + ROM[257]= 64'h0000000000000000; + ROM[258]= 64'h0000000000000000; + ROM[259]= 64'h0000000000000000; + ROM[260]= 64'h0000000000000000; + ROM[261]= 64'h0000000000000000; + ROM[262]= 64'h0000000000000000; + ROM[263]= 64'h0000000000000000; + ROM[264]= 64'h0000000000000000; + ROM[265]= 64'h0000000000000000; + ROM[266]= 64'h0000000000000000; + ROM[267]= 64'h0000000000000000; + ROM[268]= 64'h0000000000000000; + ROM[269]= 64'h0000000000000000; + ROM[270]= 64'h0000000000000000; + ROM[271]= 64'h0000000000000000; + ROM[272]= 64'h0000000000000000; + ROM[273]= 64'h0000000000000000; + ROM[274]= 64'h0000000000000000; + ROM[275]= 64'h0000000000000000; + ROM[276]= 64'h0000000000000000; + ROM[277]= 64'h0000000000000000; + ROM[278]= 64'h0000000000000000; + ROM[279]= 64'h0000000000000000; + ROM[280]= 64'h0000000000000000; + ROM[281]= 64'h0000000000000000; + ROM[282]= 64'h0000000000000000; + ROM[283]= 64'h0000000000000000; + ROM[284]= 64'h0000000000000000; + ROM[285]= 64'h0000000000000000; + ROM[286]= 64'h0000000000000000; + ROM[287]= 64'h0000000000000000; + ROM[288]= 64'h0000000000000000; + ROM[289]= 64'h0000000000000000; + ROM[290]= 64'h0000000000000000; + ROM[291]= 64'h0000000000000000; + ROM[292]= 64'h0000000000000000; + ROM[293]= 64'h0000000000000000; + ROM[294]= 64'h0000000000000000; + ROM[295]= 64'h0000000000000000; + ROM[296]= 64'h0000000000000000; + ROM[297]= 64'h0000000000000000; + ROM[298]= 64'h0000000000000000; + ROM[299]= 64'h0000000000000000; + ROM[300]= 64'h0000000000000000; + ROM[301]= 64'h0000000000000000; + ROM[302]= 64'h0000000000000000; + ROM[303]= 64'h0000000000000000; + ROM[304]= 64'h0000000000000000; + ROM[305]= 64'h0000000000000000; + ROM[306]= 64'h0000000000000000; + ROM[307]= 64'h0000000000000000; + ROM[308]= 64'h0000000000000000; + ROM[309]= 64'h0000000000000000; + ROM[310]= 64'h0000000000000000; + ROM[311]= 64'h0000000000000000; + ROM[312]= 64'h0000000000000000; + ROM[313]= 64'h0000000000000000; + ROM[314]= 64'h0000000000000000; + ROM[315]= 64'h0000000000000000; + ROM[316]= 64'h0000000000000000; + ROM[317]= 64'h0000000000000000; + ROM[318]= 64'h0000000000000000; + ROM[319]= 64'h0000000000000000; + ROM[320]= 64'h0000000000000000; + ROM[321]= 64'h0000000000000000; + ROM[322]= 64'h0000000000000000; + ROM[323]= 64'h0000000000000000; + ROM[324]= 64'h0000000000000000; + ROM[325]= 64'h0000000000000000; + ROM[326]= 64'h0000000000000000; + ROM[327]= 64'h0000000000000000; + ROM[328]= 64'h0000000000000000; + ROM[329]= 64'h0000000000000000; + ROM[330]= 64'h0000000000000000; + ROM[331]= 64'h0000000000000000; + ROM[332]= 64'h0000000000000000; + ROM[333]= 64'h0000000000000000; + ROM[334]= 64'h0000000000000000; + ROM[335]= 64'h0000000000000000; + ROM[336]= 64'h0000000000000000; + ROM[337]= 64'h0000000000000000; + ROM[338]= 64'h0000000000000000; + ROM[339]= 64'h0000000000000000; + ROM[340]= 64'h0000000000000000; + ROM[341]= 64'h0000000000000000; + ROM[342]= 64'h0000000000000000; + ROM[343]= 64'h0000000000000000; + ROM[344]= 64'h0000000000000000; + ROM[345]= 64'h0000000000000000; + ROM[346]= 64'h0000000000000000; + ROM[347]= 64'h0000000000000000; + ROM[348]= 64'h0000000000000000; + ROM[349]= 64'h0000000000000000; + ROM[350]= 64'h0000000000000000; + ROM[351]= 64'h0000000000000000; + ROM[352]= 64'h0000000000000000; + ROM[353]= 64'h0000000000000000; + ROM[354]= 64'h0000000000000000; + ROM[355]= 64'h0000000000000000; + ROM[356]= 64'h0000000000000000; + ROM[357]= 64'h0000000000000000; + ROM[358]= 64'h0000000000000000; + ROM[359]= 64'h0000000000000000; + ROM[360]= 64'h0000000000000000; + ROM[361]= 64'h0000000000000000; + ROM[362]= 64'h0000000000000000; + ROM[363]= 64'h0000000000000000; + ROM[364]= 64'h0000000000000000; + ROM[365]= 64'h0000000000000000; + ROM[366]= 64'h0000000000000000; + ROM[367]= 64'h0000000000000000; + ROM[368]= 64'h0000000000000000; + ROM[369]= 64'h0000000000000000; + ROM[370]= 64'h0000000000000000; + ROM[371]= 64'h0000000000000000; + ROM[372]= 64'h0000000000000000; + ROM[373]= 64'h0000000000000000; + ROM[374]= 64'h0000000000000000; + ROM[375]= 64'h0000000000000000; + ROM[376]= 64'h0000000000000000; + ROM[377]= 64'h0000000000000000; + ROM[378]= 64'h0000000000000000; + ROM[379]= 64'h0000000000000000; + ROM[380]= 64'h0000000000000000; + ROM[381]= 64'h0000000000000000; + ROM[382]= 64'h0000000000000000; + ROM[383]= 64'h0000000000000000; + ROM[384]= 64'h0000000000000000; + ROM[385]= 64'h0000000000000000; + ROM[386]= 64'h0000000000000000; + ROM[387]= 64'h0000000000000000; + ROM[388]= 64'h0000000000000000; + ROM[389]= 64'h0000000000000000; + ROM[390]= 64'h0000000000000000; + ROM[391]= 64'h0000000000000000; + ROM[392]= 64'h0000000000000000; + ROM[393]= 64'h0000000000000000; + ROM[394]= 64'h0000000000000000; + ROM[395]= 64'h0000000000000000; + ROM[396]= 64'h0000000000000000; + ROM[397]= 64'h0000000000000000; + ROM[398]= 64'h0000000000000000; + ROM[399]= 64'h0000000000000000; + ROM[400]= 64'h0000000000000000; + ROM[401]= 64'h0000000000000000; + ROM[402]= 64'h0000000000000000; + ROM[403]= 64'h0000000000000000; + ROM[404]= 64'h0000000000000000; + ROM[405]= 64'h0000000000000000; + ROM[406]= 64'h0000000000000000; + ROM[407]= 64'h0000000000000000; + ROM[408]= 64'h0000000000000000; + ROM[409]= 64'h0000000000000000; + ROM[410]= 64'h0000000000000000; + ROM[411]= 64'h0000000000000000; + ROM[412]= 64'h0000000000000000; + ROM[413]= 64'h0000000000000000; + ROM[414]= 64'h0000000000000000; + ROM[415]= 64'h0000000000000000; + ROM[416]= 64'h0000000000000000; + ROM[417]= 64'h0000000000000000; + ROM[418]= 64'h0000000000000000; + ROM[419]= 64'h0000000000000000; + ROM[420]= 64'h0000000000000000; + ROM[421]= 64'h0000000000000000; + ROM[422]= 64'h0000000000000000; + ROM[423]= 64'h0000000000000000; + ROM[424]= 64'h0000000000000000; + ROM[425]= 64'h0000000000000000; + ROM[426]= 64'h0000000000000000; + ROM[427]= 64'h0000000000000000; + ROM[428]= 64'h0000000000000000; + ROM[429]= 64'h0000000000000000; + ROM[430]= 64'h0000000000000000; + ROM[431]= 64'h0000000000000000; + ROM[432]= 64'h0000000000000000; + ROM[433]= 64'h0000000000000000; + ROM[434]= 64'h0000000000000000; + ROM[435]= 64'h0000000000000000; + ROM[436]= 64'h0000000000000000; + ROM[437]= 64'h0000000000000000; + ROM[438]= 64'h0000000000000000; + ROM[439]= 64'h0000000000000000; + ROM[440]= 64'h0000000000000000; + ROM[441]= 64'h0000000000000000; + ROM[442]= 64'h0000000000000000; + ROM[443]= 64'h0000000000000000; + ROM[444]= 64'h0000000000000000; + ROM[445]= 64'h0000000000000000; + ROM[446]= 64'h0000000000000000; + ROM[447]= 64'h0000000000000000; + ROM[448]= 64'h0000000000000000; + ROM[449]= 64'h0000000000000000; + ROM[450]= 64'h0000000000000000; + ROM[451]= 64'h0000000000000000; + ROM[452]= 64'h0000000000000000; + ROM[453]= 64'h0000000000000000; + ROM[454]= 64'h0000000000000000; + ROM[455]= 64'h0000000000000000; + ROM[456]= 64'h0000000000000000; + ROM[457]= 64'h0000000000000000; + ROM[458]= 64'h0000000000000000; + ROM[459]= 64'h0000000000000000; + ROM[460]= 64'h0000000000000000; + ROM[461]= 64'h0000000000000000; + ROM[462]= 64'h0000000000000000; + ROM[463]= 64'h0000000000000000; + ROM[464]= 64'h0000000000000000; + ROM[465]= 64'h0000000000000000; + ROM[466]= 64'h0000000000000000; + ROM[467]= 64'h0000000000000000; + ROM[468]= 64'h0000000000000000; + ROM[469]= 64'h0000000000000000; + ROM[470]= 64'h0000000000000000; + ROM[471]= 64'h0000000000000000; + ROM[472]= 64'h0000000000000000; + ROM[473]= 64'h0000000000000000; + ROM[474]= 64'h0000000000000000; + ROM[475]= 64'h0000000000000000; + ROM[476]= 64'h0000000000000000; + ROM[477]= 64'h0000000000000000; + ROM[478]= 64'h0000000000000000; + ROM[479]= 64'h0000000000000000; + ROM[480]= 64'h0000000000000000; + ROM[481]= 64'h0000000000000000; + ROM[482]= 64'h0000000000000000; + ROM[483]= 64'h0000000000000000; + ROM[484]= 64'h0000000000000000; + ROM[485]= 64'h0000000000000000; + ROM[486]= 64'h0000000000000000; + ROM[487]= 64'h0000000000000000; + ROM[488]= 64'h0000000000000000; + ROM[489]= 64'h0000000000000000; + ROM[490]= 64'h0000000000000000; + ROM[491]= 64'h0000000000000000; + ROM[492]= 64'h0000000000000000; + ROM[493]= 64'h0000000000000000; + ROM[494]= 64'h0000000000000000; + ROM[495]= 64'h0000000000000000; + ROM[496]= 64'h0000000000000000; + ROM[497]= 64'h0000000000000000; + ROM[498]= 64'h0000000000000000; + ROM[499]= 64'h0000000000000000; + ROM[500]= 64'h0000000000000000; + ROM[501]= 64'h0000000000000000; + ROM[502]= 64'h0000000000000000; + ROM[503]= 64'h0000000000000000; + ROM[504]= 64'h0000000000000000; + ROM[505]= 64'h0000000000000000; + ROM[506]= 64'h0000000000000000; + ROM[507]= 64'h0000000000000000; + ROM[508]= 64'h0000000000000000; + ROM[509]= 64'h0000000000000000; + ROM[510]= 64'h0000000000000000; + ROM[511]= 64'h0000000000000000; + ROM[512]= 64'h0000000000000000; + ROM[513]= 64'h0000000000000000; + ROM[514]= 64'h0000000000000000; + ROM[515]= 64'h0000000000000000; + ROM[516]= 64'h0000000000000000; + ROM[517]= 64'h0000000000000000; + ROM[518]= 64'h0000000000000000; + ROM[519]= 64'h0000000000000000; + ROM[520]= 64'h0000000000000000; + ROM[521]= 64'h0000000000000000; + ROM[522]= 64'h0000000000000000; + ROM[523]= 64'h0000000000000000; + ROM[524]= 64'h0000000000000000; + ROM[525]= 64'h0000000000000000; + ROM[526]= 64'h0000000000000000; + ROM[527]= 64'h0000000000000000; + ROM[528]= 64'h0000000000000000; + ROM[529]= 64'h0000000000000000; + ROM[530]= 64'h0000000000000000; + ROM[531]= 64'h0000000000000000; + ROM[532]= 64'h0000000000000000; + ROM[533]= 64'h0000000000000000; + ROM[534]= 64'h0000000000000000; + ROM[535]= 64'h0000000000000000; + ROM[536]= 64'h0000000000000000; + ROM[537]= 64'h0000000000000000; + ROM[538]= 64'h0000000000000000; + ROM[539]= 64'h0000000000000000; + ROM[540]= 64'h0000000000000000; + ROM[541]= 64'h0000000000000000; + ROM[542]= 64'h0000000000000000; + ROM[543]= 64'h0000000000000000; + ROM[544]= 64'h0000000000000000; + ROM[545]= 64'h0000000000000000; + ROM[546]= 64'h0000000000000000; + ROM[547]= 64'h0000000000000000; + ROM[548]= 64'h0000000000000000; + ROM[549]= 64'h0000000000000000; + ROM[550]= 64'h0000000000000000; + ROM[551]= 64'h0000000000000000; + ROM[552]= 64'h0000000000000000; + ROM[553]= 64'h0000000000000000; + ROM[554]= 64'h0000000000000000; + ROM[555]= 64'h0000000000000000; + ROM[556]= 64'h0000000000000000; + ROM[557]= 64'h0000000000000000; + ROM[558]= 64'h0000000000000000; + ROM[559]= 64'h0000000000000000; + ROM[560]= 64'h0000000000000000; + ROM[561]= 64'h0000000000000000; + ROM[562]= 64'h0000000000000000; + ROM[563]= 64'h0000000000000000; + ROM[564]= 64'h0000000000000000; + ROM[565]= 64'h0000000000000000; + ROM[566]= 64'h0000000000000000; + ROM[567]= 64'h0000000000000000; + ROM[568]= 64'h0000000000000000; + ROM[569]= 64'h0000000000000000; + ROM[570]= 64'h0000000000000000; + ROM[571]= 64'h0000000000000000; + ROM[572]= 64'h0000000000000000; + ROM[573]= 64'h0000000000000000; + ROM[574]= 64'h0000000000000000; + ROM[575]= 64'h0000000000000000; + ROM[576]= 64'h0000000000000000; + ROM[577]= 64'h0000000000000000; + ROM[578]= 64'h0000000000000000; + ROM[579]= 64'h0000000000000000; + ROM[580]= 64'h0000000000000000; + ROM[581]= 64'h0000000000000000; + ROM[582]= 64'h0000000000000000; + ROM[583]= 64'h0000000000000000; + ROM[584]= 64'h0000000000000000; + ROM[585]= 64'h0000000000000000; + ROM[586]= 64'h0000000000000000; + ROM[587]= 64'h0000000000000000; + ROM[588]= 64'h0000000000000000; + ROM[589]= 64'h0000000000000000; + ROM[590]= 64'h0000000000000000; + ROM[591]= 64'h0000000000000000; + ROM[592]= 64'h0000000000000000; + ROM[593]= 64'h0000000000000000; + ROM[594]= 64'h0000000000000000; + ROM[595]= 64'h0000000000000000; + ROM[596]= 64'h0000000000000000; + ROM[597]= 64'h0000000000000000; + ROM[598]= 64'h0000000000000000; + ROM[599]= 64'h0000000000000000; + ROM[600]= 64'h0000000000000000; + ROM[601]= 64'h0000000000000000; + ROM[602]= 64'h0000000000000000; + ROM[603]= 64'h0000000000000000; + ROM[604]= 64'h0000000000000000; + ROM[605]= 64'h0000000000000000; + ROM[606]= 64'h0000000000000000; + ROM[607]= 64'h0000000000000000; + ROM[608]= 64'h0000000000000000; + ROM[609]= 64'h0000000000000000; + ROM[610]= 64'h0000000000000000; + ROM[611]= 64'h0000000000000000; + ROM[612]= 64'h0000000000000000; + ROM[613]= 64'h0000000000000000; + ROM[614]= 64'h0000000000000000; + ROM[615]= 64'h0000000000000000; + ROM[616]= 64'h0000000000000000; + ROM[617]= 64'h0000000000000000; + ROM[618]= 64'h0000000000000000; + ROM[619]= 64'h0000000000000000; + ROM[620]= 64'h0000000000000000; + ROM[621]= 64'h0000000000000000; + ROM[622]= 64'h0000000000000000; + ROM[623]= 64'h0000000000000000; + ROM[624]= 64'h0000000000000000; + ROM[625]= 64'h0000000000000000; + ROM[626]= 64'h0000000000000000; + ROM[627]= 64'h0000000000000000; + ROM[628]= 64'h0000000000000000; + ROM[629]= 64'h0000000000000000; + ROM[630]= 64'h0000000000000000; + ROM[631]= 64'h0000000000000000; + ROM[632]= 64'h0000000000000000; + ROM[633]= 64'h0000000000000000; + ROM[634]= 64'h0000000000000000; + ROM[635]= 64'h0000000000000000; + ROM[636]= 64'h0000000000000000; + ROM[637]= 64'h0000000000000000; + ROM[638]= 64'h0000000000000000; + ROM[639]= 64'h0000000000000000; + ROM[640]= 64'h00600100d2e3ca40; end end end diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv index 845a96c14..c58babb6f 100644 --- a/src/uncore/uncore.sv +++ b/src/uncore/uncore.sv @@ -56,7 +56,7 @@ module uncore ( input logic [31:0] GPIOPinsIn, // GPIO pin input value output logic [31:0] GPIOPinsOut, GPIOPinsEn, // GPIO pin output value and enable input logic UARTSin, // UART serial input - output logic UARTSout, // UART serial output + output logic UARTSout // UART serial output /*output logic SDCCmdOut, // SD Card command output output logic SDCCmdOE, // SD Card command output enable input logic SDCCmdIn, // SD Card command input @@ -150,7 +150,8 @@ module uncore ( end else begin : uart assign UARTSout = 0; assign UARTIntr = 0; end - if (`SDC_SUPPORTED == 1) begin : sdc + /*if (`SDC_SUPPORTED == 1) begin : sdc + SDC SDC(.HCLK, .HRESETn, .HSELSDC, .HADDR(HADDR[4:0]), .HWRITE, .HREADY, .HTRANS, .HWDATA, .HREADSDC, .HRESPSDC, .HREADYSDC, // sdc interface @@ -158,11 +159,12 @@ module uncore ( // interrupt to PLIC .SDCIntM ); - /*end else begin : sdc + end else begin : sdc assign SDCCLK = 0; assign SDCCmdOut = 0; - assign SDCCmdOE = 0;*/ + assign SDCCmdOE = 0; end + */ // AHB Read Multiplexer assign HRDATA = ({`XLEN{HSELRamD}} & HREADRam) | diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv index 92dded7ad..4fd50a2fe 100644 --- a/src/wally/wallypipelinedsoc.sv +++ b/src/wally/wallypipelinedsoc.sv @@ -55,7 +55,7 @@ module wallypipelinedsoc ( output logic [31:0] GPIOPinsOut, // output values for GPIO output logic [31:0] GPIOPinsEn, // output enables for GPIO input logic UARTSin, // UART serial data input - output logic UARTSout, // UART serial data output + output logic UARTSout // UART serial data output /*input logic SDCCmdIn, // SDC Command input output logic SDCCmdOut, // SDC Command output output logic SDCCmdOE, // SDC Command output enable @@ -86,7 +86,7 @@ module wallypipelinedsoc ( .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, - .UARTSout, .MTIME_CLINT, + .UARTSout, .MTIME_CLINT /*.SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK*/); end diff --git a/tests/custom/boot/Makefile b/tests/custom/boot/Makefile index 6dec9c797..8294f2375 100644 --- a/tests/custom/boot/Makefile +++ b/tests/custom/boot/Makefile @@ -16,7 +16,7 @@ OBJECTS := $(OBJECTS:.$(CPPEXT)=.$(OBJEXT)) OBJECTS := $(patsubst $(SRCDIR)/%,$(BUILDDIR)/%,$(OBJECTS)) TARGETDIR := bin -TARGET := $(TARGETDIR)/fpga-test-sdc +TARGET := $(TARGETDIR)/boot ROOT := .. LIBRARY_DIRS := LIBRARY_FILES := @@ -24,7 +24,7 @@ LIBRARY_FILES := MARCH :=-march=rv64imfdc MABI :=-mabi=lp64d LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -LINKER :=linker.x +LINKER :=$(ROOT)/linker1000.x AFLAGS =$(MARCH) $(MABI) -W diff --git a/tests/custom/boot/boot.c b/tests/custom/boot/boot.c index f9fa2c0fe..c9b2c6451 100644 --- a/tests/custom/boot/boot.c +++ b/tests/custom/boot/boot.c @@ -1,3 +1,4 @@ +#include #include "boot.h" /* Card type flags (card_type) */ @@ -82,6 +83,8 @@ #define ERR_DATA_CRC 36 #define ERR_DATA_FIFO 37 #define ERR_BUF_ALIGNMENT 38 +#define FR_DISK_ERR 39 +#define FR_TIMEOUT 40 struct sdc_regs { volatile uint32_t argument; @@ -111,7 +114,9 @@ struct sdc_regs { volatile uint64_t dma_addres; }; -static struct sdc_regs * const regs __attribute__((section(".rodata"))) = (struct sdc_regs *)0x00013100; +#define MAX_BLOCK_CNT 0x1000 + +static struct sdc_regs * const regs __attribute__((section(".rodata"))) = (struct sdc_regs *)0x00013000; static int errno __attribute__((section(".bss"))); // static DSTATUS drv_status __attribute__((section(".bss"))); @@ -130,6 +135,8 @@ static const char * errno_to_str(void) { case ERR_DATA_CRC: return "Data CRC error"; case ERR_DATA_FIFO: return "Data FIFO error"; case ERR_BUF_ALIGNMENT: return "Bad buffer alignment"; + case FR_DISK_ERR: return "Disk error"; + case FR_TIMEOUT: return "Timeout"; } return "Unknown error code"; } @@ -285,7 +292,9 @@ static int ini_sd(void) { // This clock divider is meant to initialize the card at // 400kHz - regs->clock_divider = 0x7c; + + // 22MHz/400kHz = 55 (base 10) = 0x37 - 0x01 = 0x36 + regs->clock_divider = 0x36; regs->software_reset = 0; while (regs->software_reset) {} usleep(5000); @@ -335,7 +344,8 @@ static int ini_sd(void) { if (send_cmd(CMD7, rca << 16) < 0) return -1; /* Clock 25MHz */ - regs->clock_divider = 3; + // 22Mhz/2 = 11Mhz + regs->clock_divider = 1; usleep(10000); /* Bus width 1-bit */ @@ -365,7 +375,7 @@ int disk_read(BYTE * buf, LBA_t sector, UINT count) { while (count > 0) { UINT bcnt = count > MAX_BLOCK_CNT ? MAX_BLOCK_CNT : count; unsigned bytes = bcnt * 512; - if (send_data_cmd(bcnt == 1 ? CMD17 : CMD18, sector, buf, bcnt) < 0) return RES_ERROR; + if (send_data_cmd(bcnt == 1 ? CMD17 : CMD18, sector, buf, bcnt) < 0) return 1; if (bcnt > 1 && send_cmd(CMD12, 0) < 0) return 1; sector += (card_type & CT_BLOCK) ? bcnt : bytes; count -= bcnt; diff --git a/tests/custom/boot/boot.h b/tests/custom/boot/boot.h index ef620cda0..3dd7116a7 100644 --- a/tests/custom/boot/boot.h +++ b/tests/custom/boot/boot.h @@ -7,6 +7,9 @@ typedef unsigned char BYTE; /* char must be 8-bit */ typedef uint16_t WORD; /* 16-bit unsigned integer */ typedef uint32_t DWORD; /* 32-bit unsigned integer */ typedef uint64_t QWORD; /* 64-bit unsigned integer */ -typedef WORD WCHAR; +typedef WORD WCHAR; + +typedef QWORD LBA_t; #endif // WALLYBOOT + From 2839f4f41a93f9b78520428cb4e0663afb4a545d Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Tue, 18 Apr 2023 15:23:22 -0500 Subject: [PATCH 19/22] AHB triggers write, but AXI side doesn't update. --- fpga/constraints/debug2.xdc | 135 ++++++++++++++++++++++++++- fpga/generator/xlnx_axi_crossbar.tcl | 4 +- fpga/src/fpgaTop.v | 66 ++++++------- 3 files changed, 168 insertions(+), 37 deletions(-) diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 13733e579..ec1d1d550 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -748,9 +748,9 @@ connect_debug_port u_ila_0/probe143 [get_nets [list {m_axi_awcache[0]} {m_axi_aw create_debug_port u_ila_0 probe -set_property port_width 31 [get_debug_ports u_ila_0/probe144] +set_property port_width 32 [get_debug_ports u_ila_0/probe144] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe144] -connect_debug_port u_ila_0/probe144 [get_nets [list {m_axi_awaddr[0]} {m_axi_awaddr[1]} {m_axi_awaddr[2]} {m_axi_awaddr[3]} {m_axi_awaddr[4]} {m_axi_awaddr[5]} {m_axi_awaddr[6]} {m_axi_awaddr[7]} {m_axi_awaddr[8]} {m_axi_awaddr[9]} {m_axi_awaddr[10]} {m_axi_awaddr[11]} {m_axi_awaddr[12]} {m_axi_awaddr[13]} {m_axi_awaddr[14]} {m_axi_awaddr[15]} {m_axi_awaddr[16]} {m_axi_awaddr[17]} {m_axi_awaddr[18]} {m_axi_awaddr[19]} {m_axi_awaddr[20]} {m_axi_awaddr[21]} {m_axi_awaddr[22]} {m_axi_awaddr[23]} {m_axi_awaddr[24]} {m_axi_awaddr[25]} {m_axi_awaddr[26]} {m_axi_awaddr[27]} {m_axi_awaddr[28]} {m_axi_awaddr[29]} {m_axi_awaddr[30]} ]] +connect_debug_port u_ila_0/probe144 [get_nets [list {m_axi_awaddr[0]} {m_axi_awaddr[1]} {m_axi_awaddr[2]} {m_axi_awaddr[3]} {m_axi_awaddr[4]} {m_axi_awaddr[5]} {m_axi_awaddr[6]} {m_axi_awaddr[7]} {m_axi_awaddr[8]} {m_axi_awaddr[9]} {m_axi_awaddr[10]} {m_axi_awaddr[11]} {m_axi_awaddr[12]} {m_axi_awaddr[13]} {m_axi_awaddr[14]} {m_axi_awaddr[15]} {m_axi_awaddr[16]} {m_axi_awaddr[17]} {m_axi_awaddr[18]} {m_axi_awaddr[19]} {m_axi_awaddr[20]} {m_axi_awaddr[21]} {m_axi_awaddr[22]} {m_axi_awaddr[23]} {m_axi_awaddr[24]} {m_axi_awaddr[25]} {m_axi_awaddr[26]} {m_axi_awaddr[27]} {m_axi_awaddr[28]} {m_axi_awaddr[29]} {m_axi_awaddr[30]} {m_axi_awaddr[31]}]] create_debug_port u_ila_0 probe @@ -1016,3 +1016,134 @@ create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe191] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe191] connect_debug_port u_ila_0/probe191 [get_nets [list {axiSDC/clock_divider_reg[0]} {axiSDC/clock_divider_reg[1]} {axiSDC/clock_divider_reg[2]} {axiSDC/clock_divider_reg[3]} {axiSDC/clock_divider_reg[4]} {axiSDC/clock_divider_reg[5]} {axiSDC/clock_divider_reg[6]} {axiSDC/clock_divider_reg[7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 32 [get_debug_ports u_ila_0/probe192] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe192] +connect_debug_port u_ila_0/probe192 [get_nets [list {SDCin_axi_awaddr[0]} {SDCin_axi_awaddr[1]} {SDCin_axi_awaddr[2]} {SDCin_axi_awaddr[3]} {SDCin_axi_awaddr[4]} {SDCin_axi_awaddr[5]} {SDCin_axi_awaddr[6]} {SDCin_axi_awaddr[7]} {SDCin_axi_awaddr[8]} {SDCin_axi_awaddr[9]} {SDCin_axi_awaddr[10]} {SDCin_axi_awaddr[11]} {SDCin_axi_awaddr[12]} {SDCin_axi_awaddr[13]} {SDCin_axi_awaddr[14]} {SDCin_axi_awaddr[15]} {SDCin_axi_awaddr[16]} {SDCin_axi_awaddr[17]} {SDCin_axi_awaddr[18]} {SDCin_axi_awaddr[19]} {SDCin_axi_awaddr[20]} {SDCin_axi_awaddr[21]} {SDCin_axi_awaddr[22]} {SDCin_axi_awaddr[23]} {SDCin_axi_awaddr[24]} {SDCin_axi_awaddr[25]} {SDCin_axi_awaddr[26]} {SDCin_axi_awaddr[27]} {SDCin_axi_awaddr[28]} {SDCin_axi_awaddr[29]} {SDCin_axi_awaddr[30]} {SDCin_axi_awaddr[31]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe193] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe193] +connect_debug_port u_ila_0/probe193 [get_nets [list {SDCin_axi_awvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe194] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe194] +connect_debug_port u_ila_0/probe194 [get_nets [list {SDCin_axi_awready}]] + +create_debug_port u_ila_0 probe +set_property port_width 32 [get_debug_ports u_ila_0/probe195] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe195] +connect_debug_port u_ila_0/probe195 [get_nets [list {SDCin_axi_wdata[0]} {SDCin_axi_wdata[1]} {SDCin_axi_wdata[2]} {SDCin_axi_wdata[3]} {SDCin_axi_wdata[4]} {SDCin_axi_wdata[5]} {SDCin_axi_wdata[6]} {SDCin_axi_wdata[7]} {SDCin_axi_wdata[8]} {SDCin_axi_wdata[9]} {SDCin_axi_wdata[10]} {SDCin_axi_wdata[11]} {SDCin_axi_wdata[12]} {SDCin_axi_wdata[13]} {SDCin_axi_wdata[14]} {SDCin_axi_wdata[15]} {SDCin_axi_wdata[16]} {SDCin_axi_wdata[17]} {SDCin_axi_wdata[18]} {SDCin_axi_wdata[19]} {SDCin_axi_wdata[20]} {SDCin_axi_wdata[21]} {SDCin_axi_wdata[22]} {SDCin_axi_wdata[23]} {SDCin_axi_wdata[24]} {SDCin_axi_wdata[25]} {SDCin_axi_wdata[26]} {SDCin_axi_wdata[27]} {SDCin_axi_wdata[28]} {SDCin_axi_wdata[29]} {SDCin_axi_wdata[30]} {SDCin_axi_wdata[31]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe196] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe196] +connect_debug_port u_ila_0/probe196 [get_nets [list {SDCin_axi_wvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe197] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe197] +connect_debug_port u_ila_0/probe197 [get_nets [list {SDCin_axi_wready}]] + +create_debug_port u_ila_0 probe +set_property port_width 2 [get_debug_ports u_ila_0/probe198] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe198] +connect_debug_port u_ila_0/probe198 [get_nets [list {SDCin_axi_bresp[0]} {SDCin_axi_bresp[1]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe199] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe199] +connect_debug_port u_ila_0/probe199 [get_nets [list {SDCin_axi_bvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe200] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe200] +connect_debug_port u_ila_0/probe200 [get_nets [list {SDCin_axi_bready}]] + +create_debug_port u_ila_0 probe +set_property port_width 32 [get_debug_ports u_ila_0/probe201] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe201] +connect_debug_port u_ila_0/probe201 [get_nets [list {SDCin_axi_araddr[0]} {SDCin_axi_araddr[1]} {SDCin_axi_araddr[2]} {SDCin_axi_araddr[3]} {SDCin_axi_araddr[4]} {SDCin_axi_araddr[5]} {SDCin_axi_araddr[6]} {SDCin_axi_araddr[7]} {SDCin_axi_araddr[8]} {SDCin_axi_araddr[9]} {SDCin_axi_araddr[10]} {SDCin_axi_araddr[11]} {SDCin_axi_araddr[12]} {SDCin_axi_araddr[13]} {SDCin_axi_araddr[14]} {SDCin_axi_araddr[15]} {SDCin_axi_araddr[16]} {SDCin_axi_araddr[17]} {SDCin_axi_araddr[18]} {SDCin_axi_araddr[19]} {SDCin_axi_araddr[20]} {SDCin_axi_araddr[21]} {SDCin_axi_araddr[22]} {SDCin_axi_araddr[23]} {SDCin_axi_araddr[24]} {SDCin_axi_araddr[25]} {SDCin_axi_araddr[26]} {SDCin_axi_araddr[27]} {SDCin_axi_araddr[28]} {SDCin_axi_araddr[29]} {SDCin_axi_araddr[30]} {SDCin_axi_araddr[31]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe202] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe202] +connect_debug_port u_ila_0/probe202 [get_nets [list {SDCin_axi_arvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe203] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe203] +connect_debug_port u_ila_0/probe203 [get_nets [list {SDCin_axi_arready}]] + +create_debug_port u_ila_0 probe +set_property port_width 32 [get_debug_ports u_ila_0/probe204] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe204] +connect_debug_port u_ila_0/probe204 [get_nets [list {SDCin_axi_rdata[0]} {SDCin_axi_rdata[1]} {SDCin_axi_rdata[2]} {SDCin_axi_rdata[3]} {SDCin_axi_rdata[4]} {SDCin_axi_rdata[5]} {SDCin_axi_rdata[6]} {SDCin_axi_rdata[7]} {SDCin_axi_rdata[8]} {SDCin_axi_rdata[9]} {SDCin_axi_rdata[10]} {SDCin_axi_rdata[11]} {SDCin_axi_rdata[12]} {SDCin_axi_rdata[13]} {SDCin_axi_rdata[14]} {SDCin_axi_rdata[15]} {SDCin_axi_rdata[16]} {SDCin_axi_rdata[17]} {SDCin_axi_rdata[18]} {SDCin_axi_rdata[19]} {SDCin_axi_rdata[20]} {SDCin_axi_rdata[21]} {SDCin_axi_rdata[22]} {SDCin_axi_rdata[23]} {SDCin_axi_rdata[24]} {SDCin_axi_rdata[25]} {SDCin_axi_rdata[26]} {SDCin_axi_rdata[27]} {SDCin_axi_rdata[28]} {SDCin_axi_rdata[29]} {SDCin_axi_rdata[30]} {SDCin_axi_rdata[31]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 2 [get_debug_ports u_ila_0/probe205] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe205] +connect_debug_port u_ila_0/probe205 [get_nets [list {SDCin_axi_rresp[0]} {SDCin_axi_rresp[1]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe206] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe206] +connect_debug_port u_ila_0/probe206 [get_nets [list {SDCin_axi_rvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe207] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe207] +connect_debug_port u_ila_0/probe207 [get_nets [list {SDCin_axi_rready}]] + + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe208] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe208] +connect_debug_port u_ila_0/probe208 [get_nets [list {s01_axi_awvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe209] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe209] +connect_debug_port u_ila_0/probe209 [get_nets [list {s01_axi_awready}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe210] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe210] +connect_debug_port u_ila_0/probe210 [get_nets [list {s00_axi_awvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe211] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe211] +connect_debug_port u_ila_0/probe211 [get_nets [list {s00_axi_awready}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe212] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe212] +connect_debug_port u_ila_0/probe212 [get_nets [list {axi4in_axi_awvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe213] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe213] +connect_debug_port u_ila_0/probe213 [get_nets [list {axi4in_axi_awready}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe214] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe214] +connect_debug_port u_ila_0/probe214 [get_nets [list {SDCout_axi_awvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe215] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe215] +connect_debug_port u_ila_0/probe215 [get_nets [list {SDCout_axi_awready}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe216] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe216] +connect_debug_port u_ila_0/probe216 [get_nets [list {m01_axi_awvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe217] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe217] +connect_debug_port u_ila_0/probe217 [get_nets [list {m01_axi_awready}]] diff --git a/fpga/generator/xlnx_axi_crossbar.tcl b/fpga/generator/xlnx_axi_crossbar.tcl index 1d9eb4e78..ed44d9997 100644 --- a/fpga/generator/xlnx_axi_crossbar.tcl +++ b/fpga/generator/xlnx_axi_crossbar.tcl @@ -19,8 +19,8 @@ create_ip -name axi_crossbar -vendor xilinx.com -library ip -version 2.1 -module set_property -dict [list CONFIG.NUM_SI {2} \ CONFIG.DATA_WIDTH {64} \ CONFIG.ID_WIDTH {4} \ - CONFIG.M01_S01_READ_CONNECTIVITY {0} \ - CONFIG.M01_S01_WRITE_CONNECTIVITY {0} \ + # CONFIG.M01_S01_READ_CONNECTIVITY {0} \ + # CONFIG.M01_S01_WRITE_CONNECTIVITY {0} \ CONFIG.M00_A00_BASE_ADDR {0x0000000080000000} \ CONFIG.M01_A00_BASE_ADDR {0x0000000000013000} \ CONFIG.M00_A00_ADDR_WIDTH {31}] [get_ips $ipName] diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index 03758249e..42957f63b 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -199,8 +199,8 @@ module fpgaTop wire [2:0]s00_axi_awprot; wire [3:0]s00_axi_awregion; wire [3:0]s00_axi_awqos; - wire s00_axi_awvalid; - wire s00_axi_awready; + (* mark_debug = "true" *) wire s00_axi_awvalid; + (* mark_debug = "true" *) wire s00_axi_awready; wire [63:0]s00_axi_wdata; wire [7:0]s00_axi_wstrb; wire s00_axi_wlast; @@ -242,8 +242,8 @@ module fpgaTop wire [2:0]s01_axi_awprot; wire [3:0]s01_axi_awregion; wire [3:0]s01_axi_awqos; // qos signals need to be 0 for SDC - wire s01_axi_awvalid; - wire s01_axi_awready; + (* mark_debug = "true" *) wire s01_axi_awvalid; + (* mark_debug = "true" *) wire s01_axi_awready; wire [63:0]s01_axi_wdata; wire [7:0]s01_axi_wstrb; wire s01_axi_wlast; @@ -279,8 +279,8 @@ module fpgaTop wire [2:0]axi4in_axi_awprot; wire [3:0]axi4in_axi_awregion; wire [3:0]axi4in_axi_awqos; - wire axi4in_axi_awvalid; - wire axi4in_axi_awready; + (* mark_debug = "true" *) wire axi4in_axi_awvalid; + (* mark_debug = "true" *) wire axi4in_axi_awready; wire [31:0]axi4in_axi_wdata; wire [3:0]axi4in_axi_wstrb; wire axi4in_axi_wlast; @@ -307,25 +307,25 @@ module fpgaTop wire axi4in_axi_rready; // AXI4 to AXI4-Lite Protocol converter output - wire [31:0]SDCin_axi_awaddr; - wire [2:0]SDCin_axi_awprot; - wire SDCin_axi_awvalid; - wire SDCin_axi_awready; - wire [31:0]SDCin_axi_wdata; - wire [3:0]SDCin_axi_wstrb; - wire SDCin_axi_wvalid; - wire SDCin_axi_wready; - wire [1:0]SDCin_axi_bresp; - wire SDCin_axi_bvalid; - wire SDCin_axi_bready; - wire [31:0]SDCin_axi_araddr; - wire [2:0]SDCin_axi_arprot; - wire SDCin_axi_arvalid; - wire SDCin_axi_arready; - wire [31:0]SDCin_axi_rdata; - wire [1:0]SDCin_axi_rresp; - wire SDCin_axi_rvalid; - wire SDCin_axi_rready; + (* mark_debug = "true" *) wire [31:0]SDCin_axi_awaddr; + (* mark_debug = "true" *) wire [2:0]SDCin_axi_awprot; + (* mark_debug = "true" *) wire SDCin_axi_awvalid; + (* mark_debug = "true" *) wire SDCin_axi_awready; + (* mark_debug = "true" *) wire [31:0]SDCin_axi_wdata; + (* mark_debug = "true" *) wire [3:0]SDCin_axi_wstrb; + (* mark_debug = "true" *) wire SDCin_axi_wvalid; + (* mark_debug = "true" *) wire SDCin_axi_wready; + (* mark_debug = "true" *) wire [1:0]SDCin_axi_bresp; + (* mark_debug = "true" *) wire SDCin_axi_bvalid; + (* mark_debug = "true" *) wire SDCin_axi_bready; + (* mark_debug = "true" *) wire [31:0]SDCin_axi_araddr; + (* mark_debug = "true" *) wire [2:0]SDCin_axi_arprot; + (* mark_debug = "true" *) wire SDCin_axi_arvalid; + (* mark_debug = "true" *) wire SDCin_axi_arready; + (* mark_debug = "true" *) wire [31:0]SDCin_axi_rdata; + (* mark_debug = "true" *) wire [1:0]SDCin_axi_rresp; + (* mark_debug = "true" *) wire SDCin_axi_rvalid; + (* mark_debug = "true" *) wire SDCin_axi_rready; // ---------------------------------------------------------------- // 32to64 dwidth converter input interface ----------------------- @@ -338,8 +338,8 @@ module fpgaTop wire [2:0]SDCout_axi_awprot; wire [3:0]SDCout_axi_awregion; wire [3:0]SDCout_axi_awqos; - wire SDCout_axi_awvalid; - wire SDCout_axi_awready; + (* mark_debug = "true" *) wire SDCout_axi_awvalid; + (* mark_debug = "true" *) wire SDCout_axi_awready; wire [31:0]SDCout_axi_wdata; wire [3:0]SDCout_axi_wstrb; wire SDCout_axi_wlast; @@ -376,8 +376,8 @@ module fpgaTop wire [2:0]m01_axi_awprot; wire [3:0]m01_axi_awregion; wire [3:0]m01_axi_awqos; - wire m01_axi_awvalid; - wire m01_axi_awready; + (* mark_debug = "true" *) wire m01_axi_awvalid; + (* mark_debug = "true" *) wire m01_axi_awready; wire [63:0]m01_axi_wdata; wire [3:0]m01_axi_wstrb; wire m01_axi_wlast; @@ -571,7 +571,7 @@ module fpgaTop .aresetn(peripheral_aresetn), // Connect Masters - .s_axi_awid({4'b0001, m_axi_awid}), + .s_axi_awid({4'b1000, m_axi_awid}), .s_axi_awaddr({m01_axi_awaddr, m_axi_awaddr}), .s_axi_awlen({m01_axi_awlen, m_axi_awlen}), .s_axi_awsize({m01_axi_awsize, m_axi_awsize}), @@ -591,7 +591,7 @@ module fpgaTop .s_axi_bresp({m01_axi_bresp, m_axi_bresp}), .s_axi_bvalid({m01_axi_bvalid, m_axi_bvalid}), .s_axi_bready({m01_axi_bready, m_axi_bready}), - .s_axi_arid({4'b0001, m_axi_arid}), + .s_axi_arid({4'b1000, m_axi_arid}), .s_axi_araddr({m01_axi_araddr, m_axi_araddr}), .s_axi_arlen({m01_axi_arlen, m_axi_arlen}), .s_axi_arsize({m01_axi_arsize, m_axi_arsize}), @@ -627,7 +627,7 @@ module fpgaTop .m_axi_wlast({s01_axi_wlast, s00_axi_wlast}), .m_axi_wvalid({s01_axi_wvalid, s00_axi_wvalid}), .m_axi_wready({s01_axi_wready, s00_axi_wready}), - .m_axi_bid({4'b0001, s00_axi_bid}), + .m_axi_bid({4'b1000, s00_axi_bid}), .m_axi_bresp({s01_axi_bresp, s00_axi_bresp}), .m_axi_bvalid({s01_axi_bvalid, s00_axi_bvalid}), .m_axi_bready({s01_axi_bready, s00_axi_bready}), @@ -643,7 +643,7 @@ module fpgaTop .m_axi_araddr({s01_axi_araddr, s00_axi_araddr}), .m_axi_arlock({s01_axi_arlock, s00_axi_arlock}), .m_axi_arready({s01_axi_arready, s00_axi_arready}), - .m_axi_rid({4'b0, s00_axi_rid}), + .m_axi_rid({4'b1000, s00_axi_rid}), .m_axi_rdata({s01_axi_rdata, s00_axi_rdata}), .m_axi_rresp({s01_axi_rresp, s00_axi_rresp}), .m_axi_rvalid({s01_axi_rvalid, s00_axi_rvalid}), From 40f81d5da68202600f2f7d98fbec25643f10e5cf Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Fri, 26 May 2023 15:42:33 -0500 Subject: [PATCH 20/22] The Vivado-RISC-V SDC works. Wally is now booting through it. --- config/fpga/wally-config.vh | 6 +- fpga/constraints/debug2.xdc | 445 ++++++----- fpga/constraints/marked_debug.txt | 1 + fpga/generator/xlnx_axi_crossbar.tcl | 4 +- fpga/src/fpgaTop.v | 260 ++++--- .../src/uncore/newsdc/axi_sdc_controller.v | 2 +- pipelined/src/uncore/newsdc/sd_data_master.v | 8 +- .../src/uncore/newsdc/sd_data_serial_host.v | 2 +- src/generic/mem/ram1p1rwbe.sv | 8 +- src/generic/mem/rom1p1r.sv | 735 +++--------------- src/mmu/adrdecs.sv | 1 - src/uncore/ram_ahb.sv | 2 +- src/uncore/uncore.sv | 60 +- src/wally/wallypipelinedsoc.sv | 49 +- tests/custom/boot/boot.c | 85 +- tests/custom/linker1000.x | 1 + 16 files changed, 639 insertions(+), 1030 deletions(-) diff --git a/config/fpga/wally-config.vh b/config/fpga/wally-config.vh index 007562a17..c89d3eec8 100644 --- a/config/fpga/wally-config.vh +++ b/config/fpga/wally-config.vh @@ -93,9 +93,9 @@ `define BOOTROM_BASE 56'h00001000 `define BOOTROM_RANGE 56'h00000FFF -`define UNCORE_RAM_SUPPORTED 1'b0 -`define UNCORE_RAM_BASE 56'h100000000 -`define UNCORE_RAM_RANGE 56'h07FFFFFF +`define UNCORE_RAM_SUPPORTED 1'b1 +`define UNCORE_RAM_BASE 56'h000002000 +`define UNCORE_RAM_RANGE 56'h000000FFF `define EXT_MEM_SUPPORTED 1'b1 `define EXT_MEM_BASE 56'h80000000 diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index ec1d1d550..0db255fa0 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -717,433 +717,524 @@ set_property port_width 64 [get_debug_ports u_ila_0/probe138] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe138] connect_debug_port u_ila_0/probe138 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]] +# ============== AXI SDC STUFF ================ create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe139] +set_property port_width 1 [get_debug_ports u_ila_0/probe139] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe139] -connect_debug_port u_ila_0/probe139 [get_nets [list {m_axi_awid[0]} {m_axi_awid[1]} {m_axi_awid[2]} {m_axi_awid[3]} ]] - +connect_debug_port u_ila_0/probe139 [get_nets [list {axiSDC/clock_posedge}]] create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe140] +set_property port_width 32 [get_debug_ports u_ila_0/probe140] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe140] -connect_debug_port u_ila_0/probe140 [get_nets [list {m_axi_awlen[0]} {m_axi_awlen[1]} {m_axi_awlen[2]} {m_axi_awlen[3]} {m_axi_awlen[4]} {m_axi_awlen[5]} {m_axi_awlen[6]} {m_axi_awlen[7]} ]] - +connect_debug_port u_ila_0/probe140 [get_nets [list {axiSDC/argument_reg[0]} {axiSDC/argument_reg[1]} {axiSDC/argument_reg[2]} {axiSDC/argument_reg[3]} {axiSDC/argument_reg[4]} {axiSDC/argument_reg[5]} {axiSDC/argument_reg[6]} {axiSDC/argument_reg[7]} {axiSDC/argument_reg[8]} {axiSDC/argument_reg[9]} {axiSDC/argument_reg[10]} {axiSDC/argument_reg[11]} {axiSDC/argument_reg[12]} {axiSDC/argument_reg[13]} {axiSDC/argument_reg[14]} {axiSDC/argument_reg[15]} {axiSDC/argument_reg[16]} {axiSDC/argument_reg[17]} {axiSDC/argument_reg[18]} {axiSDC/argument_reg[19]} {axiSDC/argument_reg[20]} {axiSDC/argument_reg[21]} {axiSDC/argument_reg[22]} {axiSDC/argument_reg[23]} {axiSDC/argument_reg[24]} {axiSDC/argument_reg[25]} {axiSDC/argument_reg[26]} {axiSDC/argument_reg[27]} {axiSDC/argument_reg[28]} {axiSDC/argument_reg[29]} {axiSDC/argument_reg[30]} {axiSDC/argument_reg[31]} ]] create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe141] +set_property port_width 25 [get_debug_ports u_ila_0/probe141] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe141] -connect_debug_port u_ila_0/probe141 [get_nets [list {m_axi_awsize[0]} {m_axi_awsize[1]} {m_axi_awsize[2]} ]] - +connect_debug_port u_ila_0/probe141 [get_nets [list {axiSDC/cmd_timeout_reg[0]} {axiSDC/cmd_timeout_reg[1]} {axiSDC/cmd_timeout_reg[2]} {axiSDC/cmd_timeout_reg[3]} {axiSDC/cmd_timeout_reg[4]} {axiSDC/cmd_timeout_reg[5]} {axiSDC/cmd_timeout_reg[6]} {axiSDC/cmd_timeout_reg[7]} {axiSDC/cmd_timeout_reg[8]} {axiSDC/cmd_timeout_reg[9]} {axiSDC/cmd_timeout_reg[10]} {axiSDC/cmd_timeout_reg[11]} {axiSDC/cmd_timeout_reg[12]} {axiSDC/cmd_timeout_reg[13]} {axiSDC/cmd_timeout_reg[14]} {axiSDC/cmd_timeout_reg[15]} {axiSDC/cmd_timeout_reg[16]} {axiSDC/cmd_timeout_reg[17]} {axiSDC/cmd_timeout_reg[18]} {axiSDC/cmd_timeout_reg[19]} {axiSDC/cmd_timeout_reg[20]} {axiSDC/cmd_timeout_reg[21]} {axiSDC/cmd_timeout_reg[22]} {axiSDC/cmd_timeout_reg[23]} {axiSDC/cmd_timeout_reg[24]} ]] create_debug_port u_ila_0 probe -set_property port_width 2 [get_debug_ports u_ila_0/probe142] +set_property port_width 28 [get_debug_ports u_ila_0/probe142] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe142] -connect_debug_port u_ila_0/probe142 [get_nets [list {m_axi_awburst[0]} {m_axi_awburst[1]} ]] - +connect_debug_port u_ila_0/probe142 [get_nets [list {axiSDC/data_timeout_reg[0]} {axiSDC/data_timeout_reg[1]} {axiSDC/data_timeout_reg[2]} {axiSDC/data_timeout_reg[3]} {axiSDC/data_timeout_reg[4]} {axiSDC/data_timeout_reg[5]} {axiSDC/data_timeout_reg[6]} {axiSDC/data_timeout_reg[7]} {axiSDC/data_timeout_reg[8]} {axiSDC/data_timeout_reg[9]} {axiSDC/data_timeout_reg[10]} {axiSDC/data_timeout_reg[11]} {axiSDC/data_timeout_reg[12]} {axiSDC/data_timeout_reg[13]} {axiSDC/data_timeout_reg[14]} {axiSDC/data_timeout_reg[15]} {axiSDC/data_timeout_reg[16]} {axiSDC/data_timeout_reg[17]} {axiSDC/data_timeout_reg[18]} {axiSDC/data_timeout_reg[19]} {axiSDC/data_timeout_reg[20]} {axiSDC/data_timeout_reg[21]} {axiSDC/data_timeout_reg[22]} {axiSDC/data_timeout_reg[23]} {axiSDC/data_timeout_reg[24]} {axiSDC/data_timeout_reg[25]} {axiSDC/data_timeout_reg[26]} {axiSDC/data_timeout_reg[27]} ]] create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe143] +set_property port_width 1 [get_debug_ports u_ila_0/probe143] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe143] -connect_debug_port u_ila_0/probe143 [get_nets [list {m_axi_awcache[0]} {m_axi_awcache[1]} {m_axi_awcache[2]} {m_axi_awcache[3]} ]] - +connect_debug_port u_ila_0/probe143 [get_nets [list {axiSDC/software_reset_reg}]] create_debug_port u_ila_0 probe set_property port_width 32 [get_debug_ports u_ila_0/probe144] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe144] -connect_debug_port u_ila_0/probe144 [get_nets [list {m_axi_awaddr[0]} {m_axi_awaddr[1]} {m_axi_awaddr[2]} {m_axi_awaddr[3]} {m_axi_awaddr[4]} {m_axi_awaddr[5]} {m_axi_awaddr[6]} {m_axi_awaddr[7]} {m_axi_awaddr[8]} {m_axi_awaddr[9]} {m_axi_awaddr[10]} {m_axi_awaddr[11]} {m_axi_awaddr[12]} {m_axi_awaddr[13]} {m_axi_awaddr[14]} {m_axi_awaddr[15]} {m_axi_awaddr[16]} {m_axi_awaddr[17]} {m_axi_awaddr[18]} {m_axi_awaddr[19]} {m_axi_awaddr[20]} {m_axi_awaddr[21]} {m_axi_awaddr[22]} {m_axi_awaddr[23]} {m_axi_awaddr[24]} {m_axi_awaddr[25]} {m_axi_awaddr[26]} {m_axi_awaddr[27]} {m_axi_awaddr[28]} {m_axi_awaddr[29]} {m_axi_awaddr[30]} {m_axi_awaddr[31]}]] - +connect_debug_port u_ila_0/probe144 [get_nets [list {axiSDC/response_0_reg[0]} {axiSDC/response_0_reg[1]} {axiSDC/response_0_reg[2]} {axiSDC/response_0_reg[3]} {axiSDC/response_0_reg[4]} {axiSDC/response_0_reg[5]} {axiSDC/response_0_reg[6]} {axiSDC/response_0_reg[7]} {axiSDC/response_0_reg[8]} {axiSDC/response_0_reg[9]} {axiSDC/response_0_reg[10]} {axiSDC/response_0_reg[11]} {axiSDC/response_0_reg[12]} {axiSDC/response_0_reg[13]} {axiSDC/response_0_reg[14]} {axiSDC/response_0_reg[15]} {axiSDC/response_0_reg[16]} {axiSDC/response_0_reg[17]} {axiSDC/response_0_reg[18]} {axiSDC/response_0_reg[19]} {axiSDC/response_0_reg[20]} {axiSDC/response_0_reg[21]} {axiSDC/response_0_reg[22]} {axiSDC/response_0_reg[23]} {axiSDC/response_0_reg[24]} {axiSDC/response_0_reg[25]} {axiSDC/response_0_reg[26]} {axiSDC/response_0_reg[27]} {axiSDC/response_0_reg[28]} {axiSDC/response_0_reg[29]} {axiSDC/response_0_reg[30]} {axiSDC/response_0_reg[31]} ]] create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe145] +set_property port_width 32 [get_debug_ports u_ila_0/probe145] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe145] -connect_debug_port u_ila_0/probe145 [get_nets [list {m_axi_awprot[0]} {m_axi_awprot[1]} {m_axi_awprot[2]} ]] - +connect_debug_port u_ila_0/probe145 [get_nets [list {axiSDC/response_1_reg[0]} {axiSDC/response_1_reg[1]} {axiSDC/response_1_reg[2]} {axiSDC/response_1_reg[3]} {axiSDC/response_1_reg[4]} {axiSDC/response_1_reg[5]} {axiSDC/response_1_reg[6]} {axiSDC/response_1_reg[7]} {axiSDC/response_1_reg[8]} {axiSDC/response_1_reg[9]} {axiSDC/response_1_reg[10]} {axiSDC/response_1_reg[11]} {axiSDC/response_1_reg[12]} {axiSDC/response_1_reg[13]} {axiSDC/response_1_reg[14]} {axiSDC/response_1_reg[15]} {axiSDC/response_1_reg[16]} {axiSDC/response_1_reg[17]} {axiSDC/response_1_reg[18]} {axiSDC/response_1_reg[19]} {axiSDC/response_1_reg[20]} {axiSDC/response_1_reg[21]} {axiSDC/response_1_reg[22]} {axiSDC/response_1_reg[23]} {axiSDC/response_1_reg[24]} {axiSDC/response_1_reg[25]} {axiSDC/response_1_reg[26]} {axiSDC/response_1_reg[27]} {axiSDC/response_1_reg[28]} {axiSDC/response_1_reg[29]} {axiSDC/response_1_reg[30]} {axiSDC/response_1_reg[31]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe146] +set_property port_width 32 [get_debug_ports u_ila_0/probe146] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe146] -connect_debug_port u_ila_0/probe146 [get_nets [list {m_axi_awvalid}]] - +connect_debug_port u_ila_0/probe146 [get_nets [list {axiSDC/response_2_reg[0]} {axiSDC/response_2_reg[1]} {axiSDC/response_2_reg[2]} {axiSDC/response_2_reg[3]} {axiSDC/response_2_reg[4]} {axiSDC/response_2_reg[5]} {axiSDC/response_2_reg[6]} {axiSDC/response_2_reg[7]} {axiSDC/response_2_reg[8]} {axiSDC/response_2_reg[9]} {axiSDC/response_2_reg[10]} {axiSDC/response_2_reg[11]} {axiSDC/response_2_reg[12]} {axiSDC/response_2_reg[13]} {axiSDC/response_2_reg[14]} {axiSDC/response_2_reg[15]} {axiSDC/response_2_reg[16]} {axiSDC/response_2_reg[17]} {axiSDC/response_2_reg[18]} {axiSDC/response_2_reg[19]} {axiSDC/response_2_reg[20]} {axiSDC/response_2_reg[21]} {axiSDC/response_2_reg[22]} {axiSDC/response_2_reg[23]} {axiSDC/response_2_reg[24]} {axiSDC/response_2_reg[25]} {axiSDC/response_2_reg[26]} {axiSDC/response_2_reg[27]} {axiSDC/response_2_reg[28]} {axiSDC/response_2_reg[29]} {axiSDC/response_2_reg[30]} {axiSDC/response_2_reg[31]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe147] +set_property port_width 32 [get_debug_ports u_ila_0/probe147] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe147] -connect_debug_port u_ila_0/probe147 [get_nets [list {m_axi_awready}]] - +connect_debug_port u_ila_0/probe147 [get_nets [list {axiSDC/dma_addr_reg[0]} {axiSDC/dma_addr_reg[1]} {axiSDC/dma_addr_reg[2]} {axiSDC/dma_addr_reg[3]} {axiSDC/dma_addr_reg[4]} {axiSDC/dma_addr_reg[5]} {axiSDC/dma_addr_reg[6]} {axiSDC/dma_addr_reg[7]} {axiSDC/dma_addr_reg[8]} {axiSDC/dma_addr_reg[9]} {axiSDC/dma_addr_reg[10]} {axiSDC/dma_addr_reg[11]} {axiSDC/dma_addr_reg[12]} {axiSDC/dma_addr_reg[13]} {axiSDC/dma_addr_reg[14]} {axiSDC/dma_addr_reg[15]} {axiSDC/dma_addr_reg[16]} {axiSDC/dma_addr_reg[17]} {axiSDC/dma_addr_reg[18]} {axiSDC/dma_addr_reg[19]} {axiSDC/dma_addr_reg[20]} {axiSDC/dma_addr_reg[21]} {axiSDC/dma_addr_reg[22]} {axiSDC/dma_addr_reg[23]} {axiSDC/dma_addr_reg[24]} {axiSDC/dma_addr_reg[25]} {axiSDC/dma_addr_reg[26]} {axiSDC/dma_addr_reg[27]} {axiSDC/dma_addr_reg[28]} {axiSDC/dma_addr_reg[29]} {axiSDC/dma_addr_reg[30]} {axiSDC/dma_addr_reg[31]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe148] +set_property port_width 12 [get_debug_ports u_ila_0/probe148] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe148] -connect_debug_port u_ila_0/probe148 [get_nets [list {m_axi_awlock}]] - +connect_debug_port u_ila_0/probe148 [get_nets [list {axiSDC/block_size_reg[0]} {axiSDC/block_size_reg[1]} {axiSDC/block_size_reg[2]} {axiSDC/block_size_reg[3]} {axiSDC/block_size_reg[4]} {axiSDC/block_size_reg[5]} {axiSDC/block_size_reg[6]} {axiSDC/block_size_reg[7]} {axiSDC/block_size_reg[8]} {axiSDC/block_size_reg[9]} {axiSDC/block_size_reg[10]} {axiSDC/block_size_reg[11]} ]] create_debug_port u_ila_0 probe -set_property port_width 64 [get_debug_ports u_ila_0/probe149] +set_property port_width 2 [get_debug_ports u_ila_0/probe149] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe149] -connect_debug_port u_ila_0/probe149 [get_nets [list {m_axi_wdata[0]} {m_axi_wdata[1]} {m_axi_wdata[2]} {m_axi_wdata[3]} {m_axi_wdata[4]} {m_axi_wdata[5]} {m_axi_wdata[6]} {m_axi_wdata[7]} {m_axi_wdata[8]} {m_axi_wdata[9]} {m_axi_wdata[10]} {m_axi_wdata[11]} {m_axi_wdata[12]} {m_axi_wdata[13]} {m_axi_wdata[14]} {m_axi_wdata[15]} {m_axi_wdata[16]} {m_axi_wdata[17]} {m_axi_wdata[18]} {m_axi_wdata[19]} {m_axi_wdata[20]} {m_axi_wdata[21]} {m_axi_wdata[22]} {m_axi_wdata[23]} {m_axi_wdata[24]} {m_axi_wdata[25]} {m_axi_wdata[26]} {m_axi_wdata[27]} {m_axi_wdata[28]} {m_axi_wdata[29]} {m_axi_wdata[30]} {m_axi_wdata[31]} {m_axi_wdata[32]} {m_axi_wdata[33]} {m_axi_wdata[34]} {m_axi_wdata[35]} {m_axi_wdata[36]} {m_axi_wdata[37]} {m_axi_wdata[38]} {m_axi_wdata[39]} {m_axi_wdata[40]} {m_axi_wdata[41]} {m_axi_wdata[42]} {m_axi_wdata[43]} {m_axi_wdata[44]} {m_axi_wdata[45]} {m_axi_wdata[46]} {m_axi_wdata[47]} {m_axi_wdata[48]} {m_axi_wdata[49]} {m_axi_wdata[50]} {m_axi_wdata[51]} {m_axi_wdata[52]} {m_axi_wdata[53]} {m_axi_wdata[54]} {m_axi_wdata[55]} {m_axi_wdata[56]} {m_axi_wdata[57]} {m_axi_wdata[58]} {m_axi_wdata[59]} {m_axi_wdata[60]} {m_axi_wdata[61]} {m_axi_wdata[62]} {m_axi_wdata[63]} ]] - +connect_debug_port u_ila_0/probe149 [get_nets [list {axiSDC/controller_setting_reg[0]} {axiSDC/controller_setting_reg[1]} ]] create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe150] +set_property port_width 5 [get_debug_ports u_ila_0/probe150] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe150] -connect_debug_port u_ila_0/probe150 [get_nets [list {m_axi_wstrb[0]} {m_axi_wstrb[1]} {m_axi_wstrb[2]} {m_axi_wstrb[3]} {m_axi_wstrb[4]} {m_axi_wstrb[5]} {m_axi_wstrb[6]} {m_axi_wstrb[7]} ]] - +connect_debug_port u_ila_0/probe150 [get_nets [list {axiSDC/cmd_int_status_reg[0]} {axiSDC/cmd_int_status_reg[1]} {axiSDC/cmd_int_status_reg[2]} {axiSDC/cmd_int_status_reg[3]} {axiSDC/cmd_int_status_reg[4]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe151] +set_property port_width 6 [get_debug_ports u_ila_0/probe151] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe151] -connect_debug_port u_ila_0/probe151 [get_nets [list {m_axi_wlast}]] - +connect_debug_port u_ila_0/probe151 [get_nets [list {axiSDC/data_int_status_reg[0]} {axiSDC/data_int_status_reg[1]} {axiSDC/data_int_status_reg[2]} {axiSDC/data_int_status_reg[3]} {axiSDC/data_int_status_reg[4]} {axiSDC/data_int_status_reg[5]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe152] +set_property port_width 6 [get_debug_ports u_ila_0/probe152] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe152] -connect_debug_port u_ila_0/probe152 [get_nets [list {m_axi_wvalid}]] - +connect_debug_port u_ila_0/probe152 [get_nets [list {axiSDC/data_int_status[0]} {axiSDC/data_int_status[1]} {axiSDC/data_int_status[2]} {axiSDC/data_int_status[3]} {axiSDC/data_int_status[4]} {axiSDC/data_int_status[5]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe153] +set_property port_width 5 [get_debug_ports u_ila_0/probe153] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe153] -connect_debug_port u_ila_0/probe153 [get_nets [list {m_axi_wready}]] - +connect_debug_port u_ila_0/probe153 [get_nets [list {axiSDC/cmd_int_enable_reg[0]} {axiSDC/cmd_int_enable_reg[1]} {axiSDC/cmd_int_enable_reg[2]} {axiSDC/cmd_int_enable_reg[3]} {axiSDC/cmd_int_enable_reg[4]} ]] create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe154] +set_property port_width 6 [get_debug_ports u_ila_0/probe154] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe154] -connect_debug_port u_ila_0/probe154 [get_nets [list {m_axi_bid[0]} {m_axi_bid[1]} {m_axi_bid[2]} {m_axi_bid[3]} ]] - +connect_debug_port u_ila_0/probe154 [get_nets [list {axiSDC/data_int_enable_reg[0]} {axiSDC/data_int_enable_reg[1]} {axiSDC/data_int_enable_reg[2]} {axiSDC/data_int_enable_reg[3]} {axiSDC/data_int_enable_reg[4]} {axiSDC/data_int_enable_reg[5]} ]] create_debug_port u_ila_0 probe -set_property port_width 2 [get_debug_ports u_ila_0/probe155] +set_property port_width 16 [get_debug_ports u_ila_0/probe155] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe155] -connect_debug_port u_ila_0/probe155 [get_nets [list {m_axi_bresp[0]} {m_axi_bresp[1]} ]] - +connect_debug_port u_ila_0/probe155 [get_nets [list {axiSDC/block_count_reg[0]} {axiSDC/block_count_reg[1]} {axiSDC/block_count_reg[2]} {axiSDC/block_count_reg[3]} {axiSDC/block_count_reg[4]} {axiSDC/block_count_reg[5]} {axiSDC/block_count_reg[6]} {axiSDC/block_count_reg[7]} {axiSDC/block_count_reg[8]} {axiSDC/block_count_reg[9]} {axiSDC/block_count_reg[10]} {axiSDC/block_count_reg[11]} {axiSDC/block_count_reg[12]} {axiSDC/block_count_reg[13]} {axiSDC/block_count_reg[14]} {axiSDC/block_count_reg[15]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe156] +set_property port_width 8 [get_debug_ports u_ila_0/probe156] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe156] -connect_debug_port u_ila_0/probe156 [get_nets [list {m_axi_bvalid}]] - +connect_debug_port u_ila_0/probe156 [get_nets [list {axiSDC/clock_divider_reg[0]} {axiSDC/clock_divider_reg[1]} {axiSDC/clock_divider_reg[2]} {axiSDC/clock_divider_reg[3]} {axiSDC/clock_divider_reg[4]} {axiSDC/clock_divider_reg[5]} {axiSDC/clock_divider_reg[6]} {axiSDC/clock_divider_reg[7]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe157] +set_property port_width 4 [get_debug_ports u_ila_0/probe157] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe157] -connect_debug_port u_ila_0/probe157 [get_nets [list {m_axi_bready}]] - +connect_debug_port u_ila_0/probe157 [get_nets [list {s00_axi_awid[0]} {s00_axi_awid[1]} {s00_axi_awid[2]} {s00_axi_awid[3]} ]] create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe158] +set_property port_width 32 [get_debug_ports u_ila_0/probe158] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe158] -connect_debug_port u_ila_0/probe158 [get_nets [list {m_axi_arid[0]} {m_axi_arid[1]} {m_axi_arid[2]} {m_axi_arid[3]} ]] - +connect_debug_port u_ila_0/probe158 [get_nets [list {s00_axi_awaddr[0]} {s00_axi_awaddr[1]} {s00_axi_awaddr[2]} {s00_axi_awaddr[3]} {s00_axi_awaddr[4]} {s00_axi_awaddr[5]} {s00_axi_awaddr[6]} {s00_axi_awaddr[7]} {s00_axi_awaddr[8]} {s00_axi_awaddr[9]} {s00_axi_awaddr[10]} {s00_axi_awaddr[11]} {s00_axi_awaddr[12]} {s00_axi_awaddr[13]} {s00_axi_awaddr[14]} {s00_axi_awaddr[15]} {s00_axi_awaddr[16]} {s00_axi_awaddr[17]} {s00_axi_awaddr[18]} {s00_axi_awaddr[19]} {s00_axi_awaddr[20]} {s00_axi_awaddr[21]} {s00_axi_awaddr[22]} {s00_axi_awaddr[23]} {s00_axi_awaddr[24]} {s00_axi_awaddr[25]} {s00_axi_awaddr[26]} {s00_axi_awaddr[27]} {s00_axi_awaddr[28]} {s00_axi_awaddr[29]} {s00_axi_awaddr[30]} {s00_axi_awaddr[31]} ]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe159] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe159] -connect_debug_port u_ila_0/probe159 [get_nets [list {m_axi_arlen[0]} {m_axi_arlen[1]} {m_axi_arlen[2]} {m_axi_arlen[3]} {m_axi_arlen[4]} {m_axi_arlen[5]} {m_axi_arlen[6]} {m_axi_arlen[7]} ]] - +connect_debug_port u_ila_0/probe159 [get_nets [list {s00_axi_awlen[0]} {s00_axi_awlen[1]} {s00_axi_awlen[2]} {s00_axi_awlen[3]} {s00_axi_awlen[4]} {s00_axi_awlen[5]} {s00_axi_awlen[6]} {s00_axi_awlen[7]} ]] create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe160] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe160] -connect_debug_port u_ila_0/probe160 [get_nets [list {m_axi_arsize[0]} {m_axi_arsize[1]} {m_axi_arsize[2]} ]] - +connect_debug_port u_ila_0/probe160 [get_nets [list {s00_axi_awsize[0]} {s00_axi_awsize[1]} {s00_axi_awsize[2]} ]] create_debug_port u_ila_0 probe set_property port_width 2 [get_debug_ports u_ila_0/probe161] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe161] -connect_debug_port u_ila_0/probe161 [get_nets [list {m_axi_arburst[0]} {m_axi_arburst[1]} ]] - +connect_debug_port u_ila_0/probe161 [get_nets [list {s00_axi_awburst[0]} {s00_axi_awburst[1]} ]] create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe162] +set_property port_width 1 [get_debug_ports u_ila_0/probe162] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe162] -connect_debug_port u_ila_0/probe162 [get_nets [list {m_axi_arprot[0]} {m_axi_arprot[1]} {m_axi_arprot[2]} ]] - +connect_debug_port u_ila_0/probe162 [get_nets [list {s00_axi_awlock}]] create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe163] +set_property port_width 1 [get_debug_ports u_ila_0/probe163] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe163] -connect_debug_port u_ila_0/probe163 [get_nets [list {m_axi_arcache[0]} {m_axi_arcache[1]} {m_axi_arcache[2]} {m_axi_arcache[3]} ]] - +connect_debug_port u_ila_0/probe163 [get_nets [list {s00_axi_awvalid}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe164] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe164] -connect_debug_port u_ila_0/probe164 [get_nets [list {m_axi_arvalid}]] - +connect_debug_port u_ila_0/probe164 [get_nets [list {s00_axi_awready}]] create_debug_port u_ila_0 probe -set_property port_width 31 [get_debug_ports u_ila_0/probe165] +set_property port_width 64 [get_debug_ports u_ila_0/probe165] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe165] -connect_debug_port u_ila_0/probe165 [get_nets [list {m_axi_araddr[0]} {m_axi_araddr[1]} {m_axi_araddr[2]} {m_axi_araddr[3]} {m_axi_araddr[4]} {m_axi_araddr[5]} {m_axi_araddr[6]} {m_axi_araddr[7]} {m_axi_araddr[8]} {m_axi_araddr[9]} {m_axi_araddr[10]} {m_axi_araddr[11]} {m_axi_araddr[12]} {m_axi_araddr[13]} {m_axi_araddr[14]} {m_axi_araddr[15]} {m_axi_araddr[16]} {m_axi_araddr[17]} {m_axi_araddr[18]} {m_axi_araddr[19]} {m_axi_araddr[20]} {m_axi_araddr[21]} {m_axi_araddr[22]} {m_axi_araddr[23]} {m_axi_araddr[24]} {m_axi_araddr[25]} {m_axi_araddr[26]} {m_axi_araddr[27]} {m_axi_araddr[28]} {m_axi_araddr[29]} {m_axi_araddr[30]} ]] - +connect_debug_port u_ila_0/probe165 [get_nets [list {s00_axi_wdata[0]} {s00_axi_wdata[1]} {s00_axi_wdata[2]} {s00_axi_wdata[3]} {s00_axi_wdata[4]} {s00_axi_wdata[5]} {s00_axi_wdata[6]} {s00_axi_wdata[7]} {s00_axi_wdata[8]} {s00_axi_wdata[9]} {s00_axi_wdata[10]} {s00_axi_wdata[11]} {s00_axi_wdata[12]} {s00_axi_wdata[13]} {s00_axi_wdata[14]} {s00_axi_wdata[15]} {s00_axi_wdata[16]} {s00_axi_wdata[17]} {s00_axi_wdata[18]} {s00_axi_wdata[19]} {s00_axi_wdata[20]} {s00_axi_wdata[21]} {s00_axi_wdata[22]} {s00_axi_wdata[23]} {s00_axi_wdata[24]} {s00_axi_wdata[25]} {s00_axi_wdata[26]} {s00_axi_wdata[27]} {s00_axi_wdata[28]} {s00_axi_wdata[29]} {s00_axi_wdata[30]} {s00_axi_wdata[31]} {s00_axi_wdata[32]} {s00_axi_wdata[33]} {s00_axi_wdata[34]} {s00_axi_wdata[35]} {s00_axi_wdata[36]} {s00_axi_wdata[37]} {s00_axi_wdata[38]} {s00_axi_wdata[39]} {s00_axi_wdata[40]} {s00_axi_wdata[41]} {s00_axi_wdata[42]} {s00_axi_wdata[43]} {s00_axi_wdata[44]} {s00_axi_wdata[45]} {s00_axi_wdata[46]} {s00_axi_wdata[47]} {s00_axi_wdata[48]} {s00_axi_wdata[49]} {s00_axi_wdata[50]} {s00_axi_wdata[51]} {s00_axi_wdata[52]} {s00_axi_wdata[53]} {s00_axi_wdata[54]} {s00_axi_wdata[55]} {s00_axi_wdata[56]} {s00_axi_wdata[57]} {s00_axi_wdata[58]} {s00_axi_wdata[59]} {s00_axi_wdata[60]} {s00_axi_wdata[61]} {s00_axi_wdata[62]} {s00_axi_wdata[63]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe166] +set_property port_width 8 [get_debug_ports u_ila_0/probe166] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe166] -connect_debug_port u_ila_0/probe166 [get_nets [list {m_axi_arlock}]] - +connect_debug_port u_ila_0/probe166 [get_nets [list {s00_axi_wstrb[0]} {s00_axi_wstrb[1]} {s00_axi_wstrb[2]} {s00_axi_wstrb[3]} {s00_axi_wstrb[4]} {s00_axi_wstrb[5]} {s00_axi_wstrb[6]} {s00_axi_wstrb[7]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe167] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe167] -connect_debug_port u_ila_0/probe167 [get_nets [list {m_axi_arready}]] - +connect_debug_port u_ila_0/probe167 [get_nets [list {s00_axi_wlast}]] create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe168] +set_property port_width 1 [get_debug_ports u_ila_0/probe168] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe168] -connect_debug_port u_ila_0/probe168 [get_nets [list {m_axi_rid[0]} {m_axi_rid[1]} {m_axi_rid[2]} {m_axi_rid[3]} ]] - +connect_debug_port u_ila_0/probe168 [get_nets [list {s00_axi_wvalid}]] create_debug_port u_ila_0 probe -set_property port_width 64 [get_debug_ports u_ila_0/probe169] +set_property port_width 1 [get_debug_ports u_ila_0/probe169] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe169] -connect_debug_port u_ila_0/probe169 [get_nets [list {m_axi_rdata[0]} {m_axi_rdata[1]} {m_axi_rdata[2]} {m_axi_rdata[3]} {m_axi_rdata[4]} {m_axi_rdata[5]} {m_axi_rdata[6]} {m_axi_rdata[7]} {m_axi_rdata[8]} {m_axi_rdata[9]} {m_axi_rdata[10]} {m_axi_rdata[11]} {m_axi_rdata[12]} {m_axi_rdata[13]} {m_axi_rdata[14]} {m_axi_rdata[15]} {m_axi_rdata[16]} {m_axi_rdata[17]} {m_axi_rdata[18]} {m_axi_rdata[19]} {m_axi_rdata[20]} {m_axi_rdata[21]} {m_axi_rdata[22]} {m_axi_rdata[23]} {m_axi_rdata[24]} {m_axi_rdata[25]} {m_axi_rdata[26]} {m_axi_rdata[27]} {m_axi_rdata[28]} {m_axi_rdata[29]} {m_axi_rdata[30]} {m_axi_rdata[31]} {m_axi_rdata[32]} {m_axi_rdata[33]} {m_axi_rdata[34]} {m_axi_rdata[35]} {m_axi_rdata[36]} {m_axi_rdata[37]} {m_axi_rdata[38]} {m_axi_rdata[39]} {m_axi_rdata[40]} {m_axi_rdata[41]} {m_axi_rdata[42]} {m_axi_rdata[43]} {m_axi_rdata[44]} {m_axi_rdata[45]} {m_axi_rdata[46]} {m_axi_rdata[47]} {m_axi_rdata[48]} {m_axi_rdata[49]} {m_axi_rdata[50]} {m_axi_rdata[51]} {m_axi_rdata[52]} {m_axi_rdata[53]} {m_axi_rdata[54]} {m_axi_rdata[55]} {m_axi_rdata[56]} {m_axi_rdata[57]} {m_axi_rdata[58]} {m_axi_rdata[59]} {m_axi_rdata[60]} {m_axi_rdata[61]} {m_axi_rdata[62]} {m_axi_rdata[63]} ]] - +connect_debug_port u_ila_0/probe169 [get_nets [list {s00_axi_wready}]] create_debug_port u_ila_0 probe set_property port_width 2 [get_debug_ports u_ila_0/probe170] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe170] -connect_debug_port u_ila_0/probe170 [get_nets [list {m_axi_rresp[0]} {m_axi_rresp[1]} ]] - +connect_debug_port u_ila_0/probe170 [get_nets [list {s00_axi_bresp[0]} {s00_axi_bresp[1]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe171] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe171] -connect_debug_port u_ila_0/probe171 [get_nets [list {m_axi_rvalid}]] - +connect_debug_port u_ila_0/probe171 [get_nets [list {s00_axi_bvalid}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe172] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe172] -connect_debug_port u_ila_0/probe172 [get_nets [list {m_axi_rlast}]] - +connect_debug_port u_ila_0/probe172 [get_nets [list {s00_axi_bready}]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe173] +set_property port_width 32 [get_debug_ports u_ila_0/probe173] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe173] -connect_debug_port u_ila_0/probe173 [get_nets [list {m_axi_rready}]] +connect_debug_port u_ila_0/probe173 [get_nets [list {s00_axi_araddr[0]} {s00_axi_araddr[1]} {s00_axi_araddr[2]} {s00_axi_araddr[3]} {s00_axi_araddr[4]} {s00_axi_araddr[5]} {s00_axi_araddr[6]} {s00_axi_araddr[7]} {s00_axi_araddr[8]} {s00_axi_araddr[9]} {s00_axi_araddr[10]} {s00_axi_araddr[11]} {s00_axi_araddr[12]} {s00_axi_araddr[13]} {s00_axi_araddr[14]} {s00_axi_araddr[15]} {s00_axi_araddr[16]} {s00_axi_araddr[17]} {s00_axi_araddr[18]} {s00_axi_araddr[19]} {s00_axi_araddr[20]} {s00_axi_araddr[21]} {s00_axi_araddr[22]} {s00_axi_araddr[23]} {s00_axi_araddr[24]} {s00_axi_araddr[25]} {s00_axi_araddr[26]} {s00_axi_araddr[27]} {s00_axi_araddr[28]} {s00_axi_araddr[29]} {s00_axi_araddr[30]} {s00_axi_araddr[31]} ]] -# ============== AXI SDC STUFF ================ create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe174] +set_property port_width 8 [get_debug_ports u_ila_0/probe174] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe174] -connect_debug_port u_ila_0/probe174 [get_nets [list {axiSDC/clock_posedge}]] +connect_debug_port u_ila_0/probe174 [get_nets [list {s00_axi_arlen[0]} {s00_axi_arlen[1]} {s00_axi_arlen[2]} {s00_axi_arlen[3]} {s00_axi_arlen[4]} {s00_axi_arlen[5]} {s00_axi_arlen[6]} {s00_axi_arlen[7]} ]] create_debug_port u_ila_0 probe -set_property port_width 32 [get_debug_ports u_ila_0/probe175] +set_property port_width 3 [get_debug_ports u_ila_0/probe175] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe175] -connect_debug_port u_ila_0/probe175 [get_nets [list {axiSDC/argument_reg[0]} {axiSDC/argument_reg[1]} {axiSDC/argument_reg[2]} {axiSDC/argument_reg[3]} {axiSDC/argument_reg[4]} {axiSDC/argument_reg[5]} {axiSDC/argument_reg[6]} {axiSDC/argument_reg[7]} {axiSDC/argument_reg[8]} {axiSDC/argument_reg[9]} {axiSDC/argument_reg[10]} {axiSDC/argument_reg[11]} {axiSDC/argument_reg[12]} {axiSDC/argument_reg[13]} {axiSDC/argument_reg[14]} {axiSDC/argument_reg[15]} {axiSDC/argument_reg[16]} {axiSDC/argument_reg[17]} {axiSDC/argument_reg[18]} {axiSDC/argument_reg[19]} {axiSDC/argument_reg[20]} {axiSDC/argument_reg[21]} {axiSDC/argument_reg[22]} {axiSDC/argument_reg[23]} {axiSDC/argument_reg[24]} {axiSDC/argument_reg[25]} {axiSDC/argument_reg[26]} {axiSDC/argument_reg[27]} {axiSDC/argument_reg[28]} {axiSDC/argument_reg[29]} {axiSDC/argument_reg[30]} {axiSDC/argument_reg[31]} ]] +connect_debug_port u_ila_0/probe175 [get_nets [list {s00_axi_arsize[0]} {s00_axi_arsize[1]} {s00_axi_arsize[2]} ]] create_debug_port u_ila_0 probe -set_property port_width 25 [get_debug_ports u_ila_0/probe176] +set_property port_width 2 [get_debug_ports u_ila_0/probe176] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe176] -connect_debug_port u_ila_0/probe176 [get_nets [list {axiSDC/cmd_timeout_reg[0]} {axiSDC/cmd_timeout_reg[1]} {axiSDC/cmd_timeout_reg[2]} {axiSDC/cmd_timeout_reg[3]} {axiSDC/cmd_timeout_reg[4]} {axiSDC/cmd_timeout_reg[5]} {axiSDC/cmd_timeout_reg[6]} {axiSDC/cmd_timeout_reg[7]} {axiSDC/cmd_timeout_reg[8]} {axiSDC/cmd_timeout_reg[9]} {axiSDC/cmd_timeout_reg[10]} {axiSDC/cmd_timeout_reg[11]} {axiSDC/cmd_timeout_reg[12]} {axiSDC/cmd_timeout_reg[13]} {axiSDC/cmd_timeout_reg[14]} {axiSDC/cmd_timeout_reg[15]} {axiSDC/cmd_timeout_reg[16]} {axiSDC/cmd_timeout_reg[17]} {axiSDC/cmd_timeout_reg[18]} {axiSDC/cmd_timeout_reg[19]} {axiSDC/cmd_timeout_reg[20]} {axiSDC/cmd_timeout_reg[21]} {axiSDC/cmd_timeout_reg[22]} {axiSDC/cmd_timeout_reg[23]} {axiSDC/cmd_timeout_reg[24]} ]] +connect_debug_port u_ila_0/probe176 [get_nets [list {s00_axi_arburst[0]} {s00_axi_arburst[1]} ]] create_debug_port u_ila_0 probe -set_property port_width 28 [get_debug_ports u_ila_0/probe177] +set_property port_width 1 [get_debug_ports u_ila_0/probe177] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe177] -connect_debug_port u_ila_0/probe177 [get_nets [list {axiSDC/data_timeout_reg[0]} {axiSDC/data_timeout_reg[1]} {axiSDC/data_timeout_reg[2]} {axiSDC/data_timeout_reg[3]} {axiSDC/data_timeout_reg[4]} {axiSDC/data_timeout_reg[5]} {axiSDC/data_timeout_reg[6]} {axiSDC/data_timeout_reg[7]} {axiSDC/data_timeout_reg[8]} {axiSDC/data_timeout_reg[9]} {axiSDC/data_timeout_reg[10]} {axiSDC/data_timeout_reg[11]} {axiSDC/data_timeout_reg[12]} {axiSDC/data_timeout_reg[13]} {axiSDC/data_timeout_reg[14]} {axiSDC/data_timeout_reg[15]} {axiSDC/data_timeout_reg[16]} {axiSDC/data_timeout_reg[17]} {axiSDC/data_timeout_reg[18]} {axiSDC/data_timeout_reg[19]} {axiSDC/data_timeout_reg[20]} {axiSDC/data_timeout_reg[21]} {axiSDC/data_timeout_reg[22]} {axiSDC/data_timeout_reg[23]} {axiSDC/data_timeout_reg[24]} {axiSDC/data_timeout_reg[25]} {axiSDC/data_timeout_reg[26]} {axiSDC/data_timeout_reg[27]} ]] +connect_debug_port u_ila_0/probe177 [get_nets [list {s00_axi_arvalid}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe178] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe178] -connect_debug_port u_ila_0/probe178 [get_nets [list {axiSDC/software_reset_reg}]] +connect_debug_port u_ila_0/probe178 [get_nets [list {s00_axi_arready}]] create_debug_port u_ila_0 probe -set_property port_width 32 [get_debug_ports u_ila_0/probe179] +set_property port_width 64 [get_debug_ports u_ila_0/probe179] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe179] -connect_debug_port u_ila_0/probe179 [get_nets [list {axiSDC/response_0_reg[0]} {axiSDC/response_0_reg[1]} {axiSDC/response_0_reg[2]} {axiSDC/response_0_reg[3]} {axiSDC/response_0_reg[4]} {axiSDC/response_0_reg[5]} {axiSDC/response_0_reg[6]} {axiSDC/response_0_reg[7]} {axiSDC/response_0_reg[8]} {axiSDC/response_0_reg[9]} {axiSDC/response_0_reg[10]} {axiSDC/response_0_reg[11]} {axiSDC/response_0_reg[12]} {axiSDC/response_0_reg[13]} {axiSDC/response_0_reg[14]} {axiSDC/response_0_reg[15]} {axiSDC/response_0_reg[16]} {axiSDC/response_0_reg[17]} {axiSDC/response_0_reg[18]} {axiSDC/response_0_reg[19]} {axiSDC/response_0_reg[20]} {axiSDC/response_0_reg[21]} {axiSDC/response_0_reg[22]} {axiSDC/response_0_reg[23]} {axiSDC/response_0_reg[24]} {axiSDC/response_0_reg[25]} {axiSDC/response_0_reg[26]} {axiSDC/response_0_reg[27]} {axiSDC/response_0_reg[28]} {axiSDC/response_0_reg[29]} {axiSDC/response_0_reg[30]} {axiSDC/response_0_reg[31]} ]] +connect_debug_port u_ila_0/probe179 [get_nets [list {s00_axi_rdata[0]} {s00_axi_rdata[1]} {s00_axi_rdata[2]} {s00_axi_rdata[3]} {s00_axi_rdata[4]} {s00_axi_rdata[5]} {s00_axi_rdata[6]} {s00_axi_rdata[7]} {s00_axi_rdata[8]} {s00_axi_rdata[9]} {s00_axi_rdata[10]} {s00_axi_rdata[11]} {s00_axi_rdata[12]} {s00_axi_rdata[13]} {s00_axi_rdata[14]} {s00_axi_rdata[15]} {s00_axi_rdata[16]} {s00_axi_rdata[17]} {s00_axi_rdata[18]} {s00_axi_rdata[19]} {s00_axi_rdata[20]} {s00_axi_rdata[21]} {s00_axi_rdata[22]} {s00_axi_rdata[23]} {s00_axi_rdata[24]} {s00_axi_rdata[25]} {s00_axi_rdata[26]} {s00_axi_rdata[27]} {s00_axi_rdata[28]} {s00_axi_rdata[29]} {s00_axi_rdata[30]} {s00_axi_rdata[31]} {s00_axi_rdata[32]} {s00_axi_rdata[33]} {s00_axi_rdata[34]} {s00_axi_rdata[35]} {s00_axi_rdata[36]} {s00_axi_rdata[37]} {s00_axi_rdata[38]} {s00_axi_rdata[39]} {s00_axi_rdata[40]} {s00_axi_rdata[41]} {s00_axi_rdata[42]} {s00_axi_rdata[43]} {s00_axi_rdata[44]} {s00_axi_rdata[45]} {s00_axi_rdata[46]} {s00_axi_rdata[47]} {s00_axi_rdata[48]} {s00_axi_rdata[49]} {s00_axi_rdata[50]} {s00_axi_rdata[51]} {s00_axi_rdata[52]} {s00_axi_rdata[53]} {s00_axi_rdata[54]} {s00_axi_rdata[55]} {s00_axi_rdata[56]} {s00_axi_rdata[57]} {s00_axi_rdata[58]} {s00_axi_rdata[59]} {s00_axi_rdata[60]} {s00_axi_rdata[61]} {s00_axi_rdata[62]} {s00_axi_rdata[63]} ]] create_debug_port u_ila_0 probe -set_property port_width 32 [get_debug_ports u_ila_0/probe180] +set_property port_width 2 [get_debug_ports u_ila_0/probe180] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe180] -connect_debug_port u_ila_0/probe180 [get_nets [list {axiSDC/response_1_reg[0]} {axiSDC/response_1_reg[1]} {axiSDC/response_1_reg[2]} {axiSDC/response_1_reg[3]} {axiSDC/response_1_reg[4]} {axiSDC/response_1_reg[5]} {axiSDC/response_1_reg[6]} {axiSDC/response_1_reg[7]} {axiSDC/response_1_reg[8]} {axiSDC/response_1_reg[9]} {axiSDC/response_1_reg[10]} {axiSDC/response_1_reg[11]} {axiSDC/response_1_reg[12]} {axiSDC/response_1_reg[13]} {axiSDC/response_1_reg[14]} {axiSDC/response_1_reg[15]} {axiSDC/response_1_reg[16]} {axiSDC/response_1_reg[17]} {axiSDC/response_1_reg[18]} {axiSDC/response_1_reg[19]} {axiSDC/response_1_reg[20]} {axiSDC/response_1_reg[21]} {axiSDC/response_1_reg[22]} {axiSDC/response_1_reg[23]} {axiSDC/response_1_reg[24]} {axiSDC/response_1_reg[25]} {axiSDC/response_1_reg[26]} {axiSDC/response_1_reg[27]} {axiSDC/response_1_reg[28]} {axiSDC/response_1_reg[29]} {axiSDC/response_1_reg[30]} {axiSDC/response_1_reg[31]} ]] +connect_debug_port u_ila_0/probe180 [get_nets [list {s00_axi_rresp[0]} {s00_axi_rresp[1]} ]] create_debug_port u_ila_0 probe -set_property port_width 32 [get_debug_ports u_ila_0/probe181] +set_property port_width 1 [get_debug_ports u_ila_0/probe181] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe181] -connect_debug_port u_ila_0/probe181 [get_nets [list {axiSDC/response_2_reg[0]} {axiSDC/response_2_reg[1]} {axiSDC/response_2_reg[2]} {axiSDC/response_2_reg[3]} {axiSDC/response_2_reg[4]} {axiSDC/response_2_reg[5]} {axiSDC/response_2_reg[6]} {axiSDC/response_2_reg[7]} {axiSDC/response_2_reg[8]} {axiSDC/response_2_reg[9]} {axiSDC/response_2_reg[10]} {axiSDC/response_2_reg[11]} {axiSDC/response_2_reg[12]} {axiSDC/response_2_reg[13]} {axiSDC/response_2_reg[14]} {axiSDC/response_2_reg[15]} {axiSDC/response_2_reg[16]} {axiSDC/response_2_reg[17]} {axiSDC/response_2_reg[18]} {axiSDC/response_2_reg[19]} {axiSDC/response_2_reg[20]} {axiSDC/response_2_reg[21]} {axiSDC/response_2_reg[22]} {axiSDC/response_2_reg[23]} {axiSDC/response_2_reg[24]} {axiSDC/response_2_reg[25]} {axiSDC/response_2_reg[26]} {axiSDC/response_2_reg[27]} {axiSDC/response_2_reg[28]} {axiSDC/response_2_reg[29]} {axiSDC/response_2_reg[30]} {axiSDC/response_2_reg[31]} ]] +connect_debug_port u_ila_0/probe181 [get_nets [list {s00_axi_rlast}]] create_debug_port u_ila_0 probe -set_property port_width 32 [get_debug_ports u_ila_0/probe182] +set_property port_width 1 [get_debug_ports u_ila_0/probe182] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe182] -connect_debug_port u_ila_0/probe182 [get_nets [list {axiSDC/dma_addr_reg[0]} {axiSDC/dma_addr_reg[1]} {axiSDC/dma_addr_reg[2]} {axiSDC/dma_addr_reg[3]} {axiSDC/dma_addr_reg[4]} {axiSDC/dma_addr_reg[5]} {axiSDC/dma_addr_reg[6]} {axiSDC/dma_addr_reg[7]} {axiSDC/dma_addr_reg[8]} {axiSDC/dma_addr_reg[9]} {axiSDC/dma_addr_reg[10]} {axiSDC/dma_addr_reg[11]} {axiSDC/dma_addr_reg[12]} {axiSDC/dma_addr_reg[13]} {axiSDC/dma_addr_reg[14]} {axiSDC/dma_addr_reg[15]} {axiSDC/dma_addr_reg[16]} {axiSDC/dma_addr_reg[17]} {axiSDC/dma_addr_reg[18]} {axiSDC/dma_addr_reg[19]} {axiSDC/dma_addr_reg[20]} {axiSDC/dma_addr_reg[21]} {axiSDC/dma_addr_reg[22]} {axiSDC/dma_addr_reg[23]} {axiSDC/dma_addr_reg[24]} {axiSDC/dma_addr_reg[25]} {axiSDC/dma_addr_reg[26]} {axiSDC/dma_addr_reg[27]} {axiSDC/dma_addr_reg[28]} {axiSDC/dma_addr_reg[29]} {axiSDC/dma_addr_reg[30]} {axiSDC/dma_addr_reg[31]} ]] +connect_debug_port u_ila_0/probe182 [get_nets [list {s00_axi_rvalid}]] create_debug_port u_ila_0 probe -set_property port_width 12 [get_debug_ports u_ila_0/probe183] +set_property port_width 1 [get_debug_ports u_ila_0/probe183] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe183] -connect_debug_port u_ila_0/probe183 [get_nets [list {axiSDC/block_size_reg[0]} {axiSDC/block_size_reg[1]} {axiSDC/block_size_reg[2]} {axiSDC/block_size_reg[3]} {axiSDC/block_size_reg[4]} {axiSDC/block_size_reg[5]} {axiSDC/block_size_reg[6]} {axiSDC/block_size_reg[7]} {axiSDC/block_size_reg[8]} {axiSDC/block_size_reg[9]} {axiSDC/block_size_reg[10]} {axiSDC/block_size_reg[11]} ]] +connect_debug_port u_ila_0/probe183 [get_nets [list {s00_axi_rready}]] create_debug_port u_ila_0 probe -set_property port_width 2 [get_debug_ports u_ila_0/probe184] +set_property port_width 4 [get_debug_ports u_ila_0/probe184] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe184] -connect_debug_port u_ila_0/probe184 [get_nets [list {axiSDC/controller_setting_reg[0]} {axiSDC/controller_setting_reg[1]} ]] +connect_debug_port u_ila_0/probe184 [get_nets [list {s00_axi_bid[0]} {s00_axi_bid[1]} {s00_axi_bid[2]} {s00_axi_bid[3]} ]] create_debug_port u_ila_0 probe -set_property port_width 5 [get_debug_ports u_ila_0/probe185] +set_property port_width 4 [get_debug_ports u_ila_0/probe185] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe185] -connect_debug_port u_ila_0/probe185 [get_nets [list {axiSDC/cmd_int_status_reg[0]} {axiSDC/cmd_int_status_reg[1]} {axiSDC/cmd_int_status_reg[2]} {axiSDC/cmd_int_status_reg[3]} {axiSDC/cmd_int_status_reg[4]} ]] +connect_debug_port u_ila_0/probe185 [get_nets [list {s00_axi_rid[0]} {s00_axi_rid[1]} {s00_axi_rid[2]} {s00_axi_rid[3]} ]] create_debug_port u_ila_0 probe -set_property port_width 6 [get_debug_ports u_ila_0/probe186] +set_property port_width 1 [get_debug_ports u_ila_0/probe186] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe186] -connect_debug_port u_ila_0/probe186 [get_nets [list {axiSDC/data_int_status_reg[0]} {axiSDC/data_int_status_reg[1]} {axiSDC/data_int_status_reg[2]} {axiSDC/data_int_status_reg[3]} {axiSDC/data_int_status_reg[4]} {axiSDC/data_int_status_reg[5]} ]] +connect_debug_port u_ila_0/probe186 [get_nets [list {s00_axi_awlock}]] + create_debug_port u_ila_0 probe -set_property port_width 6 [get_debug_ports u_ila_0/probe187] +set_property port_width 4 [get_debug_ports u_ila_0/probe187] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe187] -connect_debug_port u_ila_0/probe187 [get_nets [list {axiSDC/data_int_status[0]} {axiSDC/data_int_status[1]} {axiSDC/data_int_status[2]} {axiSDC/data_int_status[3]} {axiSDC/data_int_status[4]} {axiSDC/data_int_status[5]} ]] +connect_debug_port u_ila_0/probe187 [get_nets [list {m01_axi_awid[0]} {m01_axi_awid[1]} {m01_axi_awid[2]} {m01_axi_awid[3]} ]] create_debug_port u_ila_0 probe -set_property port_width 5 [get_debug_ports u_ila_0/probe188] +set_property port_width 32 [get_debug_ports u_ila_0/probe188] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe188] -connect_debug_port u_ila_0/probe188 [get_nets [list {axiSDC/cmd_int_enable_reg[0]} {axiSDC/cmd_int_enable_reg[1]} {axiSDC/cmd_int_enable_reg[2]} {axiSDC/cmd_int_enable_reg[3]} {axiSDC/cmd_int_enable_reg[4]} ]] +connect_debug_port u_ila_0/probe188 [get_nets [list {m01_axi_awaddr[0]} {m01_axi_awaddr[1]} {m01_axi_awaddr[2]} {m01_axi_awaddr[3]} {m01_axi_awaddr[4]} {m01_axi_awaddr[5]} {m01_axi_awaddr[6]} {m01_axi_awaddr[7]} {m01_axi_awaddr[8]} {m01_axi_awaddr[9]} {m01_axi_awaddr[10]} {m01_axi_awaddr[11]} {m01_axi_awaddr[12]} {m01_axi_awaddr[13]} {m01_axi_awaddr[14]} {m01_axi_awaddr[15]} {m01_axi_awaddr[16]} {m01_axi_awaddr[17]} {m01_axi_awaddr[18]} {m01_axi_awaddr[19]} {m01_axi_awaddr[20]} {m01_axi_awaddr[21]} {m01_axi_awaddr[22]} {m01_axi_awaddr[23]} {m01_axi_awaddr[24]} {m01_axi_awaddr[25]} {m01_axi_awaddr[26]} {m01_axi_awaddr[27]} {m01_axi_awaddr[28]} {m01_axi_awaddr[29]} {m01_axi_awaddr[30]} {m01_axi_awaddr[31]} ]] create_debug_port u_ila_0 probe -set_property port_width 6 [get_debug_ports u_ila_0/probe189] +set_property port_width 8 [get_debug_ports u_ila_0/probe189] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe189] -connect_debug_port u_ila_0/probe189 [get_nets [list {axiSDC/data_int_enable_reg[0]} {axiSDC/data_int_enable_reg[1]} {axiSDC/data_int_enable_reg[2]} {axiSDC/data_int_enable_reg[3]} {axiSDC/data_int_enable_reg[4]} {axiSDC/data_int_enable_reg[5]} ]] +connect_debug_port u_ila_0/probe189 [get_nets [list {m01_axi_awlen[0]} {m01_axi_awlen[1]} {m01_axi_awlen[2]} {m01_axi_awlen[3]} {m01_axi_awlen[4]} {m01_axi_awlen[5]} {m01_axi_awlen[6]} {m01_axi_awlen[7]} ]] create_debug_port u_ila_0 probe -set_property port_width 16 [get_debug_ports u_ila_0/probe190] +set_property port_width 3 [get_debug_ports u_ila_0/probe190] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe190] -connect_debug_port u_ila_0/probe190 [get_nets [list {axiSDC/block_count_reg[0]} {axiSDC/block_count_reg[1]} {axiSDC/block_count_reg[2]} {axiSDC/block_count_reg[3]} {axiSDC/block_count_reg[4]} {axiSDC/block_count_reg[5]} {axiSDC/block_count_reg[6]} {axiSDC/block_count_reg[7]} {axiSDC/block_count_reg[8]} {axiSDC/block_count_reg[9]} {axiSDC/block_count_reg[10]} {axiSDC/block_count_reg[11]} {axiSDC/block_count_reg[12]} {axiSDC/block_count_reg[13]} {axiSDC/block_count_reg[14]} {axiSDC/block_count_reg[15]} ]] +connect_debug_port u_ila_0/probe190 [get_nets [list {m01_axi_awsize[0]} {m01_axi_awsize[1]} {m01_axi_awsize[2]} ]] create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe191] +set_property port_width 2 [get_debug_ports u_ila_0/probe191] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe191] -connect_debug_port u_ila_0/probe191 [get_nets [list {axiSDC/clock_divider_reg[0]} {axiSDC/clock_divider_reg[1]} {axiSDC/clock_divider_reg[2]} {axiSDC/clock_divider_reg[3]} {axiSDC/clock_divider_reg[4]} {axiSDC/clock_divider_reg[5]} {axiSDC/clock_divider_reg[6]} {axiSDC/clock_divider_reg[7]} ]] +connect_debug_port u_ila_0/probe191 [get_nets [list {m01_axi_awburst[0]} {m01_axi_awburst[1]} ]] create_debug_port u_ila_0 probe -set_property port_width 32 [get_debug_ports u_ila_0/probe192] +set_property port_width 1 [get_debug_ports u_ila_0/probe192] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe192] -connect_debug_port u_ila_0/probe192 [get_nets [list {SDCin_axi_awaddr[0]} {SDCin_axi_awaddr[1]} {SDCin_axi_awaddr[2]} {SDCin_axi_awaddr[3]} {SDCin_axi_awaddr[4]} {SDCin_axi_awaddr[5]} {SDCin_axi_awaddr[6]} {SDCin_axi_awaddr[7]} {SDCin_axi_awaddr[8]} {SDCin_axi_awaddr[9]} {SDCin_axi_awaddr[10]} {SDCin_axi_awaddr[11]} {SDCin_axi_awaddr[12]} {SDCin_axi_awaddr[13]} {SDCin_axi_awaddr[14]} {SDCin_axi_awaddr[15]} {SDCin_axi_awaddr[16]} {SDCin_axi_awaddr[17]} {SDCin_axi_awaddr[18]} {SDCin_axi_awaddr[19]} {SDCin_axi_awaddr[20]} {SDCin_axi_awaddr[21]} {SDCin_axi_awaddr[22]} {SDCin_axi_awaddr[23]} {SDCin_axi_awaddr[24]} {SDCin_axi_awaddr[25]} {SDCin_axi_awaddr[26]} {SDCin_axi_awaddr[27]} {SDCin_axi_awaddr[28]} {SDCin_axi_awaddr[29]} {SDCin_axi_awaddr[30]} {SDCin_axi_awaddr[31]} ]] +connect_debug_port u_ila_0/probe192 [get_nets [list {m01_axi_awlock}]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe193] +set_property port_width 4 [get_debug_ports u_ila_0/probe193] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe193] -connect_debug_port u_ila_0/probe193 [get_nets [list {SDCin_axi_awvalid}]] +connect_debug_port u_ila_0/probe193 [get_nets [list {m01_axi_awcache[0]} {m01_axi_awcache[1]} {m01_axi_awcache[2]} {m01_axi_awcache[3]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe194] +set_property port_width 3 [get_debug_ports u_ila_0/probe194] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe194] -connect_debug_port u_ila_0/probe194 [get_nets [list {SDCin_axi_awready}]] +connect_debug_port u_ila_0/probe194 [get_nets [list {m01_axi_awprot[0]} {m01_axi_awprot[1]} {m01_axi_awprot[2]} ]] create_debug_port u_ila_0 probe -set_property port_width 32 [get_debug_ports u_ila_0/probe195] +set_property port_width 4 [get_debug_ports u_ila_0/probe195] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe195] -connect_debug_port u_ila_0/probe195 [get_nets [list {SDCin_axi_wdata[0]} {SDCin_axi_wdata[1]} {SDCin_axi_wdata[2]} {SDCin_axi_wdata[3]} {SDCin_axi_wdata[4]} {SDCin_axi_wdata[5]} {SDCin_axi_wdata[6]} {SDCin_axi_wdata[7]} {SDCin_axi_wdata[8]} {SDCin_axi_wdata[9]} {SDCin_axi_wdata[10]} {SDCin_axi_wdata[11]} {SDCin_axi_wdata[12]} {SDCin_axi_wdata[13]} {SDCin_axi_wdata[14]} {SDCin_axi_wdata[15]} {SDCin_axi_wdata[16]} {SDCin_axi_wdata[17]} {SDCin_axi_wdata[18]} {SDCin_axi_wdata[19]} {SDCin_axi_wdata[20]} {SDCin_axi_wdata[21]} {SDCin_axi_wdata[22]} {SDCin_axi_wdata[23]} {SDCin_axi_wdata[24]} {SDCin_axi_wdata[25]} {SDCin_axi_wdata[26]} {SDCin_axi_wdata[27]} {SDCin_axi_wdata[28]} {SDCin_axi_wdata[29]} {SDCin_axi_wdata[30]} {SDCin_axi_wdata[31]} ]] +connect_debug_port u_ila_0/probe195 [get_nets [list {m01_axi_awregion[0]} {m01_axi_awregion[1]} {m01_axi_awregion[2]} {m01_axi_awregion[3]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe196] +set_property port_width 4 [get_debug_ports u_ila_0/probe196] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe196] -connect_debug_port u_ila_0/probe196 [get_nets [list {SDCin_axi_wvalid}]] +connect_debug_port u_ila_0/probe196 [get_nets [list {m01_axi_awqos[0]} {m01_axi_awqos[1]} {m01_axi_awqos[2]} {m01_axi_awqos[3]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe197] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe197] -connect_debug_port u_ila_0/probe197 [get_nets [list {SDCin_axi_wready}]] +connect_debug_port u_ila_0/probe197 [get_nets [list {m01_axi_awvalid}]] create_debug_port u_ila_0 probe -set_property port_width 2 [get_debug_ports u_ila_0/probe198] +set_property port_width 1 [get_debug_ports u_ila_0/probe198] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe198] -connect_debug_port u_ila_0/probe198 [get_nets [list {SDCin_axi_bresp[0]} {SDCin_axi_bresp[1]} ]] +connect_debug_port u_ila_0/probe198 [get_nets [list {m01_axi_awready}]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe199] +set_property port_width 64 [get_debug_ports u_ila_0/probe199] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe199] -connect_debug_port u_ila_0/probe199 [get_nets [list {SDCin_axi_bvalid}]] +connect_debug_port u_ila_0/probe199 [get_nets [list {m01_axi_wdata[0]} {m01_axi_wdata[1]} {m01_axi_wdata[2]} {m01_axi_wdata[3]} {m01_axi_wdata[4]} {m01_axi_wdata[5]} {m01_axi_wdata[6]} {m01_axi_wdata[7]} {m01_axi_wdata[8]} {m01_axi_wdata[9]} {m01_axi_wdata[10]} {m01_axi_wdata[11]} {m01_axi_wdata[12]} {m01_axi_wdata[13]} {m01_axi_wdata[14]} {m01_axi_wdata[15]} {m01_axi_wdata[16]} {m01_axi_wdata[17]} {m01_axi_wdata[18]} {m01_axi_wdata[19]} {m01_axi_wdata[20]} {m01_axi_wdata[21]} {m01_axi_wdata[22]} {m01_axi_wdata[23]} {m01_axi_wdata[24]} {m01_axi_wdata[25]} {m01_axi_wdata[26]} {m01_axi_wdata[27]} {m01_axi_wdata[28]} {m01_axi_wdata[29]} {m01_axi_wdata[30]} {m01_axi_wdata[31]} {m01_axi_wdata[32]} {m01_axi_wdata[33]} {m01_axi_wdata[34]} {m01_axi_wdata[35]} {m01_axi_wdata[36]} {m01_axi_wdata[37]} {m01_axi_wdata[38]} {m01_axi_wdata[39]} {m01_axi_wdata[40]} {m01_axi_wdata[41]} {m01_axi_wdata[42]} {m01_axi_wdata[43]} {m01_axi_wdata[44]} {m01_axi_wdata[45]} {m01_axi_wdata[46]} {m01_axi_wdata[47]} {m01_axi_wdata[48]} {m01_axi_wdata[49]} {m01_axi_wdata[50]} {m01_axi_wdata[51]} {m01_axi_wdata[52]} {m01_axi_wdata[53]} {m01_axi_wdata[54]} {m01_axi_wdata[55]} {m01_axi_wdata[56]} {m01_axi_wdata[57]} {m01_axi_wdata[58]} {m01_axi_wdata[59]} {m01_axi_wdata[60]} {m01_axi_wdata[61]} {m01_axi_wdata[62]} {m01_axi_wdata[63]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe200] +set_property port_width 4 [get_debug_ports u_ila_0/probe200] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe200] -connect_debug_port u_ila_0/probe200 [get_nets [list {SDCin_axi_bready}]] +connect_debug_port u_ila_0/probe200 [get_nets [list {m01_axi_wstrb[0]} {m01_axi_wstrb[1]} {m01_axi_wstrb[2]} {m01_axi_wstrb[3]} ]] create_debug_port u_ila_0 probe -set_property port_width 32 [get_debug_ports u_ila_0/probe201] +set_property port_width 1 [get_debug_ports u_ila_0/probe201] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe201] -connect_debug_port u_ila_0/probe201 [get_nets [list {SDCin_axi_araddr[0]} {SDCin_axi_araddr[1]} {SDCin_axi_araddr[2]} {SDCin_axi_araddr[3]} {SDCin_axi_araddr[4]} {SDCin_axi_araddr[5]} {SDCin_axi_araddr[6]} {SDCin_axi_araddr[7]} {SDCin_axi_araddr[8]} {SDCin_axi_araddr[9]} {SDCin_axi_araddr[10]} {SDCin_axi_araddr[11]} {SDCin_axi_araddr[12]} {SDCin_axi_araddr[13]} {SDCin_axi_araddr[14]} {SDCin_axi_araddr[15]} {SDCin_axi_araddr[16]} {SDCin_axi_araddr[17]} {SDCin_axi_araddr[18]} {SDCin_axi_araddr[19]} {SDCin_axi_araddr[20]} {SDCin_axi_araddr[21]} {SDCin_axi_araddr[22]} {SDCin_axi_araddr[23]} {SDCin_axi_araddr[24]} {SDCin_axi_araddr[25]} {SDCin_axi_araddr[26]} {SDCin_axi_araddr[27]} {SDCin_axi_araddr[28]} {SDCin_axi_araddr[29]} {SDCin_axi_araddr[30]} {SDCin_axi_araddr[31]} ]] +connect_debug_port u_ila_0/probe201 [get_nets [list {m01_axi_wlast}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe202] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe202] -connect_debug_port u_ila_0/probe202 [get_nets [list {SDCin_axi_arvalid}]] +connect_debug_port u_ila_0/probe202 [get_nets [list {m01_axi_wvalid}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe203] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe203] -connect_debug_port u_ila_0/probe203 [get_nets [list {SDCin_axi_arready}]] +connect_debug_port u_ila_0/probe203 [get_nets [list {m01_axi_wready}]] create_debug_port u_ila_0 probe -set_property port_width 32 [get_debug_ports u_ila_0/probe204] +set_property port_width 4 [get_debug_ports u_ila_0/probe204] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe204] -connect_debug_port u_ila_0/probe204 [get_nets [list {SDCin_axi_rdata[0]} {SDCin_axi_rdata[1]} {SDCin_axi_rdata[2]} {SDCin_axi_rdata[3]} {SDCin_axi_rdata[4]} {SDCin_axi_rdata[5]} {SDCin_axi_rdata[6]} {SDCin_axi_rdata[7]} {SDCin_axi_rdata[8]} {SDCin_axi_rdata[9]} {SDCin_axi_rdata[10]} {SDCin_axi_rdata[11]} {SDCin_axi_rdata[12]} {SDCin_axi_rdata[13]} {SDCin_axi_rdata[14]} {SDCin_axi_rdata[15]} {SDCin_axi_rdata[16]} {SDCin_axi_rdata[17]} {SDCin_axi_rdata[18]} {SDCin_axi_rdata[19]} {SDCin_axi_rdata[20]} {SDCin_axi_rdata[21]} {SDCin_axi_rdata[22]} {SDCin_axi_rdata[23]} {SDCin_axi_rdata[24]} {SDCin_axi_rdata[25]} {SDCin_axi_rdata[26]} {SDCin_axi_rdata[27]} {SDCin_axi_rdata[28]} {SDCin_axi_rdata[29]} {SDCin_axi_rdata[30]} {SDCin_axi_rdata[31]} ]] +connect_debug_port u_ila_0/probe204 [get_nets [list {m01_axi_bid[0]} {m01_axi_bid[1]} {m01_axi_bid[2]} {m01_axi_bid[3]} ]] create_debug_port u_ila_0 probe set_property port_width 2 [get_debug_ports u_ila_0/probe205] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe205] -connect_debug_port u_ila_0/probe205 [get_nets [list {SDCin_axi_rresp[0]} {SDCin_axi_rresp[1]} ]] +connect_debug_port u_ila_0/probe205 [get_nets [list {m01_axi_bresp[0]} {m01_axi_bresp[1]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe206] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe206] -connect_debug_port u_ila_0/probe206 [get_nets [list {SDCin_axi_rvalid}]] +connect_debug_port u_ila_0/probe206 [get_nets [list {m01_axi_bvalid}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe207] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe207] -connect_debug_port u_ila_0/probe207 [get_nets [list {SDCin_axi_rready}]] - +connect_debug_port u_ila_0/probe207 [get_nets [list {m01_axi_bready}]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe208] +set_property port_width 4 [get_debug_ports u_ila_0/probe208] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe208] -connect_debug_port u_ila_0/probe208 [get_nets [list {s01_axi_awvalid}]] +connect_debug_port u_ila_0/probe208 [get_nets [list {m01_axi_arid[0]} {m01_axi_arid[1]} {m01_axi_arid[2]} {m01_axi_arid[3]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe209] +set_property port_width 32 [get_debug_ports u_ila_0/probe209] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe209] -connect_debug_port u_ila_0/probe209 [get_nets [list {s01_axi_awready}]] +connect_debug_port u_ila_0/probe209 [get_nets [list {m01_axi_araddr[0]} {m01_axi_araddr[1]} {m01_axi_araddr[2]} {m01_axi_araddr[3]} {m01_axi_araddr[4]} {m01_axi_araddr[5]} {m01_axi_araddr[6]} {m01_axi_araddr[7]} {m01_axi_araddr[8]} {m01_axi_araddr[9]} {m01_axi_araddr[10]} {m01_axi_araddr[11]} {m01_axi_araddr[12]} {m01_axi_araddr[13]} {m01_axi_araddr[14]} {m01_axi_araddr[15]} {m01_axi_araddr[16]} {m01_axi_araddr[17]} {m01_axi_araddr[18]} {m01_axi_araddr[19]} {m01_axi_araddr[20]} {m01_axi_araddr[21]} {m01_axi_araddr[22]} {m01_axi_araddr[23]} {m01_axi_araddr[24]} {m01_axi_araddr[25]} {m01_axi_araddr[26]} {m01_axi_araddr[27]} {m01_axi_araddr[28]} {m01_axi_araddr[29]} {m01_axi_araddr[30]} {m01_axi_araddr[31]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe210] +set_property port_width 8 [get_debug_ports u_ila_0/probe210] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe210] -connect_debug_port u_ila_0/probe210 [get_nets [list {s00_axi_awvalid}]] +connect_debug_port u_ila_0/probe210 [get_nets [list {m01_axi_arlen[0]} {m01_axi_arlen[1]} {m01_axi_arlen[2]} {m01_axi_arlen[3]} {m01_axi_arlen[4]} {m01_axi_arlen[5]} {m01_axi_arlen[6]} {m01_axi_arlen[7]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe211] +set_property port_width 3 [get_debug_ports u_ila_0/probe211] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe211] -connect_debug_port u_ila_0/probe211 [get_nets [list {s00_axi_awready}]] +connect_debug_port u_ila_0/probe211 [get_nets [list {m01_axi_arsize[0]} {m01_axi_arsize[1]} {m01_axi_arsize[2]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe212] +set_property port_width 2 [get_debug_ports u_ila_0/probe212] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe212] -connect_debug_port u_ila_0/probe212 [get_nets [list {axi4in_axi_awvalid}]] +connect_debug_port u_ila_0/probe212 [get_nets [list {m01_axi_arburst[0]} {m01_axi_arburst[1]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe213] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe213] -connect_debug_port u_ila_0/probe213 [get_nets [list {axi4in_axi_awready}]] +connect_debug_port u_ila_0/probe213 [get_nets [list {m01_axi_arlock}]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe214] +set_property port_width 4 [get_debug_ports u_ila_0/probe214] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe214] -connect_debug_port u_ila_0/probe214 [get_nets [list {SDCout_axi_awvalid}]] +connect_debug_port u_ila_0/probe214 [get_nets [list {m01_axi_arcache[0]} {m01_axi_arcache[1]} {m01_axi_arcache[2]} {m01_axi_arcache[3]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe215] +set_property port_width 3 [get_debug_ports u_ila_0/probe215] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe215] -connect_debug_port u_ila_0/probe215 [get_nets [list {SDCout_axi_awready}]] +connect_debug_port u_ila_0/probe215 [get_nets [list {m01_axi_arprot[0]} {m01_axi_arprot[1]} {m01_axi_arprot[2]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe216] +set_property port_width 4 [get_debug_ports u_ila_0/probe216] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe216] -connect_debug_port u_ila_0/probe216 [get_nets [list {m01_axi_awvalid}]] +connect_debug_port u_ila_0/probe216 [get_nets [list {m01_axi_arregion[0]} {m01_axi_arregion[1]} {m01_axi_arregion[2]} {m01_axi_arregion[3]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe217] +set_property port_width 4 [get_debug_ports u_ila_0/probe217] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe217] -connect_debug_port u_ila_0/probe217 [get_nets [list {m01_axi_awready}]] +connect_debug_port u_ila_0/probe217 [get_nets [list {m01_axi_arqos[0]} {m01_axi_arqos[1]} {m01_axi_arqos[2]} {m01_axi_arqos[3]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe218] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe218] +connect_debug_port u_ila_0/probe218 [get_nets [list {m01_axi_arvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe219] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe219] +connect_debug_port u_ila_0/probe219 [get_nets [list {m01_axi_arready}]] + +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe220] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe220] +connect_debug_port u_ila_0/probe220 [get_nets [list {m01_axi_rid[0]} {m01_axi_rid[1]} {m01_axi_rid[2]} {m01_axi_rid[3]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe221] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe221] +connect_debug_port u_ila_0/probe221 [get_nets [list {m01_axi_rdata[0]} {m01_axi_rdata[1]} {m01_axi_rdata[2]} {m01_axi_rdata[3]} {m01_axi_rdata[4]} {m01_axi_rdata[5]} {m01_axi_rdata[6]} {m01_axi_rdata[7]} {m01_axi_rdata[8]} {m01_axi_rdata[9]} {m01_axi_rdata[10]} {m01_axi_rdata[11]} {m01_axi_rdata[12]} {m01_axi_rdata[13]} {m01_axi_rdata[14]} {m01_axi_rdata[15]} {m01_axi_rdata[16]} {m01_axi_rdata[17]} {m01_axi_rdata[18]} {m01_axi_rdata[19]} {m01_axi_rdata[20]} {m01_axi_rdata[21]} {m01_axi_rdata[22]} {m01_axi_rdata[23]} {m01_axi_rdata[24]} {m01_axi_rdata[25]} {m01_axi_rdata[26]} {m01_axi_rdata[27]} {m01_axi_rdata[28]} {m01_axi_rdata[29]} {m01_axi_rdata[30]} {m01_axi_rdata[31]} {m01_axi_rdata[32]} {m01_axi_rdata[33]} {m01_axi_rdata[34]} {m01_axi_rdata[35]} {m01_axi_rdata[36]} {m01_axi_rdata[37]} {m01_axi_rdata[38]} {m01_axi_rdata[39]} {m01_axi_rdata[40]} {m01_axi_rdata[41]} {m01_axi_rdata[42]} {m01_axi_rdata[43]} {m01_axi_rdata[44]} {m01_axi_rdata[45]} {m01_axi_rdata[46]} {m01_axi_rdata[47]} {m01_axi_rdata[48]} {m01_axi_rdata[49]} {m01_axi_rdata[50]} {m01_axi_rdata[51]} {m01_axi_rdata[52]} {m01_axi_rdata[53]} {m01_axi_rdata[54]} {m01_axi_rdata[55]} {m01_axi_rdata[56]} {m01_axi_rdata[57]} {m01_axi_rdata[58]} {m01_axi_rdata[59]} {m01_axi_rdata[60]} {m01_axi_rdata[61]} {m01_axi_rdata[62]} {m01_axi_rdata[63]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 2 [get_debug_ports u_ila_0/probe222] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe222] +connect_debug_port u_ila_0/probe222 [get_nets [list {m01_axi_rresp[0]} {m01_axi_rresp[1]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe223] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe223] +connect_debug_port u_ila_0/probe223 [get_nets [list {m01_axi_rlast}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe224] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe224] +connect_debug_port u_ila_0/probe224 [get_nets [list {m01_axi_rvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe225] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe225] +connect_debug_port u_ila_0/probe225 [get_nets [list {m01_axi_rready}]] + +create_debug_port u_ila_0 probe +set_property port_width 32 [get_debug_ports u_ila_0/probe226] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe226] +connect_debug_port u_ila_0/probe226 [get_nets [list {SDCout_axi_awaddr[0]} {SDCout_axi_awaddr[1]} {SDCout_axi_awaddr[2]} {SDCout_axi_awaddr[3]} {SDCout_axi_awaddr[4]} {SDCout_axi_awaddr[5]} {SDCout_axi_awaddr[6]} {SDCout_axi_awaddr[7]} {SDCout_axi_awaddr[8]} {SDCout_axi_awaddr[9]} {SDCout_axi_awaddr[10]} {SDCout_axi_awaddr[11]} {SDCout_axi_awaddr[12]} {SDCout_axi_awaddr[13]} {SDCout_axi_awaddr[14]} {SDCout_axi_awaddr[15]} {SDCout_axi_awaddr[16]} {SDCout_axi_awaddr[17]} {SDCout_axi_awaddr[18]} {SDCout_axi_awaddr[19]} {SDCout_axi_awaddr[20]} {SDCout_axi_awaddr[21]} {SDCout_axi_awaddr[22]} {SDCout_axi_awaddr[23]} {SDCout_axi_awaddr[24]} {SDCout_axi_awaddr[25]} {SDCout_axi_awaddr[26]} {SDCout_axi_awaddr[27]} {SDCout_axi_awaddr[28]} {SDCout_axi_awaddr[29]} {SDCout_axi_awaddr[30]} {SDCout_axi_awaddr[31]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 8 [get_debug_ports u_ila_0/probe227] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe227] +connect_debug_port u_ila_0/probe227 [get_nets [list {SDCout_axi_awlen[0]} {SDCout_axi_awlen[1]} {SDCout_axi_awlen[2]} {SDCout_axi_awlen[3]} {SDCout_axi_awlen[4]} {SDCout_axi_awlen[5]} {SDCout_axi_awlen[6]} {SDCout_axi_awlen[7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe228] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe228] +connect_debug_port u_ila_0/probe228 [get_nets [list {SDCout_axi_awvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe229] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe229] +connect_debug_port u_ila_0/probe229 [get_nets [list {SDCout_axi_awready}]] + +create_debug_port u_ila_0 probe +set_property port_width 32 [get_debug_ports u_ila_0/probe230] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe230] +connect_debug_port u_ila_0/probe230 [get_nets [list {SDCout_axi_wdata[0]} {SDCout_axi_wdata[1]} {SDCout_axi_wdata[2]} {SDCout_axi_wdata[3]} {SDCout_axi_wdata[4]} {SDCout_axi_wdata[5]} {SDCout_axi_wdata[6]} {SDCout_axi_wdata[7]} {SDCout_axi_wdata[8]} {SDCout_axi_wdata[9]} {SDCout_axi_wdata[10]} {SDCout_axi_wdata[11]} {SDCout_axi_wdata[12]} {SDCout_axi_wdata[13]} {SDCout_axi_wdata[14]} {SDCout_axi_wdata[15]} {SDCout_axi_wdata[16]} {SDCout_axi_wdata[17]} {SDCout_axi_wdata[18]} {SDCout_axi_wdata[19]} {SDCout_axi_wdata[20]} {SDCout_axi_wdata[21]} {SDCout_axi_wdata[22]} {SDCout_axi_wdata[23]} {SDCout_axi_wdata[24]} {SDCout_axi_wdata[25]} {SDCout_axi_wdata[26]} {SDCout_axi_wdata[27]} {SDCout_axi_wdata[28]} {SDCout_axi_wdata[29]} {SDCout_axi_wdata[30]} {SDCout_axi_wdata[31]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe231] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe231] +connect_debug_port u_ila_0/probe231 [get_nets [list {SDCout_axi_wlast}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe232] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe232] +connect_debug_port u_ila_0/probe232 [get_nets [list {SDCout_axi_wvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe233] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe233] +connect_debug_port u_ila_0/probe233 [get_nets [list {SDCout_axi_wready}]] + +create_debug_port u_ila_0 probe +set_property port_width 2 [get_debug_ports u_ila_0/probe234] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe234] +connect_debug_port u_ila_0/probe234 [get_nets [list {SDCout_axi_bresp[0]} {SDCout_axi_bresp[1]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe235] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe235] +connect_debug_port u_ila_0/probe235 [get_nets [list {SDCout_axi_bvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe236] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe236] +connect_debug_port u_ila_0/probe236 [get_nets [list {SDCout_axi_bready}]] + +create_debug_port u_ila_0 probe +set_property port_width 28 [get_debug_ports u_ila_0/probe237] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe237] +connect_debug_port u_ila_0/probe237 [get_nets [list {axiSDC/sd_data_master0/watchdog[0]} {axiSDC/sd_data_master0/watchdog[1]} {axiSDC/sd_data_master0/watchdog[2]} {axiSDC/sd_data_master0/watchdog[3]} {axiSDC/sd_data_master0/watchdog[4]} {axiSDC/sd_data_master0/watchdog[5]} {axiSDC/sd_data_master0/watchdog[6]} {axiSDC/sd_data_master0/watchdog[7]} {axiSDC/sd_data_master0/watchdog[8]} {axiSDC/sd_data_master0/watchdog[9]} {axiSDC/sd_data_master0/watchdog[10]} {axiSDC/sd_data_master0/watchdog[11]} {axiSDC/sd_data_master0/watchdog[12]} {axiSDC/sd_data_master0/watchdog[13]} {axiSDC/sd_data_master0/watchdog[14]} {axiSDC/sd_data_master0/watchdog[15]} {axiSDC/sd_data_master0/watchdog[16]} {axiSDC/sd_data_master0/watchdog[17]} {axiSDC/sd_data_master0/watchdog[18]} {axiSDC/sd_data_master0/watchdog[19]} {axiSDC/sd_data_master0/watchdog[20]} {axiSDC/sd_data_master0/watchdog[21]} {axiSDC/sd_data_master0/watchdog[22]} {axiSDC/sd_data_master0/watchdog[23]} {axiSDC/sd_data_master0/watchdog[24]} {axiSDC/sd_data_master0/watchdog[25]} {axiSDC/sd_data_master0/watchdog[26]} {axiSDC/sd_data_master0/watchdog[27]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe238] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe238] +connect_debug_port u_ila_0/probe238 [get_nets [list {axiSDC/data_busy}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe239] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe239] +connect_debug_port u_ila_0/probe239 [get_nets [list {axiSDC/sd_data_master0/en_tx_fifo}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe240] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe240] +connect_debug_port u_ila_0/probe240 [get_nets [list {axiSDC/sd_data_master0/fifo_empty}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe241] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe241] +connect_debug_port u_ila_0/probe241 [get_nets [list {axiSDC/sd_data_master0/bus_cycle}]] + +create_debug_port u_ila_0 probe +set_property port_width 12 [get_debug_ports u_ila_0/probe242] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe242] +connect_debug_port u_ila_0/probe242 [get_nets [list {axiSDC/sd_data_serial_host0/blkcnt_reg[0]} {axiSDC/sd_data_serial_host0/blkcnt_reg[1]} {axiSDC/sd_data_serial_host0/blkcnt_reg[2]} {axiSDC/sd_data_serial_host0/blkcnt_reg[3]} {axiSDC/sd_data_serial_host0/blkcnt_reg[4]} {axiSDC/sd_data_serial_host0/blkcnt_reg[5]} {axiSDC/sd_data_serial_host0/blkcnt_reg[6]} {axiSDC/sd_data_serial_host0/blkcnt_reg[7]} {axiSDC/sd_data_serial_host0/blkcnt_reg[8]} {axiSDC/sd_data_serial_host0/blkcnt_reg[9]} {axiSDC/sd_data_serial_host0/blkcnt_reg[10]} {axiSDC/sd_data_serial_host0/blkcnt_reg[11]}]] diff --git a/fpga/constraints/marked_debug.txt b/fpga/constraints/marked_debug.txt index 9e51d15ad..da96aac42 100644 --- a/fpga/constraints/marked_debug.txt +++ b/fpga/constraints/marked_debug.txt @@ -101,6 +101,7 @@ uncore/uartPC16550D.sv: logic RXerr uncore/uartPC16550D.sv: logic THRE uncore/uartPC16550D.sv: logic rxdataavailintr uncore/uartPC16550D.sv: logic intrID +uncore/uncore.sv: logic HSELEXTSDCD uncore/plic_apb.sv: logic MExtInt uncore/plic_apb.sv: logic Din uncore/plic_apb.sv: logic requests diff --git a/fpga/generator/xlnx_axi_crossbar.tcl b/fpga/generator/xlnx_axi_crossbar.tcl index ed44d9997..1d9eb4e78 100644 --- a/fpga/generator/xlnx_axi_crossbar.tcl +++ b/fpga/generator/xlnx_axi_crossbar.tcl @@ -19,8 +19,8 @@ create_ip -name axi_crossbar -vendor xilinx.com -library ip -version 2.1 -module set_property -dict [list CONFIG.NUM_SI {2} \ CONFIG.DATA_WIDTH {64} \ CONFIG.ID_WIDTH {4} \ - # CONFIG.M01_S01_READ_CONNECTIVITY {0} \ - # CONFIG.M01_S01_WRITE_CONNECTIVITY {0} \ + CONFIG.M01_S01_READ_CONNECTIVITY {0} \ + CONFIG.M01_S01_WRITE_CONNECTIVITY {0} \ CONFIG.M00_A00_BASE_ADDR {0x0000000080000000} \ CONFIG.M01_A00_BASE_ADDR {0x0000000000013000} \ CONFIG.M00_A00_ADDR_WIDTH {31}] [get_ips $ipName] diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index 42957f63b..649b7cd57 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -74,9 +74,10 @@ module fpgaTop wire HCLKOpen; wire HRESETnOpen; wire [`AHBW-1:0] HRDATAEXT; - wire HREADYEXT; + (* mark_debug = "true" *)wire HREADYEXT; wire HRESPEXT; - wire HSELEXT; + (* mark_debug = "true" *) wire HSELEXT; + (* mark_debug = "true" *) wire HSELEXTSDC; // TEMP BOOT SIGNAL - JACOB wire [31:0] HADDR; wire [`AHBW-1:0] HWDATA; wire HWRITE; @@ -96,41 +97,41 @@ module fpgaTop // wire SDCCmdOE; // wire SDCCmdOut; - (* mark_debug = "true" *) wire [3:0] m_axi_awid; - (* mark_debug = "true" *) wire [7:0] m_axi_awlen; - (* mark_debug = "true" *) wire [2:0] m_axi_awsize; - (* mark_debug = "true" *) wire [1:0] m_axi_awburst; - (* mark_debug = "true" *) wire [3:0] m_axi_awcache; - (* mark_debug = "true" *) wire [31:0] m_axi_awaddr; - (* mark_debug = "true" *) wire [2:0] m_axi_awprot; - (* mark_debug = "true" *) wire m_axi_awvalid; - (* mark_debug = "true" *) wire m_axi_awready; - (* mark_debug = "true" *) wire m_axi_awlock; - (* mark_debug = "true" *) wire [63:0] m_axi_wdata; - (* mark_debug = "true" *) wire [7:0] m_axi_wstrb; - (* mark_debug = "true" *) wire m_axi_wlast; - (* mark_debug = "true" *) wire m_axi_wvalid; - (* mark_debug = "true" *) wire m_axi_wready; - (* mark_debug = "true" *) wire [3:0] m_axi_bid; - (* mark_debug = "true" *) wire [1:0] m_axi_bresp; - (* mark_debug = "true" *) wire m_axi_bvalid; - (* mark_debug = "true" *) wire m_axi_bready; - (* mark_debug = "true" *) wire [3:0] m_axi_arid; - (* mark_debug = "true" *) wire [7:0] m_axi_arlen; - (* mark_debug = "true" *) wire [2:0] m_axi_arsize; - (* mark_debug = "true" *) wire [1:0] m_axi_arburst; - (* mark_debug = "true" *) wire [2:0] m_axi_arprot; - (* mark_debug = "true" *) wire [3:0] m_axi_arcache; - (* mark_debug = "true" *) wire m_axi_arvalid; - (* mark_debug = "true" *) wire [31:0] m_axi_araddr; - (* mark_debug = "true" *) wire m_axi_arlock; - (* mark_debug = "true" *) wire m_axi_arready; - (* mark_debug = "true" *) wire [3:0] m_axi_rid; - (* mark_debug = "true" *) wire [63:0] m_axi_rdata; - (* mark_debug = "true" *) wire [1:0] m_axi_rresp; - (* mark_debug = "true" *) wire m_axi_rvalid; - (* mark_debug = "true" *) wire m_axi_rlast; - (* mark_debug = "true" *) wire m_axi_rready; + wire [3:0] m_axi_awid; + wire [7:0] m_axi_awlen; + wire [2:0] m_axi_awsize; + wire [1:0] m_axi_awburst; + wire [3:0] m_axi_awcache; + wire [31:0] m_axi_awaddr; + wire [2:0] m_axi_awprot; + wire m_axi_awvalid; + wire m_axi_awready; + wire m_axi_awlock; + wire [63:0] m_axi_wdata; + wire [7:0] m_axi_wstrb; + wire m_axi_wlast; + wire m_axi_wvalid; + wire m_axi_wready; + wire [3:0] m_axi_bid; + wire [1:0] m_axi_bresp; + wire m_axi_bvalid; + wire m_axi_bready; + wire [3:0] m_axi_arid; + wire [7:0] m_axi_arlen; + wire [2:0] m_axi_arsize; + wire [1:0] m_axi_arburst; + wire [2:0] m_axi_arprot; + wire [3:0] m_axi_arcache; + wire m_axi_arvalid; + wire [31:0] m_axi_araddr; + wire m_axi_arlock; + wire m_axi_arready; + wire [3:0] m_axi_rid; + wire [63:0] m_axi_rdata; + wire [1:0] m_axi_rresp; + wire m_axi_rvalid; + wire m_axi_rlast; + wire m_axi_rready; // Extra Bus signals wire [3:0] BUS_axi_arregion; @@ -187,47 +188,47 @@ module fpgaTop // Crossbar to Bus ------------------------------------------------ - wire s00_axi_aclk; - wire s00_axi_aresetn; - wire [3:0] s00_axi_awid; - wire [31:0]s00_axi_awaddr; - wire [7:0]s00_axi_awlen; - wire [2:0]s00_axi_awsize; - wire [1:0]s00_axi_awburst; - wire [0:0]s00_axi_awlock; - wire [3:0]s00_axi_awcache; - wire [2:0]s00_axi_awprot; - wire [3:0]s00_axi_awregion; - wire [3:0]s00_axi_awqos; + (* mark_debug = "true" *)wire s00_axi_aclk; + (* mark_debug = "true" *)wire s00_axi_aresetn; + (* mark_debug = "true" *)wire [3:0] s00_axi_awid; + (* mark_debug = "true" *)wire [31:0]s00_axi_awaddr; + (* mark_debug = "true" *)wire [7:0]s00_axi_awlen; + (* mark_debug = "true" *)wire [2:0]s00_axi_awsize; + (* mark_debug = "true" *)wire [1:0]s00_axi_awburst; + (* mark_debug = "true" *)wire [0:0]s00_axi_awlock; + (* mark_debug = "true" *)wire [3:0]s00_axi_awcache; + (* mark_debug = "true" *)wire [2:0]s00_axi_awprot; + (* mark_debug = "true" *)wire [3:0]s00_axi_awregion; + (* mark_debug = "true" *)wire [3:0]s00_axi_awqos; (* mark_debug = "true" *) wire s00_axi_awvalid; (* mark_debug = "true" *) wire s00_axi_awready; - wire [63:0]s00_axi_wdata; - wire [7:0]s00_axi_wstrb; - wire s00_axi_wlast; - wire s00_axi_wvalid; - wire s00_axi_wready; - wire [1:0]s00_axi_bresp; - wire s00_axi_bvalid; - wire s00_axi_bready; - wire [31:0]s00_axi_araddr; - wire [7:0]s00_axi_arlen; - wire [2:0]s00_axi_arsize; - wire [1:0]s00_axi_arburst; - wire [0:0]s00_axi_arlock; - wire [3:0]s00_axi_arcache; - wire [2:0]s00_axi_arprot; - wire [3:0]s00_axi_arregion; - wire [3:0]s00_axi_arqos; - wire s00_axi_arvalid; - wire s00_axi_arready; - wire [63:0]s00_axi_rdata; - wire [1:0]s00_axi_rresp; - wire s00_axi_rlast; - wire s00_axi_rvalid; - wire s00_axi_rready; + (* mark_debug = "true" *)wire [63:0]s00_axi_wdata; + (* mark_debug = "true" *)wire [7:0]s00_axi_wstrb; + (* mark_debug = "true" *)wire s00_axi_wlast; + (* mark_debug = "true" *)wire s00_axi_wvalid; + (* mark_debug = "true" *)wire s00_axi_wready; + (* mark_debug = "true" *)wire [1:0]s00_axi_bresp; + (* mark_debug = "true" *)wire s00_axi_bvalid; + (* mark_debug = "true" *)wire s00_axi_bready; + (* mark_debug = "true" *)wire [31:0]s00_axi_araddr; + (* mark_debug = "true" *)wire [7:0]s00_axi_arlen; + (* mark_debug = "true" *)wire [2:0]s00_axi_arsize; + (* mark_debug = "true" *)wire [1:0]s00_axi_arburst; + (* mark_debug = "true" *)wire [0:0]s00_axi_arlock; + (* mark_debug = "true" *)wire [3:0]s00_axi_arcache; + (* mark_debug = "true" *)wire [2:0]s00_axi_arprot; + (* mark_debug = "true" *)wire [3:0]s00_axi_arregion; + (* mark_debug = "true" *)wire [3:0]s00_axi_arqos; + (* mark_debug = "true" *)wire s00_axi_arvalid; + (* mark_debug = "true" *)wire s00_axi_arready; + (* mark_debug = "true" *)wire [63:0]s00_axi_rdata; + (* mark_debug = "true" *)wire [1:0]s00_axi_rresp; + (* mark_debug = "true" *)wire s00_axi_rlast; + (* mark_debug = "true" *)wire s00_axi_rvalid; + (* mark_debug = "true" *)wire s00_axi_rready; - wire [3:0] s00_axi_bid; - wire [3:0] s00_axi_rid; + (* mark_debug = "true" *)wire [3:0] s00_axi_bid; + (* mark_debug = "true" *)wire [3:0] s00_axi_rid; // 64to32 dwidth converter input interface------------------------- wire s01_axi_aclk; @@ -329,8 +330,8 @@ module fpgaTop // ---------------------------------------------------------------- // 32to64 dwidth converter input interface ----------------------- - wire [31:0]SDCout_axi_awaddr; - wire [7:0]SDCout_axi_awlen; + (* mark_debug = "true" *) wire [31:0]SDCout_axi_awaddr; + (* mark_debug = "true" *) wire [7:0]SDCout_axi_awlen; wire [2:0]SDCout_axi_awsize; wire [1:0]SDCout_axi_awburst; wire [0:0]SDCout_axi_awlock; @@ -340,14 +341,14 @@ module fpgaTop wire [3:0]SDCout_axi_awqos; (* mark_debug = "true" *) wire SDCout_axi_awvalid; (* mark_debug = "true" *) wire SDCout_axi_awready; - wire [31:0]SDCout_axi_wdata; + (* mark_debug = "true" *) wire [31:0]SDCout_axi_wdata; wire [3:0]SDCout_axi_wstrb; - wire SDCout_axi_wlast; - wire SDCout_axi_wvalid; - wire SDCout_axi_wready; - wire [1:0]SDCout_axi_bresp; - wire SDCout_axi_bvalid; - wire SDCout_axi_bready; + (* mark_debug = "true" *) wire SDCout_axi_wlast; + (* mark_debug = "true" *) wire SDCout_axi_wvalid; + (* mark_debug = "true" *)wire SDCout_axi_wready; + (* mark_debug = "true" *) wire [1:0]SDCout_axi_bresp; + (* mark_debug = "true" *) wire SDCout_axi_bvalid; + (* mark_debug = "true" *) wire SDCout_axi_bready; wire [31:0]SDCout_axi_araddr; wire [7:0]SDCout_axi_arlen; wire [2:0]SDCout_axi_arsize; @@ -366,45 +367,45 @@ module fpgaTop wire SDCout_axi_rready; // Output Interface - wire [3:0]m01_axi_awid; - wire [31:0]m01_axi_awaddr; - wire [7:0]m01_axi_awlen; - wire [2:0]m01_axi_awsize; - wire [1:0]m01_axi_awburst; - wire [0:0]m01_axi_awlock; - wire [3:0]m01_axi_awcache; - wire [2:0]m01_axi_awprot; - wire [3:0]m01_axi_awregion; - wire [3:0]m01_axi_awqos; + (* mark_debug = "true" *) wire [3:0]m01_axi_awid; + (* mark_debug = "true" *) wire [31:0]m01_axi_awaddr; + (* mark_debug = "true" *) wire [7:0]m01_axi_awlen; + (* mark_debug = "true" *) wire [2:0]m01_axi_awsize; + (* mark_debug = "true" *) wire [1:0]m01_axi_awburst; + (* mark_debug = "true" *) wire [0:0]m01_axi_awlock; + (* mark_debug = "true" *) wire [3:0]m01_axi_awcache; + (* mark_debug = "true" *) wire [2:0]m01_axi_awprot; + (* mark_debug = "true" *) wire [3:0]m01_axi_awregion; + (* mark_debug = "true" *) wire [3:0]m01_axi_awqos; (* mark_debug = "true" *) wire m01_axi_awvalid; (* mark_debug = "true" *) wire m01_axi_awready; - wire [63:0]m01_axi_wdata; - wire [3:0]m01_axi_wstrb; - wire m01_axi_wlast; - wire m01_axi_wvalid; - wire m01_axi_wready; - wire [3:0] m01_axi_bid; - wire [1:0]m01_axi_bresp; - wire m01_axi_bvalid; - wire m01_axi_bready; - wire [3:0] m01_axi_arid; - wire [31:0]m01_axi_araddr; - wire [7:0]m01_axi_arlen; - wire [2:0]m01_axi_arsize; - wire [1:0]m01_axi_arburst; - wire [0:0]m01_axi_arlock; - wire [3:0]m01_axi_arcache; - wire [2:0]m01_axi_arprot; - wire [3:0]m01_axi_arregion; - wire [3:0]m01_axi_arqos; - wire m01_axi_arvalid; - wire m01_axi_arready; - wire [3:0] m01_axi_rid; - wire [63:0]m01_axi_rdata; - wire [1:0]m01_axi_rresp; - wire m01_axi_rlast; - wire m01_axi_rvalid; - wire m01_axi_rready; + (* mark_debug = "true" *) wire [63:0]m01_axi_wdata; + (* mark_debug = "true" *) wire [7:0]m01_axi_wstrb; + (* mark_debug = "true" *) wire m01_axi_wlast; + (* mark_debug = "true" *) wire m01_axi_wvalid; + (* mark_debug = "true" *) wire m01_axi_wready; + (* mark_debug = "true" *) wire [3:0] m01_axi_bid; + (* mark_debug = "true" *) wire [1:0]m01_axi_bresp; + (* mark_debug = "true" *) wire m01_axi_bvalid; + (* mark_debug = "true" *) wire m01_axi_bready; + (* mark_debug = "true" *) wire [3:0] m01_axi_arid; + (* mark_debug = "true" *) wire [31:0]m01_axi_araddr; + (* mark_debug = "true" *) wire [7:0]m01_axi_arlen; + (* mark_debug = "true" *) wire [2:0]m01_axi_arsize; + (* mark_debug = "true" *) wire [1:0]m01_axi_arburst; + (* mark_debug = "true" *) wire [0:0]m01_axi_arlock; + (* mark_debug = "true" *) wire [3:0]m01_axi_arcache; + (* mark_debug = "true" *) wire [2:0]m01_axi_arprot; + (* mark_debug = "true" *) wire [3:0]m01_axi_arregion; + (* mark_debug = "true" *) wire [3:0]m01_axi_arqos; + (* mark_debug = "true" *) wire m01_axi_arvalid; + (* mark_debug = "true" *) wire m01_axi_arready; + (* mark_debug = "true" *) wire [3:0] m01_axi_rid; + (* mark_debug = "true" *) wire [63:0]m01_axi_rdata; + (* mark_debug = "true" *) wire [1:0]m01_axi_rresp; + (* mark_debug = "true" *) wire m01_axi_rlast; + (* mark_debug = "true" *) wire m01_axi_rvalid; + (* mark_debug = "true" *) wire m01_axi_rready; // Old SDC input // wire [3:0] SDCDatIn; @@ -487,6 +488,7 @@ module fpgaTop .HREADYEXT(HREADYEXT), .HRESPEXT(HRESPEXT), .HSELEXT(HSELEXT), + .HSELEXTSDC(HSELEXTSDC), .HCLK(HCLKOpen), // open .HRESETn(HRESETnOpen), // open .HADDR(HADDR), @@ -517,7 +519,7 @@ module fpgaTop xlnx_ahblite_axi_bridge xlnx_ahblite_axi_bridge_0 (.s_ahb_hclk(CPUCLK), .s_ahb_hresetn(peripheral_aresetn), - .s_ahb_hsel(HSELEXT), + .s_ahb_hsel(HSELEXT | HSELEXTSDC), .s_ahb_haddr(HADDR), .s_ahb_hprot(HPROT), .s_ahb_htrans(HTRANS), @@ -809,7 +811,7 @@ module fpgaTop .async_resetn(peripheral_aresetn), // Slave Interface - .s_axi_awaddr(SDCin_axi_awaddr[15:0]), + .s_axi_awaddr({8'b0, SDCin_axi_awaddr[7:0]}), .s_axi_awvalid(SDCin_axi_awvalid), .s_axi_awready(SDCin_axi_awready), .s_axi_wdata(SDCin_axi_wdata), @@ -818,7 +820,7 @@ module fpgaTop .s_axi_bresp(SDCin_axi_bresp), .s_axi_bvalid(SDCin_axi_bvalid), .s_axi_bready(SDCin_axi_bready), - .s_axi_araddr(SDCin_axi_araddr[15:0]), + .s_axi_araddr({8'b0, SDCin_axi_araddr[7:0]}), .s_axi_arvalid(SDCin_axi_arvalid), .s_axi_arready(SDCin_axi_arready), .s_axi_rdata(SDCin_axi_rdata), @@ -872,8 +874,8 @@ module fpgaTop // Slave interface .s_axi_awaddr(SDCout_axi_awaddr), .s_axi_awlen(SDCout_axi_awlen), - .s_axi_awsize(3'b0), - .s_axi_awburst(2'b0), + .s_axi_awsize(3'b010), + .s_axi_awburst(2'b01), .s_axi_awlock(1'b0), .s_axi_awcache(4'b0), .s_axi_awprot(3'b0), @@ -882,7 +884,7 @@ module fpgaTop .s_axi_awvalid(SDCout_axi_awvalid), .s_axi_awready(SDCout_axi_awready), .s_axi_wdata(SDCout_axi_wdata), - .s_axi_wstrb(8'b0), + .s_axi_wstrb(8'b11111111), .s_axi_wlast(SDCout_axi_wlast), .s_axi_wvalid(SDCout_axi_wvalid), .s_axi_wready(SDCout_axi_wready), @@ -891,8 +893,8 @@ module fpgaTop .s_axi_bready(SDCout_axi_bready), .s_axi_araddr(SDCout_axi_araddr), .s_axi_arlen(SDCout_axi_arlen), - .s_axi_arsize(3'b0), - .s_axi_arburst(2'b0), + .s_axi_arsize(3'b010), + .s_axi_arburst(2'b01), .s_axi_arlock(1'b0), .s_axi_arcache(4'b0), .s_axi_arprot(3'b0), diff --git a/pipelined/src/uncore/newsdc/axi_sdc_controller.v b/pipelined/src/uncore/newsdc/axi_sdc_controller.v index 7e206c676..28994182d 100644 --- a/pipelined/src/uncore/newsdc/axi_sdc_controller.v +++ b/pipelined/src/uncore/newsdc/axi_sdc_controller.v @@ -162,7 +162,7 @@ wire [31:0] data_in_rx_fifo; wire en_tx_fifo; wire en_rx_fifo; wire sd_data_busy; -wire data_busy; +(* mark_debug = "true" *) wire data_busy; wire data_crc_ok; wire tx_fifo_re; wire rx_fifo_we; diff --git a/pipelined/src/uncore/newsdc/sd_data_master.v b/pipelined/src/uncore/newsdc/sd_data_master.v index c85d7ea7a..1fecea418 100644 --- a/pipelined/src/uncore/newsdc/sd_data_master.v +++ b/pipelined/src/uncore/newsdc/sd_data_master.v @@ -42,12 +42,12 @@ module sd_data_master ( output reg d_write, output reg d_read, // To fifo filler - output reg en_tx_fifo, + (* mark_debug = "true" *) output reg en_tx_fifo, output reg en_rx_fifo, - input fifo_empty, + (* mark_debug = "true" *) input fifo_empty, input fifo_ready, input fifo_full, - input bus_cycle, + (* mark_debug = "true" *) input bus_cycle, // SD-DATA_Host input xfr_complete, input crc_error, @@ -63,7 +63,7 @@ localparam START_TX_FIFO = 4'b0010; localparam START_RX_FIFO = 4'b0100; localparam DATA_TRANSFER = 4'b1000; -reg [`DATA_TIMEOUT_W-1:0] watchdog; +(* mark_debug = "true" *) reg [`DATA_TIMEOUT_W-1:0] watchdog; reg watchdog_enable; always @(posedge clock) begin diff --git a/pipelined/src/uncore/newsdc/sd_data_serial_host.v b/pipelined/src/uncore/newsdc/sd_data_serial_host.v index 9a35e5a88..62891d8b8 100644 --- a/pipelined/src/uncore/newsdc/sd_data_serial_host.v +++ b/pipelined/src/uncore/newsdc/sd_data_serial_host.v @@ -66,7 +66,7 @@ reg [`BLKSIZE_W+4-1:0] data_cycles; reg [`BLKSIZE_W+4-1:0] transf_cnt; reg [3:0] drt_bit; reg [3:0] drt_reg; -reg [`BLKCNT_W-1:0] blkcnt_reg; +(* mark_debug = "true" *) reg [`BLKCNT_W-1:0] blkcnt_reg; reg [1:0] byte_alignment_reg; reg [3:0] crc_bit; reg [3:0] last_din; diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv index f1e784c13..8bffee0ea 100644 --- a/src/generic/mem/ram1p1rwbe.sv +++ b/src/generic/mem/ram1p1rwbe.sv @@ -34,7 +34,7 @@ `include "wally-config.vh" -module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) ( +module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256, PRELOAD_ENABLED=0) ( input logic clk, input logic ce, input logic [$clog2(DEPTH)-1:0] addr, @@ -95,6 +95,12 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) ( end else begin: ram integer i; + if (PRELOAD_ENABLED) begin + initial begin + RAM[0] = 64'h00600100d2e3ca40; + end + end + // Read always_ff @(posedge clk) if(ce) dout <= #1 RAM[addr]; diff --git a/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv index 927462c78..d50b6c5bb 100644 --- a/src/generic/mem/rom1p1r.sv +++ b/src/generic/mem/rom1p1r.sv @@ -96,7 +96,7 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, ROM[41] = 64'h40a7853b4015551b; ROM[42] = 64'h808210a7a02367c9;*/ - ROM[0] = 64'hc001819300002197; + ROM[0] = 64'h8001819300002197; ROM[1] = 64'h4281420141014081; ROM[2] = 64'h4481440143814301; ROM[3] = 64'h4681460145814501; @@ -107,7 +107,7 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, ROM[8] = 64'h0110011b4f814f01; ROM[9] = 64'h059b45011161016e; ROM[10] = 64'h0004063705fe0010; - ROM[11] = 64'h1ee000ef8006061b; + ROM[11] = 64'h1f6000ef8006061b; ROM[12] = 64'h0ff003930000100f; ROM[13] = 64'h4e952e3110060e37; ROM[14] = 64'hc602829b0053f2b7; @@ -118,627 +118,116 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, ROM[19] = 64'h059bf1402573fdd0; ROM[20] = 64'h0000061705e20870; ROM[21] = 64'h0010029b01260613; - ROM[22] = 64'h67110002806702fe; - ROM[23] = 64'h0085179bf0070713; - ROM[24] = 64'h2781038007138ff9; - ROM[25] = 64'h7563470508a76a63; - ROM[26] = 64'h00a71733357902a7; - ROM[27] = 64'h3285350300001517; - ROM[28] = 64'h40301537e9598d79; - ROM[29] = 64'h8d7942250513051a; - ROM[30] = 64'he35d18177713e149; - ROM[31] = 64'he79300367713c295; - ROM[32] = 64'hf330674de3450207; - ROM[33] = 64'h861bc3701ff00613; - ROM[34] = 64'h01000637c730fff6; - ROM[35] = 64'hc35c674dcf10167d; - ROM[36] = 64'hd31c17fd001007b7; - ROM[37] = 64'h0007861b5b5cc30c; - ROM[38] = 64'h674d02072a23dfed; - ROM[39] = 64'h12634785fffd571c; - ROM[40] = 64'h80818793471006f6; - ROM[41] = 64'h4b10474cc3904501; - ROM[42] = 64'hc7d8c790c3cc4b58; - ROM[43] = 64'h086007138082e29d; - ROM[44] = 64'h0a90071300e50c63; - ROM[45] = 64'h0017e793f8e518e3; - ROM[46] = 64'hb74901d7e793b761; - ROM[47] = 64'h674dbfb50197e793; - ROM[48] = 64'h02072e23dffd5f5c; - ROM[49] = 64'h8513ff7d569866cd; - ROM[50] = 64'h053300a03533fff7; - ROM[51] = 64'h00a7e793808240a0; - ROM[52] = 64'h71398082557dbfa1; - ROM[53] = 64'hf8228181ca03e852; - ROM[54] = 64'hf426fc06ec4ef04a; - ROM[55] = 64'h008a7a13e05ae456; - ROM[56] = 64'h1463843289ae892a; - ROM[57] = 64'h4a8500959993000a; - ROM[58] = 64'h4549864ac4296b05; - ROM[59] = 64'h055402630009859b; - ROM[60] = 64'h008b73630004049b; - ROM[61] = 64'hecbff0ef86a66485; - ROM[62] = 64'h45814601468187aa; - ROM[63] = 64'h0207c8639c054531; - ROM[64] = 64'h0094979beb7ff0ef; - ROM[65] = 64'h0205406393811782; - ROM[66] = 64'h99ba020a1863873e; - ROM[67] = 64'ha8014501fc4d993e; - ROM[68] = 64'he93ff0ef45454685; - ROM[69] = 64'h70e24505fe055ae3; - ROM[70] = 64'h69e2790274a27442; - ROM[71] = 64'h61216b026aa26a42; - ROM[72] = 64'h9301020497138082; - ROM[73] = 64'hec26f0227179b7f9; - ROM[74] = 64'he44ef4064705e84a; - ROM[75] = 64'h842e84aad79867cd; - ROM[76] = 64'h8b85571c674d8932; - ROM[77] = 64'hd35c03600793dff5; - ROM[78] = 64'h571c674d02072423; - ROM[79] = 64'ha737b00026f3fffd; - ROM[80] = 64'h27f311f707130007; - ROM[81] = 64'hfef77de38f95b000; - ROM[82] = 64'h80018c235b1c674d; - ROM[83] = 64'he7934f5ccf9d8b89; - ROM[84] = 64'hb00026f3cf5c0027; - ROM[85] = 64'h0ff7071305f5e737; - ROM[86] = 64'h7de38f95b00027f3; - ROM[87] = 64'h9bf54f5c674dfef7; - ROM[88] = 64'h9737b00026f3cf5c; - ROM[89] = 64'h27f367f707130098; - ROM[90] = 64'hfef77de38f95b000; - ROM[91] = 64'h4501458146014681; - ROM[92] = 64'h80818993dd7ff0ef; - ROM[93] = 64'h0593460146814789; - ROM[94] = 64'h00f9882345211aa0; - ROM[95] = 64'ha783e50ddbfff0ef; - ROM[96] = 64'h17d21aa007130009; - ROM[97] = 64'h479102e79e6393d1; - ROM[98] = 64'hf0efa80900f98823; - ROM[99] = 64'ha78302054663da1f; - ROM[100]= 64'h46810207cc630009; - ROM[101]= 64'h0370051345814601; - ROM[102]= 64'h468187aad87ff0ef; - ROM[103]= 64'h0513403005b74601; - ROM[104]= 64'h8522fc07dae30a90; - ROM[105]= 64'h864a69a270a27402; - ROM[106]= 64'h614564e2694285a6; - ROM[107]= 64'hebd18b8583f9b5b9; - ROM[108]= 64'h4509458146014681; - ROM[109]= 64'hfc054de3d4fff0ef; - ROM[110]= 64'h123405b746014681; - ROM[111]= 64'h44e3d3dff0ef450d; - ROM[112]= 64'h77c10009a983fc05; - ROM[113]= 64'h460100f9f9b34681; - ROM[114]= 64'hd23ff0ef451d85ce; - ROM[115]= 64'h470567cdfa0547e3; - ROM[116]= 64'h4737b00026f3d3d8; - ROM[117]= 64'h27f323f70713000f; - ROM[118]= 64'hfef77de38f95b000; - ROM[119]= 64'h46810007ae2367cd; - ROM[120]= 64'h0370051385ce4601; - ROM[121]= 64'hf6054de3cefff0ef; - ROM[122]= 64'h0513458146014681; - ROM[123]= 64'h44e3cddff0ef0860; - ROM[124]= 64'h059346014681f605; - ROM[125]= 64'hccbff0ef45412000; - ROM[126]= 64'he7930109c783bf99; - ROM[127]= 64'hb78d00f988230087; - ROM[128]= 64'h0000000000000000; - ROM[129]= 64'h0000000000000000; - ROM[130]= 64'h0000000000000000; - ROM[131]= 64'h0000000000000000; - ROM[132]= 64'h0000000000000000; - ROM[133]= 64'h0000000000000000; - ROM[134]= 64'h0000000000000000; - ROM[135]= 64'h0000000000000000; - ROM[136]= 64'h0000000000000000; - ROM[137]= 64'h0000000000000000; - ROM[138]= 64'h0000000000000000; - ROM[139]= 64'h0000000000000000; - ROM[140]= 64'h0000000000000000; - ROM[141]= 64'h0000000000000000; - ROM[142]= 64'h0000000000000000; - ROM[143]= 64'h0000000000000000; - ROM[144]= 64'h0000000000000000; - ROM[145]= 64'h0000000000000000; - ROM[146]= 64'h0000000000000000; - ROM[147]= 64'h0000000000000000; - ROM[148]= 64'h0000000000000000; - ROM[149]= 64'h0000000000000000; - ROM[150]= 64'h0000000000000000; - ROM[151]= 64'h0000000000000000; - ROM[152]= 64'h0000000000000000; - ROM[153]= 64'h0000000000000000; - ROM[154]= 64'h0000000000000000; - ROM[155]= 64'h0000000000000000; - ROM[156]= 64'h0000000000000000; - ROM[157]= 64'h0000000000000000; - ROM[158]= 64'h0000000000000000; - ROM[159]= 64'h0000000000000000; - ROM[160]= 64'h0000000000000000; - ROM[161]= 64'h0000000000000000; - ROM[162]= 64'h0000000000000000; - ROM[163]= 64'h0000000000000000; - ROM[164]= 64'h0000000000000000; - ROM[165]= 64'h0000000000000000; - ROM[166]= 64'h0000000000000000; - ROM[167]= 64'h0000000000000000; - ROM[168]= 64'h0000000000000000; - ROM[169]= 64'h0000000000000000; - ROM[170]= 64'h0000000000000000; - ROM[171]= 64'h0000000000000000; - ROM[172]= 64'h0000000000000000; - ROM[173]= 64'h0000000000000000; - ROM[174]= 64'h0000000000000000; - ROM[175]= 64'h0000000000000000; - ROM[176]= 64'h0000000000000000; - ROM[177]= 64'h0000000000000000; - ROM[178]= 64'h0000000000000000; - ROM[179]= 64'h0000000000000000; - ROM[180]= 64'h0000000000000000; - ROM[181]= 64'h0000000000000000; - ROM[182]= 64'h0000000000000000; - ROM[183]= 64'h0000000000000000; - ROM[184]= 64'h0000000000000000; - ROM[185]= 64'h0000000000000000; - ROM[186]= 64'h0000000000000000; - ROM[187]= 64'h0000000000000000; - ROM[188]= 64'h0000000000000000; - ROM[189]= 64'h0000000000000000; - ROM[190]= 64'h0000000000000000; - ROM[191]= 64'h0000000000000000; - ROM[192]= 64'h0000000000000000; - ROM[193]= 64'h0000000000000000; - ROM[194]= 64'h0000000000000000; - ROM[195]= 64'h0000000000000000; - ROM[196]= 64'h0000000000000000; - ROM[197]= 64'h0000000000000000; - ROM[198]= 64'h0000000000000000; - ROM[199]= 64'h0000000000000000; - ROM[200]= 64'h0000000000000000; - ROM[201]= 64'h0000000000000000; - ROM[202]= 64'h0000000000000000; - ROM[203]= 64'h0000000000000000; - ROM[204]= 64'h0000000000000000; - ROM[205]= 64'h0000000000000000; - ROM[206]= 64'h0000000000000000; - ROM[207]= 64'h0000000000000000; - ROM[208]= 64'h0000000000000000; - ROM[209]= 64'h0000000000000000; - ROM[210]= 64'h0000000000000000; - ROM[211]= 64'h0000000000000000; - ROM[212]= 64'h0000000000000000; - ROM[213]= 64'h0000000000000000; - ROM[214]= 64'h0000000000000000; - ROM[215]= 64'h0000000000000000; - ROM[216]= 64'h0000000000000000; - ROM[217]= 64'h0000000000000000; - ROM[218]= 64'h0000000000000000; - ROM[219]= 64'h0000000000000000; - ROM[220]= 64'h0000000000000000; - ROM[221]= 64'h0000000000000000; - ROM[222]= 64'h0000000000000000; - ROM[223]= 64'h0000000000000000; - ROM[224]= 64'h0000000000000000; - ROM[225]= 64'h0000000000000000; - ROM[226]= 64'h0000000000000000; - ROM[227]= 64'h0000000000000000; - ROM[228]= 64'h0000000000000000; - ROM[229]= 64'h0000000000000000; - ROM[230]= 64'h0000000000000000; - ROM[231]= 64'h0000000000000000; - ROM[232]= 64'h0000000000000000; - ROM[233]= 64'h0000000000000000; - ROM[234]= 64'h0000000000000000; - ROM[235]= 64'h0000000000000000; - ROM[236]= 64'h0000000000000000; - ROM[237]= 64'h0000000000000000; - ROM[238]= 64'h0000000000000000; - ROM[239]= 64'h0000000000000000; - ROM[240]= 64'h0000000000000000; - ROM[241]= 64'h0000000000000000; - ROM[242]= 64'h0000000000000000; - ROM[243]= 64'h0000000000000000; - ROM[244]= 64'h0000000000000000; - ROM[245]= 64'h0000000000000000; - ROM[246]= 64'h0000000000000000; - ROM[247]= 64'h0000000000000000; - ROM[248]= 64'h0000000000000000; - ROM[249]= 64'h0000000000000000; - ROM[250]= 64'h0000000000000000; - ROM[251]= 64'h0000000000000000; - ROM[252]= 64'h0000000000000000; - ROM[253]= 64'h0000000000000000; - ROM[254]= 64'h0000000000000000; - ROM[255]= 64'h0000000000000000; - ROM[256]= 64'h0000000000000000; - ROM[257]= 64'h0000000000000000; - ROM[258]= 64'h0000000000000000; - ROM[259]= 64'h0000000000000000; - ROM[260]= 64'h0000000000000000; - ROM[261]= 64'h0000000000000000; - ROM[262]= 64'h0000000000000000; - ROM[263]= 64'h0000000000000000; - ROM[264]= 64'h0000000000000000; - ROM[265]= 64'h0000000000000000; - ROM[266]= 64'h0000000000000000; - ROM[267]= 64'h0000000000000000; - ROM[268]= 64'h0000000000000000; - ROM[269]= 64'h0000000000000000; - ROM[270]= 64'h0000000000000000; - ROM[271]= 64'h0000000000000000; - ROM[272]= 64'h0000000000000000; - ROM[273]= 64'h0000000000000000; - ROM[274]= 64'h0000000000000000; - ROM[275]= 64'h0000000000000000; - ROM[276]= 64'h0000000000000000; - ROM[277]= 64'h0000000000000000; - ROM[278]= 64'h0000000000000000; - ROM[279]= 64'h0000000000000000; - ROM[280]= 64'h0000000000000000; - ROM[281]= 64'h0000000000000000; - ROM[282]= 64'h0000000000000000; - ROM[283]= 64'h0000000000000000; - ROM[284]= 64'h0000000000000000; - ROM[285]= 64'h0000000000000000; - ROM[286]= 64'h0000000000000000; - ROM[287]= 64'h0000000000000000; - ROM[288]= 64'h0000000000000000; - ROM[289]= 64'h0000000000000000; - ROM[290]= 64'h0000000000000000; - ROM[291]= 64'h0000000000000000; - ROM[292]= 64'h0000000000000000; - ROM[293]= 64'h0000000000000000; - ROM[294]= 64'h0000000000000000; - ROM[295]= 64'h0000000000000000; - ROM[296]= 64'h0000000000000000; - ROM[297]= 64'h0000000000000000; - ROM[298]= 64'h0000000000000000; - ROM[299]= 64'h0000000000000000; - ROM[300]= 64'h0000000000000000; - ROM[301]= 64'h0000000000000000; - ROM[302]= 64'h0000000000000000; - ROM[303]= 64'h0000000000000000; - ROM[304]= 64'h0000000000000000; - ROM[305]= 64'h0000000000000000; - ROM[306]= 64'h0000000000000000; - ROM[307]= 64'h0000000000000000; - ROM[308]= 64'h0000000000000000; - ROM[309]= 64'h0000000000000000; - ROM[310]= 64'h0000000000000000; - ROM[311]= 64'h0000000000000000; - ROM[312]= 64'h0000000000000000; - ROM[313]= 64'h0000000000000000; - ROM[314]= 64'h0000000000000000; - ROM[315]= 64'h0000000000000000; - ROM[316]= 64'h0000000000000000; - ROM[317]= 64'h0000000000000000; - ROM[318]= 64'h0000000000000000; - ROM[319]= 64'h0000000000000000; - ROM[320]= 64'h0000000000000000; - ROM[321]= 64'h0000000000000000; - ROM[322]= 64'h0000000000000000; - ROM[323]= 64'h0000000000000000; - ROM[324]= 64'h0000000000000000; - ROM[325]= 64'h0000000000000000; - ROM[326]= 64'h0000000000000000; - ROM[327]= 64'h0000000000000000; - ROM[328]= 64'h0000000000000000; - ROM[329]= 64'h0000000000000000; - ROM[330]= 64'h0000000000000000; - ROM[331]= 64'h0000000000000000; - ROM[332]= 64'h0000000000000000; - ROM[333]= 64'h0000000000000000; - ROM[334]= 64'h0000000000000000; - ROM[335]= 64'h0000000000000000; - ROM[336]= 64'h0000000000000000; - ROM[337]= 64'h0000000000000000; - ROM[338]= 64'h0000000000000000; - ROM[339]= 64'h0000000000000000; - ROM[340]= 64'h0000000000000000; - ROM[341]= 64'h0000000000000000; - ROM[342]= 64'h0000000000000000; - ROM[343]= 64'h0000000000000000; - ROM[344]= 64'h0000000000000000; - ROM[345]= 64'h0000000000000000; - ROM[346]= 64'h0000000000000000; - ROM[347]= 64'h0000000000000000; - ROM[348]= 64'h0000000000000000; - ROM[349]= 64'h0000000000000000; - ROM[350]= 64'h0000000000000000; - ROM[351]= 64'h0000000000000000; - ROM[352]= 64'h0000000000000000; - ROM[353]= 64'h0000000000000000; - ROM[354]= 64'h0000000000000000; - ROM[355]= 64'h0000000000000000; - ROM[356]= 64'h0000000000000000; - ROM[357]= 64'h0000000000000000; - ROM[358]= 64'h0000000000000000; - ROM[359]= 64'h0000000000000000; - ROM[360]= 64'h0000000000000000; - ROM[361]= 64'h0000000000000000; - ROM[362]= 64'h0000000000000000; - ROM[363]= 64'h0000000000000000; - ROM[364]= 64'h0000000000000000; - ROM[365]= 64'h0000000000000000; - ROM[366]= 64'h0000000000000000; - ROM[367]= 64'h0000000000000000; - ROM[368]= 64'h0000000000000000; - ROM[369]= 64'h0000000000000000; - ROM[370]= 64'h0000000000000000; - ROM[371]= 64'h0000000000000000; - ROM[372]= 64'h0000000000000000; - ROM[373]= 64'h0000000000000000; - ROM[374]= 64'h0000000000000000; - ROM[375]= 64'h0000000000000000; - ROM[376]= 64'h0000000000000000; - ROM[377]= 64'h0000000000000000; - ROM[378]= 64'h0000000000000000; - ROM[379]= 64'h0000000000000000; - ROM[380]= 64'h0000000000000000; - ROM[381]= 64'h0000000000000000; - ROM[382]= 64'h0000000000000000; - ROM[383]= 64'h0000000000000000; - ROM[384]= 64'h0000000000000000; - ROM[385]= 64'h0000000000000000; - ROM[386]= 64'h0000000000000000; - ROM[387]= 64'h0000000000000000; - ROM[388]= 64'h0000000000000000; - ROM[389]= 64'h0000000000000000; - ROM[390]= 64'h0000000000000000; - ROM[391]= 64'h0000000000000000; - ROM[392]= 64'h0000000000000000; - ROM[393]= 64'h0000000000000000; - ROM[394]= 64'h0000000000000000; - ROM[395]= 64'h0000000000000000; - ROM[396]= 64'h0000000000000000; - ROM[397]= 64'h0000000000000000; - ROM[398]= 64'h0000000000000000; - ROM[399]= 64'h0000000000000000; - ROM[400]= 64'h0000000000000000; - ROM[401]= 64'h0000000000000000; - ROM[402]= 64'h0000000000000000; - ROM[403]= 64'h0000000000000000; - ROM[404]= 64'h0000000000000000; - ROM[405]= 64'h0000000000000000; - ROM[406]= 64'h0000000000000000; - ROM[407]= 64'h0000000000000000; - ROM[408]= 64'h0000000000000000; - ROM[409]= 64'h0000000000000000; - ROM[410]= 64'h0000000000000000; - ROM[411]= 64'h0000000000000000; - ROM[412]= 64'h0000000000000000; - ROM[413]= 64'h0000000000000000; - ROM[414]= 64'h0000000000000000; - ROM[415]= 64'h0000000000000000; - ROM[416]= 64'h0000000000000000; - ROM[417]= 64'h0000000000000000; - ROM[418]= 64'h0000000000000000; - ROM[419]= 64'h0000000000000000; - ROM[420]= 64'h0000000000000000; - ROM[421]= 64'h0000000000000000; - ROM[422]= 64'h0000000000000000; - ROM[423]= 64'h0000000000000000; - ROM[424]= 64'h0000000000000000; - ROM[425]= 64'h0000000000000000; - ROM[426]= 64'h0000000000000000; - ROM[427]= 64'h0000000000000000; - ROM[428]= 64'h0000000000000000; - ROM[429]= 64'h0000000000000000; - ROM[430]= 64'h0000000000000000; - ROM[431]= 64'h0000000000000000; - ROM[432]= 64'h0000000000000000; - ROM[433]= 64'h0000000000000000; - ROM[434]= 64'h0000000000000000; - ROM[435]= 64'h0000000000000000; - ROM[436]= 64'h0000000000000000; - ROM[437]= 64'h0000000000000000; - ROM[438]= 64'h0000000000000000; - ROM[439]= 64'h0000000000000000; - ROM[440]= 64'h0000000000000000; - ROM[441]= 64'h0000000000000000; - ROM[442]= 64'h0000000000000000; - ROM[443]= 64'h0000000000000000; - ROM[444]= 64'h0000000000000000; - ROM[445]= 64'h0000000000000000; - ROM[446]= 64'h0000000000000000; - ROM[447]= 64'h0000000000000000; - ROM[448]= 64'h0000000000000000; - ROM[449]= 64'h0000000000000000; - ROM[450]= 64'h0000000000000000; - ROM[451]= 64'h0000000000000000; - ROM[452]= 64'h0000000000000000; - ROM[453]= 64'h0000000000000000; - ROM[454]= 64'h0000000000000000; - ROM[455]= 64'h0000000000000000; - ROM[456]= 64'h0000000000000000; - ROM[457]= 64'h0000000000000000; - ROM[458]= 64'h0000000000000000; - ROM[459]= 64'h0000000000000000; - ROM[460]= 64'h0000000000000000; - ROM[461]= 64'h0000000000000000; - ROM[462]= 64'h0000000000000000; - ROM[463]= 64'h0000000000000000; - ROM[464]= 64'h0000000000000000; - ROM[465]= 64'h0000000000000000; - ROM[466]= 64'h0000000000000000; - ROM[467]= 64'h0000000000000000; - ROM[468]= 64'h0000000000000000; - ROM[469]= 64'h0000000000000000; - ROM[470]= 64'h0000000000000000; - ROM[471]= 64'h0000000000000000; - ROM[472]= 64'h0000000000000000; - ROM[473]= 64'h0000000000000000; - ROM[474]= 64'h0000000000000000; - ROM[475]= 64'h0000000000000000; - ROM[476]= 64'h0000000000000000; - ROM[477]= 64'h0000000000000000; - ROM[478]= 64'h0000000000000000; - ROM[479]= 64'h0000000000000000; - ROM[480]= 64'h0000000000000000; - ROM[481]= 64'h0000000000000000; - ROM[482]= 64'h0000000000000000; - ROM[483]= 64'h0000000000000000; - ROM[484]= 64'h0000000000000000; - ROM[485]= 64'h0000000000000000; - ROM[486]= 64'h0000000000000000; - ROM[487]= 64'h0000000000000000; - ROM[488]= 64'h0000000000000000; - ROM[489]= 64'h0000000000000000; - ROM[490]= 64'h0000000000000000; - ROM[491]= 64'h0000000000000000; - ROM[492]= 64'h0000000000000000; - ROM[493]= 64'h0000000000000000; - ROM[494]= 64'h0000000000000000; - ROM[495]= 64'h0000000000000000; - ROM[496]= 64'h0000000000000000; - ROM[497]= 64'h0000000000000000; - ROM[498]= 64'h0000000000000000; - ROM[499]= 64'h0000000000000000; - ROM[500]= 64'h0000000000000000; - ROM[501]= 64'h0000000000000000; - ROM[502]= 64'h0000000000000000; - ROM[503]= 64'h0000000000000000; - ROM[504]= 64'h0000000000000000; - ROM[505]= 64'h0000000000000000; - ROM[506]= 64'h0000000000000000; - ROM[507]= 64'h0000000000000000; - ROM[508]= 64'h0000000000000000; - ROM[509]= 64'h0000000000000000; - ROM[510]= 64'h0000000000000000; - ROM[511]= 64'h0000000000000000; - ROM[512]= 64'h0000000000000000; - ROM[513]= 64'h0000000000000000; - ROM[514]= 64'h0000000000000000; - ROM[515]= 64'h0000000000000000; - ROM[516]= 64'h0000000000000000; - ROM[517]= 64'h0000000000000000; - ROM[518]= 64'h0000000000000000; - ROM[519]= 64'h0000000000000000; - ROM[520]= 64'h0000000000000000; - ROM[521]= 64'h0000000000000000; - ROM[522]= 64'h0000000000000000; - ROM[523]= 64'h0000000000000000; - ROM[524]= 64'h0000000000000000; - ROM[525]= 64'h0000000000000000; - ROM[526]= 64'h0000000000000000; - ROM[527]= 64'h0000000000000000; - ROM[528]= 64'h0000000000000000; - ROM[529]= 64'h0000000000000000; - ROM[530]= 64'h0000000000000000; - ROM[531]= 64'h0000000000000000; - ROM[532]= 64'h0000000000000000; - ROM[533]= 64'h0000000000000000; - ROM[534]= 64'h0000000000000000; - ROM[535]= 64'h0000000000000000; - ROM[536]= 64'h0000000000000000; - ROM[537]= 64'h0000000000000000; - ROM[538]= 64'h0000000000000000; - ROM[539]= 64'h0000000000000000; - ROM[540]= 64'h0000000000000000; - ROM[541]= 64'h0000000000000000; - ROM[542]= 64'h0000000000000000; - ROM[543]= 64'h0000000000000000; - ROM[544]= 64'h0000000000000000; - ROM[545]= 64'h0000000000000000; - ROM[546]= 64'h0000000000000000; - ROM[547]= 64'h0000000000000000; - ROM[548]= 64'h0000000000000000; - ROM[549]= 64'h0000000000000000; - ROM[550]= 64'h0000000000000000; - ROM[551]= 64'h0000000000000000; - ROM[552]= 64'h0000000000000000; - ROM[553]= 64'h0000000000000000; - ROM[554]= 64'h0000000000000000; - ROM[555]= 64'h0000000000000000; - ROM[556]= 64'h0000000000000000; - ROM[557]= 64'h0000000000000000; - ROM[558]= 64'h0000000000000000; - ROM[559]= 64'h0000000000000000; - ROM[560]= 64'h0000000000000000; - ROM[561]= 64'h0000000000000000; - ROM[562]= 64'h0000000000000000; - ROM[563]= 64'h0000000000000000; - ROM[564]= 64'h0000000000000000; - ROM[565]= 64'h0000000000000000; - ROM[566]= 64'h0000000000000000; - ROM[567]= 64'h0000000000000000; - ROM[568]= 64'h0000000000000000; - ROM[569]= 64'h0000000000000000; - ROM[570]= 64'h0000000000000000; - ROM[571]= 64'h0000000000000000; - ROM[572]= 64'h0000000000000000; - ROM[573]= 64'h0000000000000000; - ROM[574]= 64'h0000000000000000; - ROM[575]= 64'h0000000000000000; - ROM[576]= 64'h0000000000000000; - ROM[577]= 64'h0000000000000000; - ROM[578]= 64'h0000000000000000; - ROM[579]= 64'h0000000000000000; - ROM[580]= 64'h0000000000000000; - ROM[581]= 64'h0000000000000000; - ROM[582]= 64'h0000000000000000; - ROM[583]= 64'h0000000000000000; - ROM[584]= 64'h0000000000000000; - ROM[585]= 64'h0000000000000000; - ROM[586]= 64'h0000000000000000; - ROM[587]= 64'h0000000000000000; - ROM[588]= 64'h0000000000000000; - ROM[589]= 64'h0000000000000000; - ROM[590]= 64'h0000000000000000; - ROM[591]= 64'h0000000000000000; - ROM[592]= 64'h0000000000000000; - ROM[593]= 64'h0000000000000000; - ROM[594]= 64'h0000000000000000; - ROM[595]= 64'h0000000000000000; - ROM[596]= 64'h0000000000000000; - ROM[597]= 64'h0000000000000000; - ROM[598]= 64'h0000000000000000; - ROM[599]= 64'h0000000000000000; - ROM[600]= 64'h0000000000000000; - ROM[601]= 64'h0000000000000000; - ROM[602]= 64'h0000000000000000; - ROM[603]= 64'h0000000000000000; - ROM[604]= 64'h0000000000000000; - ROM[605]= 64'h0000000000000000; - ROM[606]= 64'h0000000000000000; - ROM[607]= 64'h0000000000000000; - ROM[608]= 64'h0000000000000000; - ROM[609]= 64'h0000000000000000; - ROM[610]= 64'h0000000000000000; - ROM[611]= 64'h0000000000000000; - ROM[612]= 64'h0000000000000000; - ROM[613]= 64'h0000000000000000; - ROM[614]= 64'h0000000000000000; - ROM[615]= 64'h0000000000000000; - ROM[616]= 64'h0000000000000000; - ROM[617]= 64'h0000000000000000; - ROM[618]= 64'h0000000000000000; - ROM[619]= 64'h0000000000000000; - ROM[620]= 64'h0000000000000000; - ROM[621]= 64'h0000000000000000; - ROM[622]= 64'h0000000000000000; - ROM[623]= 64'h0000000000000000; - ROM[624]= 64'h0000000000000000; - ROM[625]= 64'h0000000000000000; - ROM[626]= 64'h0000000000000000; - ROM[627]= 64'h0000000000000000; - ROM[628]= 64'h0000000000000000; - ROM[629]= 64'h0000000000000000; - ROM[630]= 64'h0000000000000000; - ROM[631]= 64'h0000000000000000; - ROM[632]= 64'h0000000000000000; - ROM[633]= 64'h0000000000000000; - ROM[634]= 64'h0000000000000000; - ROM[635]= 64'h0000000000000000; - ROM[636]= 64'h0000000000000000; - ROM[637]= 64'h0000000000000000; - ROM[638]= 64'h0000000000000000; - ROM[639]= 64'h0000000000000000; - ROM[640]= 64'h00600100d2e3ca40; - end - end + ROM[22] = 64'h68110002806702fe; + ROM[23] = 64'h0085179bf0080813; + ROM[24] = 64'h038008130107f7b3; + ROM[25] = 64'h480508a86c632781; + ROM[26] = 64'h1533357902a87963; + ROM[27] = 64'h38030000181700a8; + ROM[28] = 64'h1c6301057833f268; + ROM[29] = 64'h081a403018370808; + ROM[30] = 64'h0105783342280813; + ROM[31] = 64'h1815751308081063; + ROM[32] = 64'h00367513c295e14d; + ROM[33] = 64'h654ded510207e793; + ROM[34] = 64'hc1701ff00613f130; + ROM[35] = 64'h0637c530fff6861b; + ROM[36] = 64'h664dcd10167d0200; + ROM[37] = 64'h17fd001007b7c25c; + ROM[38] = 64'h859b5a5cc20cd21c; + ROM[39] = 64'h02062a23dfed0007; + ROM[40] = 64'h4785fffd561c664d; + ROM[41] = 64'h4501461c06f59063; + ROM[42] = 64'h4a1cc35c465cc31c; + ROM[43] = 64'he29dc75c4a5cc71c; + ROM[44] = 64'h0c63086008138082; + ROM[45] = 64'h1ae30a9008130105; + ROM[46] = 64'hb7710017e793f905; + ROM[47] = 64'he793b75901d7e793; + ROM[48] = 64'h5f5c674db7410197; + ROM[49] = 64'h66cd02072e23dffd; + ROM[50] = 64'hfff78513ff7d5698; + ROM[51] = 64'h40a0053300a03533; + ROM[52] = 64'hbfb100a7e7938082; + ROM[53] = 64'he0a2715d8082557d; + ROM[54] = 64'he486f052f44ef84a; + ROM[55] = 64'hfa13e85aec56fc26; + ROM[56] = 64'h843289ae892a0086; + ROM[57] = 64'h00959993000a1463; + ROM[58] = 64'h864ac4396b054a85; + ROM[59] = 64'h0009859b4549870a; + ROM[60] = 64'h0004049b05540363; + ROM[61] = 64'h86a66485008b7363; + ROM[62] = 64'h870a87aaec7ff0ef; + ROM[63] = 64'h4531458146014681; + ROM[64] = 64'hf0ef0207c9639c05; + ROM[65] = 64'h17820094979beb1f; + ROM[66] = 64'h873e020541639381; + ROM[67] = 64'h993e99ba020a1963; + ROM[68] = 64'h870aa8094501f85d; + ROM[69] = 64'he8bff0ef45454685; + ROM[70] = 64'h60a64505fe0559e3; + ROM[71] = 64'h79a2794274e26406; + ROM[72] = 64'h61616b426ae27a02; + ROM[73] = 64'h9301020497138082; + ROM[74] = 64'hf426f8227139b7f1; + ROM[75] = 64'hec4efc064705f04a; + ROM[76] = 64'h84aad79867cde852; + ROM[77] = 64'h571c674d8932842e; + ROM[78] = 64'h03600793dff58b85; + ROM[79] = 64'h674d02072423d35c; + ROM[80] = 64'hb00026f3fffd571c; + ROM[81] = 64'h11f707130007a737; + ROM[82] = 64'h7de38f95b00027f3; + ROM[83] = 64'h8b895b1c674dfef7; + ROM[84] = 64'h0027e7934f5ccf9d; + ROM[85] = 64'he737b00026f3cf5c; + ROM[86] = 64'h27f30ff7071305f5; + ROM[87] = 64'hfef77de38f95b000; + ROM[88] = 64'hcf5c9bf54f5c674d; + ROM[89] = 64'h00989737b00026f3; + ROM[90] = 64'hb00027f367f70713; + ROM[91] = 64'h4681fef77de38f95; + ROM[92] = 64'h4501870a45814601; + ROM[93] = 64'h4681870adcfff0ef; + ROM[94] = 64'h45211aa005934601; + ROM[95] = 64'h4782e12ddbfff0ef; + ROM[96] = 64'h17d249911aa00713; + ROM[97] = 64'h099302e7876393d1; + ROM[98] = 64'h70e2744285220ff0; + ROM[99] = 64'h69e2864a86ce6a42; + ROM[100]= 64'h612174a285a67902; + ROM[101]= 64'h40e3d8dff0efb551; + ROM[102]= 64'h0207c7634782fe05; + ROM[103]= 64'h458146014681870a; + ROM[104]= 64'hd73ff0ef03700513; + ROM[105]= 64'h46014681870a87aa; + ROM[106]= 64'h0a900513403005b7; + ROM[107]= 64'h4989bf4dfc07d9e3; + ROM[108]= 64'hc3998b8583f9bfe1; + ROM[109]= 64'h4681870a0089e993; + ROM[110]= 64'hf0ef450945814601; + ROM[111]= 64'h870af8054ae3d41f; + ROM[112]= 64'h123405b746014681; + ROM[113]= 64'h40e3d2dff0ef450d; + ROM[114]= 64'h870a77c14a02f805; + ROM[115]= 64'h4601468100fa7a33; + ROM[116]= 64'hd13ff0ef451d85d2; + ROM[117]= 64'h470567cdf60543e3; + ROM[118]= 64'h4737b00026f3d3d8; + ROM[119]= 64'h27f323f70713000f; + ROM[120]= 64'hfef77de38f95b000; + ROM[121]= 64'h870a0007ae2367cd; + ROM[122]= 64'h051385d246014681; + ROM[123]= 64'h48e3cddff0ef0370; + ROM[124]= 64'h46014681870af205; + ROM[125]= 64'hf0ef086005134581; + ROM[126]= 64'h870af0054ee3cc9f; + ROM[127]= 64'h2000059346014681; + ROM[128]= 64'h56e3cb5ff0ef4541; + ROM[129]= 64'h00000000b711f005; + end // initial begin + end // if (PRELOAD_ENABLED) end endmodule diff --git a/src/mmu/adrdecs.sv b/src/mmu/adrdecs.sv index d5cab6f7b..364d9d200 100644 --- a/src/mmu/adrdecs.sv +++ b/src/mmu/adrdecs.sv @@ -51,7 +51,6 @@ module adrdecs ( adrdec newsdc(PhysicalAddress, `SDC2_BASE, `SDC2_RANGE, `SDC2_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE, SelRegions[11]); assign SelRegions[0] = ~|(SelRegions[11:1]); // none of the regions are selected - endmodule // verilator lint_on UNOPTFLAT diff --git a/src/uncore/ram_ahb.sv b/src/uncore/ram_ahb.sv index 09d1d6a1e..efd961e6f 100644 --- a/src/uncore/ram_ahb.sv +++ b/src/uncore/ram_ahb.sv @@ -71,7 +71,7 @@ module ram_ahb #(parameter BASE=0, RANGE = 65535) ( mux2 #(`PA_BITS) adrmux(HADDR, HADDRD, memwriteD | ~HREADY, RamAddr); // single-ported RAM - ram1p1rwbe #(.DEPTH(RANGE/8), .WIDTH(`XLEN)) memory(.clk(HCLK), .ce(1'b1), + ram1p1rwbe #(.DEPTH(RANGE/8), .WIDTH(`XLEN), .PRELOAD_ENABLED(`FPGA)) memory(.clk(HCLK), .ce(1'b1), .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .we(memwriteD), .din(HWDATA), .bwe(HWSTRB), .dout(HREADRam)); diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv index c58babb6f..5b1546c3b 100644 --- a/src/uncore/uncore.sv +++ b/src/uncore/uncore.sv @@ -33,30 +33,31 @@ // *** and use memread signal to reduce power when reads aren't needed module uncore ( // AHB Bus Interface - input logic HCLK, HRESETn, - input logic TIMECLK, - input logic [`PA_BITS-1:0] HADDR, - input logic [`AHBW-1:0] HWDATA, - input logic [`XLEN/8-1:0] HWSTRB, - input logic HWRITE, - input logic [2:0] HSIZE, - input logic [2:0] HBURST, - input logic [3:0] HPROT, - input logic [1:0] HTRANS, - input logic HMASTLOCK, - input logic [`AHBW-1:0] HRDATAEXT, - input logic HREADYEXT, HRESPEXT, - output logic [`AHBW-1:0] HRDATA, - output logic HREADY, HRESP, - output logic HSELEXT, + input logic HCLK, HRESETn, + input logic TIMECLK, + input logic [`PA_BITS-1:0] HADDR, + input logic [`AHBW-1:0] HWDATA, + input logic [`XLEN/8-1:0] HWSTRB, + input logic HWRITE, + input logic [2:0] HSIZE, + input logic [2:0] HBURST, + input logic [3:0] HPROT, + input logic [1:0] HTRANS, + input logic HMASTLOCK, + input logic [`AHBW-1:0] HRDATAEXT, + input logic HREADYEXT, HRESPEXT, + output logic [`AHBW-1:0] HRDATA, + output logic HREADY, HRESP, + output logic HSELEXT, + output logic HSELEXTSDC, // peripheral pins - output logic MTimerInt, MSwInt, // Timer and software interrupts from CLINT - output logic MExtInt, SExtInt, // External interrupts from PLIC - output logic [63:0] MTIME_CLINT, // MTIME, from CLINT - input logic [31:0] GPIOPinsIn, // GPIO pin input value - output logic [31:0] GPIOPinsOut, GPIOPinsEn, // GPIO pin output value and enable - input logic UARTSin, // UART serial input - output logic UARTSout // UART serial output + output logic MTimerInt, MSwInt, // Timer and software interrupts from CLINT + output logic MExtInt, SExtInt, // External interrupts from PLIC + output logic [63:0] MTIME_CLINT, // MTIME, from CLINT + input logic [31:0] GPIOPinsIn, // GPIO pin input value + output logic [31:0] GPIOPinsOut, GPIOPinsEn, // GPIO pin output value and enable + input logic UARTSin, // UART serial input + output logic UARTSout // UART serial output /*output logic SDCCmdOut, // SD Card command output output logic SDCCmdOE, // SD Card command output enable input logic SDCCmdIn, // SD Card command input @@ -87,13 +88,16 @@ module uncore ( logic [`XLEN-1:0] HREADBRIDGE; logic HRESPBRIDGE, HREADYBRIDGE, HSELBRIDGE, HSELBRIDGED; + (* mark_debug = "true" *) logic HSELEXTSDCD; + + // Determine which region of physical memory (if any) is being accessed // Use a trimmed down portion of the PMA checker - only the address decoders // Set access types to all 1 as don't cares because the MMU has already done access checking adrdecs adrdecs(HADDR, 1'b1, 1'b1, 1'b1, HSIZE[1:0], HSELRegions); // unswizzle HSEL signals - assign {HSELDTIM, HSELIROM, HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELSDC} = HSELRegions[10:1]; + assign {HSELEXTSDC, HSELDTIM, HSELIROM, HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELSDC} = HSELRegions[11:1]; // AHB -> APB bridge ahbapbbridge #(4) ahbapbbridge ( @@ -168,19 +172,19 @@ module uncore ( // AHB Read Multiplexer assign HRDATA = ({`XLEN{HSELRamD}} & HREADRam) | - ({`XLEN{HSELEXTD}} & HRDATAEXT) | + ({`XLEN{HSELEXTD | HSELEXTSDCD}} & HRDATAEXT) | ({`XLEN{HSELBRIDGED}} & HREADBRIDGE) | ({`XLEN{HSELBootRomD}} & HREADBootRom) | ({`XLEN{HSELSDCD}} & HREADSDC); assign HRESP = HSELRamD & HRESPRam | - HSELEXTD & HRESPEXT | + (HSELEXTD | HSELEXTSDCD) & HRESPEXT | HSELBRIDGE & HRESPBRIDGE | HSELBootRomD & HRESPBootRom | HSELSDC & HRESPSDC; assign HREADY = HSELRamD & HREADYRam | - HSELEXTD & HREADYEXT | + (HSELEXTD | HSELEXTSDCD) & HREADYEXT | HSELBRIDGED & HREADYBRIDGE | HSELBootRomD & HREADYBootRom | HSELSDCD & HREADYSDC | @@ -191,7 +195,7 @@ module uncore ( // takes more than 1 cycle to repsond it needs to hold on to the old select until the // device is ready. Hense this register must be selectively enabled by HREADY. // However on reset None must be seleted. - flopenl #(11) hseldelayreg(HCLK, ~HRESETn, HREADY, HSELRegions[10:0], 11'b1, {HSELDTIMD, HSELIROMD, HSELEXTD, HSELBootRomD, HSELRamD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD, HSELNoneD}); + flopenl #(12) hseldelayreg(HCLK, ~HRESETn, HREADY, HSELRegions[11:0], 11'b1, {HSELEXTSDCD, HSELDTIMD, HSELIROMD, HSELEXTD, HSELBootRomD, HSELRamD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD, HSELNoneD}); flopenr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HREADY, HSELBRIDGE, HSELBRIDGED); endmodule diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv index 4fd50a2fe..50946ada1 100644 --- a/src/wally/wallypipelinedsoc.sv +++ b/src/wally/wallypipelinedsoc.sv @@ -30,32 +30,33 @@ `include "wally-config.vh" module wallypipelinedsoc ( - input logic clk, - input logic reset_ext, // external asynchronous reset pin - output logic reset, // reset synchronized to clk to prevent races on release + input logic clk, + input logic reset_ext, // external asynchronous reset pin + output logic reset, // reset synchronized to clk to prevent races on release // AHB Interface - input logic [`AHBW-1:0] HRDATAEXT, - input logic HREADYEXT, HRESPEXT, - output logic HSELEXT, + input logic [`AHBW-1:0] HRDATAEXT, + input logic HREADYEXT, HRESPEXT, + output logic HSELEXT, + output logic HSELEXTSDC, // outputs to external memory, shared with uncore memory - output logic HCLK, HRESETn, - output logic [`PA_BITS-1:0] HADDR, - output logic [`AHBW-1:0] HWDATA, - output logic [`XLEN/8-1:0] HWSTRB, - output logic HWRITE, - output logic [2:0] HSIZE, - output logic [2:0] HBURST, - output logic [3:0] HPROT, - output logic [1:0] HTRANS, - output logic HMASTLOCK, - output logic HREADY, + output logic HCLK, HRESETn, + output logic [`PA_BITS-1:0] HADDR, + output logic [`AHBW-1:0] HWDATA, + output logic [`XLEN/8-1:0] HWSTRB, + output logic HWRITE, + output logic [2:0] HSIZE, + output logic [2:0] HBURST, + output logic [3:0] HPROT, + output logic [1:0] HTRANS, + output logic HMASTLOCK, + output logic HREADY, // I/O Interface - input logic TIMECLK, // optional for CLINT MTIME counter - input logic [31:0] GPIOPinsIn, // inputs from GPIO - output logic [31:0] GPIOPinsOut, // output values for GPIO - output logic [31:0] GPIOPinsEn, // output enables for GPIO - input logic UARTSin, // UART serial data input - output logic UARTSout // UART serial data output + input logic TIMECLK, // optional for CLINT MTIME counter + input logic [31:0] GPIOPinsIn, // inputs from GPIO + output logic [31:0] GPIOPinsOut, // output values for GPIO + output logic [31:0] GPIOPinsEn, // output enables for GPIO + input logic UARTSin, // UART serial data input + output logic UARTSout // UART serial data output /*input logic SDCCmdIn, // SDC Command input output logic SDCCmdOut, // SDC Command output output logic SDCCmdOE, // SDC Command output enable @@ -84,7 +85,7 @@ module wallypipelinedsoc ( if (`BUS_SUPPORTED) begin : uncore uncore uncore(.HCLK, .HRESETn, .TIMECLK, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, - .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, + .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, .HSELEXTSDC, .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT /*.SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK*/); diff --git a/tests/custom/boot/boot.c b/tests/custom/boot/boot.c index c9b2c6451..3f0a22c49 100644 --- a/tests/custom/boot/boot.c +++ b/tests/custom/boot/boot.c @@ -116,15 +116,17 @@ struct sdc_regs { #define MAX_BLOCK_CNT 0x1000 -static struct sdc_regs * const regs __attribute__((section(".rodata"))) = (struct sdc_regs *)0x00013000; +#define SDC 0x00013000; -static int errno __attribute__((section(".bss"))); +// static struct sdc_regs * const regs __attribute__((section(".rodata"))) = (struct sdc_regs *)0x00013000; + +// static int errno __attribute__((section(".bss"))); // static DSTATUS drv_status __attribute__((section(".bss"))); -static BYTE card_type __attribute__((section(".bss"))); -static uint32_t response[4] __attribute__((section(".bss"))); -static int alt_mem __attribute__((section(".bss"))); +// static BYTE card_type __attribute__((section(".bss"))); +// static uint32_t response[4] __attribute__((section(".bss"))); +// static int alt_mem __attribute__((section(".bss"))); -static const char * errno_to_str(void) { +/*static const char * errno_to_str(void) { switch (errno) { case ERR_EOF: return "Unexpected EOF"; case ERR_NOT_ELF: return "Not an ELF file"; @@ -139,7 +141,7 @@ static const char * errno_to_str(void) { case FR_TIMEOUT: return "Timeout"; } return "Unknown error code"; -} + }*/ static void usleep(unsigned us) { uintptr_t cycles0; @@ -151,7 +153,9 @@ static void usleep(unsigned us) { } } -static int sdc_cmd_finish(unsigned cmd) { +static int sdc_cmd_finish(unsigned cmd, uint32_t * response) { + struct sdc_regs * regs = (struct sdc_regs *)SDC; + while (1) { unsigned status = regs->cmd_int_status; if (status) { @@ -166,10 +170,10 @@ static int sdc_cmd_finish(unsigned cmd) { response[3] = regs->response4; return 0; } - errno = FR_DISK_ERR; + /* errno = FR_DISK_ERR; if (status & SDC_CMD_INT_STATUS_CTE) errno = FR_TIMEOUT; if (status & SDC_CMD_INT_STATUS_CCRC) errno = ERR_CMD_CRC; - if (status & SDC_CMD_INT_STATUS_CIE) errno = ERR_CMD_CHECK; + if (status & SDC_CMD_INT_STATUS_CIE) errno = ERR_CMD_CHECK;*/ break; } } @@ -178,21 +182,24 @@ static int sdc_cmd_finish(unsigned cmd) { static int sdc_data_finish(void) { int status; - + struct sdc_regs * regs = (struct sdc_regs *)SDC; + while ((status = regs->dat_int_status) == 0) {} regs->dat_int_status = 0; while (regs->software_reset != 0) {} if (status == SDC_DAT_INT_STATUS_TRS) return 0; - errno = FR_DISK_ERR; + /* errno = FR_DISK_ERR; if (status & SDC_DAT_INT_STATUS_CTE) errno = FR_TIMEOUT; if (status & SDC_DAT_INT_STATUS_CRC) errno = ERR_DATA_CRC; - if (status & SDC_DAT_INT_STATUS_CFE) errno = ERR_DATA_FIFO; + if (status & SDC_DAT_INT_STATUS_CFE) errno = ERR_DATA_FIFO;*/ return -1; } -static int send_data_cmd(unsigned cmd, unsigned arg, void * buf, unsigned blocks) { - unsigned command = (cmd & 0x3f) << 8; +static int send_data_cmd(unsigned cmd, unsigned arg, void * buf, unsigned blocks, uint32_t * response) { + struct sdc_regs * regs = (struct sdc_regs *)SDC; + + unsigned command = (cmd & 0x3f) << 8; switch (cmd) { case CMD0: case CMD4: @@ -262,29 +269,32 @@ static int send_data_cmd(unsigned cmd, unsigned arg, void * buf, unsigned blocks if (blocks) { command |= 1 << 5; if ((intptr_t)buf & 3) { - errno = ERR_BUF_ALIGNMENT; + // errno = ERR_BUF_ALIGNMENT; return -1; } regs->dma_addres = (uint64_t)(intptr_t)buf; regs->block_size = 511; regs->block_count = blocks - 1; - regs->data_timeout = 0xFFFFFF; + regs->data_timeout = 0x1FFFFFF; } regs->command = command; regs->cmd_timeout = 0xFFFFF; regs->argument = arg; - if (sdc_cmd_finish(cmd) < 0) return -1; + if (sdc_cmd_finish(cmd, response) < 0) return -1; if (blocks) return sdc_data_finish(); return 0; } -#define send_cmd(cmd, arg) send_data_cmd(cmd, arg, NULL, 0) +#define send_cmd(cmd, arg, response) send_data_cmd(cmd, arg, NULL, 0, response) -static int ini_sd(void) { +static BYTE ini_sd(void) { + struct sdc_regs * regs = (struct sdc_regs *)SDC; unsigned rca; + BYTE card_type; + uint32_t response[4]; /* Reset controller */ regs->software_reset = 1; @@ -311,12 +321,12 @@ static int ini_sd(void) { } /* Enter Idle state */ - send_cmd(CMD0, 0); + send_cmd(CMD0, 0, response); card_type = CT_SD1; - if (send_cmd(CMD8, 0x1AA) == 0) { + if (send_cmd(CMD8, 0x1AA, response) == 0) { if ((response[0] & 0xfff) != 0x1AA) { - errno = ERR_CMD_CHECK; + // errno = ERR_CMD_CHECK; return -1; } card_type = CT_SD2; @@ -325,7 +335,7 @@ static int ini_sd(void) { /* Wait for leaving idle state (ACMD41 with HCS bit) */ while (1) { /* ACMD41, Set Operating Conditions: Host High Capacity & 3.3V */ - if (send_cmd(CMD55, 0) < 0 || send_cmd(ACMD41, 0x40300000) < 0) return -1; + if (send_cmd(CMD55, 0, response) < 0 || send_cmd(ACMD41, 0x40300000, response) < 0) return -1; if (response[0] & (1 << 31)) { if (response[0] & (1 << 30)) card_type |= CT_BLOCK; break; @@ -333,15 +343,15 @@ static int ini_sd(void) { } /* Enter Identification state */ - if (send_cmd(CMD2, 0) < 0) return -1; + if (send_cmd(CMD2, 0, response) < 0) return -1; /* Get RCA (Relative Card Address) */ rca = 0x1234; - if (send_cmd(CMD3, rca << 16) < 0) return -1; + if (send_cmd(CMD3, rca << 16, response) < 0) return -1; rca = response[0] >> 16; /* Select card */ - if (send_cmd(CMD7, rca << 16) < 0) return -1; + if (send_cmd(CMD7, rca << 16, response) < 0) return -1; /* Clock 25MHz */ // 22Mhz/2 = 11Mhz @@ -350,16 +360,16 @@ static int ini_sd(void) { /* Bus width 1-bit */ regs->control = 0; - if (send_cmd(CMD55, rca << 16) < 0 || send_cmd(ACMD6, 0) < 0) return -1; + if (send_cmd(CMD55, rca << 16, response) < 0 || send_cmd(ACMD6, 0, response) < 0) return -1; /* Set R/W block length to 512 */ - if (send_cmd(CMD16, 512) < 0) return -1; + if (send_cmd(CMD16, 512, response) < 0) return -1; // drv_status &= ~STA_NOINIT; - return 0; + return card_type; } -int disk_read(BYTE * buf, LBA_t sector, UINT count) { +int disk_read(BYTE * buf, LBA_t sector, UINT count, BYTE card_type) { /* This is not needed. This has everything to do with the FAT filesystem stuff that I'm not including. All I need to do is @@ -370,13 +380,16 @@ int disk_read(BYTE * buf, LBA_t sector, UINT count) { // if (!count) return RES_PARERR; /* if (drv_status & STA_NOINIT) return RES_NOTRDY; */ + uint32_t response[4]; + struct sdc_regs * regs = (struct sdc_regs *)SDC; + /* Convert LBA to byte address if needed */ if (!(card_type & CT_BLOCK)) sector *= 512; while (count > 0) { UINT bcnt = count > MAX_BLOCK_CNT ? MAX_BLOCK_CNT : count; unsigned bytes = bcnt * 512; - if (send_data_cmd(bcnt == 1 ? CMD17 : CMD18, sector, buf, bcnt) < 0) return 1; - if (bcnt > 1 && send_cmd(CMD12, 0) < 0) return 1; + if (send_data_cmd(bcnt == 1 ? CMD17 : CMD18, sector, buf, bcnt, response) < 0) return 1; + if (bcnt > 1 && send_cmd(CMD12, 0, response) < 0) return 1; sector += (card_type & CT_BLOCK) ? bcnt : bytes; count -= bcnt; buf += bytes; @@ -386,11 +399,13 @@ int disk_read(BYTE * buf, LBA_t sector, UINT count) { } void copyFlash(QWORD address, QWORD * Dst, DWORD numBlocks) { - ini_sd(); + BYTE card_type; + + card_type = ini_sd(); BYTE * buf = (BYTE *)Dst; - if (disk_read(buf, (LBA_t)address, (UINT)numBlocks) < 0) /* UART Print function?*/; + if (disk_read(buf, (LBA_t)address, (UINT)numBlocks, card_type) < 0) /* UART Print function?*/; } /* diff --git a/tests/custom/linker1000.x b/tests/custom/linker1000.x index 4156c6571..6d9e948a6 100644 --- a/tests/custom/linker1000.x +++ b/tests/custom/linker1000.x @@ -72,6 +72,7 @@ SECTIONS PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); + . = 0x0000000000002000; .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } .rodata1 : { *(.rodata1) } .sdata2 : From b3aaa87cba400f41b76d88cb77738cc9fc7c557a Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Fri, 14 Jul 2023 13:36:44 -0500 Subject: [PATCH 21/22] Modified bootloader to access GUID partitions. SDC interrupt to PLIC. Since writing an SD card image generation script, the bootloader needed to be altered to access individual binaries from specific partitions. A new file, gpt.c with it's header gpt.h, have been added to the bootloader to facilitate this. The SDC has been added to the device tree for the VCU108 board. Additionally the SDC interrupt signal was added to the PLIC node in the device tree. The PLIC itself was modified to accept the SDC interrupt signal. --- config/fpga/wally-config.vh | 1 + fpga/proberange | 78 +++++++++++++++++++++++++++++++ fpga/probes | 76 ++++++++++++++++++++++++++++++ fpga/src/fpgaTop.v | 12 +++-- linux/buildroot-scripts/Makefile | 1 + linux/devicetree/wally-vcu108.dts | 14 ++++++ src/uncore/plic_apb.sv | 27 ++++++----- src/uncore/uncore.sv | 5 +- src/wally/wallypipelinedsoc.sv | 5 +- tests/custom/boot/Makefile | 6 ++- tests/custom/boot/boot.c | 10 ++-- tests/custom/boot/boot.h | 11 +++++ tests/custom/boot/gpt.c | 46 ++++++++++++++++++ tests/custom/boot/gpt.h | 40 ++++++++++++++++ 14 files changed, 309 insertions(+), 23 deletions(-) create mode 100755 fpga/proberange create mode 100755 fpga/probes create mode 100644 tests/custom/boot/gpt.c create mode 100644 tests/custom/boot/gpt.h diff --git a/config/fpga/wally-config.vh b/config/fpga/wally-config.vh index c89d3eec8..e3686553f 100644 --- a/config/fpga/wally-config.vh +++ b/config/fpga/wally-config.vh @@ -141,6 +141,7 @@ `define PLIC_NUM_SRC 53 `define PLIC_UART_ID 10 `define PLIC_GPIO_ID 3 +`define PLIC_SDC_ID 20 `define BPRED_SUPPORTED 1 `define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 diff --git a/fpga/proberange b/fpga/proberange new file mode 100755 index 000000000..a5eccb7f9 --- /dev/null +++ b/fpga/proberange @@ -0,0 +1,78 @@ +#!/usr/bin/python3 + +import sys + +def usage(): + print("Usage: ./probes list_of_probes outfile") + +def header(): + return """create_debug_core u_ila_0 ila + +set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_0] +set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] +set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] +set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] +set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] +set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] +startgroup +set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ] +set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ] +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ] +set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ] +endgroup +connect_debug_port u_ila_0/clk [get_nets [list xlnx_ddr4_c0/inst/u_ddr4_infrastructure/addn_ui_clkout1 ]]""" + +def convertLine(x): + temp = x.split() + temp[1] = int(temp[1]) + temp[2] = int(temp[2]) + return tuple(temp) + +def probeBits( probe ): + str = '' + + if (probe[1] > 1): + for i in range(probe[1]): + if i != (probe[1]-1): + str = str + f"{{{probe[0]}[{i}]}} " + else: + str = str + f"{{{probe[0]}[{i}]}} " + + else: + str = f'{{{probe[0]}}}' + + return str + +def printProbe( probe,): + bits = probeBits(probe) + + return ( + f'create_debug_port u_ila_0 probe\n' + f'set_property port_width {probe[1]} [get_debug_ports u_ila_0/probe{probe[2]}]\n' + f'set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe{probe[2]}]\n' + f'connect_debug_port u_ila_0/probe{probe[2]} [get_nets [list {bits}]]\n\n' + ) + +def main(args): + if (len(args) != 2): + usage() + exit() + + probeList = [] + + with open(args[0]) as probeListFile: + probeList = list(map(convertLine, probeListFile.readlines())) + + with open(args[1], 'w') as outfile: + # outfile.write(header()) + # outfile.write("\n\n") + for i in range(len(probeList)): + outfile.write(printProbe(probeList[i])) + +if __name__ == '__main__': + main(sys.argv[1:]) + + + diff --git a/fpga/probes b/fpga/probes new file mode 100755 index 000000000..5868bc80f --- /dev/null +++ b/fpga/probes @@ -0,0 +1,76 @@ +#!/usr/bin/python3 + +import sys + +def usage(): + print("Usage: ./probes list_of_probes outfile") + +def header(): + return """create_debug_core u_ila_0 ila + +set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_0] +set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] +set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] +set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] +set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] +set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] +startgroup +set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ] +set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ] +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ] +set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ] +endgroup +connect_debug_port u_ila_0/clk [get_nets [list xlnx_ddr4_c0/inst/u_ddr4_infrastructure/addn_ui_clkout1 ]]""" + +def convertLine(x): + temp = x.split() + temp[1] = int(temp[1]) + return tuple(temp) + +def probeBits( probe ): + str = '' + + if (probe[1] > 1): + for i in range(probe[1]): + if i != (probe[1]-1): + str = str + f"{{{probe[0]}[{i}]}} " + else: + str = str + f"{{{probe[0]}[{i}]}} " + + else: + str = f'{{{probe[0]}}}' + + return str + +def printProbe( probe, i ): + bits = probeBits(probe) + + return ( + f'create_debug_port u_ila_0 probe\n' + f'set_property port_width {probe[1]} [get_debug_ports u_ila_0/probe{i}]\n' + f'set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe{i}]\n' + f'connect_debug_port u_ila_0/probe{i} [get_nets [list {bits}]]\n\n' + ) + +def main(args): + if (len(args) != 2): + usage() + exit() + + probeList = [] + + with open(args[0]) as probeListFile: + probeList = list(map(convertLine, probeListFile.readlines())) + + with open(args[1], 'w') as outfile: + outfile.write(header()) + outfile.write("\n\n") + for i in range(len(probeList)): + outfile.write(printProbe(probeList[i], i)) + +if __name__ == '__main__': + main(sys.argv[1:]) + + diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index 649b7cd57..3c5b21cb2 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -41,7 +41,7 @@ module fpgaTop inout [3:0] SDCDat, output SDCCLK, inout SDCCmd, - input SDCCD, + input SDCCD, output calib, output cpu_reset, @@ -415,6 +415,9 @@ module fpgaTop wire sd_cmd_reg_o; wire sd_cmd_reg_t; + // SD Card Interrupt signal + wire SDCintr; + // New SDC Data IOBUF connections wire [3:0] sd_dat_i; wire [3:0] sd_dat_reg_o; @@ -506,7 +509,8 @@ module fpgaTop .GPIOPinsEn(GPIOPinsEn), // UART .UARTSin(UARTSin), - .UARTSout(UARTSout) + .UARTSout(UARTSout), + .SDCIntr(SDCIntr) // SD Card /*.SDCDatIn(SDCDatIn), .SDCCmdIn(SDCCmdIn), @@ -864,7 +868,9 @@ module fpgaTop .sd_cmd_i(sd_cmd_i), .sdio_clk(SDCCLK), - .sdio_cd(SDCCD) + .sdio_cd(SDCCD), + + .interrupt(SDCIntr) ); xlnx_axi_dwidth_conv_32to64 axi_conv_up diff --git a/linux/buildroot-scripts/Makefile b/linux/buildroot-scripts/Makefile index 41ceacb41..d8da7092f 100644 --- a/linux/buildroot-scripts/Makefile +++ b/linux/buildroot-scripts/Makefile @@ -9,6 +9,7 @@ all: generate: # generating device tree binary dtc -I dts -O dtb ../devicetree/wally-virt.dts > ${IMAGES}/wally-virt.dtb + dtc -I dts -O dtb ../devicetree/wally-vcu108.dts > ${IMAGES}/wally-vcu108.dtb disassemble: mkdir -p ${DIS} diff --git a/linux/devicetree/wally-vcu108.dts b/linux/devicetree/wally-vcu108.dts index a8093042e..6b02a55ba 100644 --- a/linux/devicetree/wally-vcu108.dts +++ b/linux/devicetree/wally-vcu108.dts @@ -67,6 +67,20 @@ #address-cells = <0x00>; }; + mmc@13000 { + interrupts = <0x14>; + compatible = "riscv,axi-sd-card-1.0"; + reg = <0x00 0x13000 0x00 0x7F>; + fifo-depth = <256>; + bus-width = <4>; + interrupt-parent = <0x03>; + clock = <0x14FB180>; + max-frequency = <0xA7D8C0>; + cap-sd-highspeed; + cap-mmc-highspeed; + no-sdio; + }; + clint@2000000 { interrupts-extended = <0x02 0x03 0x02 0x07>; reg = <0x00 0x2000000 0x00 0x10000>; diff --git a/src/uncore/plic_apb.sv b/src/uncore/plic_apb.sv index 76b0ebbdc..bd637c358 100644 --- a/src/uncore/plic_apb.sv +++ b/src/uncore/plic_apb.sv @@ -43,17 +43,17 @@ // hardcoded to 2 contexts for now; later upgrade to arbitrary (up to 15872) contexts module plic_apb ( - input logic PCLK, PRESETn, - input logic PSEL, - input logic [27:0] PADDR, - input logic [`XLEN-1:0] PWDATA, - input logic [`XLEN/8-1:0] PSTRB, - input logic PWRITE, - input logic PENABLE, - output logic [`XLEN-1:0] PRDATA, - output logic PREADY, - input logic UARTIntr,GPIOIntr, - output logic MExtInt, SExtInt + input logic PCLK, PRESETn, + input logic PSEL, + input logic [27:0] PADDR, + input logic [`XLEN-1:0] PWDATA, + input logic [`XLEN/8-1:0] PSTRB, + input logic PWRITE, + input logic PENABLE, + output logic [`XLEN-1:0] PRDATA, + output logic PREADY, + input logic UARTIntr,GPIOIntr,SDCIntr, + output logic MExtInt, SExtInt ); logic memwrite, memread; @@ -167,6 +167,11 @@ module plic_apb ( `ifdef PLIC_UART_ID requests[`PLIC_UART_ID] = UARTIntr; `endif + + // Jacob: July 8th 2023 + `ifdef PLIC_SDC_ID + requests[`PLIC_SDC_ID] = SDCIntr; + `endif end // pending interrupt requests diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv index 5b1546c3b..d66b0e541 100644 --- a/src/uncore/uncore.sv +++ b/src/uncore/uncore.sv @@ -57,7 +57,8 @@ module uncore ( input logic [31:0] GPIOPinsIn, // GPIO pin input value output logic [31:0] GPIOPinsOut, GPIOPinsEn, // GPIO pin output value and enable input logic UARTSin, // UART serial input - output logic UARTSout // UART serial output + output logic UARTSout, // UART serial output + input logic SDCIntr /*output logic SDCCmdOut, // SD Card command output output logic SDCCmdOE, // SD Card command output enable input logic SDCCmdIn, // SD Card command input @@ -130,7 +131,7 @@ module uncore ( if (`PLIC_SUPPORTED == 1) begin : plic plic_apb plic(.PCLK, .PRESETn, .PSEL(PSEL[2]), .PADDR(PADDR[27:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, - .PRDATA(PRDATA[2]), .PREADY(PREADY[2]), .UARTIntr, .GPIOIntr, .MExtInt, .SExtInt); + .PRDATA(PRDATA[2]), .PREADY(PREADY[2]), .UARTIntr, .GPIOIntr, .SDCIntr, .MExtInt, .SExtInt); end else begin : plic assign MExtInt = 0; assign SExtInt = 0; diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv index 50946ada1..0ecccbac0 100644 --- a/src/wally/wallypipelinedsoc.sv +++ b/src/wally/wallypipelinedsoc.sv @@ -56,7 +56,8 @@ module wallypipelinedsoc ( output logic [31:0] GPIOPinsOut, // output values for GPIO output logic [31:0] GPIOPinsEn, // output enables for GPIO input logic UARTSin, // UART serial data input - output logic UARTSout // UART serial data output + output logic UARTSout, // UART serial data output + input logic SDCIntr /*input logic SDCCmdIn, // SDC Command input output logic SDCCmdOut, // SDC Command output output logic SDCCmdOE, // SDC Command output enable @@ -87,7 +88,7 @@ module wallypipelinedsoc ( .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, .HSELEXTSDC, .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, - .UARTSout, .MTIME_CLINT + .UARTSout, .MTIME_CLINT, .SDCIntr /*.SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK*/); end diff --git a/tests/custom/boot/Makefile b/tests/custom/boot/Makefile index 8294f2375..1c3b8da6d 100644 --- a/tests/custom/boot/Makefile +++ b/tests/custom/boot/Makefile @@ -28,7 +28,9 @@ LINKER :=$(ROOT)/linker1000.x AFLAGS =$(MARCH) $(MABI) -W -CFLAGS =$(MARCH) $(MABI) -mcmodel=medany -O2 +# Override directive allows us to prepend other options on the command line +# e.g. $ make CFLAGS=-g +override CFLAGS +=$(MARCH) $(MABI) -mcmodel=medany -O2 AS=riscv64-unknown-elf-as CC=riscv64-unknown-elf-gcc AR=riscv64-unknown-elf-ar @@ -104,7 +106,7 @@ $(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(CPPEXT) # convert to hex $(TARGET).memfile: $(TARGET) @echo 'Making object dump file.' - @riscv64-unknown-elf-objdump -D $< > $<.objdump + riscv64-unknown-elf-objdump -DS $< > $<.objdump @echo 'Making memory file' riscv64-unknown-elf-elf2hex --bit-width 64 --input $^ --output $@ extractFunctionRadix.sh $<.objdump diff --git a/tests/custom/boot/boot.c b/tests/custom/boot/boot.c index 3f0a22c49..6e4780f55 100644 --- a/tests/custom/boot/boot.c +++ b/tests/custom/boot/boot.c @@ -1,5 +1,6 @@ #include #include "boot.h" +#include "gpt.h" /* Card type flags (card_type) */ #define CT_MMC 0x01 /* MMC ver 3 */ @@ -400,12 +401,15 @@ int disk_read(BYTE * buf, LBA_t sector, UINT count, BYTE card_type) { void copyFlash(QWORD address, QWORD * Dst, DWORD numBlocks) { BYTE card_type; - + int ret = 0; + card_type = ini_sd(); - BYTE * buf = (BYTE *)Dst; + // BYTE * buf = (BYTE *)Dst; - if (disk_read(buf, (LBA_t)address, (UINT)numBlocks, card_type) < 0) /* UART Print function?*/; + // if (disk_read(buf, (LBA_t)address, (UINT)numBlocks, card_type) < 0) /* UART Print function?*/; + + ret = gpt_load_partitions(card_type); } /* diff --git a/tests/custom/boot/boot.h b/tests/custom/boot/boot.h index 3dd7116a7..0f75fbf9e 100644 --- a/tests/custom/boot/boot.h +++ b/tests/custom/boot/boot.h @@ -11,5 +11,16 @@ typedef WORD WCHAR; typedef QWORD LBA_t; +// Define memory locations of boot images ===================== +// These locations are copied from the generic configuration +// of OpenSBI. These addresses can be found in: +// buildroot/output/build/opensbi-0.9/platform/generic/config.mk +#define FDT_ADDRESS 0x80200000 // FW_JUMP_FDT_ADDR +#define OPENSBI_ADDRESS 0x80000000 // FW_TEXT_START +#define KERNEL_ADDRESS 0x82200000 // FW_JUMP_ADDR + +// Export disk_read +int disk_read(BYTE * buf, LBA_t sector, UINT count, BYTE card_type); + #endif // WALLYBOOT diff --git a/tests/custom/boot/gpt.c b/tests/custom/boot/gpt.c new file mode 100644 index 000000000..97e3e4e46 --- /dev/null +++ b/tests/custom/boot/gpt.c @@ -0,0 +1,46 @@ +#include "gpt.h" +#include "boot.h" +#include + +/* PSUEDOCODE + + Need to load GPT LBA 1 and read through the partition entries. + I need to find each of the relevant partition entries, possibly + by their partition names. + +*/ + +int gpt_load_partitions(BYTE card_type) { + // In this version of the GPT partition code + // I'm going to assume that the SD card is already initialized. + + // size_t block_size = 512/8; + // long int lba1_buf[block_size]; + + BYTE lba1_buf[512]; + + int ret = 0; + //ret = disk_read(/* BYTE * buf, LBA_t sector, UINT count, BYTE card_type */); + ret = disk_read(lba1_buf, 1, 1, card_type); + + /* Possible error handling with UART message + if ( ret != 0 ) { + + }*/ + + gpt_pth_t *lba1 = (gpt_pth_t *)lba1_buf; + + BYTE lba2_buf[512]; + ret = disk_read(lba2_buf, (LBA_t)lba1->partition_entries_lba, 1, card_type); + + // Load parition entries for the relevant boot partitions. + partition_entries_t *fdt = (partition_entries_t *)(lba2_buf); + partition_entries_t *opensbi = (partition_entries_t *)(lba2_buf + 128); + partition_entries_t *kernel = (partition_entries_t *)(lba2_buf + 256); + + ret = disk_read((BYTE *)FDT_ADDRESS, fdt->first_lba, fdt->last_lba - fdt->first_lba + 1, card_type); + ret = disk_read((BYTE *)OPENSBI_ADDRESS, opensbi->first_lba, opensbi->last_lba - opensbi->first_lba + 1, card_type); + ret = disk_read((BYTE *)KERNEL_ADDRESS, kernel->first_lba,kernel->last_lba - kernel->first_lba + 1, card_type); + + return 0; +} diff --git a/tests/custom/boot/gpt.h b/tests/custom/boot/gpt.h new file mode 100644 index 000000000..4aefae229 --- /dev/null +++ b/tests/custom/boot/gpt.h @@ -0,0 +1,40 @@ +#pragma once + +#include +#include "boot.h" + +// LBA 0: Protective MBR +// ignored here + +// Partition Table Header (LBA 1) +typedef struct gpt_pth +{ + uint64_t signature; + uint32_t revision; + uint32_t header_size; //! little endian, usually 0x5c = 92 + uint32_t crc_header; + uint32_t reserved; //! must be 0 + uint64_t current_lba; + uint64_t backup_lba; + uint64_t first_usable_lba; + uint64_t last_usable_lba; + uint8_t disk_guid[16]; + uint64_t partition_entries_lba; + uint32_t nr_partition_entries; + uint32_t size_partition_entry; //! usually 0x80 = 128 + uint32_t crc_partition_entry; +} gpt_pth_t; + +// Partition Entries (LBA 2-33) +typedef struct partition_entries +{ + uint8_t partition_type_guid[16]; + uint8_t partition_guid[16]; + uint64_t first_lba; + uint64_t last_lba; //! inclusive + uint64_t attributes; + uint8_t name[72]; //! utf16 encoded +} partition_entries_t; + +// Find boot partition and load it to the destination +int gpt_load_partitions(BYTE card_type); From 380d96b359ff3099ea7c6ee0307994bdaaa563a8 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Thu, 20 Jul 2023 14:15:59 -0500 Subject: [PATCH 22/22] Working new boot process. Buildroot package for sdc. --- fpga/constraints/debug2.xdc | 5 + fpga/constraints/vcu-small-debug.xdc | 56 + fpga/generator/wally.tcl | 2 +- fpga/src/fpgaTop.v | 2 +- .../buildroot-packages/fpga-axi-sdc/Config.in | 6 + .../fpga-axi-sdc/fpga-axi-sdc.mk | 10 + .../fpga-axi-sdc/fpga-axi-sdc.mk~ | 7 + linux/buildroot-packages/linux.config | 1423 ++++++ .../package-source/Makefile | 9 + .../package-source/fpga-axi-sdc.c | 498 +++ linux/buildroot-packages/package.patch | 12 + linux/buildroot-packages/wally.config | 3808 +++++++++++++++++ linux/sdcard/Makefile | 9 + linux/sdcard/flash-sd.sh | 120 + linux/sdcard/make-img.sh | 110 + src/generic/mem/rom1p1r.sv | 146 + tests/custom/boot/bios.s | 2 +- tests/custom/boot/boot.h | 4 +- 18 files changed, 6224 insertions(+), 5 deletions(-) create mode 100644 fpga/constraints/vcu-small-debug.xdc create mode 100644 linux/buildroot-packages/fpga-axi-sdc/Config.in create mode 100644 linux/buildroot-packages/fpga-axi-sdc/fpga-axi-sdc.mk create mode 100644 linux/buildroot-packages/fpga-axi-sdc/fpga-axi-sdc.mk~ create mode 100644 linux/buildroot-packages/linux.config create mode 100644 linux/buildroot-packages/package-source/Makefile create mode 100644 linux/buildroot-packages/package-source/fpga-axi-sdc.c create mode 100644 linux/buildroot-packages/package.patch create mode 100644 linux/buildroot-packages/wally.config create mode 100644 linux/sdcard/Makefile create mode 100755 linux/sdcard/flash-sd.sh create mode 100755 linux/sdcard/make-img.sh diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 0db255fa0..0ce60a316 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -1238,3 +1238,8 @@ create_debug_port u_ila_0 probe set_property port_width 12 [get_debug_ports u_ila_0/probe242] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe242] connect_debug_port u_ila_0/probe242 [get_nets [list {axiSDC/sd_data_serial_host0/blkcnt_reg[0]} {axiSDC/sd_data_serial_host0/blkcnt_reg[1]} {axiSDC/sd_data_serial_host0/blkcnt_reg[2]} {axiSDC/sd_data_serial_host0/blkcnt_reg[3]} {axiSDC/sd_data_serial_host0/blkcnt_reg[4]} {axiSDC/sd_data_serial_host0/blkcnt_reg[5]} {axiSDC/sd_data_serial_host0/blkcnt_reg[6]} {axiSDC/sd_data_serial_host0/blkcnt_reg[7]} {axiSDC/sd_data_serial_host0/blkcnt_reg[8]} {axiSDC/sd_data_serial_host0/blkcnt_reg[9]} {axiSDC/sd_data_serial_host0/blkcnt_reg[10]} {axiSDC/sd_data_serial_host0/blkcnt_reg[11]}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe243] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe243] +connect_debug_port u_ila_0/probe243 [get_nets [list {SDCIntr}]] diff --git a/fpga/constraints/vcu-small-debug.xdc b/fpga/constraints/vcu-small-debug.xdc new file mode 100644 index 000000000..2b3fab112 --- /dev/null +++ b/fpga/constraints/vcu-small-debug.xdc @@ -0,0 +1,56 @@ +create_debug_core u_ila_0 ila + +set_property C_DATA_DEPTH 2048 [get_debug_cores u_ila_0] +set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] +set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] +set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] +set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] +set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] +startgroup +set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ] +set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ] +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ] +set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ] +endgroup +connect_debug_port u_ila_0/clk [get_nets [list xlnx_ddr4_c0/inst/u_ddr4_infrastructure/addn_ui_clkout1 ]] + +set_property port_width 64 [get_debug_ports u_ila_0/probe0] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] +connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} {wallypipelinedsoc/core/PCM[33]} {wallypipelinedsoc/core/PCM[34]} {wallypipelinedsoc/core/PCM[35]} {wallypipelinedsoc/core/PCM[36]} {wallypipelinedsoc/core/PCM[37]} {wallypipelinedsoc/core/PCM[38]} {wallypipelinedsoc/core/PCM[39]} {wallypipelinedsoc/core/PCM[40]} {wallypipelinedsoc/core/PCM[41]} {wallypipelinedsoc/core/PCM[42]} {wallypipelinedsoc/core/PCM[43]} {wallypipelinedsoc/core/PCM[44]} {wallypipelinedsoc/core/PCM[45]} {wallypipelinedsoc/core/PCM[46]} {wallypipelinedsoc/core/PCM[47]} {wallypipelinedsoc/core/PCM[48]} {wallypipelinedsoc/core/PCM[49]} {wallypipelinedsoc/core/PCM[50]} {wallypipelinedsoc/core/PCM[51]} {wallypipelinedsoc/core/PCM[52]} {wallypipelinedsoc/core/PCM[53]} {wallypipelinedsoc/core/PCM[54]} {wallypipelinedsoc/core/PCM[55]} {wallypipelinedsoc/core/PCM[56]} {wallypipelinedsoc/core/PCM[57]} {wallypipelinedsoc/core/PCM[58]} {wallypipelinedsoc/core/PCM[59]} {wallypipelinedsoc/core/PCM[60]} {wallypipelinedsoc/core/PCM[61]} {wallypipelinedsoc/core/PCM[62]} {wallypipelinedsoc/core/PCM[63]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe1] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] +connect_debug_port u_ila_0/probe1 [get_nets [list wallypipelinedsoc/core/TrapM ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe2] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] +connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsoc/core/InstrValidM ]] + +create_debug_port u_ila_0 probe +set_property port_width 32 [get_debug_ports u_ila_0/probe3] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] +connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsoc/core/InstrM[31]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 32 [get_debug_ports u_ila_0/probe4] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] +connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHADDR[0]} {wallypipelinedsoc/core/lsu/LSUHADDR[1]} {wallypipelinedsoc/core/lsu/LSUHADDR[2]} {wallypipelinedsoc/core/lsu/LSUHADDR[3]} {wallypipelinedsoc/core/lsu/LSUHADDR[4]} {wallypipelinedsoc/core/lsu/LSUHADDR[5]} {wallypipelinedsoc/core/lsu/LSUHADDR[6]} {wallypipelinedsoc/core/lsu/LSUHADDR[7]} {wallypipelinedsoc/core/lsu/LSUHADDR[8]} {wallypipelinedsoc/core/lsu/LSUHADDR[9]} {wallypipelinedsoc/core/lsu/LSUHADDR[10]} {wallypipelinedsoc/core/lsu/LSUHADDR[11]} {wallypipelinedsoc/core/lsu/LSUHADDR[12]} {wallypipelinedsoc/core/lsu/LSUHADDR[13]} {wallypipelinedsoc/core/lsu/LSUHADDR[14]} {wallypipelinedsoc/core/lsu/LSUHADDR[15]} {wallypipelinedsoc/core/lsu/LSUHADDR[16]} {wallypipelinedsoc/core/lsu/LSUHADDR[17]} {wallypipelinedsoc/core/lsu/LSUHADDR[18]} {wallypipelinedsoc/core/lsu/LSUHADDR[19]} {wallypipelinedsoc/core/lsu/LSUHADDR[20]} {wallypipelinedsoc/core/lsu/LSUHADDR[21]} {wallypipelinedsoc/core/lsu/LSUHADDR[22]} {wallypipelinedsoc/core/lsu/LSUHADDR[23]} {wallypipelinedsoc/core/lsu/LSUHADDR[24]} {wallypipelinedsoc/core/lsu/LSUHADDR[25]} {wallypipelinedsoc/core/lsu/LSUHADDR[26]} {wallypipelinedsoc/core/lsu/LSUHADDR[27]} {wallypipelinedsoc/core/lsu/LSUHADDR[28]} {wallypipelinedsoc/core/lsu/LSUHADDR[29]} {wallypipelinedsoc/core/lsu/LSUHADDR[30]} {wallypipelinedsoc/core/lsu/LSUHADDR[31]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe5] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] +connect_debug_port u_ila_0/probe5 [get_nets [list wallypipelinedsoc/core/lsu/LSUHREADY ]] + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe6] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] +connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe7] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] +connect_debug_port u_ila_0/probe7 [get_nets [list {SDCIntr}]] diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index d58199e19..0380dcb12 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -68,7 +68,7 @@ report_clock_interaction -file re write_verilog -force -mode funcsim sim/syn-funcsim.v -source ../constraints/debug2.xdc +source ../constraints/vcu-small-debug.xdc # set for RuntimeOptimized implementation diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index 3c5b21cb2..b939c6121 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -416,7 +416,7 @@ module fpgaTop wire sd_cmd_reg_t; // SD Card Interrupt signal - wire SDCintr; + (* mark_debug = "true" *) wire SDCIntr; // New SDC Data IOBUF connections wire [3:0] sd_dat_i; diff --git a/linux/buildroot-packages/fpga-axi-sdc/Config.in b/linux/buildroot-packages/fpga-axi-sdc/Config.in new file mode 100644 index 000000000..8cd3c0087 --- /dev/null +++ b/linux/buildroot-packages/fpga-axi-sdc/Config.in @@ -0,0 +1,6 @@ +config BR2_PACKAGE_FPGA_AXI_SDC + bool "FPGA AXI SDC" + help + The Vivado-RISC-V SDC Drivers. + + https://www.github.com/eugene-tarassov/vivado-risc-v \ No newline at end of file diff --git a/linux/buildroot-packages/fpga-axi-sdc/fpga-axi-sdc.mk b/linux/buildroot-packages/fpga-axi-sdc/fpga-axi-sdc.mk new file mode 100644 index 000000000..3ee762493 --- /dev/null +++ b/linux/buildroot-packages/fpga-axi-sdc/fpga-axi-sdc.mk @@ -0,0 +1,10 @@ +FPGA_AXI_SDC_MODULE_VERSION = 1.0 +# TODO This variable needs to change based on where the package +# contents are stored on each individual computer. Might parameterize +# this somehow. +FPGA_AXI_SDC_SITE = /home/jpease/repos/fpga-axi-sdc +FPGA_AXI_SDC_SITE_METHOD = local +FPGA_AXI_SDC_LICENSE = GPLv2 + +$(eval $(kernel-module)) +$(eval $(generic-package)) diff --git a/linux/buildroot-packages/fpga-axi-sdc/fpga-axi-sdc.mk~ b/linux/buildroot-packages/fpga-axi-sdc/fpga-axi-sdc.mk~ new file mode 100644 index 000000000..92308225d --- /dev/null +++ b/linux/buildroot-packages/fpga-axi-sdc/fpga-axi-sdc.mk~ @@ -0,0 +1,7 @@ +FPGA_AXI_SDC_MODULE_VERSION = 1.0 +FPGA_AXI_SDC_SITE = /home/jpease/repos/fpga-axi-sdc +FPGA_AXI_SDC_SITE_METHOD = local +FPGA_AXI_SDC_LICENSE = GPLv2 + +$(eval $(kernel-module)) +$(eval $(generic-package)) diff --git a/linux/buildroot-packages/linux.config b/linux/buildroot-packages/linux.config new file mode 100644 index 000000000..ad2ba8669 --- /dev/null +++ b/linux/buildroot-packages/linux.config @@ -0,0 +1,1423 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/riscv 5.10.7 Kernel Configuration +# +CONFIG_CC_VERSION_TEXT="riscv64-buildroot-linux-gnu-gcc.br_real (Buildroot 2021.05-dirty) 10.3.0" +CONFIG_CC_IS_GCC=y +CONFIG_GCC_VERSION=100300 +CONFIG_LD_VERSION=235020000 +CONFIG_CLANG_VERSION=0 +CONFIG_LLD_VERSION=0 +CONFIG_CC_CAN_LINK=y +CONFIG_CC_CAN_LINK_STATIC=y +CONFIG_CC_HAS_ASM_GOTO=y +CONFIG_CC_HAS_ASM_INLINE=y +CONFIG_IRQ_WORK=y +CONFIG_THREAD_INFO_IN_TASK=y + +# +# General setup +# +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +# CONFIG_COMPILE_TEST is not set +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_BUILD_SALT="" +CONFIG_DEFAULT_INIT="" +CONFIG_DEFAULT_HOSTNAME="WallyDefaultHostname" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_WATCH_QUEUE is not set +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_USELIB is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_SPARSE_IRQ=y +# CONFIG_GENERIC_IRQ_DEBUGFS is not set +# end of IRQ subsystem + +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_ARCH_CLOCKSOURCE_INIT=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_HZ_PERIODIC is not set +CONFIG_NO_HZ_IDLE=y +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +# end of Timers subsystem + +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_PREEMPT_COUNT=y + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_PSI is not set +# end of CPU/Task time and stats accounting + +# +# RCU Subsystem +# +CONFIG_TINY_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_SRCU=y +CONFIG_TINY_SRCU=y +# end of RCU Subsystem + +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +# CONFIG_IKHEADERS is not set +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 +CONFIG_GENERIC_SCHED_CLOCK=y + +# +# Scheduler features +# +# end of Scheduler features + +CONFIG_CC_HAS_INT128=y +CONFIG_ARCH_SUPPORTS_INT128=y +# CONFIG_CGROUPS is not set +# CONFIG_NAMESPACES is not set +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="${BR_BINARIES_DIR}/rootfs.cpio" +CONFIG_INITRAMFS_ROOT_UID=0 +CONFIG_INITRAMFS_ROOT_GID=0 +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +# CONFIG_RD_ZSTD is not set +CONFIG_INITRAMFS_COMPRESSION_GZIP=y +# CONFIG_INITRAMFS_COMPRESSION_NONE is not set +# CONFIG_BOOT_CONFIG is not set +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_EXPERT=y +CONFIG_MULTIUSER=y +# CONFIG_SGETMASK_SYSCALL is not set +# CONFIG_SYSFS_SYSCALL is not set +CONFIG_FHANDLE=y +CONFIG_POSIX_TIMERS=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_FUTEX_PI=y +CONFIG_HAVE_FUTEX_CMPXCHG=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_IO_URING=y +CONFIG_ADVISE_SYSCALLS=y +CONFIG_MEMBARRIER=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_KALLSYMS_BASE_RELATIVE=y +# CONFIG_BPF_SYSCALL is not set +# CONFIG_USERFAULTFD is not set +# CONFIG_EMBEDDED is not set +CONFIG_HAVE_PERF_EVENTS=y +# CONFIG_PC104 is not set + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# end of Kernel Performance Events And Counters + +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_SLAB_MERGE_DEFAULT=y +# CONFIG_SLAB_FREELIST_RANDOM is not set +# CONFIG_SLAB_FREELIST_HARDENED is not set +# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set +# CONFIG_PROFILING is not set +# end of General setup + +CONFIG_64BIT=y +CONFIG_RISCV=y +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_RISCV_SBI=y +CONFIG_MMU=y +CONFIG_ZONE_DMA32=y +CONFIG_VA_BITS=39 +CONFIG_PA_BITS=56 +CONFIG_PAGE_OFFSET=0xffffffff80000000 +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_SYS_SUPPORTS_HUGETLBFS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_PGTABLE_LEVELS=3 +CONFIG_LOCKDEP_SUPPORT=y + +# +# SoC selection +# +# CONFIG_SOC_SIFIVE is not set +# CONFIG_SOC_VIRT is not set +# end of SoC selection + +# +# Platform type +# +# CONFIG_ARCH_RV32I is not set +CONFIG_ARCH_RV64I=y +# CONFIG_CMODEL_MEDLOW is not set +CONFIG_CMODEL_MEDANY=y +CONFIG_MODULE_SECTIONS=y +CONFIG_MAXPHYSMEM_2GB=y +# CONFIG_MAXPHYSMEM_128GB is not set +# CONFIG_SMP is not set +CONFIG_TUNE_GENERIC=y +CONFIG_RISCV_ISA_C=y +CONFIG_FPU=y +# end of Platform type + +# +# Kernel features +# +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 +# CONFIG_RISCV_SBI_V01 is not set +# end of Kernel features + +# +# Boot options +# +CONFIG_CMDLINE="" +# CONFIG_EFI is not set +# end of Boot options + +# +# Power management options +# +# CONFIG_PM is not set +# end of Power management options + +# +# Firmware Drivers +# +# CONFIG_FIRMWARE_MEMMAP is not set +# CONFIG_GOOGLE_FIRMWARE is not set + +# +# Tegra firmware driver +# +# end of Tegra firmware driver +# end of Firmware Drivers + +# +# General architecture-dependent options +# +CONFIG_JUMP_LABEL=y +# CONFIG_STATIC_KEYS_SELFTEST is not set +CONFIG_HAVE_64BIT_ALIGNED_ACCESS=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_SET_DIRECT_MAP=y +CONFIG_HAVE_ASM_MODVERSIONS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y +CONFIG_HAVE_ARCH_SECCOMP=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_SECCOMP=y +CONFIG_HAVE_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y +CONFIG_CLONE_BACKWARDS=y +# CONFIG_COMPAT_32BIT_TIME is not set +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_STRICT_KERNEL_RWX=y +# CONFIG_LOCK_EVENT_COUNTS is not set + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +# end of GCOV-based kernel profiling + +CONFIG_HAVE_GCC_PLUGINS=y +# end of General architecture-dependent options + +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +# CONFIG_MODULE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +# CONFIG_MODULE_COMPRESS is not set +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_BLOCK=y +CONFIG_BLK_SCSI_REQUEST=y +CONFIG_BLK_DEV_BSG=y +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_DEV_ZONED is not set +# CONFIG_BLK_CMDLINE_PARSER is not set +# CONFIG_BLK_WBT is not set +CONFIG_BLK_DEBUG_FS=y +# CONFIG_BLK_SED_OPAL is not set +# CONFIG_BLK_INLINE_ENCRYPTION is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_EFI_PARTITION=y +# end of Partition Types + +CONFIG_BLK_MQ_VIRTIO=y + +# +# IO Schedulers +# +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MQ_IOSCHED_KYBER=y +# CONFIG_IOSCHED_BFQ is not set +# end of IO Schedulers + +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_HAS_MMIOWB=y + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ELFCORE=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_BINFMT_SCRIPT=y +CONFIG_ARCH_HAS_BINFMT_FLAT=y +# CONFIG_BINFMT_FLAT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_COREDUMP=y +# end of Executable file formats + +# +# Memory Management options +# +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_PAGE_REPORTING=y +CONFIG_MIGRATION=y +CONFIG_PHYS_ADDR_T_64BIT=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_NEED_PER_CPU_KM=y +# CONFIG_CLEANCACHE is not set +# CONFIG_FRONTSWAP is not set +# CONFIG_CMA is not set +# CONFIG_ZPOOL is not set +# CONFIG_ZBUD is not set +# CONFIG_ZSMALLOC is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_IDLE_PAGE_TRACKING is not set +# CONFIG_PERCPU_STATS is not set +# CONFIG_GUP_BENCHMARK is not set +CONFIG_ARCH_HAS_PTE_SPECIAL=y +# end of Memory Management options + +# CONFIG_NET is not set +CONFIG_HAVE_EBPF_JIT=y + +# +# Device Drivers +# +CONFIG_HAVE_PCI=y +# CONFIG_PCI is not set +# CONFIG_PCCARD is not set + +# +# Generic Driver Options +# +# CONFIG_UEVENT_HELPER is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y + +# +# Firmware loader +# +CONFIG_FW_LOADER=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_FW_LOADER_USER_HELPER is not set +# CONFIG_FW_LOADER_COMPRESS is not set +# end of Firmware loader + +CONFIG_ALLOW_DEV_COREDUMP=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set +# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y +# end of Generic Driver Options + +# +# Bus devices +# +# CONFIG_MHI_BUS is not set +# end of Bus devices + +# CONFIG_GNSS is not set +# CONFIG_MTD is not set +CONFIG_DTC=y +CONFIG_OF=y +# CONFIG_OF_UNITTEST is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_KOBJ=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_RESERVED_MEM=y +# CONFIG_OF_OVERLAY is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_NULL_BLK is not set +# CONFIG_BLK_DEV_LOOP is not set + +# +# DRBD disabled because PROC_FS or INET not selected +# +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_VIRTIO_BLK is not set + +# +# NVME Support +# +# CONFIG_NVME_FC is not set +# end of NVME Support + +# +# Misc devices +# +# CONFIG_DUMMY_IRQ is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_SRAM is not set +# CONFIG_XILINX_SDFEC is not set +# CONFIG_PVPANIC is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_93CX6 is not set +# end of EEPROM support + +# +# Texas Instruments shared transport line discipline +# +# end of Texas Instruments shared transport line discipline + +# +# Altera FPGA firmware download module (requires I2C) +# +# CONFIG_ECHO is not set +# end of Misc devices + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# end of SCSI device support + +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_TARGET_CORE is not set +# CONFIG_NVM is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_MATRIXKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set +# CONFIG_RMI4_CORE is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set +# end of Hardware I/O ports +# end of Input device support + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +CONFIG_LDISC_AUTOLOAD=y + +# +# Serial drivers +# +CONFIG_SERIAL_EARLYCON=y +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +CONFIG_SERIAL_8250_16550A_VARIANTS=y +# CONFIG_SERIAL_8250_FINTEK is not set +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=1 +CONFIG_SERIAL_8250_RUNTIME_UARTS=1 +# CONFIG_SERIAL_8250_EXTENDED is not set +# CONFIG_SERIAL_8250_DW is not set +# CONFIG_SERIAL_8250_RT288X is not set +CONFIG_SERIAL_OF_PLATFORM=y + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_SERIAL_SIFIVE=y +CONFIG_SERIAL_SIFIVE_CONSOLE=y +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_FSL_LINFLEXUART is not set +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +# CONFIG_SERIAL_SPRD is not set +# end of Serial drivers + +CONFIG_SERIAL_MCTRL_GPIO=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NULL_TTY is not set +# CONFIG_TRACE_SINK is not set +CONFIG_HVC_DRIVER=y +# CONFIG_SERIAL_DEV_BUS is not set +# CONFIG_TTY_PRINTK is not set +CONFIG_VIRTIO_CONSOLE=y +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_HW_RANDOM_BA431 is not set +CONFIG_HW_RANDOM_VIRTIO=y +# CONFIG_HW_RANDOM_CCTRNG is not set +# CONFIG_HW_RANDOM_XIPHERA is not set +CONFIG_DEVMEM=y +# CONFIG_DEVKMEM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_XILLYBUS is not set +# end of Character devices + +# CONFIG_RANDOM_TRUST_BOOTLOADER is not set + +# +# I2C support +# +# CONFIG_I2C is not set +# end of I2C support + +# CONFIG_I3C is not set +# CONFIG_SPI is not set +# CONFIG_SPMI is not set +# CONFIG_HSI is not set +# CONFIG_PPS is not set + +# +# PTP clock support +# + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +# end of PTP clock support + +# CONFIG_PINCTRL is not set +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_FASTPATH_LIMIT=32 +CONFIG_OF_GPIO=y +CONFIG_GPIOLIB_IRQCHIP=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_GPIO_SYSFS is not set +CONFIG_GPIO_CDEV=y +# CONFIG_GPIO_CDEV_V1 is not set +CONFIG_GPIO_GENERIC=y + +# +# Memory mapped GPIO drivers +# +# CONFIG_GPIO_74XX_MMIO is not set +# CONFIG_GPIO_ALTERA is not set +# CONFIG_GPIO_CADENCE is not set +# CONFIG_GPIO_DWAPB is not set +# CONFIG_GPIO_FTGPIO010 is not set +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_HLWD is not set +# CONFIG_GPIO_MB86S7X is not set +CONFIG_GPIO_SIFIVE=y +# CONFIG_GPIO_XILINX is not set +# CONFIG_GPIO_AMD_FCH is not set +# end of Memory mapped GPIO drivers + +# +# MFD GPIO expanders +# +# end of MFD GPIO expanders + +# CONFIG_GPIO_AGGREGATOR is not set +# CONFIG_GPIO_MOCKUP is not set +# CONFIG_W1 is not set +# CONFIG_POWER_RESET is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_ATMEL_FLEXCOM is not set +# CONFIG_MFD_ATMEL_HLCDC is not set +# CONFIG_MFD_MADERA is not set +# CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_SYSCON is not set +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_TQMX86 is not set +# end of Multifunction device drivers + +# CONFIG_REGULATOR is not set +# CONFIG_RC_CORE is not set +# CONFIG_MEDIA_CEC_SUPPORT is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_DRM is not set + +# +# ARM devices +# +# end of ARM devices + +# +# Frame buffer Devices +# +# CONFIG_FB is not set +# end of Frame buffer Devices + +# +# Backlight & LCD device support +# +# CONFIG_LCD_CLASS_DEVICE is not set +# CONFIG_BACKLIGHT_CLASS_DEVICE is not set +# end of Backlight & LCD device support + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_DUMMY_CONSOLE_COLUMNS=80 +CONFIG_DUMMY_CONSOLE_ROWS=25 +# end of Console display driver support +# end of Graphics support + +# CONFIG_SOUND is not set + +# +# HID support +# +# CONFIG_HID is not set +# end of HID support + +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_SUPPORT is not set +CONFIG_MMC=y +CONFIG_PWRSEQ_EMMC=y +CONFIG_PWRSEQ_SIMPLE=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_DW is not set +# CONFIG_MMC_USDHI6ROL0 is not set +# CONFIG_MMC_CQHCI is not set +# CONFIG_MMC_HSQ is not set +# CONFIG_MMC_MTK is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_EDAC_SUPPORT=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set + +# +# DMABUF options +# +# CONFIG_SYNC_FILE is not set +# CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_HEAPS is not set +# end of DMABUF options + +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_VIRT_DRIVERS is not set +CONFIG_VIRTIO=y +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VDPA is not set +# CONFIG_VHOST_MENU is not set + +# +# Microsoft Hyper-V guest support +# +# end of Microsoft Hyper-V guest support + +# CONFIG_GREYBUS is not set +# CONFIG_STAGING is not set +# CONFIG_GOLDFISH is not set +CONFIG_HAVE_CLK=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y +# CONFIG_COMMON_CLK_FIXED_MMIO is not set +# CONFIG_CLK_SIFIVE is not set +# CONFIG_HWSPINLOCK is not set + +# +# Clock Source drivers +# +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_RISCV_TIMER=y +# CONFIG_MICROCHIP_PIT64B is not set +# end of Clock Source drivers + +# CONFIG_MAILBOX is not set +# CONFIG_IOMMU_SUPPORT is not set + +# +# Remoteproc drivers +# +# CONFIG_REMOTEPROC is not set +# end of Remoteproc drivers + +# +# Rpmsg drivers +# +# CONFIG_RPMSG_VIRTIO is not set +# end of Rpmsg drivers + +# CONFIG_SOUNDWIRE is not set + +# +# SOC (System On Chip) specific Drivers +# + +# +# Amlogic SoC drivers +# +# end of Amlogic SoC drivers + +# +# Aspeed SoC drivers +# +# end of Aspeed SoC drivers + +# +# Broadcom SoC drivers +# +# end of Broadcom SoC drivers + +# +# NXP/Freescale QorIQ SoC drivers +# +# end of NXP/Freescale QorIQ SoC drivers + +# +# i.MX SoC drivers +# +# end of i.MX SoC drivers + +# +# Qualcomm SoC drivers +# +# end of Qualcomm SoC drivers + +# CONFIG_SOC_TI is not set + +# +# Xilinx SoC drivers +# +# CONFIG_XILINX_VCU is not set +# end of Xilinx SoC drivers +# end of SOC (System On Chip) specific Drivers + +# CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +# CONFIG_MEMORY is not set +# CONFIG_IIO is not set +# CONFIG_PWM is not set + +# +# IRQ chip support +# +CONFIG_IRQCHIP=y +# CONFIG_AL_FIC is not set +CONFIG_RISCV_INTC=y +CONFIG_SIFIVE_PLIC=y +# end of IRQ chip support + +# CONFIG_IPACK_BUS is not set +# CONFIG_RESET_CONTROLLER is not set + +# +# PHY Subsystem +# +# CONFIG_GENERIC_PHY is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_PHY_CADENCE_TORRENT is not set +# CONFIG_PHY_CADENCE_DPHY is not set +# CONFIG_PHY_CADENCE_SALVO is not set +# CONFIG_PHY_FSL_IMX8MQ_USB is not set +# CONFIG_PHY_MIXEL_MIPI_DPHY is not set +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# end of PHY Subsystem + +# CONFIG_POWERCAP is not set +# CONFIG_MCB is not set +# CONFIG_RAS is not set + +# +# Android +# +# CONFIG_ANDROID is not set +# end of Android + +# CONFIG_LIBNVDIMM is not set +# CONFIG_DAX is not set +# CONFIG_NVMEM is not set + +# +# HW tracing support +# +# CONFIG_STM is not set +# CONFIG_INTEL_TH is not set +# end of HW tracing support + +# CONFIG_FPGA is not set +# CONFIG_FSI is not set +# CONFIG_SIOX is not set +# CONFIG_SLIMBUS is not set +# CONFIG_INTERCONNECT is not set +# CONFIG_COUNTER is not set +# end of Device Drivers + +# +# File systems +# +# CONFIG_VALIDATE_FS_PARSER is not set +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_F2FS_FS is not set +# CONFIG_FS_DAX is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +# CONFIG_EXPORTFS_BLOCK_OPS is not set +CONFIG_FILE_LOCKING=y +CONFIG_MANDATORY_FILE_LOCKING=y +# CONFIG_FS_ENCRYPTION is not set +# CONFIG_FS_VERITY is not set +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS4_FS is not set +CONFIG_AUTOFS_FS=y +# CONFIG_FUSE_FS is not set +# CONFIG_OVERLAY_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set +# end of Caches + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set +# end of CD-ROM/DVD Filesystems + +# +# DOS/FAT/EXFAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_EXFAT_FS is not set +# CONFIG_NTFS_FS is not set +# end of DOS/FAT/EXFAT/NT Filesystems + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_PROC_CHILDREN=y +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +# CONFIG_TMPFS_INODE64 is not set +# CONFIG_HUGETLBFS is not set +CONFIG_MEMFD_CREATE=y +CONFIG_ARCH_HAS_GIGANTIC_PAGE=y +# CONFIG_CONFIGFS_FS is not set +# end of Pseudo filesystems + +# CONFIG_MISC_FILESYSTEMS is not set +# CONFIG_NLS is not set +# CONFIG_UNICODE is not set +CONFIG_IO_WQ=y +# end of File systems + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +# CONFIG_HARDENED_USERCOPY is not set +# CONFIG_STATIC_USERMODEHELPER is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity,bpf" + +# +# Kernel hardening options +# + +# +# Memory initialization +# +CONFIG_INIT_STACK_NONE=y +# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set +# end of Memory initialization +# end of Kernel hardening options +# end of Security options + +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Public-key cryptography +# +# CONFIG_CRYPTO_RSA is not set +# CONFIG_CRYPTO_DH is not set +# CONFIG_CRYPTO_ECDH is not set +# CONFIG_CRYPTO_ECRDSA is not set +# CONFIG_CRYPTO_SM2 is not set +# CONFIG_CRYPTO_CURVE25519 is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set +# CONFIG_CRYPTO_AEGIS128 is not set +# CONFIG_CRYPTO_SEQIV is not set +# CONFIG_CRYPTO_ECHAINIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CFB is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_OFB is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_KEYWRAP is not set +# CONFIG_CRYPTO_ADIANTUM is not set +# CONFIG_CRYPTO_ESSIV is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_CMAC is not set +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_XXHASH is not set +# CONFIG_CRYPTO_BLAKE2B is not set +# CONFIG_CRYPTO_BLAKE2S is not set +# CONFIG_CRYPTO_CRCT10DIF is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_POLY1305 is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_SHA3 is not set +# CONFIG_CRYPTO_SM3 is not set +# CONFIG_CRYPTO_STREEBOG is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_AES_TI is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_CHACHA20 is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_SM4 is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set +# CONFIG_CRYPTO_842 is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set +# CONFIG_CRYPTO_ZSTD is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_DRBG_MENU is not set +# CONFIG_CRYPTO_JITTERENTROPY is not set + +# +# Crypto library routines +# +# CONFIG_CRYPTO_LIB_BLAKE2S is not set +# CONFIG_CRYPTO_LIB_CHACHA is not set +# CONFIG_CRYPTO_LIB_CURVE25519 is not set +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1 +# CONFIG_CRYPTO_LIB_POLY1305 is not set +# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set +# CONFIG_CRYPTO_HW is not set + +# +# Certificates for signature checking +# +# end of Certificates for signature checking + +# +# Library routines +# +# CONFIG_PACKING is not set +CONFIG_BITREVERSE=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +# CONFIG_CORDIC is not set +# CONFIG_PRIME_NUMBERS is not set +CONFIG_RATIONAL=y +CONFIG_GENERIC_PCI_IOMAP=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC64 is not set +# CONFIG_CRC4 is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +# CONFIG_CRC8 is not set +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_ZLIB_INFLATE=y +# CONFIG_XZ_DEC is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_DMA_DECLARE_COHERENT=y +CONFIG_SWIOTLB=y +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_IRQ_POLL is not set +CONFIG_LIBFDT=y +CONFIG_HAVE_GENERIC_VDSO=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_SBITMAP=y +# CONFIG_STRING_SELFTEST is not set +# end of Library routines + +CONFIG_GENERIC_IOREMAP=y + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +# CONFIG_PRINTK_CALLER is not set +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 +CONFIG_CONSOLE_LOGLEVEL_QUIET=4 +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DYNAMIC_DEBUG_CORE is not set +CONFIG_SYMBOLIC_ERRNAME=y +CONFIG_DEBUG_BUGVERBOSE=y +# end of printk and dmesg options + +# +# Compile-time checks and compiler options +# +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_DEBUG_INFO_COMPRESSED is not set +# CONFIG_DEBUG_INFO_SPLIT is not set +# CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_DEBUG_INFO_BTF is not set +CONFIG_GDB_SCRIPTS=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=2048 +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_READABLE_ASM=y +# CONFIG_HEADERS_INSTALL is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set +CONFIG_ARCH_WANT_FRAME_POINTERS=y +CONFIG_FRAME_POINTER=y +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# end of Compile-time checks and compiler options + +# +# Generic Kernel Debugging Instruments +# +# CONFIG_MAGIC_SYSRQ is not set +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_FS_ALLOW_ALL=y +# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set +# CONFIG_DEBUG_FS_ALLOW_NONE is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_KGDB_QXFER_PKT=y +# CONFIG_KGDB is not set +# CONFIG_UBSAN is not set +# end of Generic Kernel Debugging Instruments + +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_MISC=y + +# +# Memory Debugging +# +# CONFIG_PAGE_EXTENSION is not set +CONFIG_DEBUG_PAGEALLOC=y +# CONFIG_DEBUG_PAGEALLOC_ENABLE_DEFAULT is not set +# CONFIG_PAGE_OWNER is not set +# CONFIG_PAGE_POISONING is not set +# CONFIG_DEBUG_RODATA_TEST is not set +CONFIG_ARCH_HAS_DEBUG_WX=y +# CONFIG_DEBUG_WX is not set +CONFIG_GENERIC_PTDUMP=y +# CONFIG_PTDUMP_DEBUGFS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_STATS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_STACK_USAGE is not set +CONFIG_SCHED_STACK_END_CHECK=y +CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y +CONFIG_DEBUG_VM=y +# CONFIG_DEBUG_VM_VMACACHE is not set +# CONFIG_DEBUG_VM_RB is not set +CONFIG_DEBUG_VM_PGFLAGS=y +CONFIG_DEBUG_VM_PGTABLE=y +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +# CONFIG_DEBUG_VIRTUAL is not set +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_HAVE_ARCH_KASAN=y +CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y +# end of Memory Debugging + +# CONFIG_DEBUG_SHIRQ is not set + +# +# Debug Oops, Lockups and Hangs +# +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +CONFIG_LOCKUP_DETECTOR=y +CONFIG_SOFTLOCKUP_DETECTOR=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_WQ_WATCHDOG=y +# CONFIG_TEST_LOCKUP is not set +# end of Debug Oops, Lockups and Hangs + +# +# Scheduler Debugging +# +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# end of Scheduler Debugging + +CONFIG_DEBUG_TIMEKEEPING=y + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +CONFIG_LOCK_DEBUGGING_SUPPORT=y +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +CONFIG_DEBUG_RWSEMS=y +# CONFIG_DEBUG_LOCK_ALLOC is not set +CONFIG_DEBUG_ATOMIC_SLEEP=y +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_LOCK_TORTURE_TEST is not set +# CONFIG_WW_MUTEX_SELFTEST is not set +# CONFIG_SCF_TORTURE_TEST is not set +# CONFIG_CSD_LOCK_WAIT_DEBUG is not set +# end of Lock Debugging (spinlocks, mutexes, etc...) + +CONFIG_STACKTRACE=y +# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set +# CONFIG_DEBUG_KOBJECT is not set + +# +# Debug kernel data structures +# +CONFIG_DEBUG_LIST=y +CONFIG_DEBUG_PLIST=y +CONFIG_DEBUG_SG=y +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +# end of Debug kernel data structures + +# CONFIG_DEBUG_CREDENTIALS is not set + +# +# RCU Debugging +# +# CONFIG_RCU_SCALE_TEST is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_REF_SCALE_TEST is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_EQS_DEBUG=y +# end of RCU Debugging + +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_LATENCYTOP is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_SAMPLES is not set + +# +# riscv Debugging +# + +# +# Kernel Testing and Coverage +# +# CONFIG_KUNIT is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +# CONFIG_FAULT_INJECTION is not set +CONFIG_ARCH_HAS_KCOV=y +CONFIG_CC_HAS_SANCOV_TRACE_PC=y +# CONFIG_KCOV is not set +# CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_MEMTEST=y +# end of Kernel Testing and Coverage +# end of Kernel hacking diff --git a/linux/buildroot-packages/package-source/Makefile b/linux/buildroot-packages/package-source/Makefile new file mode 100644 index 000000000..4981239eb --- /dev/null +++ b/linux/buildroot-packages/package-source/Makefile @@ -0,0 +1,9 @@ +.PHONY: all clean +obj-m += fpga-axi-sdc.o + +all: + $(MAKE) -C '$(LINUX-DIR)' M='$(PWD)' modules + $(MAKE) -C '$(LINUX-DIR)' M='$(PWD)' modules_install + +clean: + $(MAKE) -C '$(LINUX-DIR)' M='$(PWD)' clean diff --git a/linux/buildroot-packages/package-source/fpga-axi-sdc.c b/linux/buildroot-packages/package-source/fpga-axi-sdc.c new file mode 100644 index 000000000..ebe916a4c --- /dev/null +++ b/linux/buildroot-packages/package-source/fpga-axi-sdc.c @@ -0,0 +1,498 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * AXI SD Card driver. + * + * AXI SD Card is open source Verilog implementation of high speed SD card controller. + * It is mainly used in FPGA designs. + */ + +#ifdef CONFIG_DEBUG_INFO +#pragma GCC optimize("O0") +#endif + +// Capability bits +#define SDC_CAPABILITY_SD_4BIT 0x0001 +#define SDC_CAPABILITY_SD_RESET 0x0002 +#define SDC_CAPABILITY_ADDR 0xff00 + +// Control bits +#define SDC_CONTROL_SD_4BIT 0x0001 +#define SDC_CONTROL_SD_RESET 0x0002 + +// Card detect bits +#define SDC_CARD_INSERT_INT_EN 0x0001 +#define SDC_CARD_INSERT_INT_REQ 0x0002 +#define SDC_CARD_REMOVE_INT_EN 0x0004 +#define SDC_CARD_REMOVE_INT_REQ 0x0008 + +// Command status bits +#define SDC_CMD_INT_STATUS_CC 0x0001 // Command complete +#define SDC_CMD_INT_STATUS_EI 0x0002 // Any error +#define SDC_CMD_INT_STATUS_CTE 0x0004 // Timeout +#define SDC_CMD_INT_STATUS_CCRC 0x0008 // CRC error +#define SDC_CMD_INT_STATUS_CIE 0x0010 // Command code check error + +// Data status bits +#define SDC_DAT_INT_STATUS_TRS 0x0001 // Transfer complete +#define SDC_DAT_INT_STATUS_ERR 0x0002 // Any error +#define SDC_DAT_INT_STATUS_CTE 0x0004 // Timeout +#define SDC_DAT_INT_STATUS_CRC 0x0008 // CRC error +#define SDC_DAT_INT_STATUS_CFE 0x0010 // Data FIFO underrun or overrun + +#define CMD_TIMEOUT_MS 1000 +#define BUSY_TIMEOUT_MS 500 + +struct sdc_regs { + volatile uint32_t argument; + volatile uint32_t command; + volatile uint32_t response1; + volatile uint32_t response2; + volatile uint32_t response3; + volatile uint32_t response4; + volatile uint32_t data_timeout; + volatile uint32_t control; + volatile uint32_t cmd_timeout; + volatile uint32_t clock_divider; + volatile uint32_t software_reset; + volatile uint32_t power_control; + volatile uint32_t capability; + volatile uint32_t cmd_int_status; + volatile uint32_t cmd_int_enable; + volatile uint32_t dat_int_status; + volatile uint32_t dat_int_enable; + volatile uint32_t block_size; + volatile uint32_t block_count; + volatile uint32_t card_detect; + volatile uint32_t res_50; + volatile uint32_t res_54; + volatile uint32_t res_58; + volatile uint32_t res_5c; + volatile uint64_t dma_addres; +}; + +struct sdc_host { + struct platform_device * pdev; + struct sdc_regs __iomem * regs; + uint32_t clk_freq; + spinlock_t lock; + struct mmc_request * mrq; + struct mmc_data * data; + unsigned dma_addr_bits; + unsigned dma_count; + dma_addr_t dma_addr; + unsigned dma_size; + int irq; +}; + +static const struct of_device_id axi_sdc_of_match_table[] = { + { .compatible = "riscv,axi-sd-card-1.0" }, + {}, +}; +MODULE_DEVICE_TABLE(of, axi_sdc_of_match_table); + +/* Set clock prescalar value based on the required clock in HZ */ +static void sdc_set_clock(struct sdc_host * host, uint clock) { + unsigned clk_div; + + /* Min clock frequency should be 400KHz */ + if (clock < 400000) clock = 400000; + + clk_div = host->clk_freq / (2 * clock); + if (clk_div > 0x100) clk_div = 0x100; + if (clk_div < 1) clk_div = 1; + + if (host->regs->clock_divider != clk_div - 1) { + host->regs->clock_divider = clk_div - 1; + udelay(10000); + } +} + +static void sdc_cmd_finish(struct sdc_host * host, struct mmc_command * cmd) { + while (1) { + unsigned status = host->regs->cmd_int_status; + if (status) { + // clear interrupts + host->regs->cmd_int_status = 0; + while (host->regs->software_reset != 0) {} + if (status == SDC_CMD_INT_STATUS_CC) { + // get response + cmd->resp[0] = host->regs->response1; + if (cmd->flags & MMC_RSP_136) { + cmd->resp[1] = host->regs->response2; + cmd->resp[2] = host->regs->response3; + cmd->resp[3] = host->regs->response4; + } + break; + } + cmd->error = (status & SDC_CMD_INT_STATUS_CTE) ? -ETIME : -EIO; + break; + } + } +} + +static int sdc_setup_data_xfer(struct sdc_host * host, struct mmc_host * mmc, struct mmc_data * data) { + uint64_t timeout = 0; + + data->bytes_xfered = 0; + + if (host->dma_addr & 3) return -EINVAL; + if (data->blksz & 3) return -EINVAL; + if (data->blksz < 4) return -EINVAL; + if (data->blksz > 0x1000) return -EINVAL; + if (data->blocks > 0x10000) return -EINVAL; + if (host->dma_addr + data->blksz * data->blocks > ((uint64_t)1 << host->dma_addr_bits)) return -EINVAL; + if (data->sg->length < data->blksz * data->blocks) return -EINVAL; + + // SD card data transfer time + timeout += data->blocks * data->blksz * 8 / (1 << mmc->ios.bus_width); + // SD card "busy" time + timeout += (uint64_t)mmc->ios.clock * BUSY_TIMEOUT_MS / 1000 * data->blocks; + + host->regs->dma_addres = (uint64_t)host->dma_addr; + host->regs->block_size = data->blksz - 1; + host->regs->block_count = data->blocks - 1; + host->regs->data_timeout = (uint32_t)timeout; + if (host->regs->data_timeout != timeout) host->regs->data_timeout = 0; + + return 0; +} + +static int sdc_send_cmd(struct sdc_host * host, struct mmc_host * mmc, struct mmc_command * cmd, struct mmc_data * data) { + int command = cmd->opcode << 8; + uint64_t timeout = 0; + int xfer = 0; + + if (cmd->flags & MMC_RSP_PRESENT) { + if (cmd->flags & MMC_RSP_136) + command |= 2; + else { + command |= 1; + } + } + if (cmd->flags & MMC_RSP_BUSY) command |= 1 << 2; + if (cmd->flags & MMC_RSP_CRC) command |= 1 << 3; + if (cmd->flags & MMC_RSP_OPCODE) command |= 1 << 4; + + if (data && (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE)) && data->blocks) { + host->dma_count = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, mmc_get_dma_dir(data)); + if (host->dma_count != 1) { + dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len, mmc_get_dma_dir(data)); + return data->error = -EIO; + } + host->dma_addr = sg_dma_address(data->sg); + host->dma_size = sg_dma_len(data->sg); + if (data->flags & MMC_DATA_READ) command |= 1 << 5; + if (data->flags & MMC_DATA_WRITE) command |= 1 << 6; + data->error = sdc_setup_data_xfer(host, mmc, data); + if (data->error < 0) { + dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len, mmc_get_dma_dir(data)); + return data->error; + } + xfer = 1; + } + + timeout = (uint64_t)mmc->ios.clock * CMD_TIMEOUT_MS / 1000; + + host->regs->command = command; + host->regs->cmd_timeout = (uint32_t)timeout; + if (host->regs->cmd_timeout != timeout) host->regs->cmd_timeout = 0; + host->regs->argument = cmd->arg; + + sdc_cmd_finish(host, cmd); + if (cmd->error < 0) { + if (xfer) dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len, mmc_get_dma_dir(data)); + return cmd->error; + } + if (xfer) host->data = data; + + return 0; +} + +static void sdc_request(struct mmc_host * mmc, struct mmc_request * mrq) { + struct sdc_host * host = mmc_priv(mmc); + + /* Clear the error statuses in case this is a retry */ + if (mrq->sbc) mrq->sbc->error = 0; + if (mrq->cmd) mrq->cmd->error = 0; + if (mrq->data) mrq->data->error = 0; + if (mrq->stop) mrq->stop->error = 0; + + spin_lock_irq(&host->lock); + host->data = NULL; + host->mrq = mrq; + + if (!mrq->sbc || sdc_send_cmd(host, mmc, mrq->sbc, NULL) == 0) { + sdc_send_cmd(host, mmc, mrq->cmd, mrq->data); + } + + if (host->data == NULL) { + mmc_request_done(mmc, mrq); + host->mrq = NULL; + } + else { + host->regs->dat_int_enable = SDC_DAT_INT_STATUS_TRS | SDC_DAT_INT_STATUS_ERR; + } + + spin_unlock_irq(&host->lock); +} + +static void sdc_set_ios(struct mmc_host * mmc, struct mmc_ios * ios) { + struct sdc_host * host = mmc_priv(mmc); + + spin_lock_irq(&host->lock); + + sdc_set_clock(host, ios->clock); + host->regs->control = ios->bus_width == MMC_BUS_WIDTH_4 ? SDC_CONTROL_SD_4BIT : 0; + + spin_unlock_irq(&host->lock); +} + +static void sdc_reset(struct mmc_host * mmc) { + struct sdc_host * host = mmc_priv(mmc); + uint32_t card_detect = 0; + + spin_lock_irq(&host->lock); + + sdc_set_clock(host, 400000); + + // software reset + host->regs->software_reset = 1; + while ((host->regs->software_reset & 1) == 0) {} + // clear software reset + host->regs->software_reset = 0; + while (host->regs->software_reset != 0) {} + udelay(10000); + + // set bus width 1 bit + host->regs->control = 0; + + // disable cmd/data interrupts + host->regs->cmd_int_enable = 0; + host->regs->dat_int_enable = 0; + // clear cmd/data interrupts + host->regs->cmd_int_status = 0; + host->regs->dat_int_status = 0; + // enable card detect interrupt + card_detect = host->regs->card_detect; + if (card_detect & SDC_CARD_INSERT_INT_REQ) { + host->regs->card_detect = SDC_CARD_REMOVE_INT_EN; + } + else if (card_detect & SDC_CARD_REMOVE_INT_REQ) { + host->regs->card_detect = SDC_CARD_INSERT_INT_EN; + } + while (host->regs->software_reset != 0) {} + + spin_unlock_irq(&host->lock); +} + +static void sdc_card_reset(struct mmc_host * mmc) { + struct sdc_host * host = mmc_priv(mmc); + uint32_t control = 0; + + spin_lock_irq(&host->lock); + + control = host->regs->control; + host->regs->control = control | SDC_CONTROL_SD_RESET; + udelay(10); + host->regs->control = control & ~(uint32_t)SDC_CONTROL_SD_RESET; + udelay(10); + + spin_unlock_irq(&host->lock); +} + +static int sdc_get_cd(struct mmc_host * mmc) { + struct sdc_host * host = mmc_priv(mmc); + uint32_t card_detect = host->regs->card_detect; + if (card_detect == 0) return 1; /* Card detect not supported */ + return (card_detect & SDC_CARD_INSERT_INT_REQ) != 0; +} + +static irqreturn_t sdc_isr(int irq, void * dev_id) { + struct mmc_host * mmc = (struct mmc_host *)dev_id; + struct sdc_host * host = mmc_priv(mmc); + uint32_t card_detect = 0; + uint32_t data_status = 0; + unsigned long flags; + + spin_lock_irqsave(&host->lock, flags); + + card_detect = host->regs->card_detect; + if (card_detect & SDC_CARD_INSERT_INT_REQ) { + if (card_detect & SDC_CARD_INSERT_INT_EN) { + host->regs->card_detect = SDC_CARD_REMOVE_INT_EN; + mmc_detect_change(mmc, 0); + } + } + else if (card_detect & SDC_CARD_REMOVE_INT_REQ) { + if (card_detect & SDC_CARD_REMOVE_INT_EN) { + host->regs->card_detect = SDC_CARD_INSERT_INT_EN; + mmc_detect_change(mmc, 0); + } + } + + if ((data_status = host->regs->dat_int_status) != 0) { + host->regs->dat_int_enable = 0; + host->regs->dat_int_status = 0; + while (host->regs->software_reset != 0) {} + if (host->data) { + struct mmc_request * mrq = host->mrq; + struct mmc_data * data = host->data; + if (data_status == SDC_DAT_INT_STATUS_TRS) { + data->bytes_xfered = data->blksz * data->blocks; + } + else { + data->error = -EIO; + if (data_status & SDC_DAT_INT_STATUS_CTE) data->error = -ETIME; + } + if (mrq->stop) sdc_send_cmd(host, mmc, mrq->stop, NULL); + mmc_request_done(mmc, mrq); + dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len, mmc_get_dma_dir(data)); + host->data = NULL; + host->mrq = NULL; + } + } + + spin_unlock_irqrestore(&host->lock, flags); + return IRQ_HANDLED; +} + +/*---------------------------------------------------------------------*/ + +// JACOB: Had to modify this to resemble the older version of Linux +// Used to be called hw_reset in older versions. Now it's +// called .card_hw_reset to make it unambiguous what it's +// resetting. When I update Linux, this will be changed back. +static const struct mmc_host_ops axi_sdc_ops = { + .request = sdc_request, + .set_ios = sdc_set_ios, + .get_cd = sdc_get_cd, + .hw_reset = sdc_card_reset, +}; + +static int axi_sdc_probe(struct platform_device * pdev) { + struct device * dev = &pdev->dev; + struct resource * iomem; + struct sdc_host * host; + struct mmc_host * mmc; + void __iomem * ioaddr; + uint32_t capability; + int irq; + int ret; + + iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + ioaddr = devm_ioremap_resource(dev, iomem); + if (IS_ERR(ioaddr)) return PTR_ERR(ioaddr); + + irq = platform_get_irq(pdev, 0); + if (irq <= 0) return -ENXIO; + + mmc = mmc_alloc_host(sizeof(*host), dev); + if (!mmc) return -ENOMEM; + + mmc->ops = &axi_sdc_ops; + host = mmc_priv(mmc); + host->pdev = pdev; + host->regs = (struct sdc_regs __iomem *)ioaddr; + host->irq = irq; + + ret = of_property_read_u32(dev->of_node, "clock", &host->clk_freq); + if (ret) host->clk_freq = 100000000; + + ret = mmc_of_parse(mmc); + if (ret) { + mmc_free_host(mmc); + return ret; + } + + if (mmc->f_min == 0) mmc->f_min = host->clk_freq / 0x200; /* maximum clock division 256 * 2 */ + if (mmc->f_max == 0) mmc->f_max = host->clk_freq / 2; /* minimum clock division 2 */ + if ((mmc->caps2 & MMC_CAP2_NO_SDIO) == 0) { + /* TODO: deprecated 10/19/2022, set in DTS */ + mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; + mmc->caps2 |= MMC_CAP2_NO_SDIO; + } + mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; + mmc->max_segs = 1; + mmc->max_req_size = 0x2000000; + mmc->max_seg_size = 0x2000000; + mmc->max_blk_size = 0x1000; + mmc->max_blk_count = 0x10000; + + ret = request_irq(host->irq, sdc_isr, IRQF_TRIGGER_HIGH, "fpga-axi-sdc", mmc); + if (ret) { + mmc_free_host(mmc); + return ret; + } + + host->dma_addr_bits = 32; + capability = host->regs->capability; + if (capability & SDC_CAPABILITY_ADDR) { + host->dma_addr_bits = (capability & SDC_CAPABILITY_ADDR) >> __builtin_ctz(SDC_CAPABILITY_ADDR); + ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(host->dma_addr_bits)); + if (ret) { + printk(KERN_ERR "AXI-SDC: Can't set DMA mask\n"); + mmc_free_host(mmc); + return ret; + } + } + + sdc_reset(mmc); + + ret = mmc_add_host(mmc); + if (ret) { + printk(KERN_ERR "AXI-SDC: Can't register device\n"); + mmc_free_host(mmc); + return ret; + } + + spin_lock_init(&host->lock); + + platform_set_drvdata(pdev, host); + return 0; +} + +static int axi_sdc_remove(struct platform_device * pdev) { + struct sdc_host * host = platform_get_drvdata(pdev); + struct mmc_host * mmc = mmc_from_priv(host); + + free_irq(host->irq, mmc); + mmc_remove_host(mmc); + mmc_free_host(mmc); + return 0; +} + +static struct platform_driver axi_sdc_driver = { + .driver = { + .name = "riscv-axi-sdc", + .of_match_table = axi_sdc_of_match_table, + }, + .probe = axi_sdc_probe, + .remove = axi_sdc_remove, +}; + +module_platform_driver(axi_sdc_driver); + +MODULE_DESCRIPTION("AXI SD Card driver"); +MODULE_AUTHOR("Eugene Tarassov"); +MODULE_LICENSE("GPL v2"); diff --git a/linux/buildroot-packages/package.patch b/linux/buildroot-packages/package.patch new file mode 100644 index 000000000..2069a005c --- /dev/null +++ b/linux/buildroot-packages/package.patch @@ -0,0 +1,12 @@ +diff --git a/package/Config.in b/package/Config.in +index 82b28d2835..29e8bb66ac 100644 +--- a/package/Config.in ++++ b/package/Config.in +@@ -469,6 +469,7 @@ endmenu + source "package/fconfig/Config.in" + source "package/flashrom/Config.in" + source "package/fmtools/Config.in" ++ source "package/fpga-axi-sdc/Config.in" + source "package/freescale-imx/Config.in" + source "package/fxload/Config.in" + source "package/gcnano-binaries/Config.in" diff --git a/linux/buildroot-packages/wally.config b/linux/buildroot-packages/wally.config new file mode 100644 index 000000000..e5fb96464 --- /dev/null +++ b/linux/buildroot-packages/wally.config @@ -0,0 +1,3808 @@ +# +# Automatically generated file; DO NOT EDIT. +# Buildroot 2021.05-dirty Configuration +# +BR2_HAVE_DOT_CONFIG=y +BR2_HOST_GCC_AT_LEAST_4_9=y +BR2_HOST_GCC_AT_LEAST_5=y +BR2_HOST_GCC_AT_LEAST_6=y +BR2_HOST_GCC_AT_LEAST_7=y +BR2_HOST_GCC_AT_LEAST_8=y +BR2_HOST_GCC_AT_LEAST_9=y + +# +# Target options +# +BR2_ARCH_IS_64=y +BR2_ARCH_HAS_MMU_MANDATORY=y +# BR2_arcle is not set +# BR2_arceb is not set +# BR2_arm is not set +# BR2_armeb is not set +# BR2_aarch64 is not set +# BR2_aarch64_be is not set +# BR2_csky is not set +# BR2_i386 is not set +# BR2_m68k is not set +# BR2_microblazeel is not set +# BR2_microblazebe is not set +# BR2_mips is not set +# BR2_mipsel is not set +# BR2_mips64 is not set +# BR2_mips64el is not set +# BR2_nds32 is not set +# BR2_nios2 is not set +# BR2_or1k is not set +# BR2_powerpc is not set +# BR2_powerpc64 is not set +# BR2_powerpc64le is not set +BR2_riscv=y +# BR2_s390x is not set +# BR2_sh is not set +# BR2_sparc is not set +# BR2_sparc64 is not set +# BR2_x86_64 is not set +# BR2_xtensa is not set +BR2_ARCH_HAS_TOOLCHAIN_BUILDROOT=y +BR2_ARCH_NEEDS_GCC_AT_LEAST_4_8=y +BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9=y +BR2_ARCH_NEEDS_GCC_AT_LEAST_5=y +BR2_ARCH_NEEDS_GCC_AT_LEAST_6=y +BR2_ARCH_NEEDS_GCC_AT_LEAST_7=y +BR2_ARCH="riscv64" +BR2_ENDIAN="LITTLE" +BR2_GCC_TARGET_ABI="lp64d" +BR2_BINFMT_SUPPORTS_SHARED=y +BR2_READELF_ARCH_NAME="RISC-V" +BR2_BINFMT_ELF=y +BR2_RISCV_ISA_RVI=y +BR2_RISCV_ISA_RVM=y +BR2_RISCV_ISA_RVA=y +BR2_RISCV_ISA_RVF=y +BR2_RISCV_ISA_RVD=y +BR2_riscv_g=y +# BR2_riscv_custom is not set +# BR2_RISCV_32 is not set +BR2_RISCV_64=y +# BR2_RISCV_ABI_LP64 is not set +# BR2_RISCV_ABI_LP64F is not set +BR2_RISCV_ABI_LP64D=y + +# +# Build options +# + +# +# Commands +# +BR2_WGET="wget --passive-ftp -nd -t 3" +BR2_SVN="svn --non-interactive" +BR2_BZR="bzr" +BR2_GIT="git" +BR2_CVS="cvs" +BR2_LOCALFILES="cp" +BR2_SCP="scp" +BR2_HG="hg" +BR2_ZCAT="gzip -d -c" +BR2_BZCAT="bzcat" +BR2_XZCAT="xzcat" +BR2_LZCAT="lzip -d -c" +BR2_TAR_OPTIONS="" +BR2_DEFCONFIG="./board/wally/main.config" +BR2_DL_DIR="$(TOPDIR)/dl" +BR2_HOST_DIR="$(BASE_DIR)/host" + +# +# Mirrors and Download locations +# +BR2_PRIMARY_SITE="" +BR2_BACKUP_SITE="http://sources.buildroot.net" +BR2_KERNEL_MIRROR="https://cdn.kernel.org/pub" +BR2_GNU_MIRROR="http://ftpmirror.gnu.org" +BR2_LUAROCKS_MIRROR="http://rocks.moonscript.org" +BR2_CPAN_MIRROR="http://cpan.metacpan.org" +BR2_JLEVEL=0 +# BR2_CCACHE is not set +BR2_ENABLE_DEBUG=y +# BR2_DEBUG_1 is not set +# BR2_DEBUG_2 is not set +BR2_DEBUG_3=y +# BR2_STRIP_strip is not set +# BR2_OPTIMIZE_0 is not set +# BR2_OPTIMIZE_1 is not set +# BR2_OPTIMIZE_2 is not set +# BR2_OPTIMIZE_3 is not set +# BR2_OPTIMIZE_G is not set +BR2_OPTIMIZE_S=y +# BR2_OPTIMIZE_FAST is not set +# BR2_STATIC_LIBS is not set +BR2_SHARED_LIBS=y +# BR2_SHARED_STATIC_LIBS is not set +BR2_PACKAGE_OVERRIDE_FILE="$(CONFIG_DIR)/local.mk" +BR2_GLOBAL_PATCH_DIR="" + +# +# Advanced +# +BR2_COMPILER_PARANOID_UNSAFE_PATH=y +# BR2_FORCE_HOST_BUILD is not set +# BR2_REPRODUCIBLE is not set +# BR2_PER_PACKAGE_DIRECTORIES is not set + +# +# Security Hardening Options +# +# BR2_PIC_PIE is not set +BR2_SSP_NONE=y +# BR2_SSP_REGULAR is not set +# BR2_SSP_STRONG is not set +# BR2_SSP_ALL is not set +BR2_RELRO_NONE=y +# BR2_RELRO_PARTIAL is not set +# BR2_RELRO_FULL is not set +BR2_FORTIFY_SOURCE_NONE=y +# BR2_FORTIFY_SOURCE_1 is not set +# BR2_FORTIFY_SOURCE_2 is not set + +# +# Toolchain +# +BR2_TOOLCHAIN=y +BR2_TOOLCHAIN_USES_GLIBC=y +BR2_TOOLCHAIN_BUILDROOT=y +# BR2_TOOLCHAIN_EXTERNAL is not set + +# +# Toolchain Buildroot Options +# +BR2_TOOLCHAIN_BUILDROOT_VENDOR="buildroot" +# BR2_TOOLCHAIN_BUILDROOT_UCLIBC is not set +BR2_TOOLCHAIN_BUILDROOT_GLIBC=y +# BR2_TOOLCHAIN_BUILDROOT_MUSL is not set +BR2_TOOLCHAIN_BUILDROOT_LIBC="glibc" + +# +# Kernel Header Options +# +BR2_KERNEL_HEADERS_AS_KERNEL=y +# BR2_KERNEL_HEADERS_4_19 is not set +# BR2_KERNEL_HEADERS_5_4 is not set +# BR2_KERNEL_HEADERS_5_10 is not set +# BR2_KERNEL_HEADERS_5_11 is not set +# BR2_KERNEL_HEADERS_5_12 is not set +# BR2_KERNEL_HEADERS_VERSION is not set +# BR2_KERNEL_HEADERS_CUSTOM_TARBALL is not set +# BR2_KERNEL_HEADERS_CUSTOM_GIT is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_12 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_11 is not set +BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_10=y +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_9 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_8 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_7 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_6 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_5 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_4 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_3 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_2 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_1 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_0 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_20 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_19 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_18 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_17 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_16 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_15 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_14 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_13 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_12 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_11 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_10 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_9 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_8 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_7 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_6 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_5 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_4 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_3 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_2 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_1 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_0 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_19 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_18 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_17 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_16 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_15 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_14 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_13 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_12 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_11 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_10 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_9 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_8 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_7 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_6 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_5 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_4 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_3 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_2 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_1 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_0 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_REALLY_OLD is not set +BR2_PACKAGE_LINUX_HEADERS=y + +# +# Glibc Options +# +BR2_PACKAGE_GLIBC=y +# BR2_PACKAGE_GLIBC_UTILS is not set + +# +# Binutils Options +# +BR2_PACKAGE_HOST_BINUTILS_SUPPORTS_CFI=y +# BR2_BINUTILS_VERSION_2_32_X is not set +# BR2_BINUTILS_VERSION_2_34_X is not set +BR2_BINUTILS_VERSION_2_35_X=y +# BR2_BINUTILS_VERSION_2_36_X is not set +BR2_BINUTILS_VERSION="2.35.2" +BR2_BINUTILS_EXTRA_CONFIG_OPTIONS="" + +# +# GCC Options +# +# BR2_GCC_VERSION_8_X is not set +# BR2_GCC_VERSION_9_X is not set +BR2_GCC_VERSION_10_X=y +BR2_GCC_VERSION="10.3.0" +BR2_EXTRA_GCC_CONFIG_OPTIONS="" +# BR2_TOOLCHAIN_BUILDROOT_CXX is not set +# BR2_TOOLCHAIN_BUILDROOT_FORTRAN is not set +# BR2_GCC_ENABLE_LTO is not set +# BR2_GCC_ENABLE_OPENMP is not set +# BR2_GCC_ENABLE_GRAPHITE is not set + +# +# Toolchain Generic Options +# +BR2_TOOLCHAIN_SUPPORTS_ALWAYS_LOCKFREE_ATOMIC_INTS=y +BR2_TOOLCHAIN_SUPPORTS_VARIADIC_MI_THUNK=y +BR2_USE_WCHAR=y +BR2_ENABLE_LOCALE=y +BR2_TOOLCHAIN_HAS_THREADS=y +BR2_TOOLCHAIN_HAS_THREADS_DEBUG=y +BR2_TOOLCHAIN_HAS_THREADS_NPTL=y +BR2_TOOLCHAIN_HAS_SSP=y +BR2_TOOLCHAIN_HAS_SSP_STRONG=y +BR2_TOOLCHAIN_HAS_UCONTEXT=y +BR2_TOOLCHAIN_SUPPORTS_PIE=y +# BR2_TOOLCHAIN_GLIBC_GCONV_LIBS_COPY is not set +BR2_TOOLCHAIN_EXTRA_LIBS="" +BR2_TOOLCHAIN_HAS_FULL_GETTEXT=y +BR2_USE_MMU=y +BR2_TARGET_OPTIMIZATION="" +BR2_TARGET_LDFLAGS="" +# BR2_ECLIPSE_REGISTER is not set +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_0=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_1=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_2=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_3=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_4=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_5=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_6=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_7=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_8=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_9=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_10=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_11=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_12=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_13=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_14=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_15=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_16=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_17=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_18=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_19=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_0=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_1=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_2=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_3=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_4=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_5=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_6=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_7=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_8=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_9=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_10=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_11=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_12=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_13=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_14=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_15=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_16=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_17=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_18=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_19=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_20=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_0=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_1=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_2=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_3=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_4=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_5=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_6=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_7=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_8=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_9=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_10=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST="5.10" +BR2_TOOLCHAIN_GCC_AT_LEAST_4_3=y +BR2_TOOLCHAIN_GCC_AT_LEAST_4_4=y +BR2_TOOLCHAIN_GCC_AT_LEAST_4_5=y +BR2_TOOLCHAIN_GCC_AT_LEAST_4_6=y +BR2_TOOLCHAIN_GCC_AT_LEAST_4_7=y +BR2_TOOLCHAIN_GCC_AT_LEAST_4_8=y +BR2_TOOLCHAIN_GCC_AT_LEAST_4_9=y +BR2_TOOLCHAIN_GCC_AT_LEAST_5=y +BR2_TOOLCHAIN_GCC_AT_LEAST_6=y +BR2_TOOLCHAIN_GCC_AT_LEAST_7=y +BR2_TOOLCHAIN_GCC_AT_LEAST_8=y +BR2_TOOLCHAIN_GCC_AT_LEAST_9=y +BR2_TOOLCHAIN_GCC_AT_LEAST_10=y +BR2_TOOLCHAIN_GCC_AT_LEAST="10" +BR2_TOOLCHAIN_HAS_MNAN_OPTION=y +BR2_TOOLCHAIN_HAS_SYNC_1=y +BR2_TOOLCHAIN_HAS_SYNC_2=y +BR2_TOOLCHAIN_HAS_SYNC_4=y +BR2_TOOLCHAIN_HAS_SYNC_8=y +BR2_TOOLCHAIN_HAS_LIBATOMIC=y +BR2_TOOLCHAIN_HAS_ATOMIC=y + +# +# System configuration +# +BR2_ROOTFS_SKELETON_DEFAULT=y +# BR2_ROOTFS_SKELETON_CUSTOM is not set +BR2_TARGET_GENERIC_HOSTNAME="WallyHostname" +BR2_TARGET_GENERIC_ISSUE="Greetings! This RISC-V Linux image was built for Wally on Buildroot!" +BR2_TARGET_GENERIC_PASSWD_SHA256=y +# BR2_TARGET_GENERIC_PASSWD_SHA512 is not set +BR2_TARGET_GENERIC_PASSWD_METHOD="sha-256" +BR2_INIT_BUSYBOX=y +# BR2_INIT_SYSV is not set +# BR2_INIT_OPENRC is not set +# BR2_INIT_SYSTEMD is not set +# BR2_INIT_NONE is not set +# BR2_ROOTFS_DEVICE_CREATION_STATIC is not set +BR2_ROOTFS_DEVICE_CREATION_DYNAMIC_DEVTMPFS=y +# BR2_ROOTFS_DEVICE_CREATION_DYNAMIC_MDEV is not set +# BR2_ROOTFS_DEVICE_CREATION_DYNAMIC_EUDEV is not set +BR2_ROOTFS_DEVICE_TABLE="system/device_table.txt" +BR2_ROOTFS_DEVICE_TABLE_SUPPORTS_EXTENDED_ATTRIBUTES=y +# BR2_ROOTFS_MERGED_USR is not set +BR2_TARGET_ENABLE_ROOT_LOGIN=y +BR2_TARGET_GENERIC_ROOT_PASSWD="" +BR2_SYSTEM_BIN_SH_BUSYBOX=y + +# +# bash, dash, mksh, zsh need BR2_PACKAGE_BUSYBOX_SHOW_OTHERS +# +# BR2_SYSTEM_BIN_SH_NONE is not set +BR2_TARGET_GENERIC_GETTY=y +BR2_TARGET_GENERIC_GETTY_PORT="console" +BR2_TARGET_GENERIC_GETTY_BAUDRATE_KEEP=y +# BR2_TARGET_GENERIC_GETTY_BAUDRATE_9600 is not set +# BR2_TARGET_GENERIC_GETTY_BAUDRATE_19200 is not set +# BR2_TARGET_GENERIC_GETTY_BAUDRATE_38400 is not set +# BR2_TARGET_GENERIC_GETTY_BAUDRATE_57600 is not set +# BR2_TARGET_GENERIC_GETTY_BAUDRATE_115200 is not set +BR2_TARGET_GENERIC_GETTY_BAUDRATE="0" +BR2_TARGET_GENERIC_GETTY_TERM="vt100" +BR2_TARGET_GENERIC_GETTY_OPTIONS="" +BR2_TARGET_GENERIC_REMOUNT_ROOTFS_RW=y +BR2_SYSTEM_DHCP="eth0" +BR2_SYSTEM_DEFAULT_PATH="/bin:/sbin:/usr/bin:/usr/sbin" +BR2_ENABLE_LOCALE_PURGE=y +BR2_ENABLE_LOCALE_WHITELIST="C en_US" +BR2_GENERATE_LOCALE="" +# BR2_SYSTEM_ENABLE_NLS is not set +# BR2_TARGET_TZ_INFO is not set +BR2_ROOTFS_USERS_TABLES="" +BR2_ROOTFS_OVERLAY="./board/wally/rootfs_overlay" +BR2_ROOTFS_POST_BUILD_SCRIPT="" +BR2_ROOTFS_POST_FAKEROOT_SCRIPT="" +BR2_ROOTFS_POST_IMAGE_SCRIPT="" + +# +# Kernel +# +BR2_LINUX_KERNEL=y +# BR2_LINUX_KERNEL_LATEST_VERSION is not set +# BR2_LINUX_KERNEL_LATEST_CIP_VERSION is not set +# BR2_LINUX_KERNEL_LATEST_CIP_RT_VERSION is not set +BR2_LINUX_KERNEL_CUSTOM_VERSION=y +# BR2_LINUX_KERNEL_CUSTOM_TARBALL is not set +# BR2_LINUX_KERNEL_CUSTOM_GIT is not set +# BR2_LINUX_KERNEL_CUSTOM_HG is not set +# BR2_LINUX_KERNEL_CUSTOM_SVN is not set +BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.10.7" +BR2_LINUX_KERNEL_VERSION="5.10.7" +BR2_LINUX_KERNEL_PATCH="" +# BR2_LINUX_KERNEL_USE_DEFCONFIG is not set +# BR2_LINUX_KERNEL_USE_ARCH_DEFAULT_CONFIG is not set +BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y +BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="./board/wally/linux.config" +BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="" +BR2_LINUX_KERNEL_CUSTOM_LOGO_PATH="" +BR2_LINUX_KERNEL_IMAGE=y +# BR2_LINUX_KERNEL_IMAGEGZ is not set +# BR2_LINUX_KERNEL_VMLINUX is not set +# BR2_LINUX_KERNEL_IMAGE_TARGET_CUSTOM is not set +BR2_LINUX_KERNEL_GZIP=y +# BR2_LINUX_KERNEL_LZ4 is not set +# BR2_LINUX_KERNEL_LZMA is not set +# BR2_LINUX_KERNEL_LZO is not set +# BR2_LINUX_KERNEL_XZ is not set +# BR2_LINUX_KERNEL_ZSTD is not set +# BR2_LINUX_KERNEL_DTS_SUPPORT is not set +# BR2_LINUX_KERNEL_NEEDS_HOST_OPENSSL is not set +# BR2_LINUX_KERNEL_NEEDS_HOST_LIBELF is not set + +# +# Linux Kernel Extensions +# +# BR2_LINUX_KERNEL_EXT_RTAI is not set +# BR2_LINUX_KERNEL_EXT_EV3DEV_LINUX_DRIVERS is not set +# BR2_LINUX_KERNEL_EXT_FBTFT is not set +# BR2_LINUX_KERNEL_EXT_AUFS is not set + +# +# Linux Kernel Tools +# +# BR2_PACKAGE_LINUX_TOOLS_CPUPOWER is not set +# BR2_PACKAGE_LINUX_TOOLS_GPIO is not set +# BR2_PACKAGE_LINUX_TOOLS_IIO is not set +# BR2_PACKAGE_LINUX_TOOLS_PCI is not set +# BR2_PACKAGE_LINUX_TOOLS_PERF is not set + +# +# selftests needs BR2_PACKAGE_BUSYBOX_SHOW_OTHERS and a toolchain w/ dynamic library +# +# BR2_PACKAGE_LINUX_TOOLS_TMON is not set + +# +# Target packages +# +BR2_PACKAGE_BUSYBOX=y +BR2_PACKAGE_BUSYBOX_CONFIG="./board/wally/busybox.config" +BR2_PACKAGE_BUSYBOX_CONFIG_FRAGMENT_FILES="" +# BR2_PACKAGE_BUSYBOX_SHOW_OTHERS is not set +# BR2_PACKAGE_BUSYBOX_INDIVIDUAL_BINARIES is not set +# BR2_PACKAGE_BUSYBOX_WATCHDOG is not set +BR2_PACKAGE_SKELETON=y +BR2_PACKAGE_HAS_SKELETON=y +BR2_PACKAGE_PROVIDES_SKELETON="skeleton-init-sysv" +BR2_PACKAGE_SKELETON_INIT_COMMON=y +BR2_PACKAGE_SKELETON_INIT_SYSV=y + +# +# Audio and video applications +# +# BR2_PACKAGE_ALSA_UTILS is not set +# BR2_PACKAGE_ATEST is not set +# BR2_PACKAGE_AUMIX is not set +# BR2_PACKAGE_BLUEZ_ALSA is not set +# BR2_PACKAGE_DVBLAST is not set +# BR2_PACKAGE_DVDAUTHOR is not set + +# +# dvdrw-tools needs a toolchain w/ threads, C++, wchar +# + +# +# espeak needs a toolchain w/ C++, wchar, threads, dynamic library +# +# BR2_PACKAGE_FAAD2 is not set +BR2_PACKAGE_FFMPEG_ARCH_SUPPORTS=y +# BR2_PACKAGE_FFMPEG is not set +# BR2_PACKAGE_FLAC is not set +# BR2_PACKAGE_FLITE is not set +# BR2_PACKAGE_FLUID_SOUNDFONT is not set +# BR2_PACKAGE_FLUIDSYNTH is not set +# BR2_PACKAGE_GMRENDER_RESURRECT is not set +# BR2_PACKAGE_GSTREAMER1 is not set +# BR2_PACKAGE_JACK1 is not set + +# +# jack2 needs a toolchain w/ threads, C++, dynamic library +# +BR2_PACKAGE_KODI_ARCH_SUPPORTS=y + +# +# kodi needs python3 w/ .py modules, a uClibc or glibc toolchain w/ C++, threads, wchar, dynamic library, gcc >= 4.9 +# + +# +# kodi needs an OpenGL EGL backend with OpenGL or GLES support +# +# BR2_PACKAGE_LAME is not set +# BR2_PACKAGE_MADPLAY is not set +# BR2_PACKAGE_MIMIC is not set +# BR2_PACKAGE_MINIMODEM is not set + +# +# miraclecast needs systemd and a glibc toolchain w/ threads and wchar +# + +# +# mjpegtools needs a toolchain w/ C++, threads +# + +# +# modplugtools needs a toolchain w/ C++ +# +# BR2_PACKAGE_MOTION is not set + +# +# mpd needs a toolchain w/ C++, threads, wchar, gcc >= 7, host gcc >= 7 +# +# BR2_PACKAGE_MPD_MPC is not set +# BR2_PACKAGE_MPG123 is not set + +# +# mpv needs a toolchain w/ C++, threads, gcc >= 4.9 +# +# BR2_PACKAGE_MULTICAT is not set +# BR2_PACKAGE_MUSEPACK is not set + +# +# ncmpc needs a toolchain w/ C++, wchar, threads, gcc >= 7 +# +# BR2_PACKAGE_OPUS_TOOLS is not set +BR2_PACKAGE_PULSEAUDIO_HAS_ATOMIC=y +# BR2_PACKAGE_PULSEAUDIO is not set +# BR2_PACKAGE_SOX is not set +# BR2_PACKAGE_SQUEEZELITE is not set + +# +# tovid needs a toolchain w/ threads, C++, wchar, gcc >= 4.9 +# +# BR2_PACKAGE_TSTOOLS is not set +# BR2_PACKAGE_TWOLAME is not set +# BR2_PACKAGE_UDPXY is not set + +# +# upmpdcli needs a toolchain w/ C++, NPTL, gcc >= 4.9 +# + +# +# v4l2grab needs a toolchain w/ threads, dynamic library, C++ and headers >= 3.0 +# +# BR2_PACKAGE_V4L2LOOPBACK is not set + +# +# vlc needs a toolchain w/ C++, dynamic library, wchar, threads, gcc >= 4.9, headers >= 3.7 +# +# BR2_PACKAGE_VORBIS_TOOLS is not set +# BR2_PACKAGE_WAVPACK is not set +# BR2_PACKAGE_YAVTA is not set +# BR2_PACKAGE_YMPD is not set + +# +# Compressors and decompressors +# +# BR2_PACKAGE_BROTLI is not set +# BR2_PACKAGE_BZIP2 is not set + +# +# lrzip needs a toolchain w/ wchar, threads, C++ +# + +# +# lzip needs a toolchain w/ C++ +# +# BR2_PACKAGE_LZOP is not set + +# +# p7zip needs a toolchain w/ threads, wchar, C++ +# +# BR2_PACKAGE_PIGZ is not set +# BR2_PACKAGE_PIXZ is not set + +# +# unrar needs a toolchain w/ C++, wchar, threads +# +# BR2_PACKAGE_XZ is not set +# BR2_PACKAGE_ZIP is not set +# BR2_PACKAGE_ZSTD is not set + +# +# Debugging, profiling and benchmark +# +# BR2_PACKAGE_BABELTRACE2 is not set +# BR2_PACKAGE_BLKTRACE is not set + +# +# bonnie++ needs a toolchain w/ C++ +# +# BR2_PACKAGE_CACHE_CALIBRATOR is not set + +# +# clinfo needs an OpenCL provider +# +# BR2_PACKAGE_COREMARK is not set +# BR2_PACKAGE_COREMARK_PRO is not set + +# +# dacapo needs OpenJDK +# +# BR2_PACKAGE_DHRYSTONE is not set +# BR2_PACKAGE_DIEHARDER is not set +# BR2_PACKAGE_DMALLOC is not set +# BR2_PACKAGE_DROPWATCH is not set +# BR2_PACKAGE_DSTAT is not set +# BR2_PACKAGE_DT is not set + +# +# duma needs a toolchain w/ C++, threads, dynamic library +# +# BR2_PACKAGE_FIO is not set +BR2_PACKAGE_GDB_ARCH_SUPPORTS=y + +# +# gdb/gdbserver >= 8.x needs a toolchain w/ C++, gcc >= 4.8 +# +# BR2_PACKAGE_IOZONE is not set +# BR2_PACKAGE_KTAP is not set +# BR2_PACKAGE_LATENCYTOP is not set +# BR2_PACKAGE_LMBENCH is not set +BR2_PACKAGE_LTP_TESTSUITE_ARCH_SUPPORTS=y +# BR2_PACKAGE_LTP_TESTSUITE is not set +# BR2_PACKAGE_LTTNG_BABELTRACE is not set +# BR2_PACKAGE_LTTNG_MODULES is not set +# BR2_PACKAGE_LTTNG_TOOLS is not set +# BR2_PACKAGE_MEMSTAT is not set +# BR2_PACKAGE_NETPERF is not set +# BR2_PACKAGE_NETSNIFF_NG is not set +# BR2_PACKAGE_NMON is not set +# BR2_PACKAGE_PAX_UTILS is not set +# BR2_PACKAGE_PV is not set +# BR2_PACKAGE_RAMSMP is not set +# BR2_PACKAGE_RAMSPEED is not set +# BR2_PACKAGE_RT_TESTS is not set +# BR2_PACKAGE_SPIDEV_TEST is not set +# BR2_PACKAGE_STRACE is not set +# BR2_PACKAGE_STRESS is not set +# BR2_PACKAGE_STRESS_NG is not set + +# +# sysdig needs a glibc or uclibc toolchain w/ C++, threads, gcc >= 4.8, dynamic library, a Linux kernel, and luajit or lua 5.1 to be built +# +# BR2_PACKAGE_TINYMEMBENCH is not set +# BR2_PACKAGE_TRACE_CMD is not set +# BR2_PACKAGE_UCLIBC_NG_TEST is not set +# BR2_PACKAGE_VMTOUCH is not set +# BR2_PACKAGE_WHETSTONE is not set + +# +# Development tools +# +# BR2_PACKAGE_BINUTILS is not set +# BR2_PACKAGE_BITWISE is not set +# BR2_PACKAGE_BSDIFF is not set +# BR2_PACKAGE_CHECK is not set + +# +# cppunit needs a toolchain w/ C++, dynamic library +# +# BR2_PACKAGE_CUKINIA is not set +# BR2_PACKAGE_CUNIT is not set +# BR2_PACKAGE_CVS is not set + +# +# cxxtest needs a toolchain w/ C++ support +# +# BR2_PACKAGE_FLEX is not set +# BR2_PACKAGE_GETTEXT is not set +BR2_PACKAGE_PROVIDES_HOST_GETTEXT="host-gettext-tiny" +# BR2_PACKAGE_GIT is not set + +# +# git-crypt needs a toolchain w/ C++, gcc >= 4.9 +# + +# +# gperf needs a toolchain w/ C++ +# +# BR2_PACKAGE_JO is not set +# BR2_PACKAGE_JQ is not set +# BR2_PACKAGE_LIBTOOL is not set +# BR2_PACKAGE_MAKE is not set +# BR2_PACKAGE_MAWK is not set +# BR2_PACKAGE_PKGCONF is not set +# BR2_PACKAGE_SUBVERSION is not set +# BR2_PACKAGE_TREE is not set + +# +# Filesystem and flash utilities +# +# BR2_PACKAGE_ABOOTIMG is not set +# BR2_PACKAGE_AUFS_UTIL is not set +# BR2_PACKAGE_AUTOFS is not set +# BR2_PACKAGE_BTRFS_PROGS is not set +# BR2_PACKAGE_CIFS_UTILS is not set +# BR2_PACKAGE_CPIO is not set +# BR2_PACKAGE_CRAMFS is not set +# BR2_PACKAGE_CURLFTPFS is not set +# BR2_PACKAGE_DAVFS2 is not set +# BR2_PACKAGE_DOSFSTOOLS is not set +# BR2_PACKAGE_E2FSPROGS is not set +# BR2_PACKAGE_E2TOOLS is not set +# BR2_PACKAGE_ECRYPTFS_UTILS is not set +# BR2_PACKAGE_EROFS_UTILS is not set +# BR2_PACKAGE_EXFAT is not set +# BR2_PACKAGE_EXFAT_UTILS is not set +# BR2_PACKAGE_EXFATPROGS is not set +# BR2_PACKAGE_F2FS_TOOLS is not set +# BR2_PACKAGE_FLASHBENCH is not set +# BR2_PACKAGE_FSCRYPTCTL is not set +# BR2_PACKAGE_FUSE_OVERLAYFS is not set +# BR2_PACKAGE_FWUP is not set +# BR2_PACKAGE_GENEXT2FS is not set +# BR2_PACKAGE_GENPART is not set +# BR2_PACKAGE_GENROMFS is not set +# BR2_PACKAGE_IMX_USB_LOADER is not set +# BR2_PACKAGE_MMC_UTILS is not set +# BR2_PACKAGE_MTD is not set +# BR2_PACKAGE_MTOOLS is not set +# BR2_PACKAGE_NFS_UTILS is not set +# BR2_PACKAGE_NILFS_UTILS is not set +# BR2_PACKAGE_NTFS_3G is not set +# BR2_PACKAGE_SP_OOPS_EXTRACT is not set +# BR2_PACKAGE_SQUASHFS is not set +# BR2_PACKAGE_SSHFS is not set +# BR2_PACKAGE_UDFTOOLS is not set +# BR2_PACKAGE_UNIONFS is not set +# BR2_PACKAGE_XFSPROGS is not set + +# +# zfs needs udev /dev management +# + +# +# Fonts, cursors, icons, sounds and themes +# + +# +# Cursors +# +# BR2_PACKAGE_COMIX_CURSORS is not set +# BR2_PACKAGE_OBSIDIAN_CURSORS is not set + +# +# Fonts +# +# BR2_PACKAGE_BITSTREAM_VERA is not set +# BR2_PACKAGE_CANTARELL is not set +# BR2_PACKAGE_DEJAVU is not set +# BR2_PACKAGE_FONT_AWESOME is not set +# BR2_PACKAGE_GHOSTSCRIPT_FONTS is not set +# BR2_PACKAGE_INCONSOLATA is not set +# BR2_PACKAGE_LIBERATION is not set +# BR2_PACKAGE_WQY_ZENHEI is not set + +# +# Icons +# +# BR2_PACKAGE_GOOGLE_MATERIAL_DESIGN_ICONS is not set +# BR2_PACKAGE_HICOLOR_ICON_THEME is not set + +# +# Sounds +# +# BR2_PACKAGE_SOUND_THEME_BOREALIS is not set +# BR2_PACKAGE_SOUND_THEME_FREEDESKTOP is not set + +# +# Themes +# + +# +# Games +# +# BR2_PACKAGE_ASCII_INVADERS is not set +# BR2_PACKAGE_CHOCOLATE_DOOM is not set + +# +# flare-engine needs a toolchain w/ C++, dynamic library +# +# BR2_PACKAGE_FROTZ is not set + +# +# gnuchess needs a toolchain w/ C++, threads +# +# BR2_PACKAGE_LBREAKOUT2 is not set +# BR2_PACKAGE_LTRIS is not set +# BR2_PACKAGE_OPENTYRIAN is not set +# BR2_PACKAGE_PRBOOM is not set +# BR2_PACKAGE_SL is not set + +# +# solarus needs OpenGL and a toolchain w/ C++, gcc >= 4.9, NPTL, dynamic library, and luajit or lua 5.1 +# + +# +# stella needs a toolchain w/ dynamic library, C++, threads, gcc >= 6 +# +# BR2_PACKAGE_XORCURSES is not set + +# +# Graphic libraries and applications (graphic/text) +# + +# +# Graphic applications +# + +# +# cage needs udev, EGL w/ Wayland backend and OpenGL ES support +# + +# +# cog needs wpewebkit and a toolchain w/ threads +# +# BR2_PACKAGE_FSWEBCAM is not set +# BR2_PACKAGE_GHOSTSCRIPT is not set + +# +# glmark2 needs a toolchain w/ C++, gcc >= 4.9 +# + +# +# glslsandbox-player needs a toolchain w/ threads and an openGL ES and EGL driver +# +# BR2_PACKAGE_GNUPLOT is not set +# BR2_PACKAGE_JHEAD is not set + +# +# libva-utils needs a toolchain w/ C++, threads, dynamic library +# +BR2_PACKAGE_NETSURF_ARCH_SUPPORTS=y +# BR2_PACKAGE_NETSURF is not set +# BR2_PACKAGE_PNGQUANT is not set +# BR2_PACKAGE_RRDTOOL is not set + +# +# stellarium needs Qt5 and an OpenGL provider +# + +# +# tesseract-ocr needs a toolchain w/ threads, C++, gcc >= 4.8, dynamic library, wchar +# + +# +# Graphic libraries +# + +# +# cegui needs a toolchain w/ C++, threads, dynamic library, wchar +# + +# +# directfb needs a glibc or uClibc toolchain w/ C++, NPTL, gcc >= 4.5, dynamic library +# + +# +# efl needs a toolchain w/ C++, dynamic library, gcc >= 4.9, host gcc >= 4.9, threads, wchar +# +# BR2_PACKAGE_FB_TEST_APP is not set +# BR2_PACKAGE_FBDUMP is not set +# BR2_PACKAGE_FBGRAB is not set + +# +# fbterm needs a toolchain w/ C++, wchar, locale +# +# BR2_PACKAGE_FBV is not set + +# +# freerdp needs a toolchain w/ wchar, dynamic library, threads, C++ +# +# BR2_PACKAGE_GRAPHICSMAGICK is not set +# BR2_PACKAGE_IMAGEMAGICK is not set +# BR2_PACKAGE_LINUX_FUSION is not set + +# +# mesa3d needs a toolchain w/ C++, NPTL, dynamic library +# + +# +# ocrad needs a toolchain w/ C++ +# + +# +# ogre needs a toolchain w/ C++, dynamic library, gcc >= 4.8, threads, wchar +# +# BR2_PACKAGE_PSPLASH is not set +# BR2_PACKAGE_SDL is not set +# BR2_PACKAGE_SDL2 is not set + +# +# Other GUIs +# + +# +# Qt5 needs host g++ >= 5.0, and a toolchain w/ gcc >= 5.0, wchar, NPTL, C++, dynamic library +# + +# +# tekui needs a Lua interpreter and a toolchain w/ threads, dynamic library +# + +# +# weston needs udev and a toolchain w/ locale, threads, dynamic library, headers >= 3.0 +# +# BR2_PACKAGE_XORG7 is not set + +# +# apitrace needs a toolchain w/ C++, wchar, dynamic library, threads, gcc >= 4.9 +# + +# +# vte needs a toolchain w/ wchar, threads, C++, gcc >= 4.8 +# + +# +# vte needs an OpenGL or an OpenGL-EGL/wayland backend +# +# BR2_PACKAGE_XKEYBOARD_CONFIG is not set + +# +# Hardware handling +# + +# +# Firmware +# +# BR2_PACKAGE_ARMBIAN_FIRMWARE is not set +# BR2_PACKAGE_B43_FIRMWARE is not set +# BR2_PACKAGE_LINUX_FIRMWARE is not set +# BR2_PACKAGE_MURATA_CYW_FW is not set +# BR2_PACKAGE_ODROIDC2_FIRMWARE is not set +# BR2_PACKAGE_QCOM_DB410C_FIRMWARE is not set +# BR2_PACKAGE_RCW_SMARC_SAL28 is not set +# BR2_PACKAGE_UX500_FIRMWARE is not set +# BR2_PACKAGE_WILC1000_FIRMWARE is not set +# BR2_PACKAGE_WILINK_BT_FIRMWARE is not set +# BR2_PACKAGE_ZD1211_FIRMWARE is not set +# BR2_PACKAGE_18XX_TI_UTILS is not set +# BR2_PACKAGE_ACPICA is not set +# BR2_PACKAGE_ACPID is not set + +# +# acpitool needs a toolchain w/ threads, C++, dynamic library +# +# BR2_PACKAGE_AER_INJECT is not set +# BR2_PACKAGE_ALTERA_STAPL is not set + +# +# apcupsd needs a toolchain w/ C++, threads +# +# BR2_PACKAGE_AVRDUDE is not set + +# +# bcache-tools needs udev /dev management +# + +# +# brickd needs udev /dev management, a toolchain w/ threads, wchar +# +# BR2_PACKAGE_BRLTTY is not set + +# +# cc-tool needs a toolchain w/ C++, threads, wchar, gcc >= 4.9 +# +# BR2_PACKAGE_CDRKIT is not set +# BR2_PACKAGE_CRYPTSETUP is not set +# BR2_PACKAGE_CWIID is not set +# BR2_PACKAGE_DAHDI_LINUX is not set +# BR2_PACKAGE_DAHDI_TOOLS is not set +# BR2_PACKAGE_DBUS is not set +# BR2_PACKAGE_DFU_UTIL is not set +# BR2_PACKAGE_DMRAID is not set + +# +# dt-utils needs udev /dev management +# +# BR2_PACKAGE_DTV_SCAN_TABLES is not set +# BR2_PACKAGE_DUMP1090 is not set +# BR2_PACKAGE_DVB_APPS is not set +# BR2_PACKAGE_DVBSNOOP is not set + +# +# eudev needs eudev /dev management +# +# BR2_PACKAGE_EVEMU is not set +# BR2_PACKAGE_EVTEST is not set +# BR2_PACKAGE_FAN_CTRL is not set +# BR2_PACKAGE_FCONFIG is not set +BR2_PACKAGE_FLASHROM_ARCH_SUPPORTS=y +# BR2_PACKAGE_FLASHROM is not set +# BR2_PACKAGE_FMTOOLS is not set +BR2_PACKAGE_FPGA_AXI_SDC=y +# BR2_PACKAGE_FXLOAD is not set +# BR2_PACKAGE_GPM is not set +# BR2_PACKAGE_GPSD is not set + +# +# gptfdisk needs a toolchain w/ C++ +# +# BR2_PACKAGE_GVFS is not set +# BR2_PACKAGE_HWDATA is not set +# BR2_PACKAGE_HWLOC is not set +# BR2_PACKAGE_INPUT_EVENT_DAEMON is not set +# BR2_PACKAGE_IPMITOOL is not set +# BR2_PACKAGE_IRDA_UTILS is not set +# BR2_PACKAGE_KBD is not set +# BR2_PACKAGE_LCDPROC is not set + +# +# libiec61850 needs a toolchain w/ C++, threads, dynamic library +# +# BR2_PACKAGE_LIBUBOOTENV is not set +# BR2_PACKAGE_LIBUIO is not set +# BR2_PACKAGE_LINUX_BACKPORTS is not set +# BR2_PACKAGE_LINUX_SERIAL_TEST is not set +# BR2_PACKAGE_LINUXCONSOLETOOLS is not set + +# +# lirc-tools needs a toolchain w/ threads, dynamic library, C++ +# +# BR2_PACKAGE_LM_SENSORS is not set + +# +# lshw needs a toolchain w/ C++, wchar +# +# BR2_PACKAGE_LSSCSI is not set +# BR2_PACKAGE_LSUIO is not set +# BR2_PACKAGE_LUKSMETA is not set +# BR2_PACKAGE_LVM2 is not set +# BR2_PACKAGE_MBPFAN is not set +# BR2_PACKAGE_MDADM is not set +# BR2_PACKAGE_MDEVD is not set +# BR2_PACKAGE_MEMTESTER is not set +# BR2_PACKAGE_MEMTOOL is not set +# BR2_PACKAGE_MINICOM is not set +# BR2_PACKAGE_NANOCOM is not set +# BR2_PACKAGE_NEARD is not set +# BR2_PACKAGE_NVIDIA_MODPROBE is not set +# BR2_PACKAGE_NVME is not set +# BR2_PACKAGE_OFONO is not set +# BR2_PACKAGE_OPEN2300 is not set + +# +# openfpgaloader needs a toolchain w/ threads, C++, gcc >= 4.9 +# +# BR2_PACKAGE_OPENIPMI is not set +# BR2_PACKAGE_OPENOCD is not set +# BR2_PACKAGE_PARTED is not set +# BR2_PACKAGE_PCIUTILS is not set +# BR2_PACKAGE_PDBG is not set +# BR2_PACKAGE_PICOCOM is not set + +# +# powertop needs a toolchain w/ C++, threads, wchar +# +# BR2_PACKAGE_PPS_TOOLS is not set +# BR2_PACKAGE_RASPI_GPIO is not set +# BR2_PACKAGE_READ_EDID is not set +# BR2_PACKAGE_RNG_TOOLS is not set +# BR2_PACKAGE_RS485CONF is not set +# BR2_PACKAGE_RTC_TOOLS is not set +# BR2_PACKAGE_RTL8188EU is not set +# BR2_PACKAGE_RTL8189FS is not set +# BR2_PACKAGE_RTL8723BS is not set +# BR2_PACKAGE_RTL8723BU is not set +# BR2_PACKAGE_RTL8821AU is not set +# BR2_PACKAGE_SANE_BACKENDS is not set +# BR2_PACKAGE_SDPARM is not set +# BR2_PACKAGE_SETSERIAL is not set +# BR2_PACKAGE_SG3_UTILS is not set +# BR2_PACKAGE_SIGROK_CLI is not set +# BR2_PACKAGE_SISPMCTL is not set + +# +# smartmontools needs a toolchain w/ C++ +# +# BR2_PACKAGE_SMSTOOLS3 is not set +# BR2_PACKAGE_SPI_TOOLS is not set +# BR2_PACKAGE_SREDIRD is not set +# BR2_PACKAGE_STATSERIAL is not set +# BR2_PACKAGE_STM32FLASH is not set +# BR2_PACKAGE_SYSSTAT is not set + +# +# targetcli-fb depends on Python +# + +# +# ti-sgx-um needs the ti-sgx-km driver +# + +# +# ti-sgx-um needs udev and a glibc toolchain w/ threads +# +# BR2_PACKAGE_TI_UIM is not set +# BR2_PACKAGE_TI_UTILS is not set +# BR2_PACKAGE_TIO is not set +# BR2_PACKAGE_TRIGGERHAPPY is not set +# BR2_PACKAGE_UBOOT_TOOLS is not set +# BR2_PACKAGE_UBUS is not set +# BR2_PACKAGE_UCCP420WLAN is not set + +# +# udisks needs udev /dev management +# + +# +# udisks needs a glibc or musl toolchain with locale, C++, wchar, dynamic library, NPTL, gcc >= 4.9 +# +# BR2_PACKAGE_UHUBCTL is not set +# BR2_PACKAGE_UMTPRD is not set + +# +# upower needs udev /dev management +# +# BR2_PACKAGE_USB_MODESWITCH is not set +# BR2_PACKAGE_USB_MODESWITCH_DATA is not set + +# +# usbmount requires udev to be enabled +# + +# +# usbutils needs udev /dev management and toolchain w/ threads, gcc >= 4.9 +# +# BR2_PACKAGE_W_SCAN is not set +# BR2_PACKAGE_WIPE is not set +# BR2_PACKAGE_XORRISO is not set +# BR2_PACKAGE_XR819_XRADIO is not set + +# +# Interpreter languages and scripting +# +# BR2_PACKAGE_4TH is not set +# BR2_PACKAGE_ENSCRIPT is not set +BR2_PACKAGE_HOST_ERLANG_ARCH_SUPPORTS=y +# BR2_PACKAGE_EXECLINE is not set +# BR2_PACKAGE_FICL is not set +# BR2_PACKAGE_HASERL is not set +# BR2_PACKAGE_JANET is not set +# BR2_PACKAGE_JIMTCL is not set +# BR2_PACKAGE_LUA is not set +BR2_PACKAGE_PROVIDES_HOST_LUAINTERPRETER="host-lua" +# BR2_PACKAGE_MICROPYTHON is not set +BR2_PACKAGE_HOST_MONO_ARCH_SUPPORTS=y +BR2_PACKAGE_HOST_OPENJDK_BIN_ARCH_SUPPORTS=y +# BR2_PACKAGE_PERL is not set +# BR2_PACKAGE_PHP is not set +# BR2_PACKAGE_PYTHON is not set +# BR2_PACKAGE_PYTHON3 is not set +# BR2_PACKAGE_QUICKJS is not set +# BR2_PACKAGE_RUBY is not set +# BR2_PACKAGE_TCL is not set + +# +# Libraries +# + +# +# Audio/Sound +# +# BR2_PACKAGE_ALSA_LIB is not set + +# +# alure needs a toolchain w/ C++, gcc >= 4.9, NPTL, wchar +# +# BR2_PACKAGE_AUBIO is not set +# BR2_PACKAGE_BCG729 is not set + +# +# caps needs a toolchain w/ C++, dynamic library +# +# BR2_PACKAGE_LIBAO is not set + +# +# asplib needs a toolchain w/ C++ +# +# BR2_PACKAGE_LIBBROADVOICE is not set +# BR2_PACKAGE_LIBCDAUDIO is not set +# BR2_PACKAGE_LIBCDDB is not set +# BR2_PACKAGE_LIBCDIO is not set +# BR2_PACKAGE_LIBCDIO_PARANOIA is not set +# BR2_PACKAGE_LIBCODEC2 is not set +# BR2_PACKAGE_LIBCUE is not set +# BR2_PACKAGE_LIBCUEFILE is not set +# BR2_PACKAGE_LIBEBUR128 is not set +# BR2_PACKAGE_LIBG7221 is not set +# BR2_PACKAGE_LIBGSM is not set +# BR2_PACKAGE_LIBID3TAG is not set +# BR2_PACKAGE_LIBILBC is not set +# BR2_PACKAGE_LIBLO is not set +# BR2_PACKAGE_LIBMAD is not set + +# +# libmodplug needs a toolchain w/ C++ +# +# BR2_PACKAGE_LIBMPD is not set +# BR2_PACKAGE_LIBMPDCLIENT is not set +# BR2_PACKAGE_LIBREPLAYGAIN is not set +# BR2_PACKAGE_LIBSAMPLERATE is not set + +# +# libsidplay2 needs a toolchain w/ C++ +# +# BR2_PACKAGE_LIBSILK is not set +# BR2_PACKAGE_LIBSNDFILE is not set + +# +# libsoundtouch needs a toolchain w/ C++ +# +# BR2_PACKAGE_LIBSOXR is not set +# BR2_PACKAGE_LIBVORBIS is not set + +# +# mp4v2 needs a toolchain w/ C++ +# +BR2_PACKAGE_OPENAL_ARCH_SUPPORTS=y + +# +# openal needs a toolchain w/ NPTL, C++, gcc >= 4.9 +# + +# +# opencore-amr needs a toolchain w/ C++ +# +# BR2_PACKAGE_OPUS is not set +# BR2_PACKAGE_OPUSFILE is not set +# BR2_PACKAGE_PORTAUDIO is not set +# BR2_PACKAGE_SBC is not set +# BR2_PACKAGE_SPANDSP is not set +# BR2_PACKAGE_SPEEX is not set +# BR2_PACKAGE_SPEEXDSP is not set + +# +# taglib needs a toolchain w/ C++, wchar +# +# BR2_PACKAGE_TINYALSA is not set +# BR2_PACKAGE_TREMOR is not set +# BR2_PACKAGE_VO_AACENC is not set + +# +# Compression and decompression +# +# BR2_PACKAGE_LIBARCHIVE is not set +# BR2_PACKAGE_LIBMSPACK is not set + +# +# libsquish needs a toolchain w/ C++ +# +# BR2_PACKAGE_LIBZIP is not set +# BR2_PACKAGE_LZ4 is not set +# BR2_PACKAGE_LZO is not set +# BR2_PACKAGE_MINIZIP is not set + +# +# snappy needs a toolchain w/ C++ +# +# BR2_PACKAGE_SZIP is not set +# BR2_PACKAGE_ZLIB is not set +BR2_PACKAGE_PROVIDES_HOST_ZLIB="host-libzlib" +# BR2_PACKAGE_ZZIPLIB is not set + +# +# Crypto +# +# BR2_PACKAGE_BEARSSL is not set +# BR2_PACKAGE_BEECRYPT is not set +BR2_PACKAGE_BOTAN_ARCH_SUPPORTS=y + +# +# botan needs a toolchain w/ C++, threads, gcc >= 4.8 +# +# BR2_PACKAGE_CA_CERTIFICATES is not set +# BR2_PACKAGE_CRYPTODEV is not set +# BR2_PACKAGE_GCR is not set +# BR2_PACKAGE_GNUTLS is not set +# BR2_PACKAGE_LIBARGON2 is not set +# BR2_PACKAGE_LIBASSUAN is not set +# BR2_PACKAGE_LIBGCRYPT is not set +BR2_PACKAGE_LIBGPG_ERROR_ARCH_SUPPORTS=y +# BR2_PACKAGE_LIBGPG_ERROR is not set +BR2_PACKAGE_LIBGPG_ERROR_SYSCFG="riscv64-unknown-linux-gnu" +# BR2_PACKAGE_LIBGPGME is not set +# BR2_PACKAGE_LIBKCAPI is not set +# BR2_PACKAGE_LIBKSBA is not set +# BR2_PACKAGE_LIBMCRYPT is not set +# BR2_PACKAGE_LIBMHASH is not set +# BR2_PACKAGE_LIBNSS is not set + +# +# libolm needs a toolchain w/ C++, gcc >= 4.8 +# +# BR2_PACKAGE_LIBP11 is not set +# BR2_PACKAGE_LIBSCRYPT is not set +# BR2_PACKAGE_LIBSECRET is not set +# BR2_PACKAGE_LIBSHA1 is not set +# BR2_PACKAGE_LIBSODIUM is not set +# BR2_PACKAGE_LIBSSH is not set +# BR2_PACKAGE_LIBSSH2 is not set +# BR2_PACKAGE_LIBTOMCRYPT is not set +# BR2_PACKAGE_LIBUECC is not set +# BR2_PACKAGE_LIBXCRYPT is not set +# BR2_PACKAGE_MBEDTLS is not set +# BR2_PACKAGE_NETTLE is not set +# BR2_PACKAGE_OPENSSL is not set +BR2_PACKAGE_PROVIDES_HOST_OPENSSL="host-libopenssl" +# BR2_PACKAGE_PKCS11_HELPER is not set +# BR2_PACKAGE_RHASH is not set +# BR2_PACKAGE_TINYDTLS is not set +# BR2_PACKAGE_TPM2_PKCS11 is not set +# BR2_PACKAGE_TPM2_TSS is not set +# BR2_PACKAGE_TROUSERS is not set +# BR2_PACKAGE_USTREAM_SSL is not set +# BR2_PACKAGE_WOLFSSL is not set + +# +# Database +# +# BR2_PACKAGE_BERKELEYDB is not set +# BR2_PACKAGE_GDBM is not set +# BR2_PACKAGE_HIREDIS is not set + +# +# kompexsqlite needs a toolchain w/ C++, wchar, threads, dynamic library +# + +# +# leveldb needs a toolchain w/ C++, threads, gcc >= 4.8 +# +# BR2_PACKAGE_LIBGIT2 is not set +# BR2_PACKAGE_LIBMDBX is not set + +# +# libodb needs a toolchain w/ C++, threads +# + +# +# mysql needs a toolchain w/ C++, threads +# +# BR2_PACKAGE_POSTGRESQL is not set +# BR2_PACKAGE_REDIS is not set +# BR2_PACKAGE_SQLCIPHER is not set +# BR2_PACKAGE_SQLITE is not set +# BR2_PACKAGE_UNIXODBC is not set + +# +# Filesystem +# +# BR2_PACKAGE_GAMIN is not set +# BR2_PACKAGE_LIBCONFIG is not set +# BR2_PACKAGE_LIBCONFUSE is not set +# BR2_PACKAGE_LIBFUSE is not set +# BR2_PACKAGE_LIBFUSE3 is not set +# BR2_PACKAGE_LIBLOCKFILE is not set +# BR2_PACKAGE_LIBNFS is not set +# BR2_PACKAGE_LIBSYSFS is not set +# BR2_PACKAGE_LOCKDEV is not set + +# +# physfs needs a toolchain w/ C++, threads +# + +# +# Graphics +# + +# +# assimp needs libzlib +# + +# +# at-spi2-atk depends on X.org +# + +# +# at-spi2-core depends on X.org +# +# BR2_PACKAGE_ATK is not set + +# +# atkmm needs a toolchain w/ C++, wchar, threads, gcc >= 4.9 +# + +# +# bullet needs a toolchain w/ C++, dynamic library, threads, wchar +# +# BR2_PACKAGE_CAIRO is not set + +# +# cairomm needs a toolchain w/ C++, wchar, threads, gcc >= 4.8 +# + +# +# chipmunk needs an OpenGL backend +# + +# +# exempi needs a toolchain w/ C++, dynamic library, threads, wchar +# + +# +# exiv2 needs a uClibc or glibc toolchain w/ C++, wchar, dynamic library, threads +# +# BR2_PACKAGE_FONTCONFIG is not set +# BR2_PACKAGE_FREETYPE is not set +# BR2_PACKAGE_GD is not set +# BR2_PACKAGE_GDK_PIXBUF is not set +# BR2_PACKAGE_GIFLIB is not set + +# +# granite needs libgtk3 and a toolchain w/ wchar, threads +# + +# +# graphite2 needs a toolchain w/ C++ +# + +# +# gtkmm3 needs libgtk3 and a toolchain w/ C++, wchar, threads, gcc >= 4.9 +# + +# +# harfbuzz needs a toolchain w/ C++, gcc >= 4.8 +# +# BR2_PACKAGE_IJS is not set +# BR2_PACKAGE_IMLIB2 is not set + +# +# irrlicht needs a toolchain w/ C++ +# +# BR2_PACKAGE_JASPER is not set +# BR2_PACKAGE_JBIG2DEC is not set +# BR2_PACKAGE_JPEG is not set + +# +# kms++ needs a toolchain w/ threads, C++, gcc >= 4.8, headers >= 4.11, wchar +# +# BR2_PACKAGE_LCMS2 is not set + +# +# lensfun needs a toolchain w/ C++, threads, wchar +# +# BR2_PACKAGE_LEPTONICA is not set +# BR2_PACKAGE_LIBART is not set +# BR2_PACKAGE_LIBDMTX is not set +# BR2_PACKAGE_LIBDRM is not set + +# +# libepoxy needs an OpenGL and/or OpenGL EGL backend +# +# BR2_PACKAGE_LIBEXIF is not set + +# +# libfm needs X.org and a toolchain w/ wchar, threads, C++, gcc >= 4.8 +# +# BR2_PACKAGE_LIBFM_EXTRA is not set + +# +# libfreeglut depends on X.org and needs an OpenGL backend +# + +# +# libfreeimage needs a toolchain w/ C++, dynamic library, wchar +# + +# +# libgeotiff needs a toolchain w/ C++, gcc >= 4.7, threads, wchar +# + +# +# libglew depends on X.org and needs an OpenGL backend +# + +# +# libglfw depends on X.org and needs an OpenGL backend +# + +# +# libglu needs an OpenGL backend +# +# BR2_PACKAGE_LIBGTA is not set + +# +# libgtk3 needs a toolchain w/ wchar, threads, C++, gcc >= 4.8 +# + +# +# libgtk3 needs an OpenGL or an OpenGL-EGL/wayland backend +# +# BR2_PACKAGE_LIBMEDIAART is not set +# BR2_PACKAGE_LIBMNG is not set +# BR2_PACKAGE_LIBPNG is not set +# BR2_PACKAGE_LIBQRENCODE is not set + +# +# libraw needs a toolchain w/ C++ +# + +# +# libsoil needs an OpenGL backend and a toolchain w/ dynamic library +# +# BR2_PACKAGE_LIBSVG is not set +# BR2_PACKAGE_LIBSVG_CAIRO is not set +# BR2_PACKAGE_LIBSVGTINY is not set +# BR2_PACKAGE_LIBVA is not set + +# +# libvips needs a toolchain w/ wchar, threads, C++ +# + +# +# libwpe needs a toolchain w/ C++, dynamic library and an OpenEGL-capable backend +# +# BR2_PACKAGE_MENU_CACHE is not set + +# +# opencv3 needs a toolchain w/ C++, NPTL, wchar, dynamic library +# +# BR2_PACKAGE_OPENJPEG is not set + +# +# pango needs a toolchain w/ wchar, threads, C++, gcc >= 4.8 +# + +# +# pangomm needs a toolchain w/ C++, wchar, threads, gcc >= 4.9 +# +# BR2_PACKAGE_PIPEWIRE is not set +# BR2_PACKAGE_PIXMAN is not set + +# +# poppler needs a toolchain w/ wchar, C++, threads, dynamic library, gcc >= 5 +# +# BR2_PACKAGE_TIFF is not set +# BR2_PACKAGE_WAYLAND is not set +# BR2_PACKAGE_WEBP is not set + +# +# wlroots needs udev, EGL w/ Wayland backend and OpenGL ES support +# + +# +# woff2 needs a toolchain w/ C++ +# + +# +# wpebackend-fdo needs a toolchain w/ C++, wchar, threads, dynamic library and an OpenEGL-capable Wayland backend +# + +# +# zbar needs a toolchain w/ threads, C++ and headers >= 3.0 +# + +# +# zxing-cpp needs a toolchain w/ C++, dynamic library +# + +# +# Hardware handling +# +# BR2_PACKAGE_ACSCCID is not set +# BR2_PACKAGE_C_PERIPHERY is not set +# BR2_PACKAGE_CCID is not set +# BR2_PACKAGE_DTC is not set +# BR2_PACKAGE_HACKRF is not set + +# +# hidapi needs udev /dev management and a toolchain w/ NPTL, threads, gcc >= 4.9 +# +# BR2_PACKAGE_JITTERENTROPY_LIBRARY is not set + +# +# lcdapi needs a toolchain w/ C++, threads +# + +# +# let-me-create needs a toolchain w/ C++, threads, dynamic library +# +# BR2_PACKAGE_LIBAIO is not set + +# +# libatasmart requires udev to be enabled +# + +# +# libblockdev needs udev /dev management and a toolchain w/ wchar, threads, dynamic library +# + +# +# libcec needs a toolchain w/ C++, wchar, threads, dynamic library, gcc >= 4.7 +# +# BR2_PACKAGE_LIBFREEFARE is not set +# BR2_PACKAGE_LIBFTDI is not set +# BR2_PACKAGE_LIBFTDI1 is not set +# BR2_PACKAGE_LIBGPHOTO2 is not set +# BR2_PACKAGE_LIBGPIOD is not set + +# +# libgudev needs udev /dev handling and a toolchain w/ wchar, threads +# +# BR2_PACKAGE_LIBHID is not set +# BR2_PACKAGE_LIBIIO is not set + +# +# libinput needs udev /dev management +# +# BR2_PACKAGE_LIBIQRF is not set +# BR2_PACKAGE_LIBLLCP is not set +# BR2_PACKAGE_LIBMBIM is not set +# BR2_PACKAGE_LIBNFC is not set +# BR2_PACKAGE_LIBPCIACCESS is not set +# BR2_PACKAGE_LIBPHIDGET is not set +# BR2_PACKAGE_LIBPRI is not set +# BR2_PACKAGE_LIBQMI is not set +# BR2_PACKAGE_LIBQRTR_GLIB is not set +# BR2_PACKAGE_LIBRAW1394 is not set +# BR2_PACKAGE_LIBRTLSDR is not set + +# +# libserial needs a toolchain w/ C++, gcc >= 5, threads, wchar +# +# BR2_PACKAGE_LIBSERIALPORT is not set +# BR2_PACKAGE_LIBSIGROK is not set +# BR2_PACKAGE_LIBSIGROKDECODE is not set +# BR2_PACKAGE_LIBSOC is not set +# BR2_PACKAGE_LIBSS7 is not set +# BR2_PACKAGE_LIBUSB is not set +# BR2_PACKAGE_LIBUSBGX is not set + +# +# libv4l needs a toolchain w/ threads, C++ and headers >= 3.0 +# +# BR2_PACKAGE_LIBXKBCOMMON is not set +# BR2_PACKAGE_MTDEV is not set +# BR2_PACKAGE_NEARDAL is not set +# BR2_PACKAGE_OWFS is not set +# BR2_PACKAGE_PCSC_LITE is not set +# BR2_PACKAGE_TSLIB is not set + +# +# uhd needs a toolchain w/ C++, NPTL, wchar, dynamic library +# + +# +# urg needs a toolchain w/ C++ +# + +# +# Javascript +# +# BR2_PACKAGE_ANGULARJS is not set +# BR2_PACKAGE_BOOTSTRAP is not set +# BR2_PACKAGE_CHARTJS is not set +# BR2_PACKAGE_DATATABLES is not set +# BR2_PACKAGE_DUKTAPE is not set +# BR2_PACKAGE_EXPLORERCANVAS is not set +# BR2_PACKAGE_FLOT is not set +# BR2_PACKAGE_JQUERY is not set +# BR2_PACKAGE_JSMIN is not set +# BR2_PACKAGE_JSON_JAVASCRIPT is not set +# BR2_PACKAGE_JSZIP is not set +# BR2_PACKAGE_OPENLAYERS is not set +# BR2_PACKAGE_POPPERJS is not set +BR2_PACKAGE_SPIDERMONKEY_ARCH_SUPPORTS=y + +# +# spidermonkey needs a glibc or musl toolchain with C++, wchar, dynamic library, NPTL, gcc >= 4.9 +# +# BR2_PACKAGE_VUEJS is not set + +# +# JSON/XML +# + +# +# benejson needs a toolchain w/ C++ +# +# BR2_PACKAGE_CJSON is not set +# BR2_PACKAGE_EXPAT is not set +# BR2_PACKAGE_JANSSON is not set +# BR2_PACKAGE_JOSE is not set +# BR2_PACKAGE_JSMN is not set +# BR2_PACKAGE_JSON_C is not set + +# +# json-for-modern-cpp needs a toolchain w/ C++, gcc >= 4.9 +# +# BR2_PACKAGE_JSON_GLIB is not set + +# +# jsoncpp needs a toolchain w/ C++, gcc >= 4.7 +# +# BR2_PACKAGE_LIBBSON is not set +# BR2_PACKAGE_LIBFASTJSON is not set + +# +# libjson needs a toolchain w/ C++ +# +# BR2_PACKAGE_LIBROXML is not set +# BR2_PACKAGE_LIBUCL is not set +# BR2_PACKAGE_LIBXML2 is not set + +# +# libxml++ needs a toolchain w/ C++, wchar, threads, gcc >= 4.9 +# +# BR2_PACKAGE_LIBXMLRPC is not set +# BR2_PACKAGE_LIBXSLT is not set +# BR2_PACKAGE_LIBYAML is not set +# BR2_PACKAGE_MXML is not set + +# +# pugixml needs a toolchain w/ C++ +# + +# +# rapidjson needs a toolchain w/ C++ +# +# BR2_PACKAGE_RAPIDXML is not set +# BR2_PACKAGE_RAPTOR is not set + +# +# tinyxml needs a toolchain w/ C++ +# + +# +# tinyxml2 needs a toolchain w/ C++ +# + +# +# valijson needs a toolchain w/ C++, threads, wchar support +# + +# +# xerces-c++ needs a toolchain w/ C++, wchar +# +# BR2_PACKAGE_YAJL is not set + +# +# yaml-cpp needs a toolchain w/ C++, gcc >= 4.7 +# + +# +# Logging +# + +# +# glog needs a toolchain w/ C++ +# +# BR2_PACKAGE_LIBLOG4C_LOCALTIME is not set +# BR2_PACKAGE_LIBLOGGING is not set + +# +# log4cplus needs a toolchain w/ C++, wchar, threads, gcc >= 4.8 +# + +# +# log4cpp needs a toolchain w/ C++, threads +# + +# +# log4cxx needs a toolchain w/ C++, threads, dynamic library +# + +# +# log4qt needs qt5 +# + +# +# opentracing-cpp needs a toolchain w/ C++, threads, dynamic library, gcc >= 4.8 +# + +# +# spdlog needs a toolchain w/ C++, threads, wchar +# +# BR2_PACKAGE_ZLOG is not set + +# +# Multimedia +# +# BR2_PACKAGE_BITSTREAM is not set +# BR2_PACKAGE_DAV1D is not set + +# +# kvazaar needs a toolchain w/ C++, threads +# +# BR2_PACKAGE_LIBAACS is not set + +# +# libass needs a toolchain w/ C++, gcc >= 4.8 +# +# BR2_PACKAGE_LIBBDPLUS is not set +# BR2_PACKAGE_LIBBLURAY is not set +BR2_PACKAGE_LIBCAMERA_ARCH_SUPPORTS=y + +# +# libcamera needs a toolchain w/ C++, threads, wchar, dynamic library, gcc >= 7 +# +# BR2_PACKAGE_LIBDCADEC is not set +# BR2_PACKAGE_LIBDVBCSA is not set +# BR2_PACKAGE_LIBDVBPSI is not set + +# +# libdvbsi++ needs a toolchain w/ C++, wchar, threads +# +# BR2_PACKAGE_LIBDVDCSS is not set +# BR2_PACKAGE_LIBDVDNAV is not set +# BR2_PACKAGE_LIBDVDREAD is not set + +# +# libebml needs a toolchain w/ C++, wchar +# +# BR2_PACKAGE_LIBHDHOMERUN is not set + +# +# libmatroska needs a toolchain w/ C++, wchar +# +# BR2_PACKAGE_LIBMMS is not set +# BR2_PACKAGE_LIBMPEG2 is not set +# BR2_PACKAGE_LIBOGG is not set +# BR2_PACKAGE_LIBOPUSENC is not set +# BR2_PACKAGE_LIBTHEORA is not set +# BR2_PACKAGE_LIBUDFREAD is not set +# BR2_PACKAGE_LIBVPX is not set + +# +# libyuv needs a toolchain w/ C++, dynamic library +# + +# +# live555 needs a toolchain w/ C++ +# + +# +# mediastreamer needs a toolchain w/ threads, C++, dynamic library, gcc >= 5 +# +# BR2_PACKAGE_X264 is not set + +# +# x265 needs a toolchain w/ C++, threads, dynamic library +# + +# +# Networking +# + +# +# agent++ needs a toolchain w/ threads, C++, dynamic library +# + +# +# azmq needs a toolchain w/ C++11, wchar and NPTL +# + +# +# azure-iot-sdk-c needs a toolchain w/ C++, NPTL and wchar +# +# BR2_PACKAGE_BATMAN_ADV is not set + +# +# belle-sip needs a toolchain w/ threads, C++, dynamic library, wchar +# +# BR2_PACKAGE_C_ARES is not set +# BR2_PACKAGE_CGIC is not set + +# +# cppzmq needs a toolchain w/ C++, threads +# + +# +# curlpp needs a toolchain w/ C++, dynamic library +# + +# +# czmq needs a toolchain w/ C++, threads +# +# BR2_PACKAGE_DAQ is not set +# BR2_PACKAGE_DAVICI is not set +# BR2_PACKAGE_ENET is not set + +# +# filemq needs a toolchain w/ C++, threads +# +# BR2_PACKAGE_FLICKCURL is not set +# BR2_PACKAGE_FREERADIUS_CLIENT is not set +# BR2_PACKAGE_GENSIO is not set +# BR2_PACKAGE_GEOIP is not set +# BR2_PACKAGE_GLIB_NETWORKING is not set + +# +# grpc needs a toolchain w/ C++, threads, dynamic library, gcc >= 4.9, host gcc >= 4.9 +# +# BR2_PACKAGE_GSSDP is not set +# BR2_PACKAGE_GUPNP is not set +# BR2_PACKAGE_GUPNP_AV is not set +# BR2_PACKAGE_GUPNP_DLNA is not set + +# +# ibrcommon needs a toolchain w/ C++, threads +# + +# +# ibrdtn needs a toolchain w/ C++, threads +# +# BR2_PACKAGE_LIBCGI is not set + +# +# libcgicc needs a toolchain w/ C++ +# +# BR2_PACKAGE_LIBCOAP is not set + +# +# libcpprestsdk needs a toolchain w/ NPTL, C++, wchar, locale +# +# BR2_PACKAGE_LIBCURL is not set +# BR2_PACKAGE_LIBDNET is not set +# BR2_PACKAGE_LIBEXOSIP2 is not set +# BR2_PACKAGE_LIBFCGI is not set +# BR2_PACKAGE_LIBGSASL is not set +# BR2_PACKAGE_LIBHTP is not set +# BR2_PACKAGE_LIBHTTPPARSER is not set + +# +# libhttpserver needs a toolchain w/ C++, threads, gcc >= 5 +# +# BR2_PACKAGE_LIBIDN is not set +# BR2_PACKAGE_LIBIDN2 is not set +# BR2_PACKAGE_LIBISCSI is not set +# BR2_PACKAGE_LIBKRB5 is not set +# BR2_PACKAGE_LIBLDNS is not set +# BR2_PACKAGE_LIBMAXMINDDB is not set +# BR2_PACKAGE_LIBMBUS is not set + +# +# libmemcached needs a toolchain w/ C++, threads +# +# BR2_PACKAGE_LIBMICROHTTPD is not set +# BR2_PACKAGE_LIBMINIUPNPC is not set +# BR2_PACKAGE_LIBMNL is not set +# BR2_PACKAGE_LIBMODBUS is not set + +# +# libmodsecurity needs a toolchain w/ C++, dynamic library, threads +# +# BR2_PACKAGE_LIBNATPMP is not set +# BR2_PACKAGE_LIBNDP is not set +# BR2_PACKAGE_LIBNET is not set +# BR2_PACKAGE_LIBNETCONF2 is not set +# BR2_PACKAGE_LIBNETFILTER_ACCT is not set +# BR2_PACKAGE_LIBNETFILTER_CONNTRACK is not set +# BR2_PACKAGE_LIBNETFILTER_CTHELPER is not set +# BR2_PACKAGE_LIBNETFILTER_CTTIMEOUT is not set +# BR2_PACKAGE_LIBNETFILTER_LOG is not set +# BR2_PACKAGE_LIBNETFILTER_QUEUE is not set +# BR2_PACKAGE_LIBNFNETLINK is not set +# BR2_PACKAGE_LIBNFTNL is not set +# BR2_PACKAGE_LIBNICE is not set +# BR2_PACKAGE_LIBNIDS is not set +# BR2_PACKAGE_LIBNL is not set + +# +# libnpupnp needs a toolchain w/ C++, threads, gcc >= 4.9 +# +# BR2_PACKAGE_LIBOAUTH is not set +# BR2_PACKAGE_LIBOPING is not set +# BR2_PACKAGE_LIBOSIP2 is not set +# BR2_PACKAGE_LIBPAGEKITE is not set +# BR2_PACKAGE_LIBPCAP is not set + +# +# libpjsip needs a toolchain w/ C++, threads +# +# BR2_PACKAGE_LIBRELP is not set +# BR2_PACKAGE_LIBRSYNC is not set +# BR2_PACKAGE_LIBSHAIRPLAY is not set +# BR2_PACKAGE_LIBSHOUT is not set +# BR2_PACKAGE_LIBSOCKETCAN is not set +# BR2_PACKAGE_LIBSOUP is not set +# BR2_PACKAGE_LIBSRTP is not set +# BR2_PACKAGE_LIBSTROPHE is not set +# BR2_PACKAGE_LIBTELNET is not set +# BR2_PACKAGE_LIBTIRPC is not set + +# +# libtorrent needs a toolchain w/ C++, threads +# + +# +# libtorrent-rasterbar needs a toolchain w/ C++, threads, wchar, gcc >= 4.9 +# +# BR2_PACKAGE_LIBUEV is not set +# BR2_PACKAGE_LIBUHTTPD is not set +# BR2_PACKAGE_LIBUPNP is not set + +# +# libupnpp needs a toolchain w/ C++, threads, gcc >= 4.9 +# +# BR2_PACKAGE_LIBURIPARSER is not set +# BR2_PACKAGE_LIBUWSC is not set +# BR2_PACKAGE_LIBVNCSERVER is not set +# BR2_PACKAGE_LIBWEBSOCK is not set +# BR2_PACKAGE_LIBWEBSOCKETS is not set +# BR2_PACKAGE_LIBYANG is not set +# BR2_PACKAGE_LKSCTP_TOOLS is not set +# BR2_PACKAGE_MBUFFER is not set +# BR2_PACKAGE_MONGOOSE is not set +# BR2_PACKAGE_NANOMSG is not set +# BR2_PACKAGE_NEON is not set + +# +# netopeer2 needs a toolchain w/ gcc >= 4.8, C++, threads, dynamic library +# +# BR2_PACKAGE_NGHTTP2 is not set + +# +# norm needs a toolchain w/ C++, threads, dynamic library +# +# BR2_PACKAGE_NSS_MYHOSTNAME is not set +# BR2_PACKAGE_NSS_PAM_LDAPD is not set + +# +# omniORB needs a toolchain w/ C++, threads +# +# BR2_PACKAGE_OPEN62541 is not set +# BR2_PACKAGE_OPENLDAP is not set + +# +# openmpi needs a toolchain w/ dynamic library, NPTL, wchar, C++ +# +# BR2_PACKAGE_OPENPGM is not set + +# +# openzwave needs a toolchain w/ C++, dynamic library, NPTL, wchar +# + +# +# ortp needs a toolchain w/ C++, threads +# +# BR2_PACKAGE_PAHO_MQTT_C is not set + +# +# paho-mqtt-cpp needs a toolchain w/ threads, C++ +# + +# +# pistache needs a glibc toolchain w/ C++, gcc >= 4.9, threads, wchar +# +# BR2_PACKAGE_QDECODER is not set +# BR2_PACKAGE_QPID_PROTON is not set +# BR2_PACKAGE_RABBITMQ_C is not set + +# +# resiprocate needs a toolchain w/ C++, threads, wchar +# + +# +# restclient-cpp needs a toolchain w/ C++, gcc >= 4.8 +# +# BR2_PACKAGE_RTMPDUMP is not set +# BR2_PACKAGE_SIPROXD is not set +# BR2_PACKAGE_SLIRP is not set + +# +# snmp++ needs a toolchain w/ threads, C++, dynamic library +# +# BR2_PACKAGE_SOFIA_SIP is not set + +# +# sysrepo needs a toolchain w/ C++, NPTL, dynamic library, gcc >= 4.8 +# + +# +# thrift needs a toolchain w/ C++, wchar, threads +# +# BR2_PACKAGE_USBREDIR is not set + +# +# wampcc needs a toolchain w/ C++, NPTL, dynamic library +# + +# +# websocketpp needs a toolchain w/ C++ and gcc >= 4.8 +# + +# +# zeromq needs a toolchain w/ C++, threads +# + +# +# zmqpp needs a toolchain w/ C++, threads, gcc >= 4.7 +# + +# +# zyre needs a toolchain w/ C++, threads +# + +# +# Other +# +# BR2_PACKAGE_APR is not set +# BR2_PACKAGE_APR_UTIL is not set + +# +# armadillo needs a toolchain w/ C++ +# + +# +# atf needs a toolchain w/ C++ +# +# BR2_PACKAGE_AVRO_C is not set + +# +# bctoolbox needs a toolchain w/ C++, threads +# + +# +# belr needs a toolchain w/ threads, C++ +# + +# +# boost needs a toolchain w/ C++, threads, wchar +# + +# +# c-capnproto needs host and target gcc >= 5 w/ C++14, threads, atomic, ucontext and not gcc bug 64735 +# + +# +# capnproto needs host and target gcc >= 5 w/ C++14, threads, atomic, ucontext and not gcc bug 64735 +# + +# +# cctz needs a toolchain w/ C++, threads, gcc >= 4.8 +# + +# +# cereal needs a toolchain w/ C++, gcc >= 4.7, threads, wchar +# +# BR2_PACKAGE_CLAPACK is not set +# BR2_PACKAGE_CMOCKA is not set + +# +# cppcms needs a toolchain w/ C++, NPTL, wchar, dynamic library +# +# BR2_PACKAGE_CRACKLIB is not set + +# +# dawgdic needs a toolchain w/ C++, gcc >= 4.6 +# +# BR2_PACKAGE_DING_LIBS is not set + +# +# eigen needs a toolchain w/ C++ +# +# BR2_PACKAGE_ELFUTILS is not set +# BR2_PACKAGE_ELL is not set +# BR2_PACKAGE_FFTW is not set + +# +# flann needs a toolchain w/ C++, dynamic library +# + +# +# flatbuffers needs a toolchain w/ C++, gcc >= 4.7 +# +# BR2_PACKAGE_FLATCC is not set +# BR2_PACKAGE_GCONF is not set + +# +# gflags needs a toolchain w/ C++ +# + +# +# gli needs a toolchain w/ C++ +# + +# +# glibmm needs a toolchain w/ C++, wchar, threads, gcc >= 4.9 +# + +# +# glm needs a toolchain w/ C++ +# +# BR2_PACKAGE_GMP is not set +BR2_PACKAGE_GOBJECT_INTROSPECTION_ARCH_SUPPORTS=y + +# +# gobject-introspection needs python3 +# +# BR2_PACKAGE_GSL is not set + +# +# gtest needs a toolchain w/ C++, wchar, threads +# +BR2_PACKAGE_JEMALLOC_ARCH_SUPPORTS=y +# BR2_PACKAGE_JEMALLOC is not set + +# +# lapack/blas needs a toolchain w/ fortran +# +BR2_PACKAGE_LIBABSEIL_CPP_ARCH_SUPPORTS=y + +# +# libabseil-cpp needs a toolchain w/ gcc >= 4.9, C++, threads, dynamic library +# +# BR2_PACKAGE_LIBARGTABLE2 is not set +# BR2_PACKAGE_LIBAVL is not set +# BR2_PACKAGE_LIBB64 is not set +# BR2_PACKAGE_LIBBACKTRACE is not set +BR2_PACKAGE_LIBBSD_ARCH_SUPPORTS=y +# BR2_PACKAGE_LIBBSD is not set +# BR2_PACKAGE_LIBBYTESIZE is not set +# BR2_PACKAGE_LIBCAP is not set +# BR2_PACKAGE_LIBCAP_NG is not set + +# +# libcgroup needs a glibc toolchain w/ C++ +# +# BR2_PACKAGE_LIBCORRECT is not set + +# +# libcrossguid needs a toolchain w/ C++, gcc >= 4.7 +# +# BR2_PACKAGE_LIBCSV is not set +# BR2_PACKAGE_LIBDAEMON is not set +# BR2_PACKAGE_LIBEE is not set +# BR2_PACKAGE_LIBEV is not set +# BR2_PACKAGE_LIBEVDEV is not set +# BR2_PACKAGE_LIBEVENT is not set +# BR2_PACKAGE_LIBFFI is not set +# BR2_PACKAGE_LIBGEE is not set + +# +# libgeos needs a toolchain w/ C++, wchar, not binutils bug 21464, 27597 +# +# BR2_PACKAGE_LIBGLIB2 is not set +# BR2_PACKAGE_LIBGLOB is not set + +# +# libical needs a toolchain w/ C++, dynamic library, wchar +# +# BR2_PACKAGE_LIBITE is not set + +# +# liblinear needs a toolchain w/ C++ +# + +# +# libloki needs a toolchain w/ C++, threads +# +# BR2_PACKAGE_LIBNPTH is not set +BR2_PACKAGE_LIBNSPR_ARCH_SUPPORT=y +# BR2_PACKAGE_LIBNSPR is not set +# BR2_PACKAGE_LIBPFM4 is not set + +# +# libplist needs a toolchain w/ C++, threads +# +# BR2_PACKAGE_LIBPTHREAD_STUBS is not set +# BR2_PACKAGE_LIBPTHSEM is not set +# BR2_PACKAGE_LIBPWQUALITY is not set + +# +# libsigc++ needs a toolchain w/ C++, gcc >= 4.8 +# +BR2_PACKAGE_LIBSIGSEGV_ARCH_SUPPORTS=y +# BR2_PACKAGE_LIBSIGSEGV is not set + +# +# libspatialindex needs a toolchain w/ C++, gcc >= 4.7 +# +# BR2_PACKAGE_LIBTASN1 is not set +# BR2_PACKAGE_LIBTOMMATH is not set +# BR2_PACKAGE_LIBTPL is not set +# BR2_PACKAGE_LIBUBOX is not set +# BR2_PACKAGE_LIBUCI is not set +BR2_PACKAGE_LIBURCU_ARCH_SUPPORTS=y +# BR2_PACKAGE_LIBURCU is not set +# BR2_PACKAGE_LIBUV is not set +# BR2_PACKAGE_LIGHTNING is not set +# BR2_PACKAGE_LINUX_PAM is not set +# BR2_PACKAGE_LIQUID_DSP is not set +# BR2_PACKAGE_LTTNG_LIBUST is not set +# BR2_PACKAGE_MATIO is not set +# BR2_PACKAGE_MPC is not set +# BR2_PACKAGE_MPDECIMAL is not set +# BR2_PACKAGE_MPFR is not set +# BR2_PACKAGE_MPIR is not set + +# +# msgpack needs a toolchain w/ C++ +# +# BR2_PACKAGE_ORC is not set +# BR2_PACKAGE_P11_KIT is not set +BR2_PACKAGE_POCO_ARCH_SUPPORTS=y + +# +# poco needs a toolchain w/ wchar, NPTL, C++, dynamic library, gcc >= 5 w/ C++14 +# +BR2_PACKAGE_PROTOBUF_ARCH_SUPPORTS=y + +# +# protobuf needs a toolchain w/ C++, threads, dynamic library, gcc >= 4.8 +# + +# +# protobuf-c needs a toolchain w/ C++, threads +# + +# +# protozero needs a toolchain w/ C++, gcc >= 4.7 +# + +# +# qhull needs a toolchain w/ C++, gcc >= 4.4 +# +# BR2_PACKAGE_QLIBC is not set + +# +# riemann-c-client needs a toolchain w/ C++, threads +# + +# +# shapelib needs a toolchain w/ C++, threads +# +# BR2_PACKAGE_SKALIBS is not set +# BR2_PACKAGE_SPHINXBASE is not set +# BR2_PACKAGE_TINYCBOR is not set + +# +# uvw needs a toolchain w/ NPTL, dynamic library, C++, gcc >= 7 +# + +# +# xapian needs a toolchain w/ C++ +# + +# +# Security +# +# BR2_PACKAGE_LIBAPPARMOR is not set +# BR2_PACKAGE_LIBSELINUX is not set +# BR2_PACKAGE_LIBSEPOL is not set +# BR2_PACKAGE_SAFECLIB is not set + +# +# Text and terminal handling +# +# BR2_PACKAGE_AUGEAS is not set + +# +# enchant needs a toolchain w/ C++, threads, wchar +# + +# +# fmt needs a toolchain w/ C++, wchar +# +# BR2_PACKAGE_FSTRCMP is not set + +# +# icu needs a toolchain w/ C++, wchar, threads, gcc >= 4.9, host gcc >= 4.9 +# +# BR2_PACKAGE_INIH is not set +# BR2_PACKAGE_LIBCLI is not set +# BR2_PACKAGE_LIBEDIT is not set +# BR2_PACKAGE_LIBENCA is not set +# BR2_PACKAGE_LIBESTR is not set +# BR2_PACKAGE_LIBFRIBIDI is not set +# BR2_PACKAGE_LIBUNISTRING is not set +# BR2_PACKAGE_LINENOISE is not set +# BR2_PACKAGE_NCURSES is not set +# BR2_PACKAGE_NEWT is not set +# BR2_PACKAGE_ONIGURUMA is not set +# BR2_PACKAGE_PCRE is not set +# BR2_PACKAGE_PCRE2 is not set +# BR2_PACKAGE_POPT is not set + +# +# re2 needs a toolchain w/ C++, threads, gcc >= 4.8 +# +# BR2_PACKAGE_READLINE is not set +# BR2_PACKAGE_SLANG is not set + +# +# tclap needs a toolchain w/ C++ +# +# BR2_PACKAGE_UTF8PROC is not set + +# +# Mail +# +# BR2_PACKAGE_DOVECOT is not set +# BR2_PACKAGE_EXIM is not set +# BR2_PACKAGE_FETCHMAIL is not set +# BR2_PACKAGE_HEIRLOOM_MAILX is not set +# BR2_PACKAGE_LIBESMTP is not set +# BR2_PACKAGE_MSMTP is not set +# BR2_PACKAGE_MUTT is not set + +# +# Miscellaneous +# +# BR2_PACKAGE_AESPIPE is not set +# BR2_PACKAGE_BC is not set +BR2_PACKAGE_BITCOIN_ARCH_SUPPORTS=y + +# +# bitcoin needs a toolchain w/ C++, threads, wchar +# + +# +# clamav needs a toolchain w/ C++, dynamic library, threads, wchar +# +# BR2_PACKAGE_COLLECTD is not set +# BR2_PACKAGE_COLLECTL is not set + +# +# domoticz needs lua 5.3 and a toolchain w/ C++, gcc >= 6, NPTL, wchar, dynamic library +# +# BR2_PACKAGE_EMPTY is not set + +# +# gnuradio needs a toolchain w/ C++, NPTL, wchar, dynamic library +# +# BR2_PACKAGE_GOOGLEFONTDIRECTORY is not set + +# +# gqrx needs a toolchain w/ C++, threads, wchar, dynamic library +# + +# +# gqrx needs qt5 +# +# BR2_PACKAGE_GSETTINGS_DESKTOP_SCHEMAS is not set +# BR2_PACKAGE_HAVEGED is not set +# BR2_PACKAGE_LINUX_SYSCALL_SUPPORT is not set +# BR2_PACKAGE_MCRYPT is not set +# BR2_PACKAGE_MOBILE_BROADBAND_PROVIDER_INFO is not set +# BR2_PACKAGE_NETDATA is not set + +# +# proj needs a toolchain w/ C++, gcc >= 4.7, threads, wchar +# + +# +# qpdf needs a toolchain w/ C++, wchar, gcc >= 4.7 +# +# BR2_PACKAGE_SHARED_MIME_INFO is not set + +# +# sunwait needs a toolchain w/ C++ +# + +# +# taskd needs a toolchain w/ C++, wchar, dynamic library +# +# BR2_PACKAGE_XUTIL_UTIL_MACROS is not set + +# +# Networking applications +# + +# +# aircrack-ng needs a toolchain w/ dynamic library, threads, C++ +# +# BR2_PACKAGE_AOETOOLS is not set +# BR2_PACKAGE_APACHE is not set +# BR2_PACKAGE_ARGUS is not set +# BR2_PACKAGE_ARP_SCAN is not set +# BR2_PACKAGE_ARPTABLES is not set + +# +# asterisk needs a glibc or uClibc toolchain w/ C++, dynamic library, threads, wchar +# +# BR2_PACKAGE_ATFTP is not set +# BR2_PACKAGE_AVAHI is not set +# BR2_PACKAGE_AXEL is not set +# BR2_PACKAGE_BABELD is not set +# BR2_PACKAGE_BANDWIDTHD is not set +# BR2_PACKAGE_BATCTL is not set + +# +# bcusdk needs a toolchain w/ C++ +# +# BR2_PACKAGE_BIND is not set +# BR2_PACKAGE_BIRD is not set +# BR2_PACKAGE_BLUEZ5_UTILS is not set +# BR2_PACKAGE_BMON is not set + +# +# boinc needs a toolchain w/ dynamic library, C++, threads +# +# BR2_PACKAGE_BRCM_PATCHRAM_PLUS is not set +# BR2_PACKAGE_BRIDGE_UTILS is not set +# BR2_PACKAGE_BWM_NG is not set +# BR2_PACKAGE_C_ICAP is not set +# BR2_PACKAGE_CAN_UTILS is not set + +# +# cannelloni needs a toolchain w/ C++, threads, dynamic library, gcc >= 4.8 +# +# BR2_PACKAGE_CASYNC is not set +# BR2_PACKAGE_CHRONY is not set +# BR2_PACKAGE_CIVETWEB is not set +# BR2_PACKAGE_CONNMAN is not set + +# +# connman-gtk needs libgtk3 and a glibc or uClibc toolchain w/ wchar, threads, resolver, dynamic library +# +# BR2_PACKAGE_CONNTRACK_TOOLS is not set +# BR2_PACKAGE_CORKSCREW is not set +# BR2_PACKAGE_CRDA is not set + +# +# ctorrent needs a toolchain w/ C++ +# + +# +# cups needs a toolchain w/ C++, threads +# + +# +# cups-filters needs a toolchain w/ wchar, C++, threads and dynamic library, gcc >= 4.8 +# +# BR2_PACKAGE_DANTE is not set +# BR2_PACKAGE_DARKHTTPD is not set +# BR2_PACKAGE_DEHYDRATED is not set +# BR2_PACKAGE_DHCPCD is not set +# BR2_PACKAGE_DHCPDUMP is not set +# BR2_PACKAGE_DNSMASQ is not set +# BR2_PACKAGE_DRBD_UTILS is not set +# BR2_PACKAGE_DROPBEAR is not set +# BR2_PACKAGE_EASYFRAMES is not set +# BR2_PACKAGE_EBTABLES is not set + +# +# ejabberd needs erlang, toolchain w/ C++ +# +# BR2_PACKAGE_ETHTOOL is not set +# BR2_PACKAGE_FAIFA is not set +# BR2_PACKAGE_FASTD is not set +# BR2_PACKAGE_FCGIWRAP is not set +# BR2_PACKAGE_FPING is not set + +# +# freeswitch needs a toolchain w/ C++, dynamic library, threads, wchar +# +# BR2_PACKAGE_FRR is not set + +# +# gerbera needs a toolchain w/ C++, dynamic library, threads, wchar, gcc >= 8 +# +# BR2_PACKAGE_GESFTPSERVER is not set + +# +# gloox needs a toolchain w/ C++ +# +# BR2_PACKAGE_GLORYTUN is not set + +# +# gupnp-tools needs libgtk3 +# + +# +# hans needs a toolchain w/ C++ +# +BR2_PACKAGE_HAPROXY_ARCH_SUPPORTS=y +# BR2_PACKAGE_HAPROXY is not set +# BR2_PACKAGE_HIAWATHA is not set +# BR2_PACKAGE_HOSTAPD is not set +# BR2_PACKAGE_HTPDATE is not set +# BR2_PACKAGE_HTTPING is not set + +# +# i2pd needs a toolchain w/ C++, NPTL, wchar +# + +# +# ibrdtn-tools needs a toolchain w/ C++, threads +# + +# +# ibrdtnd needs a toolchain w/ C++, threads +# +# BR2_PACKAGE_IFMETRIC is not set +# BR2_PACKAGE_IFTOP is not set +# BR2_PACKAGE_IFUPDOWN_SCRIPTS is not set +# BR2_PACKAGE_IGD2_FOR_LINUX is not set +# BR2_PACKAGE_IGH_ETHERCAT is not set +# BR2_PACKAGE_IGMPPROXY is not set +# BR2_PACKAGE_INADYN is not set +# BR2_PACKAGE_IODINE is not set + +# +# iperf needs a toolchain w/ C++ +# +# BR2_PACKAGE_IPERF3 is not set +# BR2_PACKAGE_IPROUTE2 is not set +# BR2_PACKAGE_IPSET is not set +# BR2_PACKAGE_IPTABLES is not set +# BR2_PACKAGE_IPTRAF_NG is not set +# BR2_PACKAGE_IPUTILS is not set +# BR2_PACKAGE_IRSSI is not set +# BR2_PACKAGE_IW is not set +# BR2_PACKAGE_IWD is not set +# BR2_PACKAGE_JANUS_GATEWAY is not set +# BR2_PACKAGE_KEEPALIVED is not set + +# +# kismet needs a toolchain w/ threads, C++ +# +# BR2_PACKAGE_KNOCK is not set +# BR2_PACKAGE_LEAFNODE2 is not set +# BR2_PACKAGE_LFT is not set + +# +# lftp requires a toolchain w/ C++, wchar +# +# BR2_PACKAGE_LIGHTTPD is not set + +# +# linknx needs a toolchain w/ C++ +# +# BR2_PACKAGE_LINKS is not set + +# +# linphone needs a toolchain w/ threads, C++, dynamic library, wchar, gcc >= 5 +# +# BR2_PACKAGE_LINUX_ZIGBEE is not set +# BR2_PACKAGE_LINUXPTP is not set +# BR2_PACKAGE_LLDPD is not set +# BR2_PACKAGE_LRZSZ is not set +# BR2_PACKAGE_LYNX is not set +# BR2_PACKAGE_MACCHANGER is not set +# BR2_PACKAGE_MEMCACHED is not set +# BR2_PACKAGE_MII_DIAG is not set +# BR2_PACKAGE_MINI_SNMPD is not set +# BR2_PACKAGE_MINIDLNA is not set +# BR2_PACKAGE_MINISSDPD is not set +# BR2_PACKAGE_MJPG_STREAMER is not set +# BR2_PACKAGE_MODEM_MANAGER is not set +BR2_PACKAGE_MONGREL2_LIBC_SUPPORTS=y + +# +# mongrel2 needs a uClibc or glibc toolchain w/ C++, threads, dynamic library +# + +# +# mosh needs a toolchain w/ C++, threads, dynamic library, wchar, gcc >= 4.8 +# +# BR2_PACKAGE_MOSQUITTO is not set +# BR2_PACKAGE_MROUTED is not set +# BR2_PACKAGE_MRP is not set +# BR2_PACKAGE_MTR is not set +# BR2_PACKAGE_NBD is not set +# BR2_PACKAGE_NCFTP is not set +# BR2_PACKAGE_NDISC6 is not set +# BR2_PACKAGE_NETATALK is not set +# BR2_PACKAGE_NETCALC is not set +# BR2_PACKAGE_NETPLUG is not set +# BR2_PACKAGE_NETSNMP is not set +# BR2_PACKAGE_NETSTAT_NAT is not set + +# +# NetworkManager needs udev /dev management and a glibc toolchain w/ headers >= 3.2, dynamic library, wchar, threads +# +# BR2_PACKAGE_NFACCT is not set +# BR2_PACKAGE_NFTABLES is not set +# BR2_PACKAGE_NGINX is not set +# BR2_PACKAGE_NGIRCD is not set +# BR2_PACKAGE_NGREP is not set + +# +# nload needs a toolchain w/ C++ +# + +# +# nmap-nmap needs a toolchain w/ C++, threads +# +# BR2_PACKAGE_NOIP is not set +# BR2_PACKAGE_NTP is not set +# BR2_PACKAGE_NUTTCP is not set +# BR2_PACKAGE_ODHCP6C is not set +# BR2_PACKAGE_ODHCPLOC is not set +# BR2_PACKAGE_OLSR is not set +# BR2_PACKAGE_OPEN_LLDP is not set +# BR2_PACKAGE_OPEN_PLC_UTILS is not set +# BR2_PACKAGE_OPENNTPD is not set +# BR2_PACKAGE_OPENOBEX is not set +# BR2_PACKAGE_OPENRESOLV is not set +# BR2_PACKAGE_OPENSSH is not set +# BR2_PACKAGE_OPENSWAN is not set +# BR2_PACKAGE_OPENVPN is not set +# BR2_PACKAGE_P910ND is not set +# BR2_PACKAGE_PARPROUTED is not set +# BR2_PACKAGE_PHIDGETWEBSERVICE is not set +# BR2_PACKAGE_PHYTOOL is not set +# BR2_PACKAGE_PIMD is not set +# BR2_PACKAGE_PIXIEWPS is not set +# BR2_PACKAGE_POUND is not set +# BR2_PACKAGE_PPPD is not set +# BR2_PACKAGE_PPTP_LINUX is not set +# BR2_PACKAGE_PRIVOXY is not set +# BR2_PACKAGE_PROFTPD is not set + +# +# prosody needs the lua interpreter, dynamic library +# +# BR2_PACKAGE_PROXYCHAINS_NG is not set +# BR2_PACKAGE_PTPD is not set +# BR2_PACKAGE_PTPD2 is not set +# BR2_PACKAGE_PURE_FTPD is not set +# BR2_PACKAGE_PUTTY is not set +# BR2_PACKAGE_QUAGGA is not set + +# +# rabbitmq-server needs erlang +# +# BR2_PACKAGE_RADVD is not set +# BR2_PACKAGE_REAVER is not set +# BR2_PACKAGE_REDIR is not set +# BR2_PACKAGE_RP_PPPOE is not set +# BR2_PACKAGE_RPCBIND is not set +# BR2_PACKAGE_RSH_REDONE is not set +# BR2_PACKAGE_RSYNC is not set + +# +# rtorrent needs a toolchain w/ C++, threads, wchar, gcc >= 4.9 +# +# BR2_PACKAGE_RTPTOOLS is not set +# BR2_PACKAGE_RYGEL is not set +# BR2_PACKAGE_S6_DNS is not set +# BR2_PACKAGE_S6_NETWORKING is not set +# BR2_PACKAGE_SAMBA4 is not set + +# +# sconeserver needs a toolchain with dynamic library, C++, NPTL +# +# BR2_PACKAGE_SER2NET is not set +# BR2_PACKAGE_SHADOWSOCKS_LIBEV is not set + +# +# shairport-sync needs a toolchain w/ C++, NPTL +# +# BR2_PACKAGE_SHELLINABOX is not set +# BR2_PACKAGE_SMCROUTE is not set +# BR2_PACKAGE_SNGREP is not set +# BR2_PACKAGE_SNORT is not set +# BR2_PACKAGE_SOCAT is not set +# BR2_PACKAGE_SOCKETCAND is not set +# BR2_PACKAGE_SOFTETHER is not set +# BR2_PACKAGE_SPAWN_FCGI is not set +# BR2_PACKAGE_SPICE_PROTOCOL is not set + +# +# squid needs a toolchain w/ C++, gcc >= 4.8 not affected by bug 64735 +# +# BR2_PACKAGE_SSDP_RESPONDER is not set +# BR2_PACKAGE_SSHGUARD is not set +# BR2_PACKAGE_SSHPASS is not set +# BR2_PACKAGE_SSLH is not set +# BR2_PACKAGE_STRONGSWAN is not set +# BR2_PACKAGE_STUNNEL is not set +# BR2_PACKAGE_TCPDUMP is not set +# BR2_PACKAGE_TCPING is not set +# BR2_PACKAGE_TCPREPLAY is not set +# BR2_PACKAGE_THTTPD is not set +# BR2_PACKAGE_TINC is not set +# BR2_PACKAGE_TINYPROXY is not set +# BR2_PACKAGE_TINYSSH is not set +# BR2_PACKAGE_TOR is not set +# BR2_PACKAGE_TRACEROUTE is not set +# BR2_PACKAGE_TRANSMISSION is not set +# BR2_PACKAGE_TUNCTL is not set +# BR2_PACKAGE_TVHEADEND is not set +# BR2_PACKAGE_UACME is not set +# BR2_PACKAGE_UDPCAST is not set +# BR2_PACKAGE_UFTP is not set +# BR2_PACKAGE_UHTTPD is not set +# BR2_PACKAGE_ULOGD is not set +# BR2_PACKAGE_UNBOUND is not set +# BR2_PACKAGE_UREDIR is not set +# BR2_PACKAGE_USHARE is not set +# BR2_PACKAGE_USSP_PUSH is not set +# BR2_PACKAGE_VDE2 is not set + +# +# vdr needs a glibc toolchain w/ C++, dynamic library, NPTL, wchar, headers >= 3.9 +# +# BR2_PACKAGE_VNSTAT is not set +# BR2_PACKAGE_VPNC is not set +# BR2_PACKAGE_VSFTPD is not set +# BR2_PACKAGE_VTUN is not set +# BR2_PACKAGE_WAVEMON is not set +# BR2_PACKAGE_WIREGUARD_TOOLS is not set +# BR2_PACKAGE_WIRELESS_REGDB is not set +# BR2_PACKAGE_WIRELESS_TOOLS is not set +# BR2_PACKAGE_WIRESHARK is not set +# BR2_PACKAGE_WPA_SUPPLICANT is not set +# BR2_PACKAGE_WPAN_TOOLS is not set +# BR2_PACKAGE_XINETD is not set +# BR2_PACKAGE_XL2TP is not set +# BR2_PACKAGE_XTABLES_ADDONS is not set + +# +# znc needs a toolchain w/ C++, dynamic library, gcc >= 4.8, threads +# + +# +# Package managers +# + +# +# ------------------------------------------------------- +# + +# +# Please note: +# + +# +# - Buildroot does *not* generate binary packages, +# + +# +# - Buildroot does *not* install any package database. +# + +# +# * +# + +# +# It is up to you to provide those by yourself if you +# + +# +# want to use any of those package managers. +# + +# +# * +# + +# +# See the manual: +# + +# +# http://buildroot.org/manual.html#faq-no-binary-packages +# + +# +# ------------------------------------------------------- +# +# BR2_PACKAGE_OPKG is not set +# BR2_PACKAGE_OPKG_UTILS is not set + +# +# Real-Time +# +# BR2_PACKAGE_XENOMAI is not set + +# +# Security +# + +# +# apparmor needs a toolchain w/ headers >= 3.16, threads, C++ +# +# BR2_PACKAGE_CHECKPOLICY is not set +# BR2_PACKAGE_IMA_EVM_UTILS is not set +# BR2_PACKAGE_OPTEE_BENCHMARK is not set +# BR2_PACKAGE_OPTEE_CLIENT is not set +# BR2_PACKAGE_PAXTEST is not set +# BR2_PACKAGE_REFPOLICY is not set +# BR2_PACKAGE_RESTORECOND is not set +# BR2_PACKAGE_SELINUX_PYTHON is not set +# BR2_PACKAGE_SEMODULE_UTILS is not set + +# +# setools needs python3 +# +# BR2_PACKAGE_URANDOM_SCRIPTS is not set + +# +# Shell and utilities +# + +# +# Shells +# +# BR2_PACKAGE_MKSH is not set +# BR2_PACKAGE_ZSH is not set + +# +# Utilities +# +# BR2_PACKAGE_AT is not set +# BR2_PACKAGE_CCRYPT is not set +# BR2_PACKAGE_DIALOG is not set +# BR2_PACKAGE_DTACH is not set +# BR2_PACKAGE_EASY_RSA is not set +# BR2_PACKAGE_FILE is not set +# BR2_PACKAGE_GNUPG is not set +# BR2_PACKAGE_GNUPG2 is not set +# BR2_PACKAGE_INOTIFY_TOOLS is not set +# BR2_PACKAGE_LOCKFILE_PROGS is not set +# BR2_PACKAGE_LOGROTATE is not set +# BR2_PACKAGE_LOGSURFER is not set +# BR2_PACKAGE_PDMENU is not set +# BR2_PACKAGE_PINENTRY is not set +# BR2_PACKAGE_QPRINT is not set +# BR2_PACKAGE_RANGER is not set +# BR2_PACKAGE_RTTY is not set +# BR2_PACKAGE_SCREEN is not set +# BR2_PACKAGE_SUDO is not set +# BR2_PACKAGE_TINI is not set +# BR2_PACKAGE_TMUX is not set +# BR2_PACKAGE_TTYD is not set +# BR2_PACKAGE_XMLSTARLET is not set +# BR2_PACKAGE_XXHASH is not set +# BR2_PACKAGE_YTREE is not set + +# +# System tools +# +# BR2_PACKAGE_ACL is not set +# BR2_PACKAGE_ANDROID_TOOLS is not set +# BR2_PACKAGE_ATOP is not set +# BR2_PACKAGE_ATTR is not set +# BR2_PACKAGE_BUBBLEWRAP is not set +# BR2_PACKAGE_CGROUPFS_MOUNT is not set + +# +# circus needs Python 3 and a toolchain w/ C++, threads +# +# BR2_PACKAGE_CPULOAD is not set +# BR2_PACKAGE_DAEMON is not set +# BR2_PACKAGE_DC3DD is not set + +# +# ddrescue needs a toolchain w/ C++ +# + +# +# docker-compose needs a toolchain w/ C++, wchar, threads, dynamic library +# +# BR2_PACKAGE_EARLYOOM is not set +# BR2_PACKAGE_EMLOG is not set +# BR2_PACKAGE_FTOP is not set +# BR2_PACKAGE_GETENT is not set +# BR2_PACKAGE_GKRELLM is not set +# BR2_PACKAGE_HTOP is not set +# BR2_PACKAGE_IBM_SW_TPM2 is not set +BR2_PACKAGE_INITSCRIPTS=y + +# +# iotop depends on python or python3 +# +# BR2_PACKAGE_IPRUTILS is not set +# BR2_PACKAGE_IRQBALANCE is not set +# BR2_PACKAGE_KEYUTILS is not set +# BR2_PACKAGE_KMOD is not set +# BR2_PACKAGE_LIBOSTREE is not set +# BR2_PACKAGE_LXC is not set +# BR2_PACKAGE_MFOC is not set +# BR2_PACKAGE_MONIT is not set + +# +# multipath-tools needs udev and a uClibc or glibc toolchain w/ threads, dynamic library +# +# BR2_PACKAGE_NCDU is not set + +# +# netifrc needs openrc as init system +# +# BR2_PACKAGE_NUMACTL is not set + +# +# nut needs a toolchain w/ C++ +# + +# +# pamtester depends on linux-pam +# + +# +# polkit needs a glibc or musl toolchain with C++, wchar, dynamic library, NPTL, gcc >= 4.9 +# +# BR2_PACKAGE_PROCRANK_LINUX is not set +# BR2_PACKAGE_PWGEN is not set +# BR2_PACKAGE_QUOTA is not set +# BR2_PACKAGE_QUOTATOOL is not set +# BR2_PACKAGE_RAUC is not set +# BR2_PACKAGE_S6 is not set +# BR2_PACKAGE_S6_LINUX_INIT is not set +# BR2_PACKAGE_S6_LINUX_UTILS is not set +# BR2_PACKAGE_S6_PORTABLE_UTILS is not set +# BR2_PACKAGE_S6_RC is not set +# BR2_PACKAGE_SCRUB is not set +# BR2_PACKAGE_SCRYPT is not set + +# +# sdbusplus needs systemd and a toolchain w/ C++, gcc >= 7 +# +# BR2_PACKAGE_SMACK is not set + +# +# supervisor needs a python interpreter +# +# BR2_PACKAGE_SWUPDATE is not set +BR2_PACKAGE_SYSTEMD_ARCH_SUPPORTS=y +# BR2_PACKAGE_TPM_TOOLS is not set +# BR2_PACKAGE_TPM2_ABRMD is not set +# BR2_PACKAGE_TPM2_TOOLS is not set +# BR2_PACKAGE_TPM2_TOTP is not set +# BR2_PACKAGE_UNSCD is not set +# BR2_PACKAGE_UTIL_LINUX is not set +# BR2_PACKAGE_WATCHDOG is not set +# BR2_PACKAGE_XDG_DBUS_PROXY is not set + +# +# Text editors and viewers +# +# BR2_PACKAGE_ED is not set +# BR2_PACKAGE_JOE is not set +# BR2_PACKAGE_MC is not set +# BR2_PACKAGE_MG is not set +# BR2_PACKAGE_MOST is not set +# BR2_PACKAGE_NANO is not set +# BR2_PACKAGE_UEMACS is not set + +# +# Filesystem images +# +# BR2_TARGET_ROOTFS_AXFS is not set +# BR2_TARGET_ROOTFS_BTRFS is not set +# BR2_TARGET_ROOTFS_CLOOP is not set +BR2_TARGET_ROOTFS_CPIO=y +BR2_TARGET_ROOTFS_CPIO_NONE=y +# BR2_TARGET_ROOTFS_CPIO_GZIP is not set +# BR2_TARGET_ROOTFS_CPIO_BZIP2 is not set +# BR2_TARGET_ROOTFS_CPIO_LZ4 is not set +# BR2_TARGET_ROOTFS_CPIO_LZMA is not set +# BR2_TARGET_ROOTFS_CPIO_LZO is not set +# BR2_TARGET_ROOTFS_CPIO_XZ is not set +# BR2_TARGET_ROOTFS_CPIO_ZSTD is not set +# BR2_TARGET_ROOTFS_CPIO_UIMAGE is not set +# BR2_TARGET_ROOTFS_CRAMFS is not set +# BR2_TARGET_ROOTFS_EROFS is not set +# BR2_TARGET_ROOTFS_EXT2 is not set +# BR2_TARGET_ROOTFS_F2FS is not set +BR2_TARGET_ROOTFS_INITRAMFS=y +# BR2_TARGET_ROOTFS_JFFS2 is not set +# BR2_TARGET_ROOTFS_ROMFS is not set +# BR2_TARGET_ROOTFS_SQUASHFS is not set +# BR2_TARGET_ROOTFS_TAR is not set +# BR2_TARGET_ROOTFS_UBI is not set +# BR2_TARGET_ROOTFS_UBIFS is not set +# BR2_TARGET_ROOTFS_YAFFS2 is not set + +# +# Bootloaders +# +# BR2_TARGET_BAREBOX is not set +# BR2_TARGET_BEAGLEV_DDRINIT is not set +# BR2_TARGET_BEAGLEV_SECONDBOOT is not set +BR2_TARGET_OPENSBI=y +BR2_TARGET_OPENSBI_LATEST_VERSION=y +# BR2_TARGET_OPENSBI_CUSTOM_VERSION is not set +# BR2_TARGET_OPENSBI_CUSTOM_TARBALL is not set +# BR2_TARGET_OPENSBI_CUSTOM_GIT is not set +BR2_TARGET_OPENSBI_VERSION="0.9" +BR2_TARGET_OPENSBI_PLAT="generic" +BR2_TARGET_OPENSBI_INSTALL_DYNAMIC_IMG=y +BR2_TARGET_OPENSBI_INSTALL_JUMP_IMG=y +# BR2_TARGET_OPENSBI_INSTALL_PAYLOAD_IMG is not set +# BR2_TARGET_OPENSBI_LINUX_PAYLOAD is not set +# BR2_TARGET_UBOOT is not set + +# +# Host utilities +# +# BR2_PACKAGE_HOST_ABOOTIMG is not set +# BR2_PACKAGE_HOST_AESPIPE is not set +# BR2_PACKAGE_HOST_ANDROID_TOOLS is not set +# BR2_PACKAGE_HOST_ASN1C is not set +# BR2_PACKAGE_HOST_BABELTRACE2 is not set +# BR2_PACKAGE_HOST_BTRFS_PROGS is not set +# BR2_PACKAGE_HOST_CHECKPOLICY is not set +# BR2_PACKAGE_HOST_CHECKSEC is not set +# BR2_PACKAGE_HOST_CMAKE is not set +# BR2_PACKAGE_HOST_CRAMFS is not set +# BR2_PACKAGE_HOST_CRYPTSETUP is not set +# BR2_PACKAGE_HOST_DBUS_PYTHON is not set +# BR2_PACKAGE_HOST_DFU_UTIL is not set +# BR2_PACKAGE_HOST_DOS2UNIX is not set +# BR2_PACKAGE_HOST_DOSFSTOOLS is not set +# BR2_PACKAGE_HOST_DOXYGEN is not set +# BR2_PACKAGE_HOST_DTC is not set +BR2_PACKAGE_HOST_E2FSPROGS=y +# BR2_PACKAGE_HOST_E2TOOLS is not set +# BR2_PACKAGE_HOST_ENVIRONMENT_SETUP is not set +# BR2_PACKAGE_HOST_EROFS_UTILS is not set +# BR2_PACKAGE_HOST_EXFATPROGS is not set +# BR2_PACKAGE_HOST_F2FS_TOOLS is not set +# BR2_PACKAGE_HOST_FAKETIME is not set +# BR2_PACKAGE_HOST_FATCAT is not set +# BR2_PACKAGE_HOST_FWUP is not set +# BR2_PACKAGE_HOST_GENEXT2FS is not set +# BR2_PACKAGE_HOST_GENIMAGE is not set +# BR2_PACKAGE_HOST_GENPART is not set +# BR2_PACKAGE_HOST_GNUPG is not set +BR2_PACKAGE_HOST_GO_HOST_ARCH_SUPPORTS=y +BR2_PACKAGE_HOST_GO_BOOTSTRAP_ARCH_SUPPORTS=y +BR2_PACKAGE_HOST_GOOGLE_BREAKPAD_ARCH_SUPPORTS=y +# BR2_PACKAGE_HOST_GPTFDISK is not set +# BR2_PACKAGE_HOST_IMAGEMAGICK is not set +# BR2_PACKAGE_HOST_IMX_MKIMAGE is not set +# BR2_PACKAGE_HOST_JH71XX_TOOLS is not set +# BR2_PACKAGE_HOST_JQ is not set +# BR2_PACKAGE_HOST_JSMIN is not set +BR2_PACKAGE_HOST_KMOD=y +# BR2_PACKAGE_HOST_KMOD_GZ is not set +# BR2_PACKAGE_HOST_KMOD_ZSTD is not set +# BR2_PACKAGE_HOST_KMOD_XZ is not set +# BR2_PACKAGE_HOST_LIBP11 is not set +# BR2_PACKAGE_HOST_LPC3250LOADER is not set +# BR2_PACKAGE_HOST_LTTNG_BABELTRACE is not set +# BR2_PACKAGE_HOST_MENDER_ARTIFACT is not set +# BR2_PACKAGE_HOST_MESON_TOOLS is not set +# BR2_PACKAGE_HOST_MKPASSWD is not set +# BR2_PACKAGE_HOST_MTD is not set +# BR2_PACKAGE_HOST_MTOOLS is not set +# BR2_PACKAGE_HOST_ODB is not set +# BR2_PACKAGE_HOST_OPENOCD is not set +# BR2_PACKAGE_HOST_OPKG_UTILS is not set +# BR2_PACKAGE_HOST_PARTED is not set +BR2_PACKAGE_HOST_PATCHELF=y +# BR2_PACKAGE_HOST_PIGZ is not set +# BR2_PACKAGE_HOST_PKGCONF is not set +# BR2_PACKAGE_HOST_PWGEN is not set +# BR2_PACKAGE_HOST_PYTHON is not set +# BR2_PACKAGE_HOST_PYTHON_CYTHON is not set +# BR2_PACKAGE_HOST_PYTHON_LXML is not set +# BR2_PACKAGE_HOST_PYTHON_SIX is not set +# BR2_PACKAGE_HOST_PYTHON_XLRD is not set +# BR2_PACKAGE_HOST_PYTHON3 is not set +BR2_PACKAGE_HOST_QEMU_ARCH_SUPPORTS=y +BR2_PACKAGE_HOST_QEMU_SYSTEM_ARCH_SUPPORTS=y +BR2_PACKAGE_HOST_QEMU_USER_ARCH_SUPPORTS=y +BR2_PACKAGE_HOST_QEMU=y + +# +# Emulators selection +# +BR2_PACKAGE_HOST_QEMU_SYSTEM_MODE=y +# BR2_PACKAGE_HOST_QEMU_LINUX_USER_MODE is not set +# BR2_PACKAGE_HOST_QEMU_VDE2 is not set +# BR2_PACKAGE_HOST_QEMU_VIRTFS is not set +# BR2_PACKAGE_HOST_QEMU_USB is not set +# BR2_PACKAGE_HOST_QORIQ_RCW is not set +# BR2_PACKAGE_HOST_RAUC is not set +BR2_PACKAGE_HOST_RUSTC_ARCH_SUPPORTS=y +BR2_PACKAGE_HOST_RUSTC_ARCH="riscv64" +# BR2_PACKAGE_HOST_RUSTC is not set +BR2_PACKAGE_PROVIDES_HOST_RUSTC="host-rust-bin" +# BR2_PACKAGE_HOST_SAM_BA is not set +# BR2_PACKAGE_HOST_SDBUSPLUS is not set +# BR2_PACKAGE_HOST_SENTRY_CLI is not set +# BR2_PACKAGE_HOST_SQUASHFS is not set +# BR2_PACKAGE_HOST_SWIG is not set +# BR2_PACKAGE_HOST_UBOOT_TOOLS is not set +BR2_PACKAGE_HOST_UTIL_LINUX=y +# BR2_PACKAGE_HOST_UTP_COM is not set +# BR2_PACKAGE_HOST_VBOOT_UTILS is not set +# BR2_PACKAGE_HOST_XORRISO is not set +# BR2_PACKAGE_HOST_ZIP is not set +# BR2_PACKAGE_HOST_ZSTD is not set + +# +# Legacy config options +# + +# +# Legacy options removed in 2021.05 +# +# BR2_PACKAGE_UDISKS_LVM2 is not set +# BR2_PACKAGE_LVM2_APP_LIBRARY is not set +# BR2_PACKAGE_LVM2_LVMETAD is not set +# BR2_PACKAGE_MONKEY is not set +# BR2_PACKAGE_DOCKER_CONTAINERD is not set +# BR2_PACKAGE_IOSTAT is not set +# BR2_PACKAGE_SCONESERVER_HTTP_SCONESITE_IMAGE is not set +# BR2_PACKAGE_XSERVER_XORG_SERVER_KDRIVE_EVDEV is not set +# BR2_PACKAGE_XSERVER_XORG_SERVER_KDRIVE_KBD is not set +# BR2_PACKAGE_XSERVER_XORG_SERVER_KDRIVE_MOUSE is not set +# BR2_PACKAGE_MESA3D_OSMESA_CLASSIC is not set +# BR2_PACKAGE_MESA3D_DRI_DRIVER_SWRAST is not set +# BR2_PACKAGE_KODI_SCREENSAVER_CRYSTALMORPH is not set + +# +# Legacy options removed in 2021.02 +# +# BR2_PACKAGE_MPD_AUDIOFILE is not set +# BR2_PACKAGE_AUDIOFILE is not set +# BR2_BINUTILS_VERSION_2_33_X is not set +# BR2_PACKAGE_LIBUPNP18 is not set +# BR2_PACKAGE_BOA is not set +# BR2_PACKAGE_LINUX_FIRMWARE_IMX_SDMA is not set +# BR2_GDB_VERSION_8_2 is not set +# BR2_PACKAGE_HOST_RCW is not set +# BR2_KERNEL_HEADERS_5_9 is not set +# BR2_KERNEL_HEADERS_5_8 is not set +# BR2_powerpc_601 is not set +# BR2_PACKAGE_TI_SGX_LIBGBM is not set +# BR2_PACKAGE_IPSEC_TOOLS is not set + +# +# Legacy options removed in 2020.11 +# +# BR2_PACKAGE_OPENCV is not set +# BR2_PACKAGE_LIBCROCO is not set +# BR2_PACKAGE_BELLAGIO is not set +# BR2_PACKAGE_SYSTEMD_JOURNAL_GATEWAY is not set +# BR2_TARGET_UBOOT_BOOT_SCRIPT is not set +# BR2_TARGET_UBOOT_ENVIMAGE is not set +# BR2_PACKAGE_KISMET_CLIENT is not set +# BR2_PACKAGE_KISMET_DRONE is not set +# BR2_GCC_VERSION_7_X is not set +# BR2_PACKAGE_GST1_VALIDATE is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_YADIF is not set +# BR2_PACKAGE_GQVIEW is not set +# BR2_PACKAGE_WESTON_IMX is not set +# BR2_KERNEL_HEADERS_5_7 is not set +# BR2_PACKAGE_TINYHTTPD is not set +# BR2_PACKAGE_XSERVER_XORG_SERVER_AIGLX is not set +# BR2_PACKAGE_AMD_CATALYST is not set +# BR2_PACKAGE_NVIDIA_TEGRA23 is not set +# BR2_GDB_VERSION_8_1 is not set + +# +# Legacy options removed in 2020.08 +# +# BR2_TOOLCHAIN_EXTERNAL_CODESOURCERY_AMD64 is not set +# BR2_KERNEL_HEADERS_5_6 is not set +# BR2_KERNEL_HEADERS_5_5 is not set +# BR2_BINUTILS_VERSION_2_31_X is not set +# BR2_PACKAGE_KODI_PERIPHERAL_STEAMCONTROLLER is not set + +# +# Legacy options removed in 2020.05 +# +# BR2_PACKAGE_WIRINGPI is not set +# BR2_PACKAGE_PYTHON_PYCRYPTO is not set +# BR2_PACKAGE_MTDEV2TUIO is not set +# BR2_PACKAGE_EZXML is not set +# BR2_PACKAGE_COLLECTD_LVM is not set +# BR2_PACKAGE_PYTHON_PYASN is not set +# BR2_PACKAGE_PYTHON_PYASN_MODULES is not set +# BR2_PACKAGE_LINUX_FIRMWARE_ATHEROS_10K_QCA6174 is not set +# BR2_PACKAGE_QT5CANVAS3D is not set +# BR2_PACKAGE_KODI_LIBTHEORA is not set +# BR2_PACKAGE_CEGUI06 is not set +# BR2_GCC_VERSION_5_X is not set + +# +# Legacy options removed in 2020.02 +# +# BR2_PACKAGE_JAMVM is not set +# BR2_PACKAGE_CLASSPATH is not set +# BR2_PACKAGE_QT5_VERSION_5_6 is not set +# BR2_PACKAGE_CURL is not set +# BR2_PACKAGE_GSTREAMER is not set +# BR2_PACKAGE_NVIDIA_TEGRA23_BINARIES_GSTREAMER_PLUGINS is not set +# BR2_PACKAGE_NVIDIA_TEGRA23_BINARIES_NV_SAMPLE_APPS is not set +# BR2_PACKAGE_FREERDP_GSTREAMER is not set +# BR2_PACKAGE_OPENCV3_WITH_GSTREAMER is not set +# BR2_PACKAGE_OPENCV_WITH_GSTREAMER is not set +# BR2_PACKAGE_LIBPLAYER is not set +# BR2_GCC_VERSION_OR1K is not set +# BR2_PACKAGE_BLUEZ_UTILS is not set +# BR2_PACKAGE_GADGETFS_TEST is not set +# BR2_PACKAGE_FIS is not set +BR2_PACKAGE_REFPOLICY_POLICY_VERSION="" +# BR2_PACKAGE_CELT051 is not set +# BR2_PACKAGE_WIREGUARD is not set +# BR2_PACKAGE_PERL_NET_PING is not set +# BR2_PACKAGE_PERL_MIME_BASE64 is not set +# BR2_PACKAGE_PERL_DIGEST_MD5 is not set +# BR2_PACKAGE_ERLANG_P1_ICONV is not set +# BR2_KERNEL_HEADERS_5_3 is not set +# BR2_PACKAGE_PYTHON_SCAPY3K is not set +# BR2_BINUTILS_VERSION_2_30_X is not set +# BR2_PACKAGE_RPI_USERLAND_START_VCFILED is not set + +# +# Legacy options removed in 2019.11 +# +# BR2_PACKAGE_OPENVMTOOLS_PROCPS is not set +# BR2_PACKAGE_ALLJOYN is not set +# BR2_PACKAGE_ALLJOYN_BASE is not set +# BR2_PACKAGE_ALLJOYN_BASE_CONTROLPANEL is not set +# BR2_PACKAGE_ALLJOYN_BASE_NOTIFICATION is not set +# BR2_PACKAGE_ALLJOYN_BASE_ONBOARDING is not set +# BR2_PACKAGE_ALLJOYN_TCL_BASE is not set +# BR2_PACKAGE_ALLJOYN_TCL is not set +BR2_TOOLCHAIN_EXTRA_EXTERNAL_LIBS="" +# BR2_PACKAGE_PYTHON_PYSNMP_APPS is not set +# BR2_KERNEL_HEADERS_5_2 is not set +# BR2_TARGET_RISCV_PK is not set +# BR2_PACKAGE_SQLITE_STAT3 is not set +# BR2_KERNEL_HEADERS_5_1 is not set +# BR2_PACKAGE_DEVMEM2 is not set +# BR2_PACKAGE_USTR is not set +# BR2_PACKAGE_KODI_SCREENSAVER_PLANESTATE is not set +# BR2_PACKAGE_KODI_VISUALISATION_WAVEFORHUE is not set +# BR2_PACKAGE_KODI_AUDIODECODER_OPUS is not set +# BR2_PACKAGE_MESA3D_OSMESA is not set +# BR2_PACKAGE_HOSTAPD_DRIVER_RTW is not set +# BR2_PACKAGE_WPA_SUPPLICANT_DBUS_NEW is not set +# BR2_PACKAGE_WPA_SUPPLICANT_DBUS_OLD is not set + +# +# Legacy options removed in 2019.08 +# +# BR2_TARGET_TS4800_MBRBOOT is not set +# BR2_PACKAGE_LIBAMCODEC is not set +# BR2_PACKAGE_ODROID_SCRIPTS is not set +# BR2_PACKAGE_ODROID_MALI is not set +# BR2_PACKAGE_KODI_PLATFORM_AML is not set +# BR2_GCC_VERSION_6_X is not set +# BR2_GCC_VERSION_4_9_X is not set +# BR2_GDB_VERSION_7_12 is not set +# BR2_PACKAGE_XAPP_MKFONTDIR is not set +# BR2_GDB_VERSION_8_0 is not set +# BR2_KERNEL_HEADERS_4_20 is not set +# BR2_KERNEL_HEADERS_5_0 is not set + +# +# Legacy options removed in 2019.05 +# +# BR2_CSKY_DSP is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_COMPOSITOR is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_IQA is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_OPENCV is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_STEREO is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_VCD is not set +# BR2_PACKAGE_LUNIT is not set +# BR2_PACKAGE_FFMPEG_FFSERVER is not set +# BR2_PACKAGE_LIBUMP is not set +# BR2_PACKAGE_SUNXI_MALI is not set +# BR2_BINUTILS_VERSION_2_29_X is not set +# BR2_BINUTILS_VERSION_2_28_X is not set +# BR2_PACKAGE_GST_PLUGINS_BAD_PLUGIN_APEXSINK is not set + +# +# Legacy options removed in 2019.02 +# +# BR2_PACKAGE_QT is not set +# BR2_PACKAGE_QTUIO is not set +# BR2_PACKAGE_PINENTRY_QT4 is not set +# BR2_PACKAGE_POPPLER_QT is not set +# BR2_PACKAGE_OPENCV3_WITH_QT is not set +# BR2_PACKAGE_OPENCV_WITH_QT is not set +# BR2_PACKAGE_AMD_CATALYST_CCCLE is not set +# BR2_PACKAGE_SDL_QTOPIA is not set +# BR2_PACKAGE_PYTHON_PYQT is not set +# BR2_PACKAGE_LUACRYPTO is not set +# BR2_PACKAGE_TN5250 is not set +# BR2_PACKAGE_BOOST_SIGNALS is not set +# BR2_PACKAGE_FFTW_PRECISION_SINGLE is not set +# BR2_PACKAGE_FFTW_PRECISION_DOUBLE is not set +# BR2_PACKAGE_FFTW_PRECISION_LONG_DOUBLE is not set +# BR2_PACKAGE_LUA_5_2 is not set +# BR2_TARGET_GENERIC_PASSWD_MD5 is not set + +# +# Legacy options removed in 2018.11 +# +# BR2_TARGET_XLOADER is not set +# BR2_PACKAGE_TIDSP_BINARIES is not set +# BR2_PACKAGE_DSP_TOOLS is not set +# BR2_PACKAGE_GST_DSP is not set +# BR2_PACKAGE_BOOTUTILS is not set +# BR2_PACKAGE_EXPEDITE is not set +# BR2_PACKAGE_MESA3D_OPENGL_TEXTURE_FLOAT is not set +# BR2_KERNEL_HEADERS_4_10 is not set +# BR2_KERNEL_HEADERS_4_11 is not set +# BR2_KERNEL_HEADERS_4_12 is not set +# BR2_KERNEL_HEADERS_4_13 is not set +# BR2_KERNEL_HEADERS_4_15 is not set +# BR2_KERNEL_HEADERS_4_17 is not set +# BR2_PACKAGE_LIBNFTNL_XML is not set +# BR2_KERNEL_HEADERS_3_2 is not set +# BR2_KERNEL_HEADERS_4_1 is not set +# BR2_KERNEL_HEADERS_4_16 is not set +# BR2_KERNEL_HEADERS_4_18 is not set + +# +# Legacy options removed in 2018.08 +# +# BR2_PACKAGE_DOCKER_ENGINE_STATIC_CLIENT is not set +# BR2_PACKAGE_XPROTO_APPLEWMPROTO is not set +# BR2_PACKAGE_XPROTO_BIGREQSPROTO is not set +# BR2_PACKAGE_XPROTO_COMPOSITEPROTO is not set +# BR2_PACKAGE_XPROTO_DAMAGEPROTO is not set +# BR2_PACKAGE_XPROTO_DMXPROTO is not set +# BR2_PACKAGE_XPROTO_DRI2PROTO is not set +# BR2_PACKAGE_XPROTO_DRI3PROTO is not set +# BR2_PACKAGE_XPROTO_FIXESPROTO is not set +# BR2_PACKAGE_XPROTO_FONTCACHEPROTO is not set +# BR2_PACKAGE_XPROTO_FONTSPROTO is not set +# BR2_PACKAGE_XPROTO_GLPROTO is not set +# BR2_PACKAGE_XPROTO_INPUTPROTO is not set +# BR2_PACKAGE_XPROTO_KBPROTO is not set +# BR2_PACKAGE_XPROTO_PRESENTPROTO is not set +# BR2_PACKAGE_XPROTO_RANDRPROTO is not set +# BR2_PACKAGE_XPROTO_RECORDPROTO is not set +# BR2_PACKAGE_XPROTO_RENDERPROTO is not set +# BR2_PACKAGE_XPROTO_RESOURCEPROTO is not set +# BR2_PACKAGE_XPROTO_SCRNSAVERPROTO is not set +# BR2_PACKAGE_XPROTO_VIDEOPROTO is not set +# BR2_PACKAGE_XPROTO_WINDOWSWMPROTO is not set +# BR2_PACKAGE_XPROTO_XCMISCPROTO is not set +# BR2_PACKAGE_XPROTO_XEXTPROTO is not set +# BR2_PACKAGE_XPROTO_XF86BIGFONTPROTO is not set +# BR2_PACKAGE_XPROTO_XF86DGAPROTO is not set +# BR2_PACKAGE_XPROTO_XF86DRIPROTO is not set +# BR2_PACKAGE_XPROTO_XF86VIDMODEPROTO is not set +# BR2_PACKAGE_XPROTO_XINERAMAPROTO is not set +# BR2_PACKAGE_XPROTO_XPROTO is not set +# BR2_PACKAGE_XPROTO_XPROXYMANAGEMENTPROTOCOL is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_LIB_OPENGL_OPENGL is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_LIB_OPENGL_GLES2 is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_LIB_OPENGL_GLX is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_LIB_OPENGL_EGL is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_LIB_OPENGL_X11 is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_LIB_OPENGL_WAYLAND is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_LIB_OPENGL_DISPMANX is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_AUDIOMIXER is not set +# BR2_PACKAGE_GST1_PLUGINS_UGLY_PLUGIN_LAME is not set +# BR2_PACKAGE_GST1_PLUGINS_UGLY_PLUGIN_MPG123 is not set +# BR2_GDB_VERSION_7_11 is not set +# BR2_GDB_VERSION_7_10 is not set + +# +# Legacy options removed in 2018.05 +# +# BR2_PACKAGE_MEDIAART_BACKEND_NONE is not set +# BR2_PACKAGE_MEDIAART_BACKEND_GDK_PIXBUF is not set +# BR2_PACKAGE_TI_SGX_AM335X is not set +# BR2_PACKAGE_TI_SGX_AM437X is not set +# BR2_PACKAGE_TI_SGX_AM4430 is not set +# BR2_PACKAGE_TI_SGX_AM5430 is not set +# BR2_PACKAGE_JANUS_AUDIO_BRIDGE is not set +# BR2_PACKAGE_JANUS_ECHO_TEST is not set +# BR2_PACKAGE_JANUS_RECORDPLAY is not set +# BR2_PACKAGE_JANUS_SIP_GATEWAY is not set +# BR2_PACKAGE_JANUS_STREAMING is not set +# BR2_PACKAGE_JANUS_TEXT_ROOM is not set +# BR2_PACKAGE_JANUS_VIDEO_CALL is not set +# BR2_PACKAGE_JANUS_VIDEO_ROOM is not set +# BR2_PACKAGE_JANUS_MQTT is not set +# BR2_PACKAGE_JANUS_RABBITMQ is not set +# BR2_PACKAGE_JANUS_REST is not set +# BR2_PACKAGE_JANUS_UNIX_SOCKETS is not set +# BR2_PACKAGE_JANUS_WEBSOCKETS is not set +# BR2_PACKAGE_IPSEC_SECCTX_DISABLE is not set +# BR2_PACKAGE_IPSEC_SECCTX_ENABLE is not set +# BR2_PACKAGE_IPSEC_SECCTX_KERNEL is not set +# BR2_PACKAGE_LIBTFDI_CPP is not set +# BR2_PACKAGE_JQUERY_UI_THEME_BLACK_TIE is not set +# BR2_PACKAGE_JQUERY_UI_THEME_BLITZER is not set +# BR2_PACKAGE_JQUERY_UI_THEME_CUPERTINO is not set +# BR2_PACKAGE_JQUERY_UI_THEME_DARK_HIVE is not set +# BR2_PACKAGE_JQUERY_UI_THEME_DOT_LUV is not set +# BR2_PACKAGE_JQUERY_UI_THEME_EGGPLANT is not set +# BR2_PACKAGE_JQUERY_UI_THEME_EXCITE_BIKE is not set +# BR2_PACKAGE_JQUERY_UI_THEME_FLICK is not set +# BR2_PACKAGE_JQUERY_UI_THEME_HOT_SNEAKS is not set +# BR2_PACKAGE_JQUERY_UI_THEME_HUMANITY is not set +# BR2_PACKAGE_JQUERY_UI_THEME_LE_FROG is not set +# BR2_PACKAGE_JQUERY_UI_THEME_MINT_CHOC is not set +# BR2_PACKAGE_JQUERY_UI_THEME_OVERCAST is not set +# BR2_PACKAGE_JQUERY_UI_THEME_PEPPER_GRINDER is not set +# BR2_PACKAGE_JQUERY_UI_THEME_REDMOND is not set +# BR2_PACKAGE_JQUERY_UI_THEME_SMOOTHNESS is not set +# BR2_PACKAGE_JQUERY_UI_THEME_SOUTH_STREET is not set +# BR2_PACKAGE_JQUERY_UI_THEME_START is not set +# BR2_PACKAGE_JQUERY_UI_THEME_SUNNY is not set +# BR2_PACKAGE_JQUERY_UI_THEME_SWANKY_PURSE is not set +# BR2_PACKAGE_JQUERY_UI_THEME_TRONTASTIC is not set +# BR2_PACKAGE_JQUERY_UI_THEME_UI_DARKNESS is not set +# BR2_PACKAGE_JQUERY_UI_THEME_UI_LIGHTNESS is not set +# BR2_PACKAGE_JQUERY_UI_THEME_VADER is not set +# BR2_PACKAGE_BLUEZ5_PLUGINS_HEALTH is not set +# BR2_PACKAGE_BLUEZ5_PLUGINS_MIDI is not set +# BR2_PACKAGE_BLUEZ5_PLUGINS_NFC is not set +# BR2_PACKAGE_BLUEZ5_PLUGINS_SAP is not set +# BR2_PACKAGE_BLUEZ5_PLUGINS_SIXAXIS is not set +# BR2_PACKAGE_TRANSMISSION_REMOTE is not set +# BR2_PACKAGE_LIBKCAPI_APPS is not set +# BR2_PACKAGE_MPLAYER is not set +# BR2_PACKAGE_MPLAYER_MPLAYER is not set +# BR2_PACKAGE_MPLAYER_MENCODER is not set +# BR2_PACKAGE_LIBPLAYER_MPLAYER is not set +# BR2_PACKAGE_IQVLINUX is not set +# BR2_BINFMT_FLAT_SEP_DATA is not set +# BR2_bfin is not set +# BR2_PACKAGE_KODI_ADSP_BASIC is not set +# BR2_PACKAGE_KODI_ADSP_FREESURROUND is not set + +# +# Legacy options removed in 2018.02 +# +# BR2_KERNEL_HEADERS_3_4 is not set +# BR2_KERNEL_HEADERS_3_10 is not set +# BR2_KERNEL_HEADERS_3_12 is not set +# BR2_BINUTILS_VERSION_2_27_X is not set +# BR2_PACKAGE_EEPROG is not set +# BR2_PACKAGE_GNUPG2_GPGV2 is not set +# BR2_PACKAGE_IMX_GPU_VIV_APITRACE is not set +# BR2_PACKAGE_IMX_GPU_VIV_G2D is not set + +# +# Legacy options removed in 2017.11 +# +# BR2_PACKAGE_RFKILL is not set +# BR2_PACKAGE_UTIL_LINUX_RESET is not set +# BR2_PACKAGE_POLICYCOREUTILS_AUDIT2ALLOW is not set +# BR2_PACKAGE_POLICYCOREUTILS_RESTORECOND is not set +# BR2_PACKAGE_SEPOLGEN is not set +# BR2_PACKAGE_OPENOBEX_BLUEZ is not set +# BR2_PACKAGE_OPENOBEX_LIBUSB is not set +# BR2_PACKAGE_OPENOBEX_APPS is not set +# BR2_PACKAGE_OPENOBEX_SYSLOG is not set +# BR2_PACKAGE_OPENOBEX_DUMP is not set +# BR2_PACKAGE_AICCU is not set +# BR2_PACKAGE_UTIL_LINUX_LOGIN_UTILS is not set + +# +# Legacy options removed in 2017.08 +# +# BR2_TARGET_GRUB is not set +# BR2_PACKAGE_SIMICSFS is not set +# BR2_BINUTILS_VERSION_2_26_X is not set +BR2_XTENSA_OVERLAY_DIR="" +BR2_XTENSA_CUSTOM_NAME="" +# BR2_PACKAGE_HOST_MKE2IMG is not set +BR2_TARGET_ROOTFS_EXT2_BLOCKS=0 +BR2_TARGET_ROOTFS_EXT2_EXTRA_INODES=0 +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_CDXAPARSE is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_DATAURISRC is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_DCCP is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_HDVPARSE is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_MVE is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_NUVDEMUX is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_PATCHDETECT is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_SDI is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_TTA is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_VIDEOMEASURE is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_APEXSINK is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_SDL is not set +# BR2_PACKAGE_GST1_PLUGINS_UGLY_PLUGIN_MAD is not set +# BR2_STRIP_none is not set +# BR2_PACKAGE_BEECRYPT_CPP is not set +# BR2_PACKAGE_SPICE_CLIENT is not set +# BR2_PACKAGE_SPICE_GUI is not set +# BR2_PACKAGE_SPICE_TUNNEL is not set +# BR2_PACKAGE_INPUT_TOOLS is not set +# BR2_PACKAGE_INPUT_TOOLS_INPUTATTACH is not set +# BR2_PACKAGE_INPUT_TOOLS_JSCAL is not set +# BR2_PACKAGE_INPUT_TOOLS_JSTEST is not set +# BR2_TOOLCHAIN_EXTERNAL_CODESOURCERY_SH is not set +# BR2_TOOLCHAIN_EXTERNAL_CODESOURCERY_X86 is not set +# BR2_GCC_VERSION_4_8_X is not set + +# +# Legacy options removed in 2017.05 +# +# BR2_PACKAGE_SUNXI_MALI_R2P4 is not set +# BR2_PACKAGE_NODEJS_MODULES_COFFEESCRIPT is not set +# BR2_PACKAGE_NODEJS_MODULES_EXPRESS is not set +# BR2_PACKAGE_BLUEZ5_UTILS_GATTTOOL is not set +# BR2_PACKAGE_OPENOCD_FT2XXX is not set +# BR2_PACKAGE_KODI_RTMPDUMP is not set +# BR2_PACKAGE_KODI_VISUALISATION_FOUNTAIN is not set +# BR2_PACKAGE_PORTMAP is not set +# BR2_BINUTILS_VERSION_2_25_X is not set +# BR2_TOOLCHAIN_BUILDROOT_INET_RPC is not set +BR2_TARGET_ROOTFS_EXT2_EXTRA_BLOCKS=0 +# BR2_PACKAGE_SYSTEMD_KDBUS is not set +# BR2_PACKAGE_POLARSSL is not set +# BR2_NBD_CLIENT is not set +# BR2_NBD_SERVER is not set +# BR2_PACKAGE_GMOCK is not set +# BR2_KERNEL_HEADERS_4_8 is not set +# BR2_KERNEL_HEADERS_3_18 is not set +# BR2_GLIBC_VERSION_2_22 is not set + +# +# Legacy options removed in 2017.02 +# +# BR2_PACKAGE_PERL_DB_FILE is not set +# BR2_KERNEL_HEADERS_4_7 is not set +# BR2_KERNEL_HEADERS_4_6 is not set +# BR2_KERNEL_HEADERS_4_5 is not set +# BR2_KERNEL_HEADERS_3_14 is not set +# BR2_TOOLCHAIN_EXTERNAL_MUSL_CROSS is not set +# BR2_UCLIBC_INSTALL_TEST_SUITE is not set +# BR2_TOOLCHAIN_EXTERNAL_BLACKFIN_UCLINUX is not set +# BR2_PACKAGE_MAKEDEVS is not set +# BR2_TOOLCHAIN_EXTERNAL_ARAGO_ARMV7A is not set +# BR2_TOOLCHAIN_EXTERNAL_ARAGO_ARMV5TE is not set +# BR2_PACKAGE_SNOWBALL_HDMISERVICE is not set +# BR2_PACKAGE_SNOWBALL_INIT is not set +# BR2_GDB_VERSION_7_9 is not set + +# +# Legacy options removed in 2016.11 +# +# BR2_PACKAGE_PHP_SAPI_CLI_CGI is not set +# BR2_PACKAGE_PHP_SAPI_CLI_FPM is not set +# BR2_PACKAGE_WVSTREAMS is not set +# BR2_PACKAGE_WVDIAL is not set +# BR2_PACKAGE_WEBKITGTK24 is not set +# BR2_PACKAGE_TORSMO is not set +# BR2_PACKAGE_SSTRIP is not set +# BR2_KERNEL_HEADERS_4_3 is not set +# BR2_KERNEL_HEADERS_4_2 is not set +# BR2_PACKAGE_KODI_ADDON_XVDR is not set +# BR2_PACKAGE_IPKG is not set +# BR2_GCC_VERSION_4_7_X is not set +# BR2_BINUTILS_VERSION_2_24_X is not set +# BR2_PACKAGE_WESTON_RPI is not set +# BR2_LINUX_KERNEL_TOOL_CPUPOWER is not set +# BR2_LINUX_KERNEL_TOOL_PERF is not set +# BR2_LINUX_KERNEL_TOOL_SELFTESTS is not set +# BR2_GCC_VERSION_4_8_ARC is not set +# BR2_KERNEL_HEADERS_4_0 is not set +# BR2_KERNEL_HEADERS_3_19 is not set +# BR2_PACKAGE_LIBEVAS_GENERIC_LOADERS is not set +# BR2_PACKAGE_ELEMENTARY is not set +# BR2_LINUX_KERNEL_CUSTOM_LOCAL is not set + +# +# Legacy options removed in 2016.08 +# +# BR2_PACKAGE_EFL_JP2K is not set +# BR2_PACKAGE_SYSTEMD_COMPAT is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_LIVEADDER is not set +# BR2_PACKAGE_LIBFSLVPUWRAP is not set +# BR2_PACKAGE_LIBFSLPARSER is not set +# BR2_PACKAGE_LIBFSLCODEC is not set +# BR2_PACKAGE_UBOOT_TOOLS_MKIMAGE_FIT_SIGNATURE_SUPPORT is not set +# BR2_PTHREADS_OLD is not set +# BR2_BINUTILS_VERSION_2_23_X is not set +# BR2_TOOLCHAIN_BUILDROOT_EGLIBC is not set +# BR2_GDB_VERSION_7_8 is not set + +# +# Legacy options removed in 2016.05 +# +# BR2_PACKAGE_OPENVPN_CRYPTO_POLARSSL is not set +# BR2_PACKAGE_NGINX_HTTP_SPDY_MODULE is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_RTP is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_MPG123 is not set +# BR2_TOOLCHAIN_EXTERNAL_CODESOURCERY_POWERPC is not set +# BR2_TOOLCHAIN_EXTERNAL_CODESOURCERY_POWERPC_E500V2 is not set +# BR2_x86_i386 is not set +# BR2_PACKAGE_QT5QUICK1 is not set +BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR="" +# BR2_PACKAGE_XDRIVER_XF86_INPUT_VOID is not set +# BR2_KERNEL_HEADERS_3_17 is not set +# BR2_GDB_VERSION_7_7 is not set +# BR2_PACKAGE_FOOMATIC_FILTERS is not set +# BR2_PACKAGE_SAMBA is not set +# BR2_PACKAGE_KODI_WAVPACK is not set +# BR2_PACKAGE_KODI_RSXS is not set +# BR2_PACKAGE_KODI_GOOM is not set +# BR2_PACKAGE_SYSTEMD_ALL_EXTRAS is not set +# BR2_GCC_VERSION_4_5_X is not set +# BR2_PACKAGE_SQLITE_READLINE is not set + +# +# Legacy options removed in 2016.02 +# +# BR2_PACKAGE_DOVECOT_BZIP2 is not set +# BR2_PACKAGE_DOVECOT_ZLIB is not set +# BR2_PACKAGE_E2FSPROGS_FINDFS is not set +# BR2_PACKAGE_OPENPOWERLINK_DEBUG_LEVEL is not set +# BR2_PACKAGE_OPENPOWERLINK_KERNEL_MODULE is not set +# BR2_PACKAGE_OPENPOWERLINK_LIBPCAP is not set +# BR2_LINUX_KERNEL_SAME_AS_HEADERS is not set +# BR2_PACKAGE_CUPS_PDFTOPS is not set +# BR2_KERNEL_HEADERS_3_16 is not set +# BR2_PACKAGE_PYTHON_PYXML is not set +# BR2_ENABLE_SSP is not set +# BR2_PACKAGE_DIRECTFB_CLE266 is not set +# BR2_PACKAGE_DIRECTFB_UNICHROME is not set +# BR2_PACKAGE_LIBELEMENTARY is not set +# BR2_PACKAGE_LIBEINA is not set +# BR2_PACKAGE_LIBEET is not set +# BR2_PACKAGE_LIBEVAS is not set +# BR2_PACKAGE_LIBECORE is not set +# BR2_PACKAGE_LIBEDBUS is not set +# BR2_PACKAGE_LIBEFREET is not set +# BR2_PACKAGE_LIBEIO is not set +# BR2_PACKAGE_LIBEMBRYO is not set +# BR2_PACKAGE_LIBEDJE is not set +# BR2_PACKAGE_LIBETHUMB is not set +# BR2_PACKAGE_INFOZIP is not set +# BR2_BR2_PACKAGE_NODEJS_0_10_X is not set +# BR2_BR2_PACKAGE_NODEJS_0_12_X is not set +# BR2_BR2_PACKAGE_NODEJS_4_X is not set + +# +# Legacy options removed in 2015.11 +# +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_REAL is not set +# BR2_PACKAGE_MEDIA_CTL is not set +# BR2_PACKAGE_SCHIFRA is not set +# BR2_PACKAGE_ZXING is not set +# BR2_PACKAGE_BLACKBOX is not set +# BR2_KERNEL_HEADERS_3_0 is not set +# BR2_KERNEL_HEADERS_3_11 is not set +# BR2_KERNEL_HEADERS_3_13 is not set +# BR2_KERNEL_HEADERS_3_15 is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_ANDI is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_BLTLOAD is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_CPULOAD is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_DATABUFFER is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_DIOLOAD is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_DOK is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_DRIVERTEST is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_FIRE is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_FLIP is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_FONTS is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_INPUT is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_JOYSTICK is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_KNUCKLES is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_LAYER is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_MATRIX is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_MATRIX_WATER is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_NEO is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_NETLOAD is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_PALETTE is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_PARTICLE is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_PORTER is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_STRESS is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_TEXTURE is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_VIDEO is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_VIDEO_PARTICLE is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_WINDOW is not set +# BR2_PACKAGE_KOBS_NG is not set +# BR2_PACKAGE_SAWMAN is not set +# BR2_PACKAGE_DIVINE is not set + +# +# Legacy options removed in 2015.08 +# +# BR2_PACKAGE_KODI_PVR_ADDONS is not set +# BR2_BINUTILS_VERSION_2_23_2 is not set +# BR2_BINUTILS_VERSION_2_24 is not set +# BR2_BINUTILS_VERSION_2_25 is not set +# BR2_PACKAGE_PERF is not set +# BR2_BINUTILS_VERSION_2_22 is not set +# BR2_PACKAGE_GPU_VIV_BIN_MX6Q is not set +# BR2_TARGET_UBOOT_NETWORK is not set diff --git a/linux/sdcard/Makefile b/linux/sdcard/Makefile new file mode 100644 index 000000000..7c6c012f9 --- /dev/null +++ b/linux/sdcard/Makefile @@ -0,0 +1,9 @@ +RISCV := /opt/riscv + +.PHONY: all clean + +all: + ./make-img.sh test.img + +clean: + rm -f test.img diff --git a/linux/sdcard/flash-sd.sh b/linux/sdcard/flash-sd.sh new file mode 100755 index 000000000..edc1ca5eb --- /dev/null +++ b/linux/sdcard/flash-sd.sh @@ -0,0 +1,120 @@ +#!/bin/bash + +# Exit on any error (return code != 0) +set -e + +# Output colors +GREEN='\033[1;32m' +RED='\033[1;31m' +NC='\033[0m' +NAME="$GREEN"${0:2}"$NC" + +# File location variables +RISCV=/opt/riscv +IMAGES=$RISCV/buildroot/output/images +FW_JUMP=$IMAGES/fw_jump.bin +LINUX_KERNEL=$IMAGES/Image +DEVICE_TREE=$IMAGES/wally-vcu108.dtb + +# Mount Directory +MNT_DIR=wallyimg + +if [ "$#" -eq "0" ] ; then + echo "$NAME: $RED ERROR $NC: You must supply the SD card device." + echo "usage: ./flash-sd.sh " + exit 1 +fi + +if [ ! -e "$1" ] ; then + echo "$NAME:$RED ERROR $NC: SD card device does not exist." + exit 1 +fi + +if [ ! -z "$2" ] ; then + MNT_DIR=$2 +fi + +# If images are not built, exit +if [ ! -e $FW_JUMP ] || [ ! -e $LINUX_KERNEL ] ; then + echo 'ERROR: Missing images in buildroot output directory.' + echo ' Build images before running this script.' + exit 1 +fi + +if [ ! -e $DEVICE_TREE ] ; then + echo 'ERROR: Missing device tree file' + exit 1 +fi + +# Size of OpenSBI and the Kernel in 512B blocks +DST_SIZE=$(ls -la --block-size=512 $DEVICE_TREE | cut -d' ' -f 5 ) +FW_JUMP_SIZE=$(ls -la --block-size=512 $FW_JUMP | cut -d' ' -f 5 ) +KERNEL_SIZE=$(ls -la --block-size=512 $LINUX_KERNEL | cut -d' ' -f 5 ) + +# Start sectors of OpenSBI and Kernel Partitions +FW_JUMP_START=$(( 34 + $DST_SIZE )) +KERNEL_START=$(( $FW_JUMP_START + $FW_JUMP_SIZE )) +FS_START=$(( $KERNEL_START + $KERNEL_SIZE )) + +# Print out the sizes of the binaries in 512B blocks +echo -e "$NAME: Device tree block size: $DST_SIZE" +echo -e "$NAME: OpenSBI FW_JUMP block size: $FW_JUMP_SIZE" +echo -e "$NAME: Kernel block size: $KERNEL_SIZE" + +read -p "Warning: " -n 1 -r +echo +if [[ $REPLY =~ ^[Yy]$ ]] ; then + # Make empty image + #echo -e "$NAME: Creating blank image" + #sudo dd if=/dev/zero of=$1 bs=4k conv=noerror status=progress && sync + + # GUID Partition Tables (GPT) + # =============================================== + # -g Converts any existing mbr record to a gpt record + # --clear clears any GPT partition table that already exists. + # --set-alignment=1 that we want to align partition starting sectors + # to 1 sector boundaries I think? This would normally be set to 2048 + # apparently. + + # sudo sgdisk -g --clear --set-alignment=1 \ + # --new=1:34:+$FW_JUMP_SIZE: --change-name=1:'opensbi' --typecode=1:2E54B353-1271-4842-806F-E436D6AF6985 \ + # --new=2:$KERNEL_START:+$KERNEL_SIZE --change-name=2:'kernel' --typecode=2:3000 \ + # --new=3:$FS_START:-0 --change-name=3:'filesystem' \ + # $1 + + echo -e "$NAME: Creating GUID Partition Table" + sudo sgdisk -g --clear --set-alignment=1 \ + --new=1:34:+$DST_SIZE: --change-name=1:'fdt' \ + --new=2:$FW_JUMP_START:+$FW_JUMP_SIZE --change-name=2:'opensbi' --typecode=1:2E54B353-1271-4842-806F-E436D6AF6985 \ + --new=3:$KERNEL_START:+$KERNEL_SIZE --change-name=3:'kernel' \ + --new=4:$FS_START:-0 --change-name=4:'filesystem' \ + $1 + + sudo partprobe $1 + + echo -e "$NAME: Copying binaries into their partitions." + DD_FLAGS="bs=4k iflag=fullblock oflag=direct conv=fsync status=progress" + + echo -e "$NAME: Copying device tree" + sudo dd if=$DEVICE_TREE of="$1"1 $DD_FLAGS + + echo -e "$NAME: Copying OpenSBI" + sudo dd if=$FW_JUMP of="$1"2 $DD_FLAGS + + echo -e "$NAME: Copying Kernel" + sudo dd if=$LINUX_KERNEL of="$1"3 $DD_FLAGS + + sudo mkfs.ext4 "$1"4 + sudo mkdir /mnt/$MNT_DIR + + sudo mount -v "$1"4 /mnt/$MNT_DIR + + sudo umount -v /mnt/$MNT_DIR + + sudo rmdir /mnt/$MNT_DIR + #sudo losetup -d $LOOPDEVICE +fi + +echo +echo "GPT Information for $1 ===================================" +sgdisk -p $1 diff --git a/linux/sdcard/make-img.sh b/linux/sdcard/make-img.sh new file mode 100755 index 000000000..a635d04db --- /dev/null +++ b/linux/sdcard/make-img.sh @@ -0,0 +1,110 @@ +#!/bin/bash + +# Exit on any error (return code != 0) +set -e + +# Output colors +GREEN='\033[1;32m' +NC='\033[0m' +NAME="$GREEN"${0:2}"$NC" + +# File location variables +RISCV=/opt/riscv +IMAGES=$RISCV/buildroot/output/images +FW_JUMP=$IMAGES/fw_jump.bin +LINUX_KERNEL=$IMAGES/Image +DEVICE_TREE=$IMAGES/wally-vcu108.dtb + +# Mount Directory +MNT_DIR=wallyimg + +if [ ! -z "$2" ] ; then + MNT_DIR=$2 +fi + +# If images are not built, exit +if [ ! -e $FW_JUMP ] || [ ! -e $LINUX_KERNEL ] ; then + echo 'ERROR: Missing images in buildroot output directory.' + echo ' Build images before running this script.' + exit 1 +fi + +if [ ! -e $DEVICE_TREE ] ; then + echo 'ERROR: Missing device tree file' + exit 1 +fi + +# Size of OpenSBI and the Kernel in 512B blocks +DST_SIZE=$(ls -la --block-size=512 $DEVICE_TREE | cut -d' ' -f 5 ) +FW_JUMP_SIZE=$(ls -la --block-size=512 $FW_JUMP | cut -d' ' -f 5 ) +KERNEL_SIZE=$(ls -la --block-size=512 $LINUX_KERNEL | cut -d' ' -f 5 ) + +# Start sectors of OpenSBI and Kernel Partitions +FW_JUMP_START=$(( 34 + $DST_SIZE )) +KERNEL_START=$(( $FW_JUMP_START + $FW_JUMP_SIZE )) +FS_START=$(( $KERNEL_START + $KERNEL_SIZE )) + +# Print out the sizes of the binaries in 512B blocks +echo -e "$NAME: Device tree block size: $DST_SIZE" +echo -e "$NAME: OpenSBI FW_JUMP block size: $FW_JUMP_SIZE" +echo -e "$NAME: Kernel block size: $KERNEL_SIZE" + +if [ ! -e $1 ] ; then + # Make empty image + echo -e "$NAME: Creating blank image" + sudo dd if=/dev/zero of=$1 bs=1M count=1536 + + # GUID Partition Tables (GPT) + # =============================================== + # -g Converts any existing mbr record to a gpt record + # --clear clears any GPT partition table that already exists. + # --set-alignment=1 that we want to align partition starting sectors + # to 1 sector boundaries I think? This would normally be set to 2048 + # apparently. + + # sudo sgdisk -g --clear --set-alignment=1 \ + # --new=1:34:+$FW_JUMP_SIZE: --change-name=1:'opensbi' --typecode=1:2E54B353-1271-4842-806F-E436D6AF6985 \ + # --new=2:$KERNEL_START:+$KERNEL_SIZE --change-name=2:'kernel' --typecode=2:3000 \ + # --new=3:$FS_START:-0 --change-name=3:'filesystem' \ + # $1 + + echo -e "$NAME: Creating GUID Partition Table" + sudo sgdisk -g --clear --set-alignment=1 \ + --new=1:34:+$DST_SIZE: --change-name=1:'fdt' \ + --new=2:$FW_JUMP_START:+$FW_JUMP_SIZE --change-name=2:'opensbi' --typecode=1:2E54B353-1271-4842-806F-E436D6AF6985 \ + --new=3:$KERNEL_START:+$KERNEL_SIZE --change-name=3:'kernel' \ + --new=4:$FS_START:-0 --change-name=4:'filesystem' \ + $1 + + LOOPDEVICE=$(sudo losetup -f) + echo -e "$NAME: Loop device: $LOOPDEVICE" + + sudo losetup --partscan $LOOPDEVICE $1 + + echo -e "$NAME: Copying binaries into their partitions." + DD_FLAGS="bs=4k iflag=fullblock oflag=direct conv=fsync status=progress" + # Store device tree in device tree partition + + echo -e "$NAME: Copying device tree" + sudo dd if=$DEVICE_TREE of="$LOOPDEVICE"p1 $DD_FLAGS + + echo -e "$NAME: Copying OpenSBI" + sudo dd if=$FW_JUMP of="$LOOPDEVICE"p2 $DD_FLAGS + + echo -e "$NAME: Copying Kernel" + sudo dd if=$LINUX_KERNEL of="$LOOPDEVICE"p3 $DD_FLAGS + + sudo mkfs.ext4 "$LOOPDEVICE"p4 + sudo mkdir /mnt/$MNT_DIR + + sudo mount -v "$LOOPDEVICE"p4 /mnt/$MNT_DIR + + sudo umount -v /mnt/$MNT_DIR + + sudo rmdir /mnt/$MNT_DIR + sudo losetup -d $LOOPDEVICE +fi + +echo +echo "GPT Information for $1 ===================================" +sgdisk -p $1 diff --git a/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv index d50b6c5bb..f9e9cb39d 100644 --- a/src/generic/mem/rom1p1r.sv +++ b/src/generic/mem/rom1p1r.sv @@ -96,6 +96,7 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, ROM[41] = 64'h40a7853b4015551b; ROM[42] = 64'h808210a7a02367c9;*/ + /* ROM[0] = 64'h8001819300002197; ROM[1] = 64'h4281420141014081; ROM[2] = 64'h4481440143814301; @@ -226,6 +227,151 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, ROM[127]= 64'h2000059346014681; ROM[128]= 64'h56e3cb5ff0ef4541; ROM[129]= 64'h00000000b711f005; + */ + + ROM[0]=64'h8001819300002197; + ROM[1]=64'h4281420141014081; + ROM[2]=64'h4481440143814301; + ROM[3]=64'h4681460145814501; + ROM[4]=64'h4881480147814701; + ROM[5]=64'h4a814a0149814901; + ROM[6]=64'h4c814c014b814b01; + ROM[7]=64'h4e814e014d814d01; + ROM[8]=64'h0110011b4f814f01; + ROM[9]=64'h059b45011161016e; + ROM[10]=64'h0004063705fe0010; + ROM[11]=64'h1f6000ef8006061b; + ROM[12]=64'h0ff003930000100f; + ROM[13]=64'h4e952e3110060e37; + ROM[14]=64'hc602829b0053f2b7; + ROM[15]=64'h2023fe02dfe312fd; + ROM[16]=64'h829b0053f2b7007e; + ROM[17]=64'hfe02dfe312fdc602; + ROM[18]=64'h4de31efd000e2023; + ROM[19]=64'h059bf1402573fdd0; + ROM[20]=64'h0000061705e20870; + ROM[21]=64'h0010029b01260613; + ROM[22]=64'h68110002806702fe; + ROM[23]=64'h0085179bf0080813; + ROM[24]=64'h038008130107f7b3; + ROM[25]=64'h480508a86c632781; + ROM[26]=64'h1533357902a87963; + ROM[27]=64'h38030000181700a8; + ROM[28]=64'h1c6301057833f268; + ROM[29]=64'h081a403018370808; + ROM[30]=64'h0105783342280813; + ROM[31]=64'h1815751308081063; + ROM[32]=64'h00367513c295e14d; + ROM[33]=64'h654ded510207e793; + ROM[34]=64'hc1701ff00613f130; + ROM[35]=64'h0637c530fff6861b; + ROM[36]=64'h664dcd10167d0200; + ROM[37]=64'h17fd001007b7c25c; + ROM[38]=64'h859b5a5cc20cd21c; + ROM[39]=64'h02062a23dfed0007; + ROM[40]=64'h4785fffd561c664d; + ROM[41]=64'h4501461c06f59063; + ROM[42]=64'h4a1cc35c465cc31c; + ROM[43]=64'he29dc75c4a5cc71c; + ROM[44]=64'h0c63086008138082; + ROM[45]=64'h1ae30a9008130105; + ROM[46]=64'hb7710017e793f905; + ROM[47]=64'he793b75901d7e793; + ROM[48]=64'h5f5c674db7410197; + ROM[49]=64'h66cd02072e23dffd; + ROM[50]=64'hfff78513ff7d5698; + ROM[51]=64'h40a0053300a03533; + ROM[52]=64'hbfb100a7e7938082; + ROM[53]=64'he0a2715d8082557d; + ROM[54]=64'he486f052f44ef84a; + ROM[55]=64'hfa13e85aec56fc26; + ROM[56]=64'h843289ae892a0086; + ROM[57]=64'h00959993000a1463; + ROM[58]=64'h864ac4396b054a85; + ROM[59]=64'h0009859b4549870a; + ROM[60]=64'h0004049b05540363; + ROM[61]=64'h86a66485008b7363; + ROM[62]=64'h870a87aaec7ff0ef; + ROM[63]=64'h4531458146014681; + ROM[64]=64'hf0ef0207c9639c05; + ROM[65]=64'h17820094979beb1f; + ROM[66]=64'h873e020541639381; + ROM[67]=64'h993e99ba020a1963; + ROM[68]=64'h870aa8094501f85d; + ROM[69]=64'he8bff0ef45454685; + ROM[70]=64'h60a64505fe0559e3; + ROM[71]=64'h79a2794274e26406; + ROM[72]=64'h61616b426ae27a02; + ROM[73]=64'h9301020497138082; + ROM[74]=64'hf40647057179b7f1; + ROM[75]=64'hd79867cdec26f022; + ROM[76]=64'hdff58b85571c674d; + ROM[77]=64'h2423d35c03600793; + ROM[78]=64'hfffd571c674d0207; + ROM[79]=64'h0007a737b00026f3; + ROM[80]=64'hb00027f311f70713; + ROM[81]=64'h674dfef77de38f95; + ROM[82]=64'h4f5ccf9d8b895b1c; + ROM[83]=64'h26f3cf5c0027e793; + ROM[84]=64'h071305f5e737b000; + ROM[85]=64'h8f95b00027f30ff7; + ROM[86]=64'h4f5c674dfef77de3; + ROM[87]=64'hb00026f3cf5c9bf5; + ROM[88]=64'h67f7071300989737; + ROM[89]=64'h7de38f95b00027f3; + ROM[90]=64'h458146014681fef7; + ROM[91]=64'hddbff0ef4501870a; + ROM[92]=64'h059346014681870a; + ROM[93]=64'hdcbff0ef45211aa0; + ROM[94]=64'h1aa007134782e939; + ROM[95]=64'h816393d117d24411; + ROM[96]=64'h85220ff0041302e7; + ROM[97]=64'h614564e270a27402; + ROM[98]=64'h46e3da5ff0efa0cd; + ROM[99]=64'h0207c7634782fe05; + ROM[100]=64'h458146014681870a; + ROM[101]=64'hd8bff0ef03700513; + ROM[102]=64'h46014681870a87aa; + ROM[103]=64'h0a900513403005b7; + ROM[104]=64'h4409bf7dfc07d9e3; + ROM[105]=64'hc3998b8583f9bfe1; + ROM[106]=64'h4681870a00846413; + ROM[107]=64'hf0ef450945814601; + ROM[108]=64'h870afa0540e3d59f; + ROM[109]=64'h123405b746014681; + ROM[110]=64'h46e3d45ff0ef450d; + ROM[111]=64'h870a77c14482f805; + ROM[112]=64'h85a6460146818cfd; + ROM[113]=64'h4ae3d2dff0ef451d; + ROM[114]=64'hd3d8470567cdf605; + ROM[115]=64'h000f4737b00026f3; + ROM[116]=64'hb00027f323f70713; + ROM[117]=64'h67cdfef77de38f95; + ROM[118]=64'h4681870a0007ae23; + ROM[119]=64'h0370051385a64601; + ROM[120]=64'hf2054fe3cf7ff0ef; + ROM[121]=64'h458146014681870a; + ROM[122]=64'hce3ff0ef08600513; + ROM[123]=64'h4681870af20545e3; + ROM[124]=64'h4541200005934601; + ROM[125]=64'hf0055de3ccfff0ef; + ROM[126]=64'h3023bf010113bf09; + ROM[127]=64'h4605842a86aa4081; + ROM[128]=64'h40113423850a4585; + ROM[129]=64'h86a265a6da5ff0ef; + ROM[130]=64'hd99ff0ef04084605; + ROM[131]=64'h2201358322813603; + ROM[132]=64'h86a2260508700513; + ROM[133]=64'hd81ff0ef05629e0d; + ROM[134]=64'h2a0135832a813603; + ROM[135]=64'h9e0d86a226054505; + ROM[136]=64'h3603d6bff0ef057e; + ROM[137]=64'h0513320135833281; + ROM[138]=64'h9e0d86a226054010; + ROM[139]=64'h3083d53ff0ef0556; + ROM[140]=64'h4501400134034081; + ROM[141]=64'h0000808241010113; + end // initial begin end // if (PRELOAD_ENABLED) end diff --git a/tests/custom/boot/bios.s b/tests/custom/boot/bios.s index 8057a277d..9a5d6e21f 100644 --- a/tests/custom/boot/bios.s +++ b/tests/custom/boot/bios.s @@ -87,7 +87,7 @@ delay2: # jump to the copied contents of the sd card. jumpToLinux: - csrrs a0, 0xF14, x0 # copy hard ID to a0 + csrrs a0, 0xF14, x0 # copy hart ID to a0 li a1, 0x87000000 # end of memory? not 100% sure on this but it's 112MB la a2, end_of_bios li t0, 0x80000000 # start of code diff --git a/tests/custom/boot/boot.h b/tests/custom/boot/boot.h index 0f75fbf9e..77d403145 100644 --- a/tests/custom/boot/boot.h +++ b/tests/custom/boot/boot.h @@ -15,9 +15,9 @@ typedef QWORD LBA_t; // These locations are copied from the generic configuration // of OpenSBI. These addresses can be found in: // buildroot/output/build/opensbi-0.9/platform/generic/config.mk -#define FDT_ADDRESS 0x80200000 // FW_JUMP_FDT_ADDR +#define FDT_ADDRESS 0x87000000 // FW_JUMP_FDT_ADDR #define OPENSBI_ADDRESS 0x80000000 // FW_TEXT_START -#define KERNEL_ADDRESS 0x82200000 // FW_JUMP_ADDR +#define KERNEL_ADDRESS 0x80200000 // FW_JUMP_ADDR // Export disk_read int disk_read(BYTE * buf, LBA_t sector, UINT count, BYTE card_type);