diff --git a/.gitignore b/.gitignore index 26cfe6b84..a01f1c07d 100644 --- a/.gitignore +++ b/.gitignore @@ -184,3 +184,4 @@ sim/cfi/* sim/branch/* sim/obj_dir examples/verilog/fulladder/obj_dir +config/deriv diff --git a/bin/CModelBTBAccuracy.sh b/bin/CModelBTBAccuracy.sh index 479340eb2..20a65bf98 100755 --- a/bin/CModelBTBAccuracy.sh +++ b/bin/CModelBTBAccuracy.sh @@ -9,6 +9,7 @@ ## Computes the geometric mean for btb accuracy ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/CModelBranchAccuracy.sh b/bin/CModelBranchAccuracy.sh index 8253891bb..2fb7b164a 100755 --- a/bin/CModelBranchAccuracy.sh +++ b/bin/CModelBranchAccuracy.sh @@ -9,6 +9,7 @@ ## Computes the geometric mean. ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/CacheSim.py b/bin/CacheSim.py index 24857837b..f6b2cb7e1 100755 --- a/bin/CacheSim.py +++ b/bin/CacheSim.py @@ -10,6 +10,7 @@ ## Purpose: Simulate a L1 D$ or I$ for comparison with Wally ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/SeparateBranch.sh b/bin/SeparateBranch.sh index c81ba32c9..87648589f 100755 --- a/bin/SeparateBranch.sh +++ b/bin/SeparateBranch.sh @@ -12,6 +12,7 @@ ## separated by benchmark application. Example names are aha-mot64bd_sizeopt_speed_branch.log ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/derivgen.pl b/bin/derivgen.pl new file mode 100755 index 000000000..096918400 --- /dev/null +++ b/bin/derivgen.pl @@ -0,0 +1,124 @@ +#!/bin/perl -W + +########################################### +## derivgen.pl +## +## Written: David_Harris@hmc.edu +## Created: 29 January 2024 +## Modified: +## +## Purpose: Read config/derivlist.txt and generate config/deriv/*/config.vh +## derivative configurations from the base configurations +## +## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw +## https://github.com/openhwgroup/cvw +## +## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +## +## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +## +## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +## except in compliance with the License, or, at your option, the Apache License version 2.0. You +## may obtain a copy of the License at +## +## https:##solderpad.org/licenses/SHL-2.1/ +## +## Unless required by applicable law or agreed to in writing, any work distributed under the +## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +## either express or implied. See the License for the specific language governing permissions +## and limitations under the License. +################################################################################################ + + +use strict; +use warnings; +import os; +use Data::Dumper; + +my $curderiv = ""; +my @derivlist = (); +my %derivs; +my %basederiv; + +if ($#ARGV != -1) { + die("Usage: $0") +} +my $derivlist = "$ENV{WALLY}/config/derivlist.txt"; +open(my $fh, $derivlist) or die "Could not open file '$derivlist' $!"; +foreach my $line (<$fh>) { + chomp $line; + my @tokens = split('\s+', $line); + if ($#tokens < 0 || $tokens[0] =~ /^#/) { # skip blank lines and comments + next; + } + if ($tokens[0] =~ /deriv/) { # start of a new derivative + &terminateDeriv(); + $curderiv = $tokens[1]; + $basederiv{$curderiv} = $tokens[2]; + @derivlist = (); + if ($#tokens > 2) { + my $inherits = $derivs{$tokens[3]}; + @derivlist = @{$inherits}; + } + } else { # add to the current derivative + $line =~ /\s*(\S+)\s*(.*)/; + my @entry = ($1, $2); + push(@derivlist, \@entry); + } +} +&terminateDeriv(); +close($fh); +foreach my $key (keys %derivs) { + my $dir = "$ENV{WALLY}/config/deriv/$key"; + system("rm -rf $dir"); + system("mkdir -p $dir"); + my $configunmod = "$dir/config_unmod.vh"; + my $config = "$dir/config.vh"; + my $base = "$ENV{WALLY}/config/$basederiv{$key}/config.vh"; + system("cp $base $configunmod"); + open(my $unmod, $configunmod) or die "Could not open file '$configunmod' $!"; + open(my $fh, '>>', $config) or die "Could not open file '$config' $!"; + + my $datestring = localtime(); + my %hit = (); + print $fh "// Config $key automatically derived from $basederiv{$key} on $datestring usubg derivgen.pl\n"; + foreach my $line (<$unmod>) { + foreach my $entry (@{$derivs{$key}}) { + my @ent = @{$entry}; + my $param = $ent[0]; + my $value = $ent[1]; + if ($line =~ s/$param\s*=\s*.*;/$param = $value;/) { + $hit{$param} = 1; +# print("Hit: new line in $config for $param is $line"); + } + } + print $fh $line; + } + close($fh); + close($unmod); + foreach my $entry (@{$derivs{$key}}) { + my @ent = @{$entry}; + my $param = $ent[0]; + if (!exists($hit{$param})) { + print("Unable to find $param in $key\n"); + } + } + system("rm -f $dir/config_unmod.vh"); +} + +sub terminateDeriv { + if ($curderiv ne "") { # close out the previous derivative + my @dl = @derivlist; + $derivs{$curderiv} = \@dl; + } +}; + +sub printref { + my $ref = shift; + my @array = @{$ref}; + foreach my $entry (@array) { + print join('_', @{$entry}), ', '; + } + print("\n"); +} \ No newline at end of file diff --git a/bin/elf2hex.sh b/bin/elf2hex.sh index 56f286135..d36678e9c 100755 --- a/bin/elf2hex.sh +++ b/bin/elf2hex.sh @@ -9,6 +9,7 @@ ## Imperas and riscv-arch-test benchmarks ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/exe2memfile.pl b/bin/exe2memfile.pl index 2af665bbd..4f04ff512 100755 --- a/bin/exe2memfile.pl +++ b/bin/exe2memfile.pl @@ -11,6 +11,7 @@ ## to read into a Verilog simulation with $readmemh ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/fparchtest.sh b/bin/fparchtest.sh new file mode 100755 index 000000000..7ea690e96 --- /dev/null +++ b/bin/fparchtest.sh @@ -0,0 +1,21 @@ +#!/usr/bin/bash +# +# fparchtest.sh +# David_Harris@hmc.edu 26 December 2023 +# +# Drive the riscv-isac and riscv-ctg tools to generate floating-point tests + +# Set up with (not retested) +# cd ~/repos +# git clone https://github.com/riscv/riscv-ctg.git +# git clone https://github.com/riscv/riscv-isac.git +# pip3 install git+https://github.com/riscv/riscv-ctg.git +# pip3 install git+https://github.com/riscv/riscv-isac.git +# Put ~/.local/bin in $PATH to find riscv_isac and riscv_ctg + +RISCVCTG=/home/harris/repos/riscv-ctg + +#riscv_isac --verbose debug normalize -c $RISCVCTG/sample_cgfs/dataset.cgf -c $RISCVCTG/sample_cgfs/sample_cgfs_fext/RV32F/fadd.s.cgf -o $RISCVCTG/tests/normalizedfadd.cgf -x 32 +#riscv_isac --verbose debug normalize -c $RISCVCTG/sample_cgfs/dataset.cgf -c $RISCVCTG/sample_cgfs/sample_cgfs_fext/RV32H/fadd_b1.s.cgf -o $RISCVCTG/tests/normalizedfadd16_b1.cgf -x 32 +riscv_ctg -cf $RISCVCTG/tests/normalizedfadd16_b1.cgf -d $RISCVCTG/tests --base-isa rv32i --verbose debug +#riscv_ctg -cf $RISCVCTG/sample_cgfs/dataset.cgf -cf $RISCVCTG/sample_cgfs/rv32im.cgf -d $RISCVCTG/tests --base-isa rv32i # --verbose debug diff --git a/bin/imperas-one-time.sh b/bin/imperas-one-time.sh index 404636d7c..339b4c74f 100755 --- a/bin/imperas-one-time.sh +++ b/bin/imperas-one-time.sh @@ -9,6 +9,7 @@ ## Purpose: One time setup script for running imperas. ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/libppa.pl b/bin/libppa.pl index ccf4f1548..9f1e8515d 100755 --- a/bin/libppa.pl +++ b/bin/libppa.pl @@ -13,6 +13,7 @@ ## and for TSMC change the $cellname to the actual name of the inverter. ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/parseHPMC.py b/bin/parseHPMC.py index 7e8eb7cde..73535c430 100755 --- a/bin/parseHPMC.py +++ b/bin/parseHPMC.py @@ -8,6 +8,7 @@ ## Purpose: Parses the performance counters from a modelsim trace. ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/testcount.pl b/bin/testcount.pl index e801ed0e4..139902dd3 100755 --- a/bin/testcount.pl +++ b/bin/testcount.pl @@ -12,6 +12,7 @@ ## and count how many tests are in each ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/testlist.pl b/bin/testlist.pl index 655cdd6f8..c72b96961 100755 --- a/bin/testlist.pl +++ b/bin/testlist.pl @@ -11,6 +11,7 @@ ## and generate a list of tests and signature addresses for tests.vh ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/vclean.pl b/bin/vclean.pl index f947ed9d0..294d1d435 100755 --- a/bin/vclean.pl +++ b/bin/vclean.pl @@ -11,6 +11,7 @@ ## verilator should do this, but it also reports partially used signals ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 7ccb1a138..6e7e4c8e9 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -10,6 +10,7 @@ ## Purpose: Open source tool chain installation script ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/config/buildroot/config.vh b/config/buildroot/config.vh index de6e4800d..6629af297 100644 --- a/config/buildroot/config.vh +++ b/config/buildroot/config.vh @@ -130,6 +130,10 @@ localparam logic [63:0] SPI_RANGE = 64'h00000FFF; // Bus Interface width localparam AHBW = 32'd64; +// AHB +localparam RAM_LATENCY = 32'b0; +localparam BURST_EN = 1; + // Test modes // Tie GPIO outputs back to inputs @@ -153,7 +157,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; - +localparam INSTR_CLASS_PRED = 1; localparam SVADU_SUPPORTED = 1; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/derivlist.txt b/config/derivlist.txt new file mode 100644 index 000000000..bcffb1ec5 --- /dev/null +++ b/config/derivlist.txt @@ -0,0 +1,551 @@ +########################################### +## derivlist.txt +## Wally Derivative Configuration List +## +## Written: David_Harris@hmc.edu +## Created: 29 January 2024 +## Modified: +## +## Purpose: Used by sim/make deriv to generate derivative configurations +## in config/deriv that are variants of the base configurations. +## +## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw +## +## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +## +## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +## +## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +## except in compliance with the License, or, at your option, the Apache License version 2.0. You +## may obtain a copy of the License at +## +## https:##solderpad.org/licenses/SHL-2.1/ +## +## Unless required by applicable law or agreed to in writing, any work distributed under the +## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +## either express or implied. See the License for the specific language governing permissions +## and limitations under the License. +################################################################################################ + +# Format: +# begin a derivative with "deriv +# Followed by a list of parameters and their new value in the derivative configuration +# All other parameter values are inherited from the original configuration +# If is not empty, all the list of parameter changes in the inherited +# configuration are also applied to this configuration + +# buildroot is used for the Linux boot +deriv buildroot rv64gc +RESET_VECTOR 64'h1000 +UNCORE_RAM_RANGE 64'h0FFFFFFF +UNCORE_RAM_PRELOAD 1 +GPIO_LOOPBACK_TEST 0 +SPI_LOOPBACK_TEST 0 +UART_PRESCALE 0 +PLIC_NUM_SRC 32'd53 + +# fpga is used for FPGA hardware. It adds the SDC and DDR (EXT_MEM) +deriv fpga rv64gc buildroot +BOOTROM_PRELOAD 1 +UNCORE_RAM_BASE 64'h2000 +UNCORE_RAM_RANGE 64'hFFF +EXT_MEM_SUPPORTED 1 +EXT_MEM_BASE 64'h80000000 +EXT_MEM_RANGE 64'h0FFFFFFF +SDC_SUPPORTED 1 +PLIC_SDC_ID 32'd20 +BPRED_SIZE 32'd12 + +# The syn configurations are trimmed down for faster synthesis. +deriv syn_rv32e rv32e +DTIM_RANGE 32'h1FF +IROM_RANGE 32'h1FF +BOOTROM_RANGE 32'h1FF +UNCORE_RAM_RANGE 32'h1FF +WAYSIZEINBYTES 32'd512 +NUMWAYS 32'd1 +BPRED_SIZE 32'd5 +BTB_SIZE 32'd5 + +# The other syn configurations have the same trimming +deriv syn_rv32i rv32i syn_rv32e +deriv syn_rv32imc rv32imc syn_rv32e +deriv syn_rv32gc rv32gc syn_rv32e +deriv syn_rv64i rv64i syn_rv32e +deriv syn_rv64gc rv64gc syn_rv32e + +# The syn_sram configurations use SRAM macros +deriv syn_sram_rv32e rv32e +DTIM_RANGE 32'h1FF +IROM_RANGE 32'h1FF +USE_SRAM 1 + +# The other syn configurations have the same trimming +deriv syn_sram_rv32i rv32i syn_sram_rv32e +deriv syn_sram_rv32imc rv32imc syn_sram_rv32e +deriv syn_sram_rv32gc rv32gc syn_sram_rv32e +deriv syn_sram_rv64i rv64i syn_sram_rv32e +deriv syn_sram_rv64gc rv64gc syn_sram_rv32e + +# The following syn configurations gradually turn off features +deriv syn_pmp0_rv64gc rv64gc syn_rv64gc +PMP_ENTRIES 0 +deriv syn_sram_pmp0_rv64gc rv64gc syn_sram_rv64gc +PMP_ENTRIES 0 + +deriv syn_noPriv_rv64gc rv64gc syn_pmp0_rv64gc +ZICSR_SUPPORTED 0 +deriv syn_sram_noPriv_rv64gc rv64gc syn_sram_pmp0_rv64gc +ZICSR_SUPPORTED 0 + +deriv syn_noFPU_rv64gc rv64gc syn_noPriv_rv64gc +MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +deriv syn_sram_noFPU_rv64gc rv64gc syn_sram_noPriv_rv64gc +MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) + +deriv syn_noMulDiv_rv64gc rv64gc syn_noFPU_rv64gc +MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 0) +deriv syn_sram_noMulDiv_rv64gc rv64gc syn_sram_noFPU_rv64gc +MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 0) + +deriv syn_noAtomic_rv64gc rv64gc syn_noMulDiv_rv64gc +MISA (32'h00000104 | 1 << 18 | 1 << 20) +deriv syn_sram_noAtomic_rv64gc rv64gc syn_sram_noMulDiv_rv64gc +MISA (32'h00000104 | 1 << 18 | 1 << 20) + +# Divider variants to check logical correctness + +deriv div_2_1_rv32gc rv32gc +RADIX 32'd2 +DIVCOPIES 32'd1 + +deriv div_2_2_rv32gc rv32gc +RADIX 32'd2 +DIVCOPIES 32'd2 + +deriv div_2_4_rv32gc rv32gc +RADIX 32'd2 +DIVCOPIES 32'd4 + +deriv div_4_1_rv32gc rv32gc +RADIX 32'd4 +DIVCOPIES 32'd1 + +deriv div_4_2_rv32gc rv32gc +RADIX 32'd4 +DIVCOPIES 32'd2 + +deriv div_4_4_rv32gc rv32gc +RADIX 32'd4 +DIVCOPIES 32'd4 + +deriv div_2_1i_rv32gc rv32gc div_2_1_rv32gc +IDIV_ON_FPU 1 + +deriv div_2_2i_rv32gc rv32gc div_2_2_rv32gc +IDIV_ON_FPU 1 + +deriv div_2_4i_rv32gc rv32gc div_2_4_rv32gc +IDIV_ON_FPU 1 + +deriv div_4_1i_rv32gc rv32gc div_4_1_rv32gc +IDIV_ON_FPU 1 + +deriv div_4_2i_rv32gc rv32gc div_4_2_rv32gc +IDIV_ON_FPU 1 + +deriv div_4_4i_rv32gc rv32gc div_4_4_rv32gc +IDIV_ON_FPU 1 + +deriv div_2_1_rv64gc rv64gc +RADIX 32'd2 +DIVCOPIES 32'd1 + +deriv div_2_2_rv64gc rv64gc +RADIX 32'd2 +DIVCOPIES 32'd2 + +deriv div_2_4_rv64gc rv64gc +RADIX 32'd2 +DIVCOPIES 32'd4 + +deriv div_4_1_rv64gc rv64gc +RADIX 32'd4 +DIVCOPIES 32'd1 + +deriv div_4_2_rv64gc rv64gc +RADIX 32'd4 +DIVCOPIES 32'd2 + +deriv div_4_4_rv64gc rv64gc +RADIX 32'd4 +DIVCOPIES 32'd4 + +deriv div_2_1i_rv64gc rv64gc div_2_1_rv64gc +IDIV_ON_FPU 1 + +deriv div_2_2i_rv64gc rv64gc div_2_2_rv64gc +IDIV_ON_FPU 1 + +deriv div_2_4i_rv64gc rv64gc div_2_4_rv64gc +IDIV_ON_FPU 1 + +deriv div_4_1i_rv64gc rv64gc div_4_1_rv64gc +IDIV_ON_FPU 1 + +deriv div_4_2i_rv64gc rv64gc div_4_2_rv64gc +IDIV_ON_FPU 1 + +deriv div_4_4i_rv64gc rv64gc div_4_4_rv64gc +IDIV_ON_FPU 1 + +# RAM latency and Burst mode for bus stress testing + +deriv ram_0_0_rv64gc rv64gc +RAM_LATENCY 0 +BURST_EN 0 + +deriv ram_1_0_rv64gc rv64gc +RAM_LATENCY 1 +BURST_EN 0 + +deriv ram_2_0_rv64gc rv64gc +RAM_LATENCY 2 +BURST_EN 0 + +deriv ram_1_1_rv64gc rv64gc +RAM_LATENCY 1 +BURST_EN 1 + +deriv ram_2_1_rv64gc rv64gc +RAM_LATENCY 2 +BURST_EN 1 + +# Branch predictor simulations + +deriv bpred_GSHARE_6_16_10_1_rv32gc rv32gc +BPRED_SIZE 6 + +deriv bpred_GSHARE_8_16_10_1_rv32gc rv32gc +BPRED_SIZE 8 + +deriv bpred_GSHARE_10_16_10_1_rv32gc rv32gc +BPRED_SIZE 10 + +deriv bpred_GSHARE_12_16_10_1_rv32gc rv32gc +BPRED_SIZE 12 + +deriv bpred_GSHARE_14_16_10_1_rv32gc rv32gc +BPRED_SIZE 14 + +deriv bpred_GSHARE_16_16_10_1_rv32gc rv32gc +BPRED_SIZE 16 + +deriv bpred_TWOBIT_6_16_10_1_rv32gc rv32gc bpred_GSHARE_6_16_10_1_rv32gc +BPRED_TYPE BP_TWOBIT + +deriv bpred_TWOBIT_8_16_10_1_rv32gc rv32gc bpred_GSHARE_8_16_10_1_rv32gc +BPRED_TYPE BP_TWOBIT + +deriv bpred_TWOBIT_10_16_10_1_rv32gc rv32gc bpred_GSHARE_10_16_10_1_rv32gc +BPRED_TYPE BP_TWOBIT + +deriv bpred_TWOBIT_12_16_10_1_rv32gc rv32gc bpred_GSHARE_12_16_10_1_rv32gc +BPRED_TYPE BP_TWOBIT + +deriv bpred_TWOBIT_14_16_10_1_rv32gc rv32gc bpred_GSHARE_14_16_10_1_rv32gc +BPRED_TYPE BP_TWOBIT + +deriv bpred_TWOBIT_16_16_10_1_rv32gc rv32gc bpred_GSHARE_16_16_10_1_rv32gc +BPRED_TYPE BP_TWOBIT + +deriv bpred_GSHARE_10_2_10_1_rv32gc rv32gc +RAS_SIZE 2 + +deriv bpred_GSHARE_10_3_10_1_rv32gc rv32gc +RAS_SIZE 3 + +deriv bpred_GSHARE_10_4_10_1_rv32gc rv32gc +RAS_SIZE 4 + +deriv bpred_GSHARE_10_6_10_1_rv32gc rv32gc +RAS_SIZE 6 + +deriv bpred_GSHARE_10_2_10_1_rv32gc rv32gc +RAS_SIZE 10 + +deriv bpred_GSHARE_10_16_10_1_rv32gc rv32gc +RAS_SIZE 16 + +deriv bpred_GSHARE_10_2_6_1_rv32gc rv32gc +BTB_SIZE 6 + +deriv bpred_GSHARE_10_2_8_1_rv32gc rv32gc +BTB_SIZE 8 + +deriv bpred_GSHARE_10_2_12_1_rv32gc rv32gc +BTB_SIZE 12 + +deriv bpred_GSHARE_10_2_14_1_rv32gc rv32gc +BTB_SIZE 14 + +deriv bpred_GSHARE_10_2_16_1_rv32gc rv32gc +BTB_SIZE 16 + +deriv bpred_GSHARE_6_16_10_0_rv32gc rv32gc bpred_GSHARE_6_16_10_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_GSHARE_8_16_10_0_rv32gc rv32gc bpred_GSHARE_8_16_10_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_GSHARE_10_16_10_0_rv32gc rv32gc bpred_GSHARE_10_16_10_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_GSHARE_12_16_10_0_rv32gc rv32gc bpred_GSHARE_12_16_10_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_GSHARE_14_16_10_0_rv32gc rv32gc bpred_GSHARE_14_16_10_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_GSHARE_16_16_10_0_rv32gc rv32gc bpred_GSHARE_16_16_10_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_TWOBIT_6_16_10_0_rv32gc rv32gc bpred_GSHARE_6_16_10_0_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_TWOBIT_8_16_10_0_rv32gc rv32gc bpred_GSHARE_8_16_10_0_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_TWOBIT_10_16_10_0_rv32gc rv32gc bpred_GSHARE_10_16_10_0_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_TWOBIT_12_16_10_0_rv32gc rv32gc bpred_GSHARE_12_16_10_0_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_TWOBIT_14_16_10_0_rv32gc rv32gc bpred_GSHARE_14_16_10_0_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_TWOBIT_16_16_10_0_rv32gc rv32gc bpred_GSHARE_16_16_10_0_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_GSHARE_10_2_10_0_rv32gc rv32gc bpred_GSHARE_10_2_10_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_GSHARE_10_3_10_0_rv32gc rv32gc bpred_GSHARE_10_3_10_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_GSHARE_10_4_10_0_rv32gc rv32gc bpred_GSHARE_10_4_10_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_GSHARE_10_6_10_0_rv32gc rv32gc bpred_GSHARE_10_6_10_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_GSHARE_10_2_10_0_rv32gc rv32gc bpred_GSHARE_10_2_10_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_GSHARE_10_16_10_0_rv32gc rv32gc bpred_GSHARE_10_16_10_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_GSHARE_10_2_6_0_rv32gc rv32gc bpred_GSHARE_10_2_6_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_GSHARE_10_2_8_0_rv32gc rv32gc bpred_GSHARE_10_2_8_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_GSHARE_10_2_12_0_rv32gc rv32gc bpred_GSHARE_10_2_12_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_GSHARE_10_2_14_0_rv32gc rv32gc bpred_GSHARE_10_2_14_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_GSHARE_10_2_16_0_rv32gc rv32gc bpred_GSHARE_10_2_16_1_rv32gc +INSTR_CLASS_PRED 0 + +# Cache configurations + +deriv noicache_rv32gc rv32gc +ICACHE_SUPPORTED 0 + +deriv nodcache_rv32gc rv32gc +DCACHE_SUPPORTED 0 + +deriv nocache_rv32gc rv32gc +ICACHE_SUPPORTED 0 +DCACHE_SUPPORTED 0 + +deriv way_1_4096_512_rv32gc rv32gc +DCACHE_NUMWAYS 1 +DCACHE_WAYSIZEINBYTES 4096 +DCACHE_LINELENINBITS 512 +ICACHE_NUMWAYS 1 +ICACHE_WAYSIZEINBYTES 4096 +ICACHE_LINELENINBITS 512 + +deriv way_2_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc +DCACHE_NUMWAYS 1 +ICACHE_NUMWAYS 1 + +deriv way_4_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc +DCACHE_NUMWAYS 4 +ICACHE_NUMWAYS 4 + +deriv way_8_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc +DCACHE_NUMWAYS 8 +ICACHE_NUMWAYS 8 + +deriv way_4_2048_512_rv32gc rv32gc way_4_4096_512_rv32gc +DCACHE_WAYSIZEINBYTES 2048 +ICACHE_WAYSIZEINBYTES 2048 + +deriv way_4_4096_256_rv32gc rv32gc way_4_4096_512_rv32gc +DCACHE_LINELENINBITS 256 +ICACHE_LINELENINBITS 256 + +deriv way_4_4096_1024_rv32gc rv32gc way_4_4096_512_rv32gc +DCACHE_LINELENINBITS 1024 +ICACHE_LINELENINBITS 1024 + +deriv noicache_rv64gc rv64gc +ICACHE_SUPPORTED 0 + +deriv nodcache_rv64gc rv64gc +DCACHE_SUPPORTED 0 + +deriv nocache_rv64gc rv64gc +ICACHE_SUPPORTED 0 +DCACHE_SUPPORTED 0 + +deriv way_1_4096_512_rv64gc rv64gc +DCACHE_NUMWAYS 1 +DCACHE_WAYSIZEINBYTES 4096 +DCACHE_LINELENINBITS 512 +ICACHE_NUMWAYS 1 +ICACHE_WAYSIZEINBYTES 4096 +ICACHE_LINELENINBITS 512 + +deriv way_2_4096_512_rv64gc rv64gc way_1_4096_512_rv64gc +DCACHE_NUMWAYS 1 +ICACHE_NUMWAYS 1 + +deriv way_4_4096_512_rv64gc rv64gc way_1_4096_512_rv64gc +DCACHE_NUMWAYS 4 +ICACHE_NUMWAYS 4 + +deriv way_4_2048_512_rv64gc rv64gc way_4_4096_512_rv64gc +DCACHE_WAYSIZEINBYTES 2048 +ICACHE_WAYSIZEINBYTES 2048 + +deriv way_4_4096_256_rv64gc rv64gc way_4_4096_512_rv64gc +DCACHE_LINELENINBITS 256 +ICACHE_LINELENINBITS 256 + +deriv way_4_4096_1024_rv64gc rv64gc way_4_4096_512_rv64gc +DCACHE_LINELENINBITS 1024 +ICACHE_LINELENINBITS 1024 + +# TLB Size variants + +deriv tlb2_rv32gc rv32gc +ITLB_ENTRIES 2 +DTLB_ENTRIES 2 + +deriv tlb16_rv32gc rv32gc +ITLB_ENTRIES 16 +DTLB_ENTRIES 16 + +deriv tlb2_rv64gc rv64gc +ITLB_ENTRIES 2 +DTLB_ENTRIES 2 + +deriv tlb16_rv64gc rv64gc +ITLB_ENTRIES 16 +DTLB_ENTRIES 16 + +# Feature variants + +deriv misaligned_rv32gc rv32gc +ZICCLSM_SUPPORTED 1 + +deriv nomisaligned_rv64gc rv64gc +ZICCLSM_SUPPORTED 0 + +deriv nobigendian_rv32gc rv32gc +BIGENDIAN_SUPPORTED 0 + +deriv nobigendian_rv64gc rv64gc +BIGENDIAN_SUPPORTED 0 + +# Floating-point modes supported + +deriv f_rv32gc rv32gc +MISA (32'h00000104 | 1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fh_rv32gc rv32gc +MISA (32'h00000104 | 1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdh_rv32gc rv32gc +MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdq_rv32gc rv32gc +MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fdqh_rv32gc rv32gc +MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv f_rv64gc rv64gc +MISA (32'h00000104 | 1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fh_rv64gc rv64gc +MISA (32'h00000104 | 1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fd_rv64gc rv64gc +MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fdq_rv64gc rv64gc +MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fdqh_rv64gc rv64gc +MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +# IEEE compatible variants for TestFloat + +deriv f_ieee_rv32gc rv32gc f_rv32gc +IEEE754 1 + +deriv fh_ieee_v32gc rv32gc fh_rv32gc +IEEE754 1 + +deriv fdh_ieee_rv32gc rv32gc fdh_rv32gc +IEEE754 1 + +deriv fdq_ieee_rv32gc rv32gc fdq_rv32gc +IEEE754 1 + +deriv fdqh_ieee_rv32gc rv32gc fdqh_rv32gc +IEEE754 1 + +deriv f_ieee_rv64gc rv64gc f_rv64gc +IEEE754 1 + +deriv fh_ieee_rv64gc rv64gc fh_rv64gc +IEEE754 1 + +deriv fd_ieee_rv64gc rv64gc fd_rv64gc +IEEE754 1 + +deriv fdq_ieee_rv64gc rv64gc fdq_rv64gc +IEEE754 1 + +deriv fdqh_ieee_rv64gc rv64gc fdqh_rv64gc +IEEE754 1 diff --git a/config/rv32e/config.vh b/config/rv32e/config.vh index 70d455b4e..9f0056fad 100644 --- a/config/rv32e/config.vh +++ b/config/rv32e/config.vh @@ -132,6 +132,10 @@ localparam AHBW = 32'd32; // Test modes +// AHB +localparam RAM_LATENCY = 32'b0; +localparam BURST_EN = 1; + // Tie GPIO outputs back to inputs localparam GPIO_LOOPBACK_TEST = 1; localparam SPI_LOOPBACK_TEST = 0; @@ -154,6 +158,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; +localparam INSTR_CLASS_PRED = 0; localparam SVADU_SUPPORTED = 0; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh index 4baef0075..8b4b78a4f 100644 --- a/config/rv32gc/config.vh +++ b/config/rv32gc/config.vh @@ -133,6 +133,10 @@ localparam AHBW = 32'd32; // Test modes +// AHB +localparam RAM_LATENCY = 32'b0; +localparam BURST_EN = 1; + // Tie GPIO outputs back to inputs localparam GPIO_LOOPBACK_TEST = 1; localparam SPI_LOOPBACK_TEST = 1; @@ -166,6 +170,7 @@ localparam RAS_SIZE = `RAS_SIZE; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; `endif +localparam INSTR_CLASS_PRED = 1; localparam SVADU_SUPPORTED = 1; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/rv32i/config.vh b/config/rv32i/config.vh index 6e5d08803..81b25bc2b 100644 --- a/config/rv32i/config.vh +++ b/config/rv32i/config.vh @@ -132,6 +132,10 @@ localparam AHBW = 32'd32; // Test modes +// AHB +localparam RAM_LATENCY = 32'b0; +localparam BURST_EN = 1; + // Tie GPIO outputs back to inputs localparam GPIO_LOOPBACK_TEST = 1; localparam SPI_LOOPBACK_TEST = 1; @@ -155,6 +159,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; +localparam INSTR_CLASS_PRED = 0; localparam SVADU_SUPPORTED = 0; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/rv32imc/config.vh b/config/rv32imc/config.vh index a32dc3bd6..931725cc4 100644 --- a/config/rv32imc/config.vh +++ b/config/rv32imc/config.vh @@ -131,6 +131,10 @@ localparam AHBW = 32'd32; // Test modes +// AHB +localparam RAM_LATENCY = 32'b0; +localparam BURST_EN = 1; + // Tie GPIO outputs back to inputs localparam GPIO_LOOPBACK_TEST = 1; localparam SPI_LOOPBACK_TEST = 1; @@ -153,6 +157,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; +localparam INSTR_CLASS_PRED = 0; localparam SVADU_SUPPORTED = 0; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/rv64fpquad/config.vh b/config/rv64fpquad/config.vh deleted file mode 100644 index 09885808f..000000000 --- a/config/rv64fpquad/config.vh +++ /dev/null @@ -1,182 +0,0 @@ -////////////////////////////////////////// -// config.vh -// -// Written: David_Harris@hmc.edu 4 January 2021 -// Modified: -// -// Purpose: Specify which features are configured -// Macros to determine which modes are supported based on MISA -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "BranchPredictorType.vh" - -// RV32 or RV64: XLEN = 32 or 64 -localparam XLEN = 32'd64; - -// IEEE 754 compliance -localparam IEEE754 = 1; - -// MISA RISC-V configuration per specification -localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 ); -localparam ZICSR_SUPPORTED = 1; -localparam ZIFENCEI_SUPPORTED = 1; -localparam COUNTERS = 12'd32; -localparam ZICNTR_SUPPORTED = 1; -localparam ZIHPM_SUPPORTED = 1; -localparam ZFH_SUPPORTED = 1; -localparam ZFA_SUPPORTED = 0; -localparam SSTC_SUPPORTED = 0; -localparam ZICBOM_SUPPORTED = 0; -localparam ZICBOZ_SUPPORTED = 0; -localparam ZICBOP_SUPPORTED = 0; -localparam ZICCLSM_SUPPORTED = 0; -localparam ZICOND_SUPPORTED = 0; -localparam SVPBMT_SUPPORTED = 0; -localparam SVNAPOT_SUPPORTED = 0; -localparam SVINVAL_SUPPORTED = 1; - -// LSU microarchitectural Features -localparam BUS_SUPPORTED = 1; -localparam DCACHE_SUPPORTED = 1; -localparam ICACHE_SUPPORTED = 1; -localparam VIRTMEM_SUPPORTED = 1; -localparam VECTORED_INTERRUPTS_SUPPORTED = 1 ; -localparam BIGENDIAN_SUPPORTED = 1; - -// TLB configuration. Entries should be a power of 2 -localparam ITLB_ENTRIES = 32'd32; -localparam DTLB_ENTRIES = 32'd32; - -// Cache configuration. Sizes should be a power of two -// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines -localparam DCACHE_NUMWAYS = 32'd4; -localparam DCACHE_WAYSIZEINBYTES = 32'd4096; -localparam DCACHE_LINELENINBITS = 32'd512; -localparam ICACHE_NUMWAYS = 32'd4; -localparam ICACHE_WAYSIZEINBYTES = 32'd4096; -localparam ICACHE_LINELENINBITS = 32'd512; -localparam CACHE_SRAMLEN = 32'd128; - -// Integer Divider Configuration -// IDIV_BITSPERCYCLE must be 1, 2, or 4 -localparam IDIV_BITSPERCYCLE = 32'd4; -localparam IDIV_ON_FPU = 1; - -// Legal number of PMP entries are 0, 16, or 64 -localparam PMP_ENTRIES = 32'd16; - -// Address space -localparam logic [63:0] RESET_VECTOR = 64'h0000000080000000; - -// Bus Interface width -localparam AHBW = 32'd64; - -// WFI Timeout Wait -localparam WFI_TIMEOUT_BIT = 32'd16; - -// Peripheral Physiccal Addresses -// Peripheral memory space extends from BASE to BASE+RANGE -// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits - -// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? -localparam DTIM_SUPPORTED = 1'b0; -localparam logic [63:0] DTIM_BASE = 64'h80000000; -localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF; -localparam IROM_SUPPORTED = 1'b0; -localparam logic [63:0] IROM_BASE = 64'h80000000; -localparam logic [63:0] IROM_RANGE = 64'h007FFFFF; -localparam BOOTROM_SUPPORTED = 1'b1; -localparam logic [63:0] BOOTROM_BASE = 64'h00001000; // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF; -localparam BOOTROM_PRELOAD = 1'b0; -localparam UNCORE_RAM_SUPPORTED = 1'b1; -localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000; -localparam logic [63:0] UNCORE_RAM_RANGE = 64'h7FFFFFFF; -localparam UNCORE_RAM_PRELOAD = 1'b0; -localparam EXT_MEM_SUPPORTED = 1'b0; -localparam logic [63:0] EXT_MEM_BASE = 64'h80000000; -localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF; -localparam CLINT_SUPPORTED = 1'b1; -localparam logic [63:0] CLINT_BASE = 64'h02000000; -localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF; -localparam GPIO_SUPPORTED = 1'b1; -localparam logic [63:0] GPIO_BASE = 64'h10060000; -localparam logic [63:0] GPIO_RANGE = 64'h000000FF; -localparam UART_SUPPORTED = 1'b1; -localparam logic [63:0] UART_BASE = 64'h10000000; -localparam logic [63:0] UART_RANGE = 64'h00000007; -localparam PLIC_SUPPORTED = 1'b1; -localparam logic [63:0] PLIC_BASE = 64'h0C000000; -localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF; -localparam SDC_SUPPORTED = 1'b0; -localparam logic [63:0] SDC_BASE = 64'h00013000; -localparam logic [63:0] SDC_RANGE = 64'h0000007F; -localparam SPI_SUPPORTED = 1'b1; -localparam logic [63:0] SPI_BASE = 64'h10040000; -localparam logic [63:0] SPI_RANGE = 64'h00000FFF; - -// Test modes - -// Tie GPIO outputs back to inputs -localparam GPIO_LOOPBACK_TEST = 1; -localparam SPI_LOOPBACK_TEST = 1; - -// Hardware configuration -localparam UART_PRESCALE = 32'd1; - -// Interrupt configuration -localparam PLIC_NUM_SRC = 32'd10; -// comment out the following if >=32 sources -localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32); -localparam PLIC_GPIO_ID = 32'd3; -localparam PLIC_UART_ID = 32'd10; -localparam PLIC_SPI_ID = 32'd6; -localparam PLIC_SDC_ID = 32'd9; - -localparam BPRED_SUPPORTED = 1; -localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT -localparam BPRED_SIZE = 32'd10; -localparam BPRED_NUM_LHR = 32'd6; -localparam BTB_SIZE = 32'd10; -localparam RAS_SIZE = 32'd16; - -localparam SVADU_SUPPORTED = 0; -localparam ZMMUL_SUPPORTED = 0; - -// FPU division architecture -localparam RADIX = 32'h4; -localparam DIVCOPIES = 32'h4; - -// bit manipulation -localparam ZBA_SUPPORTED = 0; -localparam ZBB_SUPPORTED = 0; -localparam ZBC_SUPPORTED = 0; -localparam ZBS_SUPPORTED = 0; - -// New compressed instructions -localparam ZCB_SUPPORTED = 0; -localparam ZCA_SUPPORTED = 0; -localparam ZCF_SUPPORTED = 0; -localparam ZCD_SUPPORTED = 0; - -// Memory synthesis configuration -localparam USE_SRAM = 0; - -`include "config-shared.vh" diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh index 04a674b47..7f038d87e 100644 --- a/config/rv64gc/config.vh +++ b/config/rv64gc/config.vh @@ -134,6 +134,10 @@ localparam logic [63:0] SPI_RANGE = 64'h00000FFF; // Test modes +// AHB +localparam RAM_LATENCY = 32'b0; +localparam BURST_EN = 1; + // Tie GPIO outputs back to inputs localparam GPIO_LOOPBACK_TEST = 1; localparam SPI_LOOPBACK_TEST = 1; @@ -156,6 +160,7 @@ localparam BPRED_NUM_LHR = 32'd6; localparam BPRED_SIZE = 32'd10; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; +localparam INSTR_CLASS_PRED = 1; localparam SVADU_SUPPORTED = 1; localparam ZMMUL_SUPPORTED = 0; @@ -180,3 +185,4 @@ localparam ZCD_SUPPORTED = 0; localparam USE_SRAM = 0; `include "config-shared.vh" + diff --git a/config/rv64i/config.vh b/config/rv64i/config.vh index 609a50f97..4dd540a9f 100644 --- a/config/rv64i/config.vh +++ b/config/rv64i/config.vh @@ -134,6 +134,10 @@ localparam logic [63:0] SPI_RANGE = 64'h00000FFF; // Test modes +// AHB +localparam RAM_LATENCY = 32'b0; +localparam BURST_EN = 1; + // Tie GPIO outputs back to inputs localparam GPIO_LOOPBACK_TEST = 1; localparam SPI_LOOPBACK_TEST = 1; @@ -156,6 +160,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; +localparam INSTR_CLASS_PRED = 0; localparam SVADU_SUPPORTED = 0; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh index 7dc0a0bcf..bf4c11198 100644 --- a/config/shared/parameter-defs.vh +++ b/config/shared/parameter-defs.vh @@ -8,6 +8,8 @@ localparam cvw_t P = '{ IEEE754 : IEEE754, MISA : MISA, AHBW : AHBW, + RAM_LATENCY : RAM_LATENCY, + BURST_EN : BURST_EN, ZICSR_SUPPORTED : ZICSR_SUPPORTED, ZIFENCEI_SUPPORTED : ZIFENCEI_SUPPORTED, COUNTERS : COUNTERS, diff --git a/docs/Dockerfile b/docs/Dockerfile index b06f9ad67..8df933363 100755 --- a/docs/Dockerfile +++ b/docs/Dockerfile @@ -7,6 +7,7 @@ ## Purpose: Dockerfile for Wally docker container creation ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/fpga/generator/insert_debug_comment.sh b/fpga/generator/insert_debug_comment.sh index 66c232e16..35fa05a02 100755 --- a/fpga/generator/insert_debug_comment.sh +++ b/fpga/generator/insert_debug_comment.sh @@ -7,6 +7,7 @@ ## Modified: 20 January 2023 ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/fpga/probe b/fpga/probe index 21e5d8240..1cf1104c1 100755 --- a/fpga/probe +++ b/fpga/probe @@ -7,6 +7,7 @@ ## Modified: 16 August 2023 ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/fpga/proberange b/fpga/proberange index 715cba46e..73bfc3383 100755 --- a/fpga/proberange +++ b/fpga/proberange @@ -7,6 +7,7 @@ ## Modified: 16 August 2023 ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/fpga/probes b/fpga/probes index 83c2ddf7c..1ea571057 100755 --- a/fpga/probes +++ b/fpga/probes @@ -7,6 +7,7 @@ ## Modified: 16 August 2023 ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/gitflow.txt b/gitflow.txt index 57300830a..f6f70de74 100644 --- a/gitflow.txt +++ b/gitflow.txt @@ -1,5 +1,6 @@ ########################################### ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/sim/Makefile b/sim/Makefile index 5889d1df9..d7d259632 100644 --- a/sim/Makefile +++ b/sim/Makefile @@ -1,5 +1,5 @@ -all: riscoftests memfiles coveragetests +all: riscoftests memfiles coveragetests deriv # *** Build old tests/imperas-riscv-tests for now; # Delete this part when the privileged tests transition over to tests/wally-riscv-arch-test # DH: 2/27/22 temporarily commented out imperas-riscv-tests because license expired @@ -60,3 +60,7 @@ memfiles: coveragetests: make -C ../tests/coverage/ --jobs + +deriv: + derivgen.pl + \ No newline at end of file diff --git a/sim/coverage-exclusions-rv64gc.do b/sim/coverage-exclusions-rv64gc.do index e39128f5a..b6eb0214f 100644 --- a/sim/coverage-exclusions-rv64gc.do +++ b/sim/coverage-exclusions-rv64gc.do @@ -7,6 +7,7 @@ #// For example, signals hardwired to 0 should not be checked for toggle coverage #// #// A component of the CORE-V-WALLY configurable RISC-V project. +#// https://github.com/openhwgroup/cvw #// #// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University #// diff --git a/sim/lint-wally b/sim/lint-wally index eb6ad62b0..3125e79ea 100755 --- a/sim/lint-wally +++ b/sim/lint-wally @@ -1,14 +1,14 @@ #!/bin/bash # check for warnings in Verilog code -# The verilator lint tool is faster and better than Modelsim so it is best to run this first. +# The verilator lint tool is faster and better than Questa so it is best to run this first. export PATH=$PATH:/usr/local/bin/ verilator=`which verilator` basepath=$(dirname $0)/.. -for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i rv64fpquad; do +for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i fdqh_rv64gc; do #for config in rv64gc; do echo "$config linting..." - if !($verilator --no-timing --lint-only "$@" --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then + if !($verilator --no-timing --lint-only "$@" --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then echo "Exiting after $config lint due to errors or warnings" exit 1 fi diff --git a/sim/rv64gc_CacheSim.py b/sim/rv64gc_CacheSim.py index 42f21c8c6..bc75fc13a 100755 --- a/sim/rv64gc_CacheSim.py +++ b/sim/rv64gc_CacheSim.py @@ -10,6 +10,7 @@ ## Purpose: Run the cache simulator on each rv64gc test suite in turn. ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/sim/sim-imperas b/sim/sim-imperas index aa1dc3a01..556cdebf6 100755 --- a/sim/sim-imperas +++ b/sim/sim-imperas @@ -10,6 +10,7 @@ ## Purpose: Run wally with imperas ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/sim/sim-testfloat b/sim/sim-testfloat index 7f22690c0..b7da7104a 100755 --- a/sim/sim-testfloat +++ b/sim/sim-testfloat @@ -9,4 +9,4 @@ # sqrt - test square root # all - test everything -vsim -do "do testfloat.do rv64fpquad $1" +vsim -do "do testfloat.do fdqh_ieee_rv64gc $1" diff --git a/sim/sim-testfloat-batch b/sim/sim-testfloat-batch index 073553e52..96fb0f345 100755 --- a/sim/sim-testfloat-batch +++ b/sim/sim-testfloat-batch @@ -10,4 +10,4 @@ # sqrt - test square root # all - test everything -vsim -c -do "do testfloat.do rv64fpquad $1" \ No newline at end of file +vsim -c -do "do testfloat.do fdqh_ieee_rv64gc $1" diff --git a/sim/testfloat.do b/sim/testfloat.do index f21975389..796b540f3 100644 --- a/sim/testfloat.do +++ b/sim/testfloat.do @@ -25,7 +25,7 @@ vlib work # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals # $num = the added words after the call -vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697 +vlog +incdir+../config/deriv/$1 +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697 # Change TEST_SIZE to only test certain FP width # values are QP, DP, SP, HP or all for all tests diff --git a/src/cache/cache.sv b/src/cache/cache.sv index 86aba57a0..4a97a29d4 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 7 (Figures 7.9, 7.10, and 7.19) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv index b593f2ae6..70f129d4b 100644 --- a/src/cache/cacheLRU.sv +++ b/src/cache/cacheLRU.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 7 (Figures 7.8 and 7.15 to 7.18) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index 07494c2a9..0d3b2c0e0 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.14 and Table 7.1) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index 9c5523cec..b2be76838 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.11) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/cache/subcachelineread.sv b/src/cache/subcachelineread.sv index db80cfc83..95920ec7e 100644 --- a/src/cache/subcachelineread.sv +++ b/src/cache/subcachelineread.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 7 // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/cvw.sv b/src/cvw.sv index a9ee9d093..c9d737d8f 100644 --- a/src/cvw.sv +++ b/src/cvw.sv @@ -41,6 +41,8 @@ typedef struct packed { logic IEEE754; // IEEE754 NaN handling (0 = use RISC-V NaN propagation instead) int MISA; // Machine Instruction Set Architecture int AHBW; // AHB bus width (usually = XLEN) + int RAM_LATENCY; // Latency to stress AHB + logic BURST_EN; // Support AHB Burst Mode // RISC-V Features logic ZICSR_SUPPORTED; diff --git a/src/ebu/ahbcacheinterface.sv b/src/ebu/ahbcacheinterface.sv index 5f2dff313..f033b40cc 100644 --- a/src/ebu/ahbcacheinterface.sv +++ b/src/ebu/ahbcacheinterface.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.8) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -27,10 +28,8 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module ahbcacheinterface #( - parameter AHBW, - parameter LLEN, - parameter PA_BITS, +module ahbcacheinterface import cvw::*; #( + parameter cvw_t P, parameter BEATSPERLINE, // Number of AHBW words (beats) in cacheline parameter AHBWLOGBWPL, // Log2 of ^ parameter LINELEN, // Number of bits in cacheline @@ -45,14 +44,14 @@ module ahbcacheinterface #( output logic [2:0] HSIZE, // AHB transaction width output logic [2:0] HBURST, // AHB burst length // bus interface buses - input logic [AHBW-1:0] HRDATA, // AHB read data - output logic [PA_BITS-1:0] HADDR, // AHB address - output logic [AHBW-1:0] HWDATA, // AHB write data - output logic [AHBW/8-1:0] HWSTRB, // AHB byte mask + input logic [P.AHBW-1:0] HRDATA, // AHB read data + output logic [P.PA_BITS-1:0] HADDR, // AHB address + output logic [P.AHBW-1:0] HWDATA, // AHB write data + output logic [P.AHBW/8-1:0] HWSTRB, // AHB byte mask // cache interface - input logic [PA_BITS-1:0] CacheBusAdr, // Address of cache line - input logic [LLEN-1:0] CacheReadDataWordM, // One word of cache line during a writeback + input logic [P.PA_BITS-1:0] CacheBusAdr, // Address of cache line + input logic [P.LLEN-1:0] CacheReadDataWordM, // One word of cache line during a writeback input logic CacheableOrFlushCacheM, // Memory operation is cacheable or flushing D$ input logic Cacheable, // Memory operation is cachable input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch @@ -62,8 +61,8 @@ module ahbcacheinterface #( output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr // uncached interface - input logic [PA_BITS-1:0] PAdr, // Physical address of uncached memory operation - input logic [LLEN-1:0] WriteDataM, // IEU write data for uncached store + input logic [P.PA_BITS-1:0] PAdr, // Physical address of uncached memory operation + input logic [P.LLEN-1:0] WriteDataM, // IEU write data for uncached store input logic [1:0] BusRW, // Uncached memory operation read/write control: 10: read, 01: write input logic BusAtomic, // Uncache atomic memory operation input logic [2:0] Funct3, // Size of uncached memory operation @@ -77,12 +76,12 @@ module ahbcacheinterface #( localparam BeatCountThreshold = BEATSPERLINE - 1; // Largest beat index - logic [PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation + logic [P.PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation logic [AHBWLOGBWPL-1:0] BeatCountDelayed; // Beat within the cache line in the second (Data) cache stage logic CaptureEn; // Enable updating the Fetch buffer with valid data from HRDATA - logic [AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s - logic [AHBW-1:0] PreHWDATA; // AHB Address phase write data - logic [PA_BITS-1:0] PAdrZero; + logic [P.AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s + logic [P.AHBW-1:0] PreHWDATA; // AHB Address phase write data + logic [P.PA_BITS-1:0] PAdrZero; genvar index; @@ -90,38 +89,38 @@ module ahbcacheinterface #( for (index = 0; index < BEATSPERLINE; index++) begin:fetchbuffer logic [BEATSPERLINE-1:0] CaptureBeat; assign CaptureBeat[index] = CaptureEn & (index == BeatCountDelayed); - flopen #(AHBW) fb(.clk(HCLK), .en(CaptureBeat[index]), .d(HRDATA), - .q(FetchBuffer[(index+1)*AHBW-1:index*AHBW])); + flopen #(P.AHBW) fb(.clk(HCLK), .en(CaptureBeat[index]), .d(HRDATA), + .q(FetchBuffer[(index+1)*P.AHBW-1:index*P.AHBW])); end - assign PAdrZero = BusCMOZero ? {PAdr[PA_BITS-1:$clog2(LINELEN/8)], {$clog2(LINELEN/8){1'b0}}} : PAdr; - mux2 #(PA_BITS) localadrmux(PAdrZero, CacheBusAdr, Cacheable, LocalHADDR); - assign HADDR = ({{PA_BITS-AHBWLOGBWPL{1'b0}}, BeatCount} << $clog2(AHBW/8)) + LocalHADDR; + assign PAdrZero = BusCMOZero ? {PAdr[P.PA_BITS-1:$clog2(LINELEN/8)], {$clog2(LINELEN/8){1'b0}}} : PAdr; + mux2 #(P.PA_BITS) localadrmux(PAdrZero, CacheBusAdr, Cacheable, LocalHADDR); + assign HADDR = ({{P.PA_BITS-AHBWLOGBWPL{1'b0}}, BeatCount} << $clog2(P.AHBW/8)) + LocalHADDR; - mux2 #(3) sizemux(.d0(Funct3), .d1(AHBW == 32 ? 3'b010 : 3'b011), .s(Cacheable | BusCMOZero), .y(HSIZE)); + mux2 #(3) sizemux(.d0(Funct3), .d1(P.AHBW == 32 ? 3'b010 : 3'b011), .s(Cacheable | BusCMOZero), .y(HSIZE)); // When AHBW is less than LLEN need extra muxes to select the subword from cache's read data. - logic [AHBW-1:0] CacheReadDataWordAHB; + logic [P.AHBW-1:0] CacheReadDataWordAHB; if(LLENPOVERAHBW > 1) begin - logic [AHBW-1:0] AHBWordSets [(LLENPOVERAHBW)-1:0]; + logic [P.AHBW-1:0] AHBWordSets [(LLENPOVERAHBW)-1:0]; genvar index; for (index = 0; index < LLENPOVERAHBW; index++) begin:readdatalinesetsmux - assign AHBWordSets[index] = CacheReadDataWordM[(index*AHBW)+AHBW-1: (index*AHBW)]; + assign AHBWordSets[index] = CacheReadDataWordM[(index*P.AHBW)+P.AHBW-1: (index*P.AHBW)]; end assign CacheReadDataWordAHB = AHBWordSets[BeatCount[$clog2(LLENPOVERAHBW)-1:0]]; - end else assign CacheReadDataWordAHB = CacheReadDataWordM[AHBW-1:0]; + end else assign CacheReadDataWordAHB = CacheReadDataWordM[P.AHBW-1:0]; - mux2 #(AHBW) HWDATAMux(.d0(CacheReadDataWordAHB), .d1(WriteDataM[AHBW-1:0]), + mux2 #(P.AHBW) HWDATAMux(.d0(CacheReadDataWordAHB), .d1(WriteDataM[P.AHBW-1:0]), .s(~(CacheableOrFlushCacheM)), .y(PreHWDATA)); - flopen #(AHBW) wdreg(HCLK, HREADY, PreHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec + flopen #(P.AHBW) wdreg(HCLK, HREADY, PreHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec // *** bummer need a second byte mask for bus as it is AHBW rather than LLEN. // probably can merge by muxing PAdrM's LLEN/8-1 index bit based on HTRANS being != 0. - swbytemask #(AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(AHBW/8)-1:0]), .ByteMask(BusByteMaskM), .ByteMaskExtended()); + swbytemask #(P.AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(P.AHBW/8)-1:0]), .ByteMask(BusByteMaskM), .ByteMaskExtended()); - flopen #(AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[AHBW/8-1:0], HWSTRB); + flopen #(P.AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[P.AHBW/8-1:0], HWSTRB); - buscachefsm #(BeatCountThreshold, AHBWLOGBWPL, READ_ONLY_CACHE) AHBBuscachefsm( + buscachefsm #(BeatCountThreshold, AHBWLOGBWPL, READ_ONLY_CACHE, P.BURST_EN) AHBBuscachefsm( .HCLK, .HRESETn, .Flush, .BusRW, .BusAtomic, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat, .CacheBusRW, .BusCMOZero, .CacheBusAck, .BeatCount, .BeatCountDelayed, .HREADY, .HTRANS, .HWRITE, .HBURST); diff --git a/src/ebu/ahbinterface.sv b/src/ebu/ahbinterface.sv index df84175f0..8852b52c3 100644 --- a/src/ebu/ahbinterface.sv +++ b/src/ebu/ahbinterface.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.21) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv index 8d434c678..75f444e4b 100644 --- a/src/ebu/buscachefsm.sv +++ b/src/ebu/buscachefsm.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.9) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -27,13 +28,12 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`define BURST_EN 1 // Enables burst mode. Disable to show the lost performance. - // HCLK and clk must be the same clock! module buscachefsm #( parameter BeatCountThreshold, // Largest beat index parameter AHBWLOGBWPL, // Log2 of BEATSPERLINE - parameter READ_ONLY_CACHE + parameter READ_ONLY_CACHE, // 1 for read-only instruction cache + parameter BURST_EN // burst mode supported )( input logic HCLK, input logic HRESETn, @@ -141,11 +141,11 @@ module buscachefsm #( assign HTRANS = (CurrState == ADR_PHASE & HREADY & ((|BusRW) | (|CacheBusRW) | BusCMOZero) & ~Flush) | (CurrState == ATOMIC_READ_DATA_PHASE & BusAtomic) | (CacheAccess & FinalBeatCount & |CacheBusRW & HREADY & ~Flush) ? AHB_NONSEQ : // if we have a pipelined request - (CacheAccess & |BeatCount) ? (`BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE; + (CacheAccess & |BeatCount) ? (BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE; assign HWRITE = ((BusRW[0] & ~BusAtomic) | BusWrite & ~Flush) | (CurrState == ATOMIC_READ_DATA_PHASE & BusAtomic) | (CurrState == CACHE_WRITEBACK & |BeatCount); - assign HBURST = `BURST_EN & ((|CacheBusRW & ~Flush) | (CacheAccess & |BeatCount)) ? LocalBurstType : 3'b0; + assign HBURST = BURST_EN & ((|CacheBusRW & ~Flush) | (CacheAccess & |BeatCount)) ? LocalBurstType : 3'b0; always_comb begin case(BeatCountThreshold) diff --git a/src/ebu/busfsm.sv b/src/ebu/busfsm.sv index 81d11715e..e49a6313a 100644 --- a/src/ebu/busfsm.sv +++ b/src/ebu/busfsm.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.23) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ebu/controllerinput.sv b/src/ebu/controllerinput.sv index 60df9e44b..67e4795a6 100644 --- a/src/ebu/controllerinput.sv +++ b/src/ebu/controllerinput.sv @@ -14,6 +14,7 @@ // Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.25) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ebu/ebu.sv b/src/ebu/ebu.sv index 4a1b00b57..b91eb75b0 100644 --- a/src/ebu/ebu.sv +++ b/src/ebu/ebu.sv @@ -14,6 +14,7 @@ // Documentation: RISC-V System on Chip Design Chapter 6 (Figures 6.25 and 6.26) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -31,31 +32,31 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module ebu #(parameter XLEN, PA_BITS, AHBW)( +module ebu import cvw::*; #(parameter cvw_t P) ( input logic clk, reset, // Signals from IFU input logic [1:0] IFUHTRANS, // IFU AHB transaction request input logic [2:0] IFUHSIZE, // IFU AHB transaction size input logic [2:0] IFUHBURST, // IFU AHB burst length - input logic [PA_BITS-1:0] IFUHADDR, // IFU AHB address + input logic [P.PA_BITS-1:0] IFUHADDR, // IFU AHB address output logic IFUHREADY, // AHB peripheral ready gated by possible non-grant // Signals from LSU input logic [1:0] LSUHTRANS, // LSU AHB transaction request input logic LSUHWRITE, // LSU AHB transaction direction. 1: write, 0: read input logic [2:0] LSUHSIZE, // LSU AHB size input logic [2:0] LSUHBURST, // LSU AHB burst length - input logic [PA_BITS-1:0] LSUHADDR, // LSU AHB address - input logic [XLEN-1:0] LSUHWDATA, // initially support AHBW = XLEN - input logic [XLEN/8-1:0] LSUHWSTRB, // AHB byte mask + input logic [P.PA_BITS-1:0] LSUHADDR, // LSU AHB address + input logic [P.XLEN-1:0] LSUHWDATA, // initially support AHBW = XLEN + input logic [P.XLEN/8-1:0] LSUHWSTRB, // AHB byte mask output logic LSUHREADY, // AHB peripheral. Never gated as LSU always has priority // AHB-Lite external signals output logic HCLK, HRESETn, input logic HREADY, // AHB peripheral ready input logic HRESP, // AHB peripheral response. 0: OK 1: Error. Presently ignored. - output logic [PA_BITS-1:0] HADDR, // AHB address to peripheral after arbitration - output logic [AHBW-1:0] HWDATA, // AHB Write data after arbitration - output logic [XLEN/8-1:0] HWSTRB, // AHB byte write enables after arbitration + output logic [P.PA_BITS-1:0] HADDR, // AHB address to peripheral after arbitration + output logic [P.AHBW-1:0] HWDATA, // AHB Write data after arbitration + output logic [P.XLEN/8-1:0] HWSTRB, // AHB byte write enables after arbitration output logic HWRITE, // AHB transaction direction after arbitration output logic [2:0] HSIZE, // AHB transaction size after arbitration output logic [2:0] HBURST, // AHB burst length after arbitration @@ -71,13 +72,13 @@ module ebu #(parameter XLEN, PA_BITS, AHBW)( logic IFUDisable; logic IFUSelect; - logic [PA_BITS-1:0] IFUHADDROut; + logic [P.PA_BITS-1:0] IFUHADDROut; logic [1:0] IFUHTRANSOut; logic [2:0] IFUHBURSTOut; logic [2:0] IFUHSIZEOut; logic IFUHWRITEOut; - logic [PA_BITS-1:0] LSUHADDROut; + logic [P.PA_BITS-1:0] LSUHADDROut; logic [1:0] LSUHTRANSOut; logic [2:0] LSUHBURSTOut; logic [2:0] LSUHSIZEOut; @@ -96,14 +97,14 @@ module ebu #(parameter XLEN, PA_BITS, AHBW)( // input stages and muxing for IFU and LSU //////////////////////////////////////////////////////////////////////////////////////////////////// - controllerinput #(PA_BITS) IFUInput(.HCLK, .HRESETn, .Save(IFUSave), .Restore(IFURestore), .Disable(IFUDisable), + controllerinput #(P.PA_BITS) IFUInput(.HCLK, .HRESETn, .Save(IFUSave), .Restore(IFURestore), .Disable(IFUDisable), .Request(IFUReq), .HWRITEIn(1'b0), .HSIZEIn(IFUHSIZE), .HBURSTIn(IFUHBURST), .HTRANSIn(IFUHTRANS), .HADDRIn(IFUHADDR), .HWRITEOut(IFUHWRITEOut), .HSIZEOut(IFUHSIZEOut), .HBURSTOut(IFUHBURSTOut), .HREADYOut(IFUHREADY), .HTRANSOut(IFUHTRANSOut), .HADDROut(IFUHADDROut), .HREADYIn(HREADY)); // LSU always has priority so there should never be a need to save and restore the address phase inputs. - controllerinput #(PA_BITS, 0) LSUInput(.HCLK, .HRESETn, .Save(1'b0), .Restore(1'b0), .Disable(LSUDisable), + controllerinput #(P.PA_BITS, 0) LSUInput(.HCLK, .HRESETn, .Save(1'b0), .Restore(1'b0), .Disable(LSUDisable), .Request(LSUReq), .HWRITEIn(LSUHWRITE), .HSIZEIn(LSUHSIZE), .HBURSTIn(LSUHBURST), .HTRANSIn(LSUHTRANS), .HADDRIn(LSUHADDR), .HREADYOut(LSUHREADY), .HWRITEOut(LSUHWRITEOut), .HSIZEOut(LSUHSIZEOut), .HBURSTOut(LSUHBURSTOut), diff --git a/src/ebu/ebufsmarb.sv b/src/ebu/ebufsmarb.sv index 302c4752f..55ba9a506 100644 --- a/src/ebu/ebufsmarb.sv +++ b/src/ebu/ebufsmarb.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 6 (Figures 6.25 and 6.26) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fclassify.sv b/src/fpu/fclassify.sv index bfc7a53dd..f35f71869 100644 --- a/src/fpu/fclassify.sv +++ b/src/fpu/fclassify.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fcmp.sv b/src/fpu/fcmp.sv index 227676203..0944090fc 100755 --- a/src/fpu/fcmp.sv +++ b/src/fpu/fcmp.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index 705a112d1..60edbfd8a 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrt.sv b/src/fpu/fdivsqrt/fdivsqrt.sv index a4e20f229..85a1a5494 100644 --- a/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/src/fpu/fdivsqrt/fdivsqrt.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtcycles.sv b/src/fpu/fdivsqrt/fdivsqrtcycles.sv index 1e6eda56c..2649632eb 100644 --- a/src/fpu/fdivsqrt/fdivsqrtcycles.sv +++ b/src/fpu/fdivsqrt/fdivsqrtcycles.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv index bbb2d9360..d24b490ab 100644 --- a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtfgen2.sv b/src/fpu/fdivsqrt/fdivsqrtfgen2.sv index cf398f570..bc9dce536 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfgen2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfgen2.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtfgen4.sv b/src/fpu/fdivsqrt/fdivsqrtfgen4.sv index e2cec1ab4..a04523e58 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfgen4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfgen4.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/src/fpu/fdivsqrt/fdivsqrtfsm.sv index cd890ed87..f7d21e5d8 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfsm.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfsm.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtiter.sv b/src/fpu/fdivsqrt/fdivsqrtiter.sv index 863d94837..20f88b6cb 100644 --- a/src/fpu/fdivsqrt/fdivsqrtiter.sv +++ b/src/fpu/fdivsqrt/fdivsqrtiter.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index 5a40a3bdc..c3954bc0a 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index 939b9c133..1c56e04e5 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtstage2.sv b/src/fpu/fdivsqrt/fdivsqrtstage2.sv index 40a2a5a01..c3d6e210c 100644 --- a/src/fpu/fdivsqrt/fdivsqrtstage2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtstage2.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtstage4.sv b/src/fpu/fdivsqrt/fdivsqrtstage4.sv index a24c1155f..0d7a722ff 100644 --- a/src/fpu/fdivsqrt/fdivsqrtstage4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtstage4.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv b/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv index c895fa2ce..032bb700e 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv b/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv index b12b9174b..19e322013 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtuslc2.sv b/src/fpu/fdivsqrt/fdivsqrtuslc2.sv index e4fcfeadf..2d4cd5e48 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuslc2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuslc2.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtuslc4.sv b/src/fpu/fdivsqrt/fdivsqrtuslc4.sv index b44b34a35..63ea5aae2 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuslc4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuslc4.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv b/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv index ccb5e618a..c0cbe9b1c 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fhazard.sv b/src/fpu/fhazard.sv index 14f8c945f..e68934294 100644 --- a/src/fpu/fhazard.sv +++ b/src/fpu/fhazard.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fli.sv b/src/fpu/fli.sv index e61415388..cf3b736d7 100644 --- a/src/fpu/fli.sv +++ b/src/fpu/fli.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 16 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -174,7 +175,7 @@ module fli import cvw::*; #(parameter cvw_t P) ( //////////////////////////// if (P.Q_SUPPORTED) begin - logic [63:0] QImm; + logic [127:0] QImm; always_comb begin case(Rs1) 0: QImm = 128'hBFFF0000000000000000000000000000; diff --git a/src/fpu/fma/fma.sv b/src/fpu/fma/fma.sv index a6e87a240..321bfe8bc 100644 --- a/src/fpu/fma/fma.sv +++ b/src/fpu/fma/fma.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.7, 9) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fma/fmaadd.sv b/src/fpu/fma/fmaadd.sv index 98ff21491..1ad3b0b83 100644 --- a/src/fpu/fma/fmaadd.sv +++ b/src/fpu/fma/fmaadd.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.11) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fma/fmaalign.sv b/src/fpu/fma/fmaalign.sv index efc4a4c5f..9001742e4 100644 --- a/src/fpu/fma/fmaalign.sv +++ b/src/fpu/fma/fmaalign.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.10) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fma/fmaexpadd.sv b/src/fpu/fma/fmaexpadd.sv index bb7bf2437..06ac7e290 100644 --- a/src/fpu/fma/fmaexpadd.sv +++ b/src/fpu/fma/fmaexpadd.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.9) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fma/fmalza.sv b/src/fpu/fma/fmalza.sv index 66659665a..822f857c2 100644 --- a/src/fpu/fma/fmalza.sv +++ b/src/fpu/fma/fmalza.sv @@ -10,6 +10,7 @@ // See also [Schmookler & Nowka, Leading zero anticipation and detection, IEEE Sym. Computer Arithmetic, 2001] // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fma/fmamult.sv b/src/fpu/fma/fmamult.sv index 91f255b87..8ce492f03 100644 --- a/src/fpu/fma/fmamult.sv +++ b/src/fpu/fma/fmamult.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.7) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fma/fmasign.sv b/src/fpu/fma/fmasign.sv index aca6c8f8c..2a8b827d2 100644 --- a/src/fpu/fma/fmasign.sv +++ b/src/fpu/fma/fmasign.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.8) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fpu.sv b/src/fpu/fpu.sv index 05d5f2e00..90ec10dee 100755 --- a/src/fpu/fpu.sv +++ b/src/fpu/fpu.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fregfile.sv b/src/fpu/fregfile.sv index 6ab14df20..2de41088b 100644 --- a/src/fpu/fregfile.sv +++ b/src/fpu/fregfile.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fsgninj.sv b/src/fpu/fsgninj.sv index cee13f4f9..4fe03522b 100755 --- a/src/fpu/fsgninj.sv +++ b/src/fpu/fsgninj.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/cvtshiftcalc.sv b/src/fpu/postproc/cvtshiftcalc.sv index 77b8543fd..8b7587e49 100644 --- a/src/fpu/postproc/cvtshiftcalc.sv +++ b/src/fpu/postproc/cvtshiftcalc.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -98,6 +99,6 @@ module cvtshiftcalc import cvw::*; #(parameter cvw_t P) ( // determine if the result underflows ??? -> fp // - if the first 1 is shifted out of the result then the result underflows // - can't underflow an integer to fp conversions - assign CvtResUf = ($signed(CvtCe) < $signed({{P.NE-$clog2(P.NF){1'b1}}, ResNegNF}))&~XZero; // dh &~IntToFp not necessary because integer to float conversion never underflows + assign CvtResUf = ($signed(CvtCe) < $signed({{P.NE-$clog2(P.NF){1'b1}}, ResNegNF}))&~XZero&~IntToFp; endmodule diff --git a/src/fpu/postproc/divshiftcalc.sv b/src/fpu/postproc/divshiftcalc.sv index 9e5de7173..0a222d724 100644 --- a/src/fpu/postproc/divshiftcalc.sv +++ b/src/fpu/postproc/divshiftcalc.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/flags.sv b/src/fpu/postproc/flags.sv index 40fe887ca..21160e0c5 100644 --- a/src/fpu/postproc/flags.sv +++ b/src/fpu/postproc/flags.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/fmashiftcalc.sv b/src/fpu/postproc/fmashiftcalc.sv index b13b6d3da..e16f51615 100644 --- a/src/fpu/postproc/fmashiftcalc.sv +++ b/src/fpu/postproc/fmashiftcalc.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/negateintres.sv b/src/fpu/postproc/negateintres.sv index d0aaf760b..5ca848b0b 100644 --- a/src/fpu/postproc/negateintres.sv +++ b/src/fpu/postproc/negateintres.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/normshift.sv b/src/fpu/postproc/normshift.sv index f24a75fe1..f235d4d5b 100644 --- a/src/fpu/postproc/normshift.sv +++ b/src/fpu/postproc/normshift.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/postprocess.sv b/src/fpu/postproc/postprocess.sv index 1d51fdf85..e30058538 100644 --- a/src/fpu/postproc/postprocess.sv +++ b/src/fpu/postproc/postprocess.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/resultsign.sv b/src/fpu/postproc/resultsign.sv index 0dd22c1f4..2d5587dcf 100644 --- a/src/fpu/postproc/resultsign.sv +++ b/src/fpu/postproc/resultsign.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/round.sv b/src/fpu/postproc/round.sv index 445f563d9..aae3d68f4 100644 --- a/src/fpu/postproc/round.sv +++ b/src/fpu/postproc/round.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/roundsign.sv b/src/fpu/postproc/roundsign.sv index 6c1135602..521675ac4 100644 --- a/src/fpu/postproc/roundsign.sv +++ b/src/fpu/postproc/roundsign.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/shiftcorrection.sv b/src/fpu/postproc/shiftcorrection.sv index f5860b42d..275ee4cff 100644 --- a/src/fpu/postproc/shiftcorrection.sv +++ b/src/fpu/postproc/shiftcorrection.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/specialcase.sv b/src/fpu/postproc/specialcase.sv index ba30daaf2..0a787c27c 100644 --- a/src/fpu/postproc/specialcase.sv +++ b/src/fpu/postproc/specialcase.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/unpack.sv b/src/fpu/unpack.sv index 145d6a701..eab224dd9 100644 --- a/src/fpu/unpack.sv +++ b/src/fpu/unpack.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/unpackinput.sv b/src/fpu/unpackinput.sv index b3d7f901e..ca58c9d9f 100644 --- a/src/fpu/unpackinput.sv +++ b/src/fpu/unpackinput.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/adder.sv b/src/generic/adder.sv index 4d341d6c1..f499eca88 100644 --- a/src/generic/adder.sv +++ b/src/generic/adder.sv @@ -7,6 +7,7 @@ // Purpose: Adder // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/aplusbeq0.sv b/src/generic/aplusbeq0.sv index f8d675b33..dc5f6450c 100644 --- a/src/generic/aplusbeq0.sv +++ b/src/generic/aplusbeq0.sv @@ -7,6 +7,7 @@ // Purpose: Determine if A+B = 0. Used in FP divider. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/arrs.sv b/src/generic/arrs.sv index dd473b307..cbff0e82b 100644 --- a/src/generic/arrs.sv +++ b/src/generic/arrs.sv @@ -10,6 +10,7 @@ // rising edge, but then syncs the falling edge to the posedge clk. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/binencoder.sv b/src/generic/binencoder.sv index 89093ea5b..a9349879a 100644 --- a/src/generic/binencoder.sv +++ b/src/generic/binencoder.sv @@ -6,6 +6,7 @@ // Purpose: one-hot to binary encoding. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/clockgater.sv b/src/generic/clockgater.sv index c0150133c..48282ccfa 100644 --- a/src/generic/clockgater.sv +++ b/src/generic/clockgater.sv @@ -7,6 +7,7 @@ // Purpose: Clock gater model. Must use standard cell for synthesis. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/counter.sv b/src/generic/counter.sv index faba2e5e5..cc20ae71e 100644 --- a/src/generic/counter.sv +++ b/src/generic/counter.sv @@ -7,6 +7,7 @@ // Purpose: Counter with reset and enable // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/csa.sv b/src/generic/csa.sv index 91aef44dd..ac9dfe098 100644 --- a/src/generic/csa.sv +++ b/src/generic/csa.sv @@ -7,6 +7,7 @@ // Purpose: 3:2 carry-save adder // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/decoder.sv b/src/generic/decoder.sv index 6284a454c..78b816c3c 100644 --- a/src/generic/decoder.sv +++ b/src/generic/decoder.sv @@ -7,6 +7,7 @@ // Purpose: Binary encoding to one-hot decoder // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/flop/flop.sv b/src/generic/flop/flop.sv index 97e0ac7e4..b7e7a82ee 100644 --- a/src/generic/flop/flop.sv +++ b/src/generic/flop/flop.sv @@ -7,6 +7,7 @@ // Purpose: D flip-flop // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/flop/flopen.sv b/src/generic/flop/flopen.sv index 2e6432519..f1db84776 100644 --- a/src/generic/flop/flopen.sv +++ b/src/generic/flop/flopen.sv @@ -7,6 +7,7 @@ // Purpose: D flip-flop with enable // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/flop/flopenl.sv b/src/generic/flop/flopenl.sv index 562c4565a..08b6590a8 100644 --- a/src/generic/flop/flopenl.sv +++ b/src/generic/flop/flopenl.sv @@ -7,6 +7,7 @@ // Purpose: D flip-flop with enable and synchronous load // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/flop/flopenr.sv b/src/generic/flop/flopenr.sv index 2c2144ab8..565fbfa7a 100644 --- a/src/generic/flop/flopenr.sv +++ b/src/generic/flop/flopenr.sv @@ -7,6 +7,7 @@ // Purpose: D flip-flop with enable, synchronous reset // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/flop/flopenrc.sv b/src/generic/flop/flopenrc.sv index 94b2b3cb0..983fae5f2 100644 --- a/src/generic/flop/flopenrc.sv +++ b/src/generic/flop/flopenrc.sv @@ -7,6 +7,7 @@ // Purpose: D flip-flop with enable, synchronous reset, enabled clear // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/flop/flopens.sv b/src/generic/flop/flopens.sv index c4fc5d01b..11c128393 100644 --- a/src/generic/flop/flopens.sv +++ b/src/generic/flop/flopens.sv @@ -7,6 +7,7 @@ // Purpose: D flip-flop with enable, synchronous set // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/flop/flopr.sv b/src/generic/flop/flopr.sv index 2e39ee8d6..b3edcbdf9 100644 --- a/src/generic/flop/flopr.sv +++ b/src/generic/flop/flopr.sv @@ -7,6 +7,7 @@ // Purpose: D flip-flop with synchronous reset // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/flop/floprc.sv b/src/generic/flop/floprc.sv index b35e9ccce..59f2e2862 100644 --- a/src/generic/flop/floprc.sv +++ b/src/generic/flop/floprc.sv @@ -7,6 +7,7 @@ // Purpose: D flip-flop with synchronous reset and clear // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/flop/synchronizer.sv b/src/generic/flop/synchronizer.sv index f99088af4..d4a63cd53 100644 --- a/src/generic/flop/synchronizer.sv +++ b/src/generic/flop/synchronizer.sv @@ -7,6 +7,7 @@ // Purpose: Two-stage flip-flop synchronizer // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/lzc.sv b/src/generic/lzc.sv index aa5381a22..855b64d88 100644 --- a/src/generic/lzc.sv +++ b/src/generic/lzc.sv @@ -6,6 +6,7 @@ // Purpose: Leading Zero Counter // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv index 4af3c255c..ccfce5da2 100644 --- a/src/generic/mem/ram1p1rwbe.sv +++ b/src/generic/mem/ram1p1rwbe.sv @@ -13,6 +13,7 @@ // Documentation: // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram1p1rwbe_64x128.sv b/src/generic/mem/ram1p1rwbe_64x128.sv index 55b1d75b0..64ddec259 100755 --- a/src/generic/mem/ram1p1rwbe_64x128.sv +++ b/src/generic/mem/ram1p1rwbe_64x128.sv @@ -7,6 +7,7 @@ // Purpose: RAM wrapper for instantiating RAM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram1p1rwbe_64x22.sv b/src/generic/mem/ram1p1rwbe_64x22.sv index 5e7a4c5cf..1b5e1bdb7 100755 --- a/src/generic/mem/ram1p1rwbe_64x22.sv +++ b/src/generic/mem/ram1p1rwbe_64x22.sv @@ -7,6 +7,7 @@ // Purpose: RAM wrapper for instantiating RAM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram1p1rwbe_64x44.sv b/src/generic/mem/ram1p1rwbe_64x44.sv index a2c2c81fa..1744ba59f 100644 --- a/src/generic/mem/ram1p1rwbe_64x44.sv +++ b/src/generic/mem/ram1p1rwbe_64x44.sv @@ -7,6 +7,7 @@ // Purpose: RAM wrapper for instantiating RAM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram1p1rwe.sv b/src/generic/mem/ram1p1rwe.sv index e3746c181..ebe7e336b 100644 --- a/src/generic/mem/ram1p1rwe.sv +++ b/src/generic/mem/ram1p1rwe.sv @@ -11,6 +11,7 @@ // Documentation: // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram2p1r1wbe.sv b/src/generic/mem/ram2p1r1wbe.sv index 42435c607..0945684d3 100644 --- a/src/generic/mem/ram2p1r1wbe.sv +++ b/src/generic/mem/ram2p1r1wbe.sv @@ -12,6 +12,7 @@ // Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram2p1r1wbe_1024x36.sv b/src/generic/mem/ram2p1r1wbe_1024x36.sv index 302277ed0..d499442b4 100755 --- a/src/generic/mem/ram2p1r1wbe_1024x36.sv +++ b/src/generic/mem/ram2p1r1wbe_1024x36.sv @@ -7,6 +7,7 @@ // Purpose: RAM wrapper for instantiating RAM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram2p1r1wbe_1024x68.sv b/src/generic/mem/ram2p1r1wbe_1024x68.sv index 6da7e06d6..a1633f8e9 100755 --- a/src/generic/mem/ram2p1r1wbe_1024x68.sv +++ b/src/generic/mem/ram2p1r1wbe_1024x68.sv @@ -7,6 +7,7 @@ // Purpose: RAM wrapper for instantiating RAM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram2p1r1wbe_128x64.sv b/src/generic/mem/ram2p1r1wbe_128x64.sv index e181fdd07..54d0ee8dc 100644 --- a/src/generic/mem/ram2p1r1wbe_128x64.sv +++ b/src/generic/mem/ram2p1r1wbe_128x64.sv @@ -7,6 +7,7 @@ // Purpose: RAM wrapper for instantiating RAM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram2p1r1wbe_512x64.sv b/src/generic/mem/ram2p1r1wbe_512x64.sv index 442eff90d..95185346a 100644 --- a/src/generic/mem/ram2p1r1wbe_512x64.sv +++ b/src/generic/mem/ram2p1r1wbe_512x64.sv @@ -7,6 +7,7 @@ // Purpose: RAM wrapper for instantiating RAM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram2p1r1wbe_64x32.sv b/src/generic/mem/ram2p1r1wbe_64x32.sv index 4236bb3f6..db3cbc846 100755 --- a/src/generic/mem/ram2p1r1wbe_64x32.sv +++ b/src/generic/mem/ram2p1r1wbe_64x32.sv @@ -7,6 +7,7 @@ // Purpose: RAM wrapper for instantiating RAM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv index c298dba63..cc94f1b96 100644 --- a/src/generic/mem/rom1p1r.sv +++ b/src/generic/mem/rom1p1r.sv @@ -6,6 +6,7 @@ // Purpose: Single-ported ROM // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/rom1p1r_128x32.sv b/src/generic/mem/rom1p1r_128x32.sv index ea5b92054..0854f1557 100755 --- a/src/generic/mem/rom1p1r_128x32.sv +++ b/src/generic/mem/rom1p1r_128x32.sv @@ -7,6 +7,7 @@ // Purpose: ROM wrapper for instantiating ROM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/rom1p1r_128x64.sv b/src/generic/mem/rom1p1r_128x64.sv index 6712d10fa..7a86bc50e 100755 --- a/src/generic/mem/rom1p1r_128x64.sv +++ b/src/generic/mem/rom1p1r_128x64.sv @@ -7,6 +7,7 @@ // Purpose: ROM wrapper for instantiating ROM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mux.sv b/src/generic/mux.sv index 9c1dfe335..5a4767c87 100644 --- a/src/generic/mux.sv +++ b/src/generic/mux.sv @@ -7,6 +7,7 @@ // Purpose: Various flavors of multiplexers // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/neg.sv b/src/generic/neg.sv index e971fc232..8621e510e 100644 --- a/src/generic/neg.sv +++ b/src/generic/neg.sv @@ -7,6 +7,7 @@ // Purpose: 2's complement negator // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/onehotdecoder.sv b/src/generic/onehotdecoder.sv index b672a08e5..9b25feb65 100644 --- a/src/generic/onehotdecoder.sv +++ b/src/generic/onehotdecoder.sv @@ -7,6 +7,7 @@ // Purpose: Bin to one hot decoder. Power of 2 only. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/or_rows.sv b/src/generic/or_rows.sv index 476b62586..56e693abb 100644 --- a/src/generic/or_rows.sv +++ b/src/generic/or_rows.sv @@ -7,6 +7,7 @@ // Purpose: Perform OR across a 2-dimensional array of inputs to produce a 1-D array of outputs // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/priorityonehot.sv b/src/generic/priorityonehot.sv index 1cddb2bfc..65882dd75 100644 --- a/src/generic/priorityonehot.sv +++ b/src/generic/priorityonehot.sv @@ -17,6 +17,7 @@ // out 00000000000100000 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/prioritythermometer.sv b/src/generic/prioritythermometer.sv index f779d4748..23acfcfb3 100644 --- a/src/generic/prioritythermometer.sv +++ b/src/generic/prioritythermometer.sv @@ -13,6 +13,7 @@ // out 00000000000011111 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/src/hazard/hazard.sv b/src/hazard/hazard.sv index 3728ceb17..140c3e74e 100644 --- a/src/hazard/hazard.sv +++ b/src/hazard/hazard.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4, Figure 13.54 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 4c296fda2..51cf00b97 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv index 4a5b4bfab..3f7d0ae7a 100644 --- a/src/ieu/bmu/bitmanipalu.sv +++ b/src/ieu/bmu/bitmanipalu.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/bitreverse.sv b/src/ieu/bmu/bitreverse.sv index fc2530aab..3876c31e4 100644 --- a/src/ieu/bmu/bitreverse.sv +++ b/src/ieu/bmu/bitreverse.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 59a8e4a16..5b758f123 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/byteop.sv b/src/ieu/bmu/byteop.sv index 2879ba042..191919ecc 100644 --- a/src/ieu/bmu/byteop.sv +++ b/src/ieu/bmu/byteop.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/clmul.sv b/src/ieu/bmu/clmul.sv index 675387577..f32fcece9 100644 --- a/src/ieu/bmu/clmul.sv +++ b/src/ieu/bmu/clmul.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv index d015c1195..eb54d6e3c 100644 --- a/src/ieu/bmu/cnt.sv +++ b/src/ieu/bmu/cnt.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/ext.sv b/src/ieu/bmu/ext.sv index 1feca6e1e..5ce1139fb 100644 --- a/src/ieu/bmu/ext.sv +++ b/src/ieu/bmu/ext.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/popcnt.sv b/src/ieu/bmu/popcnt.sv index 7701c0d65..903b67eeb 100644 --- a/src/ieu/bmu/popcnt.sv +++ b/src/ieu/bmu/popcnt.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 9ae3df42d..52ed8ef34 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/zbc.sv b/src/ieu/bmu/zbc.sv index 4dc3ad1bd..6e1948c33 100644 --- a/src/ieu/bmu/zbc.sv +++ b/src/ieu/bmu/zbc.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/comparator.sv b/src/ieu/comparator.sv index 0803d8b2f..466167fb3 100644 --- a/src/ieu/comparator.sv +++ b/src/ieu/comparator.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.7) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 35da15efe..d9c076dbd 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Section 4.1.4, Figure 4.8, Table 4.5) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index c2bcaf8c3..eb6fd1d81 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/extend.sv b/src/ieu/extend.sv index 4f7ee387f..b090c3f5e 100644 --- a/src/ieu/extend.sv +++ b/src/ieu/extend.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.3) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index ddd6fe089..438ca7534 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/regfile.sv b/src/ieu/regfile.sv index 2b76bca17..bf6990ea9 100644 --- a/src/ieu/regfile.sv +++ b/src/ieu/regfile.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/shifter.sv b/src/ieu/shifter.sv index bb0160c71..af44b6136 100644 --- a/src/ieu/shifter.sv +++ b/src/ieu/shifter.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.5, Table 4.3) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/RASPredictor.sv b/src/ifu/bpred/RASPredictor.sv index bc245d984..9f5dd2a43 100644 --- a/src/ifu/bpred/RASPredictor.sv +++ b/src/ifu/bpred/RASPredictor.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 10 (Figure ***) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index 64297c44a..faf537d91 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -9,6 +9,7 @@ // Prediction made during the fetch stage and corrected in the execution stage. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv index 567e4d3cd..2d0d30727 100644 --- a/src/ifu/bpred/btb.sv +++ b/src/ifu/bpred/btb.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 10 (Figure ***) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/gshare.sv b/src/ifu/bpred/gshare.sv index fcdf46655..7f5906084 100644 --- a/src/ifu/bpred/gshare.sv +++ b/src/ifu/bpred/gshare.sv @@ -10,6 +10,7 @@ // Purpose: gshare and Global History Branch predictors // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/gsharebasic.sv b/src/ifu/bpred/gsharebasic.sv index 7ae9f0282..1fa6f21f6 100644 --- a/src/ifu/bpred/gsharebasic.sv +++ b/src/ifu/bpred/gsharebasic.sv @@ -10,6 +10,7 @@ // Purpose: Global History Branch predictor with parameterized global history register // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/icpred.sv b/src/ifu/bpred/icpred.sv index e4895d4b7..42bde6f4e 100644 --- a/src/ifu/bpred/icpred.sv +++ b/src/ifu/bpred/icpred.sv @@ -9,6 +9,7 @@ // Call, Return, Jump, and Branch // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/localaheadbp.sv b/src/ifu/bpred/localaheadbp.sv index 4d6d536a7..fd8acbc82 100644 --- a/src/ifu/bpred/localaheadbp.sv +++ b/src/ifu/bpred/localaheadbp.sv @@ -8,6 +8,7 @@ // Purpose: local history branch predictor with ahead pipelining and SRAM memories. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/localbpbasic.sv b/src/ifu/bpred/localbpbasic.sv index d3a694c33..5c4485f3f 100644 --- a/src/ifu/bpred/localbpbasic.sv +++ b/src/ifu/bpred/localbpbasic.sv @@ -9,6 +9,7 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/localrepairbp.sv b/src/ifu/bpred/localrepairbp.sv index 95399e65a..3a730bd41 100644 --- a/src/ifu/bpred/localrepairbp.sv +++ b/src/ifu/bpred/localrepairbp.sv @@ -8,6 +8,7 @@ // Purpose: Local history branch predictor with speculation and repair using CBH. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/satCounter2.sv b/src/ifu/bpred/satCounter2.sv index 470375adc..7dd33ffb3 100644 --- a/src/ifu/bpred/satCounter2.sv +++ b/src/ifu/bpred/satCounter2.sv @@ -9,6 +9,7 @@ // Purpose: 2 bit starting counter // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/twoBitPredictor.sv b/src/ifu/bpred/twoBitPredictor.sv index 5b2fcb9b8..583b8d805 100644 --- a/src/ifu/bpred/twoBitPredictor.sv +++ b/src/ifu/bpred/twoBitPredictor.sv @@ -9,6 +9,7 @@ // Purpose: 2 bit saturating counter predictor with parameterized table depth. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/decompress.sv b/src/ifu/decompress.sv index 50617d3c5..e6c4fcd9a 100644 --- a/src/ifu/decompress.sv +++ b/src/ifu/decompress.sv @@ -12,6 +12,7 @@ // *** probably need more documentation in this file since the book is very light on decompression. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index 0bd899306..4848b5ebb 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -8,6 +8,7 @@ // PC, branch prediction, instruction cache // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -254,7 +255,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( .PAdr(PCPF), .CacheCommitted(CacheCommittedF), .InvalidateCache(InvalidateICacheM), .CMOpM('0)); - ahbcacheinterface #(P.AHBW, P.LLEN, P.PA_BITS, WORDSPERLINE, LOGBWPL, LINELEN, LLENPOVERAHBW, 1) + ahbcacheinterface #(P, WORDSPERLINE, LOGBWPL, LINELEN, LLENPOVERAHBW, 1) ahbcacheinterface(.HCLK(clk), .HRESETn(~reset), .HRDATA, .Flush(FlushD), .CacheBusRW, .BusCMOZero(1'b0), .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(), diff --git a/src/ifu/irom.sv b/src/ifu/irom.sv index 0b29c72cf..e5e7a7f96 100644 --- a/src/ifu/irom.sv +++ b/src/ifu/irom.sv @@ -7,6 +7,7 @@ // // Purpose: simple instruction ROM // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/spill.sv b/src/ifu/spill.sv index 39b30abd1..ea045c43f 100644 --- a/src/ifu/spill.sv +++ b/src/ifu/spill.sv @@ -12,6 +12,7 @@ // Documentation: RISC-V System on Chip Design Chapter 11 (Figure 11.5) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/lsu/align.sv b/src/lsu/align.sv index 8710b1d6a..d516dad2a 100644 --- a/src/lsu/align.sv +++ b/src/lsu/align.sv @@ -12,6 +12,7 @@ // Documentation: RISC-V System on Chip Design Chapter 11 (Figure 11.5) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/lsu/amoalu.sv b/src/lsu/amoalu.sv index c8b7ccee3..4d6330215 100644 --- a/src/lsu/amoalu.sv +++ b/src/lsu/amoalu.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 14 (Figure ***) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/lsu/atomic.sv b/src/lsu/atomic.sv index 117a42c2b..7dbd0c8a2 100644 --- a/src/lsu/atomic.sv +++ b/src/lsu/atomic.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 14 (Figure ***) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/lsu/dtim.sv b/src/lsu/dtim.sv index a44086a15..1386db96f 100644 --- a/src/lsu/dtim.sv +++ b/src/lsu/dtim.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/lsu/endianswap.sv b/src/lsu/endianswap.sv index 551f08de4..7c042886a 100644 --- a/src/lsu/endianswap.sv +++ b/src/lsu/endianswap.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 (Figure 5.9) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/lsu/lrsc.sv b/src/lsu/lrsc.sv index 66a9956dc..f7d1d4799 100644 --- a/src/lsu/lrsc.sv +++ b/src/lsu/lrsc.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 14 (Figure ***) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index a63468d61..5599ac5e3 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -12,6 +12,7 @@ // Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.2) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -345,7 +346,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( assign DCacheStallM = CacheStall & ~IgnoreRequestTLB; assign CacheBusRW = CacheBusRWTemp; - ahbcacheinterface #(.AHBW(P.AHBW), .LLEN(P.LLEN), .PA_BITS(P.PA_BITS), .BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface( + ahbcacheinterface #(.P(P), .BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface( .HCLK(clk), .HRESETn(~reset), .Flush(FlushW | IgnoreRequestTLB), .HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY), diff --git a/src/lsu/subwordread.sv b/src/lsu/subwordread.sv index e5666eb84..82fb80fb1 100644 --- a/src/lsu/subwordread.sv +++ b/src/lsu/subwordread.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/lsu/subwordwrite.sv b/src/lsu/subwordwrite.sv index ad21b3c25..705672ff7 100644 --- a/src/lsu/subwordwrite.sv +++ b/src/lsu/subwordwrite.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/lsu/swbytemask.sv b/src/lsu/swbytemask.sv index 5737bdc9b..60164e081 100644 --- a/src/lsu/swbytemask.sv +++ b/src/lsu/swbytemask.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mdu/div.sv b/src/mdu/div.sv index c550c06fc..2ae35d8f4 100644 --- a/src/mdu/div.sv +++ b/src/mdu/div.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.19) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mdu/divstep.sv b/src/mdu/divstep.sv index 712e98866..f478ad86f 100644 --- a/src/mdu/divstep.sv +++ b/src/mdu/divstep.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.19) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mdu/mdu.sv b/src/mdu/mdu.sv index e152fc6de..886eaf2b3 100644 --- a/src/mdu/mdu.sv +++ b/src/mdu/mdu.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.21) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mdu/mul.sv b/src/mdu/mul.sv index a5946b95c..65eaefd82 100644 --- a/src/mdu/mul.sv +++ b/src/mdu/mul.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.18) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/adrdec.sv b/src/mmu/adrdec.sv index 492d55372..05ac45bd0 100644 --- a/src/mmu/adrdec.sv +++ b/src/mmu/adrdec.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/adrdecs.sv b/src/mmu/adrdecs.sv index 282918484..d71fef82a 100644 --- a/src/mmu/adrdecs.sv +++ b/src/mmu/adrdecs.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index 2a99b14fd..0823dc7e0 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -13,6 +13,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/mmu.sv b/src/mmu/mmu.sv index 6957ed315..e842016a2 100644 --- a/src/mmu/mmu.sv +++ b/src/mmu/mmu.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/pmachecker.sv b/src/mmu/pmachecker.sv index 896274554..84e41ba65 100644 --- a/src/mmu/pmachecker.sv +++ b/src/mmu/pmachecker.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/pmpadrdec.sv b/src/mmu/pmpadrdec.sv index 9f283772d..7226237f6 100644 --- a/src/mmu/pmpadrdec.sv +++ b/src/mmu/pmpadrdec.sv @@ -13,6 +13,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/pmpchecker.sv b/src/mmu/pmpchecker.sv index 97cc6a18d..30a525744 100644 --- a/src/mmu/pmpchecker.sv +++ b/src/mmu/pmpchecker.sv @@ -12,6 +12,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/tlb/tlb.sv b/src/mmu/tlb/tlb.sv index a417bb530..5fbd10caf 100644 --- a/src/mmu/tlb/tlb.sv +++ b/src/mmu/tlb/tlb.sv @@ -12,6 +12,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/tlb/tlbcam.sv b/src/mmu/tlb/tlbcam.sv index e591498c4..aa569f2dd 100644 --- a/src/mmu/tlb/tlbcam.sv +++ b/src/mmu/tlb/tlbcam.sv @@ -12,6 +12,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/tlb/tlbcamline.sv b/src/mmu/tlb/tlbcamline.sv index 9471fb3d9..f5856ef56 100644 --- a/src/mmu/tlb/tlbcamline.sv +++ b/src/mmu/tlb/tlbcamline.sv @@ -12,6 +12,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/tlb/tlbcontrol.sv b/src/mmu/tlb/tlbcontrol.sv index aa9ec348a..83074deb3 100644 --- a/src/mmu/tlb/tlbcontrol.sv +++ b/src/mmu/tlb/tlbcontrol.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/tlb/tlblru.sv b/src/mmu/tlb/tlblru.sv index 18014155a..4776b5afb 100644 --- a/src/mmu/tlb/tlblru.sv +++ b/src/mmu/tlb/tlblru.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/tlb/tlbmixer.sv b/src/mmu/tlb/tlbmixer.sv index 9652e21ef..4a8712da9 100644 --- a/src/mmu/tlb/tlbmixer.sv +++ b/src/mmu/tlb/tlbmixer.sv @@ -12,6 +12,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/tlb/tlbram.sv b/src/mmu/tlb/tlbram.sv index 1a667d847..620f338a1 100644 --- a/src/mmu/tlb/tlbram.sv +++ b/src/mmu/tlb/tlbram.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/tlb/tlbramline.sv b/src/mmu/tlb/tlbramline.sv index 5e17e86eb..910db3aec 100644 --- a/src/mmu/tlb/tlbramline.sv +++ b/src/mmu/tlb/tlbramline.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/tlb/vm64check.sv b/src/mmu/tlb/vm64check.sv index a089031c2..4a4e96387 100644 --- a/src/mmu/tlb/vm64check.sv +++ b/src/mmu/tlb/vm64check.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index 9405cfdb9..4be12e383 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/csrc.sv b/src/privileged/csrc.sv index bc8768f47..722449284 100644 --- a/src/privileged/csrc.sv +++ b/src/privileged/csrc.sv @@ -11,6 +11,7 @@ // MHPMEVENT is not supported // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/csri.sv b/src/privileged/csri.sv index ea7bf7afb..35b6f3fe6 100644 --- a/src/privileged/csri.sv +++ b/src/privileged/csri.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index 056e8f2f9..9f5b29428 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -14,6 +14,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv index e107fc0f7..2357fc131 100644 --- a/src/privileged/csrs.sv +++ b/src/privileged/csrs.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/csrsr.sv b/src/privileged/csrsr.sv index 9935da179..3a28c5075 100644 --- a/src/privileged/csrsr.sv +++ b/src/privileged/csrsr.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/csru.sv b/src/privileged/csru.sv index 3a0f8c909..37891d009 100644 --- a/src/privileged/csru.sv +++ b/src/privileged/csru.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/privdec.sv b/src/privileged/privdec.sv index a5bfde1cf..bc9f9235f 100644 --- a/src/privileged/privdec.sv +++ b/src/privileged/privdec.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/privileged.sv b/src/privileged/privileged.sv index 063504730..09a56259f 100644 --- a/src/privileged/privileged.sv +++ b/src/privileged/privileged.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 (Figure 5.8) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/privmode.sv b/src/privileged/privmode.sv index 5ac4cae78..f1c5bfd76 100644 --- a/src/privileged/privmode.sv +++ b/src/privileged/privmode.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/privpiperegs.sv b/src/privileged/privpiperegs.sv index 5dea45972..ed43571bd 100644 --- a/src/privileged/privpiperegs.sv +++ b/src/privileged/privpiperegs.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/trap.sv b/src/privileged/trap.sv index 43ff8eadc..f20604379 100644 --- a/src/privileged/trap.sv +++ b/src/privileged/trap.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 (Figure 5.9) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/uncore/ahbapbbridge.sv b/src/uncore/ahbapbbridge.sv index 454f4d5df..dc7ceeab3 100644 --- a/src/uncore/ahbapbbridge.sv +++ b/src/uncore/ahbapbbridge.sv @@ -8,6 +8,7 @@ // Documentation: RISC-V System on Chip Design Chapter 6 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/uncore/clint_apb.sv b/src/uncore/clint_apb.sv index 6e35ffdaf..691ba372d 100644 --- a/src/uncore/clint_apb.sv +++ b/src/uncore/clint_apb.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/uncore/gpio_apb.sv b/src/uncore/gpio_apb.sv index 4ba3e1ccf..3b4ae1cb0 100644 --- a/src/uncore/gpio_apb.sv +++ b/src/uncore/gpio_apb.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/uncore/plic_apb.sv b/src/uncore/plic_apb.sv index 8ced27319..4c0602353 100644 --- a/src/uncore/plic_apb.sv +++ b/src/uncore/plic_apb.sv @@ -14,6 +14,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/uncore/ram_ahb.sv b/src/uncore/ram_ahb.sv index 896c2a4cb..e14728513 100644 --- a/src/uncore/ram_ahb.sv +++ b/src/uncore/ram_ahb.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 6 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -26,8 +27,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`define RAM_LATENCY 0 - module ram_ahb import cvw::*; #(parameter cvw_t P, parameter BASE=0, RANGE = 65535, PRELOAD = 0) ( input logic HCLK, HRESETn, @@ -75,7 +74,7 @@ module ram_ahb import cvw::*; #(parameter cvw_t P, .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .we(memwriteD), .din(HWDATA), .bwe(HWSTRB), .dout(HREADRam)); // use this to add arbitrary latency to ram. Helps test AHB controller correctness - if(`RAM_LATENCY > 0) begin + if(P.RAM_LATENCY > 0) begin logic [7:0] NextCycle, Cycle; logic CntEn, CntRst; logic CycleFlag; @@ -100,7 +99,7 @@ module ram_ahb import cvw::*; #(parameter cvw_t P, endcase end - assign CycleFlag = Cycle == `RAM_LATENCY; + assign CycleFlag = Cycle == P.RAM_LATENCY; assign CntEn = NextState == DELAY; assign DelayReady = NextState == DELAY; assign CntRst = NextState == READY; diff --git a/src/uncore/rom_ahb.sv b/src/uncore/rom_ahb.sv index d94cd6e07..9576f33d7 100644 --- a/src/uncore/rom_ahb.sv +++ b/src/uncore/rom_ahb.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 6 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/uncore/uartPC16550D.sv b/src/uncore/uartPC16550D.sv index ad1e0f259..f8aa4e016 100644 --- a/src/uncore/uartPC16550D.sv +++ b/src/uncore/uartPC16550D.sv @@ -16,6 +16,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/uncore/uart_apb.sv b/src/uncore/uart_apb.sv index 6fab04189..eeecb7ea5 100644 --- a/src/uncore/uart_apb.sv +++ b/src/uncore/uart_apb.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv index 1675d5a38..22e0a35fc 100644 --- a/src/uncore/uncore.sv +++ b/src/uncore/uncore.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 (and Figure 6.20) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index 9f84cc7bf..440307806 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design (Figure 4.1) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -252,7 +253,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( .LSUStallM); if(P.BUS_SUPPORTED) begin : ebu - ebu #(P.XLEN, P.PA_BITS, P.AHBW) ebu(// IFU connections + ebu #(P) ebu(// IFU connections .clk, .reset, // IFU interface .IFUHADDR, .IFUHBURST, .IFUHTRANS, .IFUHREADY, .IFUHSIZE, diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv index ab0071fff..d82a5c0d4 100644 --- a/src/wally/wallypipelinedsoc.sv +++ b/src/wally/wallypipelinedsoc.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design (Figure 6.20) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/studies/comparator.sv b/studies/comparator.sv index a5dbb6cb6..01d38181b 100644 --- a/studies/comparator.sv +++ b/studies/comparator.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.7) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/synthDC/extractArea.pl b/synthDC/extractArea.pl index 5f595dad8..fa630a3e7 100755 --- a/synthDC/extractArea.pl +++ b/synthDC/extractArea.pl @@ -10,6 +10,7 @@ ## Purpose: Pull area statistics from run directory ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/testbench/testbench-fp.sv b/testbench/testbench-fp.sv index b19542d62..5eab7c7ec 100644 --- a/testbench/testbench-fp.sv +++ b/testbench/testbench-fp.sv @@ -35,6 +35,8 @@ module testbenchfp; `include "parameter-defs.vh" + parameter MAXVECTORS = 8388610; + // FIXME: needs cleaning of unused variables (jes) string Tests[]; // list of tests to be run logic [2:0] OpCtrl[]; // list of op controls @@ -49,7 +51,7 @@ module testbenchfp; logic [31:0] errors=0; // how many errors logic [31:0] VectorNum=0; // index for test vector logic [31:0] FrmNum=0; // index for rounding mode - logic [P.FLEN*4+7:0] TestVectors[8388609:0]; // list of test vectors + logic [P.FLEN*4+7:0] TestVectors[MAXVECTORS-1:0]; // list of test vectors logic [1:0] FmtVal; // value of the current Fmt logic [2:0] UnitVal, OpCtrlVal, FrmVal; // value of the currnet Unit/OpCtrl/FrmVal @@ -83,7 +85,7 @@ module testbenchfp; logic [P.LOGCVTLEN-1:0] CvtShiftAmtE; // how much to shift by logic [P.DIVb:0] Quot; logic CvtResSubnormUfE; - logic DivStart; + logic DivStart=0; logic FDivBusyE; logic OldFDivBusyE; logic reset = 1'b0; @@ -120,7 +122,11 @@ module testbenchfp; logic ResMatch; // Check if result match logic FlagMatch; // Check if IEEE flags match logic CheckNow; // Final check - logic FMAop; // Is this a FMA operation? + logic FMAop; // Is this a FMA operation? + + // FSM for testing each item per clock + typedef enum logic [2:0] {S0, Start, S2, Done} statetype; + statetype state, nextstate; /////////////////////////////////////////////////////////////////////////////////////////////// @@ -676,7 +682,7 @@ module testbenchfp; .VectorNum, .Ans(Ans), .AnsFlg(AnsFlg), .SrcA, .Xs, .Ys, .Zs, .Unit(UnitVal), .Xe, .Ye, .Ze, .TestNum, .OpCtrl(OpCtrlVal), - .Xm, .Ym, .Zm, .DivStart, + .Xm, .Ym, .Zm, .XNaN, .YNaN, .ZNaN, .XSNaN, .YSNaN, .ZSNaN, .XSubnorm, .ZSubnorm, @@ -748,16 +754,6 @@ module testbenchfp; clk = 1; #5; clk = 0; #5; end - // Provide reset for divsqrt to reset state to IDLE - // Previous version did not initiate a divide due to missing state - // information. This starts the FSM by putting the fdivsqrt into - // the IDLE state. - initial - begin - #0 reset = 1'b1; - #25 reset = 1'b0; - end - /////////////////////////////////////////////////////////////////////////////////////////////// // ||||| ||| |||||||||| ||||| ||| @@ -835,45 +831,64 @@ module testbenchfp; `CMPUNIT: ResFlg = CmpFlg; `CVTINTUNIT: ResFlg = Flg; `CVTFPUNIT: ResFlg = Flg; - endcase - end + endcase + // Use four state test sequence to handle div properly. + // Four states should allow other operations to finish + // properly and within time. + case (state) + S0: begin + DivStart = 1'b0; + nextstate = Start; + end + Start: begin + if (UnitVal == `DIVUNIT) + DivStart = 1'b1; + else + DivStart = 1'b0; + nextstate = S2; + end + S2: begin + DivStart = 1'b0; + if ((FDivBusyE|~DivDone)&(UnitVal == `DIVUNIT)) + nextstate = S2; + else + nextstate = Done; + end + Done: begin + DivStart = 1'b0; + nextstate = S0; + end + endcase // case (state) + + end + + // Provide reset for divsqrt to reset state + initial + begin + #0 reset = 1'b1; + #25 reset = 1'b0; + end + + // Left-over from before - will remove soon always @(posedge clk) OldFDivBusyE = FDivDoneE; - // For FP division this adds extra clock cycles to make sure the - // computation completes. + // state machine to handle timing for testing due + // various cycle counts for different fp/int operations + // Adds vector at start of clock always @(posedge clk) begin - // Add extra clock cycles in beginning for fdivsqrt to adequate reset state - if (~(FDivBusyE|DivStart)|(UnitVal != `DIVUNIT)) begin - // This allows specific number of clocks to allow each vector - // to complete for division or square root. It is an - // arbitrary value and can be changed, if needed. - case (FmtVal) - // QP - 2'b11: begin - repeat (20) - @(posedge clk); - end - // HP - 2'b10: begin - repeat (14) - @(posedge clk); - end - // DP - 2'b01: begin - repeat (18) - @(posedge clk); - end - // SP - 2'b00: begin - repeat (16) - @(posedge clk); - end - endcase // case (FmtVal) - if (reset != 1'b1) - VectorNum += 1; // increment the vector - end + + // state machine element for testing + if (reset) + state <= S0; + else + state <= nextstate; + + // Increment the vector when Done with each test + if (state == Done) + VectorNum += 1; // increment the vector + end // check results on falling edge of clk @@ -904,7 +919,7 @@ module testbenchfp; (YNaN&(Res[P.H_LEN-2:0] === {Y[P.H_LEN-2:P.H_NF],1'b1,Y[P.H_NF-2:0]})) | (ZNaN&(Res[P.H_LEN-2:0] === {Z[P.H_LEN-2:P.H_NF],1'b1,Z[P.H_NF-2:0]}))); endcase - else if (UnitVal === `CVTFPUNIT) // if converting from floating point to floating point OpCtrl contains the final FP format + else if (UnitVal === `CVTFPUNIT) // if converting from FP to FP OpCtrl contains the final FP format case (OpCtrlVal[1:0]) 2'b11: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res === {1'b0, {P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) | (AnsFlg[4]&(Res[P.Q_LEN-2:0] === {{P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) | @@ -941,35 +956,28 @@ module testbenchfp; /////////////////////////////////////////////////////////////////////////////////////////////// // check if result is correct - // wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage) assign ResMatch = ((Res === Ans) | NaNGood | (NaNGood === 1'bx)); assign FlagMatch = ((ResFlg === AnsFlg) | (AnsFlg === 5'bx)); assign divsqrtop = (OpCtrlVal == `SQRT_OPCTRL) | (OpCtrlVal == `DIV_OPCTRL); assign FMAop = (OpCtrlVal == `FMAUNIT); assign DivDone = OldFDivBusyE & ~FDivBusyE; - - // Maybe change OpCtrl but for now just look at TEST for fma test - assign CheckNow = ((DivDone | ~divsqrtop) | (TEST == "add" | TEST == "fma" | TEST == "sub")) & (UnitVal !== `CVTINTUNIT) & (UnitVal !== `CMPUNIT); - if (~(ResMatch & FlagMatch) & CheckNow) begin + assign CheckNow = ((DivDone | ~divsqrtop) | + (TEST == "add" | TEST == "fma" | TEST == "sub") | + ((TEST == "all") & (DivDone | ~divsqrtop))); + + if (~(ResMatch & FlagMatch) & CheckNow & (Ans[0] !== 1'bx)) begin errors += 1; $display("\nError in %s", Tests[TestNum]); $display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]); $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Expected: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg); $stop; - end else if (((UnitVal === `CVTINTUNIT) | (UnitVal === `CMPUNIT)) & - ~(ResMatch & FlagMatch) & (Ans[0] !== 1'bx)) begin // Check for conversion and comparisons - errors += 1; - $display("\nError in %s", Tests[TestNum]); - $display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]); - $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg); - $stop; end if (TestVectors[VectorNum][0] === 1'bx & Tests[TestNum] !== "") begin // if reached the eof // increment the test TestNum += 1; // clear the vectors - for(int i=0; i<6133248; i++) TestVectors[i] = {P.FLEN*4+8{1'bx}}; + for(int i=0; i