From ac047a04fac4ad96b846acb125fa43cac8646c27 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Wed, 4 Sep 2024 17:51:48 -0700 Subject: [PATCH] Fixed bug in SPI with the help of Naiche and Jacob. Have yet to test if SPI will now run correctly with div=0 (SYSTEMCLOCK/2), but the SPI flash card now correctly loads into the Linux OS and mount and is reading and writting without error. --- src/uncore/spi_apb.sv | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/uncore/spi_apb.sv b/src/uncore/spi_apb.sv index 4c2cea733..6af9a1388 100644 --- a/src/uncore/spi_apb.sv +++ b/src/uncore/spi_apb.sv @@ -90,6 +90,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) ( logic TransmitWriteMark, TransmitReadMark, RecieveWriteMark, RecieveReadMark; logic TransmitFIFOWriteFull, TransmitFIFOReadEmpty; logic TransmitFIFOWriteIncrement; + logic ReceiveFiFoWriteInc; logic ReceiveFIFOReadIncrement; logic ReceiveFIFOWriteFull, ReceiveFIFOReadEmpty; logic [7:0] TransmitFIFOReadData; @@ -301,7 +302,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) ( // Tx/Rx FIFOs spi_fifo #(3,8) txFIFO(PCLK, 1'b1, SCLKenable, PRESETn, TransmitFIFOWriteIncrement, TransmitFIFOReadIncrement, TransmitData[7:0], TransmitWriteWatermarkLevel, TransmitWatermark[2:0], TransmitFIFOReadData[7:0], TransmitFIFOWriteFull, TransmitFIFOReadEmpty, TransmitWriteMark, TransmitReadMark); - spi_fifo #(3,8) rxFIFO(PCLK, SCLKenable, 1'b1, PRESETn, ReceiveShiftFullDelay, ReceiveFIFOReadIncrement, ReceiveShiftRegEndian, ReceiveWatermark[2:0], ReceiveReadWatermarkLevel, + spi_fifo #(3,8) rxFIFO(PCLK, SCLKenable, 1'b1, PRESETn, ReceiveFiFoWriteInc, ReceiveFIFOReadIncrement, ReceiveShiftRegEndian, ReceiveWatermark[2:0], ReceiveReadWatermarkLevel, ReceiveData[7:0], ReceiveFIFOWriteFull, ReceiveFIFOReadEmpty, RecieveWriteMark, RecieveReadMark); always_ff @(posedge PCLK) @@ -311,6 +312,13 @@ module spi_apb import cvw::*; #(parameter cvw_t P) ( always_ff @(posedge PCLK) if (~PRESETn) ReceiveShiftFullDelay <= 1'b0; else if (SCLKenable) ReceiveShiftFullDelay <= ReceiveShiftFull; + + assign ReceiveFiFoTakingData = ReceiveFiFoWriteInc & ~ReceiveFIFOWriteFull; + + always_ff @(posedge PCLK) + if (~PRESETn) ReceiveFiFoWriteInc <= 1'b0; + else if (SCLKenable & ReceiveShiftFull) ReceiveFiFoWriteInc <= 1'b1; + else if (SCLKenable & ReceiveFiFoTakingData) ReceiveFiFoWriteInc <= 1'b0; always_ff @(posedge PCLK) if (~PRESETn) ReceiveShiftFullDelayPCLK <= 1'b0; else if (SCLKenableEarly) ReceiveShiftFullDelayPCLK <= ReceiveShiftFull;