From 6bec559ba60d568493e33c3e7b7435232fc49dee Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 21 Nov 2023 19:49:14 -0800 Subject: [PATCH 1/2] Removed stale signals from wave.do --- sim/wave.do | 4 ---- 1 file changed, 4 deletions(-) diff --git a/sim/wave.do b/sim/wave.do index 3f2bcd72a..3a5fd9369 100644 --- a/sim/wave.do +++ b/sim/wave.do @@ -120,7 +120,6 @@ add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/z add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/ByteMaskMuxM add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskSpillM add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/LSUWriteDataM -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/LSUWriteDataShiftedM add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/LSUWriteDataSpillM add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteData add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/ByteMask @@ -128,14 +127,12 @@ add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/b add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/DemuxedByteMask add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/FetchBufferByteSel add wave -noupdate -expand -group lsu -group alignment {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/LineWriteData} -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/IncrementAmount add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IEUAdrExtE add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IEUAdrExtM add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/NextSet add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CMOp -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CMOZeroHit add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid @@ -212,7 +209,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM w add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/we} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/bwe} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelNotHit2} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelNonHit} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelData} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} From d1bb5c7512957b3bc4c1cf5956526182ddbfe254 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 21 Nov 2023 21:52:11 -0800 Subject: [PATCH 2/2] Imperas fix for satp modes supported --- linux/Makefile | 3 ++- sim/imperas.ic | 3 +++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/linux/Makefile b/linux/Makefile index 520c7cd44..a2cded5ea 100644 --- a/linux/Makefile +++ b/linux/Makefile @@ -39,6 +39,7 @@ Image: # source ../setup.sh; $(MAKE) disassemble install: + sudo rm -rf $(RISCV)/$(BUILDROOT) sudo mv $(BUILDROOT) $(RISCV)/$(BUILDROOT) # Temp rule for debugging @@ -62,10 +63,10 @@ $(RISCV): disassemble: + rm -rf $(BUILDROOT)/output/images/disassembly find $(BUILDROOT)/output/build/linux-* -maxdepth 1 -name "vmlinux" | xargs cp -t $(BUILDROOT)/output/images/ mkdir -p $(DIS) make -j $(OBJDUMPS) - make -j $(OBJDUMPS).addr $(DIS)/%.objdump: $(IMAGES)/%.elf riscv64-unknown-elf-objdump -DS $< >> $@ diff --git a/sim/imperas.ic b/sim/imperas.ic index 4106968ed..be6b7cca6 100644 --- a/sim/imperas.ic +++ b/sim/imperas.ic @@ -32,6 +32,9 @@ --override cpu/Svpbmt=T --override cpu/Svnapot_page_mask=65536 +# SV39 and SV48 supported +--override cpu/Sv_modes=768 + # clarify #--override refRoot/cpu/mtvec_sext=F