From 23e51e7277687151b8a7ba246d30374d05b58e8e Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Thu, 4 Apr 2024 15:44:57 -0500 Subject: [PATCH 1/5] starting on functional coverage for fence.i. --- testbench/coverage/test_fencei_coverage.svh | 25 +++++++++++++++++++ .../coverage/test_fencei_coverage_init.svh | 4 +++ 2 files changed, 29 insertions(+) create mode 100644 testbench/coverage/test_fencei_coverage.svh create mode 100644 testbench/coverage/test_fencei_coverage_init.svh diff --git a/testbench/coverage/test_fencei_coverage.svh b/testbench/coverage/test_fencei_coverage.svh new file mode 100644 index 000000000..bb492b1cb --- /dev/null +++ b/testbench/coverage/test_fencei_coverage.svh @@ -0,0 +1,25 @@ +typedef RISCV_instruction #(ILEN, XLEN, FLEN, VLEN, NHART, RETIRE) test_ins_rv64i_t; + +covergroup test_fencei_cg with function sample(test_ins_rv64i_t ins); + option.per_instance = 1; + option.comment = "Fence.I"; + + cp_asm_count : coverpoint ins.ins_str == "fence.i" iff (ins.trap == 0 ) { + option.comment = "Number of times instruction is executed"; + bins count[] = {1}; + } +endgroup + +function void test_fencei_sample(int hart, int issue); + test_ins_rv64i_t ins; + + case (traceDataQ[hart][issue][0].inst_name) + "fenci" : begin + ins = new(hart, issue, traceDataQ); + test_fencei_cg.sample(ins); + end + endcase + +endfunction + + diff --git a/testbench/coverage/test_fencei_coverage_init.svh b/testbench/coverage/test_fencei_coverage_init.svh new file mode 100644 index 000000000..c07507d43 --- /dev/null +++ b/testbench/coverage/test_fencei_coverage_init.svh @@ -0,0 +1,4 @@ +test_fencei_cg = new(); test_fencei_cg.set_inst_name("obj_fencei"); + +// test_fencei_cg = new(); +//test_fencei_cg.set_inst_name("obj_fencei"); From 46fdfde7ec98e1760901bd588cbd9557b7a13944 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Sat, 6 Apr 2024 16:10:18 -0500 Subject: [PATCH 2/5] Removed unnecessary display from testbench. --- sim/questa/sim-wally-batch | 2 +- testbench/testbench.sv | 11 +++++------ 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/sim/questa/sim-wally-batch b/sim/questa/sim-wally-batch index 58497efe9..7b3c69339 100755 --- a/sim/questa/sim-wally-batch +++ b/sim/questa/sim-wally-batch @@ -1 +1 @@ -../wsim rv64gc arch64i +wsim rv64gc arch64i diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 62f45691b..7145a2735 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -108,8 +108,6 @@ module testbench; TEST = "none"; if (!$value$plusargs("INSTR_LIMIT=%d", INSTR_LIMIT)) INSTR_LIMIT = 0; - $display("INSTR_LIMIT = ", INSTR_LIMIT); - // pick tests based on modes supported //tests = '{}; @@ -246,7 +244,7 @@ module testbench; logic ResetCntRst; logic CopyRAM; - string signame, memfilename, bootmemfilename, uartoutfilename, pathname; + string signame, memfilename, bootmemfilename, uartoutfilename, pathname, rmCmd; integer begin_signature_addr, end_signature_addr, signature_size; assign ResetThreshold = 3'd5; @@ -338,8 +336,9 @@ module testbench; else if(TEST == "buildroot") begin memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"}; bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"}; - uartoutfilename = {"logs/",TEST,"_uart.out"}; - $system("rm ",uartoutfilename); // Delete existing UARToutfile + uartoutfilename = {"logs/", TEST, "_uart.out"}; + rmCmd = {"rm ", uartoutfilename}; + $system(rmCmd); // Delete existing UARToutfile end else memfilename = {pathname, tests[test], ".elf.memfile"}; if (riscofTest) begin @@ -582,7 +581,7 @@ module testbench; // Append UART output to file for tests always @(posedge clk) begin - if (TEST == "buildroot") begin + if (P.UART_SUPPORTED & TEST == "buildroot") begin if (~dut.uncore.uncore.uart.uart.MEMWb & dut.uncore.uncore.uart.uart.u.A == 3'b000 & ~dut.uncore.uncore.uart.uart.u.DLAB) begin memFile = $fopen(uartoutfilename, "ab"); $fwrite(memFile, "%c", dut.uncore.uncore.uart.uart.u.Din); From 41845ec17e96d5241e58f2d92c928da084f986ce Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Sat, 6 Apr 2024 16:29:58 -0500 Subject: [PATCH 3/5] Fixed issues around missing directories. --- bin/regression-wally | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index 0cd195db7..7473a4058 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -246,10 +246,10 @@ def run_test_case(config): # Main body ################################## -regressionDir = os.path.dirname(os.path.abspath(__file__)) -os.chdir(regressionDir) WALLY = os.environ.get('WALLY') +regressionDir = WALLY + '/sim' +os.chdir(regressionDir) coveragesim = "questa" # Questa is required for code/functional coverage defaultsim = "questa" # Default simulator for all other tests; change to Verilator when flow is ready @@ -347,6 +347,8 @@ def main(): try: os.mkdir(d) except: + print(f'Failed to make logs and wkdir {d}') + print(f'regressionDir is {regressionDir}') pass if '-makeTests' in sys.argv: From cdcff9d368782276011d2c2b853e78f05eb7485d Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Sat, 6 Apr 2024 16:32:07 -0500 Subject: [PATCH 4/5] Updated sim-wally to work with new run scripts. --- sim/questa/sim-wally | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sim/questa/sim-wally b/sim/questa/sim-wally index 78558c7f1..3359be0eb 100755 --- a/sim/questa/sim-wally +++ b/sim/questa/sim-wally @@ -1,2 +1,2 @@ -vsim -do "do wally.do rv64gc wally64periph" +wsim rv64gc arch64i --gui From d0d1166e3f66f7c163fbdbbe2304d4bf3d4f7dd9 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Sat, 6 Apr 2024 18:04:48 -0500 Subject: [PATCH 5/5] Got the separation of the -G and +variable arguments in the questa do file. regression still runs. --- bin/regression-wally | 2 - bin/wsim | 10 ++++ sim/questa/sim-testfloat | 4 +- sim/questa/wally.do | 33 ++++++++--- sim/questa/wave.do | 123 +++++++++++++++++++-------------------- 5 files changed, 100 insertions(+), 72 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index 7473a4058..be56a049c 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -347,8 +347,6 @@ def main(): try: os.mkdir(d) except: - print(f'Failed to make logs and wkdir {d}') - print(f'regressionDir is {regressionDir}') pass if '-makeTests' in sys.argv: diff --git a/bin/wsim b/bin/wsim index f492b121b..7e386e4a3 100755 --- a/bin/wsim +++ b/bin/wsim @@ -37,6 +37,16 @@ if (args.coverage): print("Coverage option only available for Questa") exit(1) + +# create the output sub-directories. +WALLY = os.environ.get('WALLY') +regressionDir = WALLY + '/sim/' +for d in ["logs", "wkdir", "cov"]: + try: + os.mkdir(regressionDir+args.sim+"/"+d) + except: + pass + # Launch selected simulator cd = "cd $WALLY/sim/" +args.sim if (args.sim == "questa"): diff --git a/sim/questa/sim-testfloat b/sim/questa/sim-testfloat index b7da7104a..ee13f17c9 100755 --- a/sim/questa/sim-testfloat +++ b/sim/questa/sim-testfloat @@ -9,4 +9,6 @@ # sqrt - test square root # all - test everything -vsim -do "do testfloat.do fdqh_ieee_rv64gc $1" + +wsim fdqh_ieee_rv64gc $1 --tb testbench_fp --gui + diff --git a/sim/questa/wally.do b/sim/questa/wally.do index e5c268e0d..25dc33c6d 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -50,6 +50,9 @@ set from 4 set step 1 set lst {} set GUI 0 +set PlusArgs {} +set ParamArgs {} +set accFlag "" for {set i 0} true {incr i} { set x [expr {$i*$step + $from}] if {$x > $argc} break @@ -58,13 +61,29 @@ for {set i 0} true {incr i} { } if {$argc >= 3} { - set tbArgs $lst - puts $tbArgs - if {[lindex $lst [expr { [llength $lst] -1 } ]] eq "+acc"} { set GUI 1 - } - + set accFlag "+acc" + set tbArgs [lrange $lst 0 end-1] + } else { + set tbArgs $lst + } + set tbArgsLst [split $lst " "] + # might be able to remove this, but I'm keeping the code for now in case we need to separate the two types of args. + foreach otherArg $tbArgsLst { + if {[string index $otherArg 0] eq "+"} { + lappend PlusArgs $otherArg + } else { + lappend ParamArgs $otherArg + } + } + #echo "PlusArgs" + #echo $PlusArgs + #echo "ParamArgs" + #echo $ParamArgs + #echo "accFlag" + #echo $accFlag + #if {$3 eq "-coverage" || ($argc >= 7 && $7 eq "-coverage")} { # set coverage 1 # set CoverageVoptArg "+cover=sbecf" @@ -84,9 +103,9 @@ vlog -lint -work ${WKDIR} +incdir+${CONFIG}/$1 +incdir+${CONFIG}/deriv/$1 +incdi # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals -vopt wkdir/${CFG}_${TESTSUITE}.${TESTBENCH} -work ${WKDIR} ${tbArgs} -o testbenchopt ${CoverageVoptArg} +vopt $accFlag wkdir/${CFG}_${TESTSUITE}.${TESTBENCH} -work ${WKDIR} ${tbArgs} -o testbenchopt ${CoverageVoptArg} # *** tbArgs producees a warning that TEST not found in design when running sim-testfloat-batch. Need to separate -G and + arguments to pass separately to vopt and vsim -vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} ${tbArgs} -fatal 7 -suppress 3829 ${CoverageVsimArg} +vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} -fatal 7 -suppress 3829 ${CoverageVsimArg} # vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829 # power add generates the logging necessary for said generation. diff --git a/sim/questa/wave.do b/sim/questa/wave.do index 7c8eae184..bb6b1d54b 100644 --- a/sim/questa/wave.do +++ b/sim/questa/wave.do @@ -6,43 +6,43 @@ add wave -noupdate /testbench/reset add wave -noupdate /testbench/memfilename add wave -noupdate /testbench/dut/core/SATP_REGW add wave -noupdate /testbench/dut/core/InstrValidM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM -add wave -noupdate -expand -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ieu/c/LoadStallD -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/BPWrongE -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ieu/c/MDUStallD -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/pmd/WFITimeoutM -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW -add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallF -add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallD -add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallE -add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallM -add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallW -add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/PendingIntsM -add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/InstrValidM -add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/ValidIntsM -add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/hzu/WFIInterruptedM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM +add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ieu/c/LoadStallD +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPWrongE +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ieu/c/MDUStallD +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/pmd/WFITimeoutM +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW +add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallF +add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallD +add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallE +add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallM +add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallW +add wave -noupdate -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/PendingIntsM +add wave -noupdate -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/InstrValidM +add wave -noupdate -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/ValidIntsM +add wave -noupdate -group HDU -group interrupts /testbench/dut/core/hzu/WFIInterruptedM add wave -noupdate -group {instruction pipeline} /testbench/InstrFName add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD @@ -205,7 +205,6 @@ add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/SrcAE add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/SrcBE add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ALUResultE add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ResultW -add wave -noupdate -expand -group {Memory Stage} /testbench/FunctionName/FunctionName/FunctionName add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrValidM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM @@ -407,29 +406,29 @@ add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dm add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk -add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextWalkerState -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/PBMTFaultM +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk +add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextWalkerState +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE +add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF +add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM +add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF +add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM +add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWFaultM +add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM +add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF +add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM +add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM +add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault +add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/PBMTFaultM add wave -noupdate -group {WriteBack stage} /testbench/InstrW add wave -noupdate -group {WriteBack stage} /testbench/InstrWName add wave -noupdate -group {WriteBack stage} /testbench/dut/core/priv/priv/pmd/wfiW @@ -678,4 +677,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {11566 ns} {11760 ns} +WaveRestoreZoom {0 ns} {284634 ns}