diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl
index d5a2fca43..c7ae69d48 100644
--- a/fpga/generator/wally.tcl
+++ b/fpga/generator/wally.tcl
@@ -23,7 +23,7 @@ if {$board=="ArtyA7"} {
     read_ip IP/xlnx_ddr4.srcs/sources_1/ip/xlnx_ddr4/xlnx_ddr4.xci
 }
 
-read_verilog -sv [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv]
+read_verilog -sv [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv]
 if {$board=="ArtyA7"} {
     read_verilog  {../src/fpgaTopArtyA7.v}
 } else {
diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v
index 990495f44..0076e0279 100644
--- a/fpga/src/fpgaTop.v
+++ b/fpga/src/fpgaTop.v
@@ -24,7 +24,7 @@
 // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 ///////////////////////////////////////////
 
-`include "wally-config.vh"
+`include "config.vh"
 
 module fpgaTop 
   (input           default_250mhz_clk1_0_n,
@@ -62,6 +62,9 @@ module fpgaTop
    output [0 : 0]  c0_ddr4_ck_t
    );
 
+`include "parameter-defs.vh"
+  
+
   wire 			   CPUCLK;
   wire 			   c0_ddr4_ui_clk_sync_rst;
   wire 			   bus_struct_reset;
@@ -72,12 +75,12 @@ module fpgaTop
   
   wire 			   HCLKOpen;
   wire 			   HRESETnOpen;
-  wire [`AHBW-1:0] HRDATAEXT;
+  wire [P.AHBW-1:0] HRDATAEXT;
   wire 			   HREADYEXT;
   wire 			   HRESPEXT;
   wire 			   HSELEXT;
   wire [31:0] 	   HADDR;
-  wire [`AHBW-1:0] HWDATA;
+  wire [P.AHBW-1:0] HWDATA;
   wire 			   HWRITE;
   wire [2:0] 	   HSIZE;
   wire [2:0] 	   HBURST;
@@ -211,7 +214,7 @@ module fpgaTop
   
 
   // wally
-  wallypipelinedsoc wallypipelinedsoc
+  wallypipelinedsoc #(P) wallypipelinedsoc
     (.clk(CPUCLK),
      .reset_ext(bus_struct_reset),
      // bus interface
diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv
index d1cd99002..b703d72fe 100644
--- a/src/uncore/uncore.sv
+++ b/src/uncore/uncore.sv
@@ -146,7 +146,7 @@ module uncore import cvw::*;  #(parameter cvw_t P)(
     assign UARTSout = 0; assign UARTIntr = 0; 
   end
   if (P.SDC_SUPPORTED == 1) begin : sdc
-    SDC SDC(.HCLK, .HRESETn, .HSELSDC, .HADDR(HADDR[4:0]), .HWRITE, .HREADY, .HTRANS,
+    SDC #(P) SDC(.HCLK, .HRESETn, .HSELSDC, .HADDR(HADDR[4:0]), .HWRITE, .HREADY, .HTRANS,
       .HWDATA, .HREADSDC, .HRESPSDC, .HREADYSDC,
       // sdc interface
       .SDCCmdOut, .SDCCmdIn, .SDCCmdOE, .SDCDatIn, .SDCCLK,