From 7164841f83d60ed5b078ad22890672e84cbcec87 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 6 Aug 2024 18:34:46 -0500 Subject: [PATCH 01/19] Added padding into the hw rvvi format. --- fpga/rvvidaemon/rvvidaemon.c | 211 +++++++++++------------------- fpga/src/fpgaTopArtyA7.sv | 2 +- src/rvvi/packetizer.sv | 16 ++- src/rvvi/rvvisynth.sv | 18 +-- testbench/common/rvvitbwrapper.sv | 2 +- 5 files changed, 97 insertions(+), 152 deletions(-) diff --git a/fpga/rvvidaemon/rvvidaemon.c b/fpga/rvvidaemon/rvvidaemon.c index 1e9d17f66..1932038ad 100644 --- a/fpga/rvvidaemon/rvvidaemon.c +++ b/fpga/rvvidaemon/rvvidaemon.c @@ -92,13 +92,47 @@ typedef struct { } RequiredRVVI_t; // total size is 241 bits or 30.125 bytes +typedef struct __attribute__((packed)) { + uint64_t PC; + uint32_t insn; + uint64_t Mcycle; + uint64_t Minstret; + uint8_t Trap : 1; + uint8_t PrivilegeMode : 2; + uint8_t GPREn : 1; + uint8_t FPREn : 1; + uint8_t Pad3: 3; + uint16_t CSRCount : 12; + uint16_t Pad4 : 4; + uint8_t GPRReg : 5; + uint8_t PadG3 : 3; + uint64_t GPRValue; + uint8_t FPRReg : 5; + uint8_t PadF3 : 3; + uint64_t FPRValue; + uint16_t CSR0Wen : 12; + uint16_t PadC04 : 4; + uint64_t CSR0Value; + uint16_t CSR1Wen : 12; + uint16_t PadC14 : 4; + uint64_t CSR1Value; + uint16_t CSR2Wen : 12; + uint16_t PadC24 : 4; + uint64_t CSR2Value; + uint16_t CSR3Wen : 12; + uint16_t PadC34 : 4; + uint64_t CSR3Value; + uint16_t CSR4Wen : 12; + uint16_t PadC44 : 4; + uint64_t CSR4Value; +} FixedRequiredRVVI_t; // 904 bits + typedef struct { uint8_t RegAddress : 5; uint64_t RegValue; } Reg_t; void DecodeRVVI(uint8_t *payload, ssize_t payloadsize, RequiredRVVI_t *InstructionData); -void BitShiftArray(uint8_t *dst, uint8_t *src, uint8_t ShiftAmount, int Length); void PrintInstructionData(RequiredRVVI_t *InstructionData); int ProcessRvviAll(RequiredRVVI_t *InstructionData); void set_gpr(int hart, int reg, uint64_t value); @@ -345,111 +379,50 @@ void set_fpr(int hart, int reg, uint64_t value){ } void DecodeRVVI(uint8_t *payload, ssize_t payloadsize, RequiredRVVI_t *InstructionData){ - // you know this actually easiser in assembly. :( - uint8_t buf2[BUF_SIZ], buf3[BUF_SIZ]; - uint8_t * buf2ptr, *buf3ptr; - buf2ptr = buf2; - buf3ptr = buf3; - //int PayloadSize = sizeof(RequiredRVVI_t) - 1; - int PayloadSize = 30; - int Buf2Size = BUF_SIZ - PayloadSize; - uint64_t Mcycle, Minstret; - uint64_t PC; - uint32_t insn; - // unforunately the struct appoarch does not work?!? - PC = * (uint64_t *) payload; - payload += 8; - insn = * (uint32_t *) payload; - payload += 4; - Mcycle = * (uint64_t *) payload; - payload += 8; - Minstret = * (uint64_t *) payload; - payload += 8; - // the next 4 bytes contain CSRCount (12), FPRWen(1), GPRWen(1), PrivilegeMode(2), Trap(1) - uint32_t RequiredFlags; - RequiredFlags = * (uint32_t *) payload; - uint8_t Trap, PrivilegeMode, GPRWen, FPRWen; - uint16_t CSRCount = 0; - uint8_t GPRReg = 0; - uint64_t GPRData = 0; - uint8_t FPRReg = 0; - uint64_t FPRData = 0; - uint8_t CSRWen[3] = {0, 0, 0}; - uint16_t CSRReg[3]; - uint64_t CSRValue[3]; - int CSRIndex; - Trap = RequiredFlags & 0x1; - PrivilegeMode = (RequiredFlags >> 1) & 0x3; - GPRWen = (RequiredFlags >> 3) & 0x1; - FPRWen = (RequiredFlags >> 4) & 0x1; - CSRCount = (RequiredFlags >> 5) & 0xFFF; - payload += 2; + FixedRequiredRVVI_t *FixedInstructionData = (FixedRequiredRVVI_t *) payload; + InstructionData->PC = FixedInstructionData->PC; + InstructionData->insn = FixedInstructionData->insn; + InstructionData->Mcycle = FixedInstructionData->Mcycle; + InstructionData->Minstret = FixedInstructionData->Minstret; + InstructionData->Trap = FixedInstructionData->Trap; + InstructionData->PrivilegeMode = FixedInstructionData->PrivilegeMode; + InstructionData->GPREn = FixedInstructionData->GPREn; + InstructionData->FPREn = FixedInstructionData->FPREn; + InstructionData->CSRCount = FixedInstructionData->CSRCount; + InstructionData->GPRReg = FixedInstructionData->GPRReg; + InstructionData->GPRValue = FixedInstructionData->GPRValue; + InstructionData->FPRReg = FixedInstructionData->FPRReg; + InstructionData->FPRValue = FixedInstructionData->FPRValue; - if(GPRWen || FPRWen || (CSRCount != 0)){ - // the first bit of payload is the last bit of CSRCount. - ssize_t newPayloadSize = payloadsize - 30; - BitShiftArray(buf2, payload, 1, newPayloadSize); - int index; - if(GPRWen){ - GPRReg = * (uint8_t *) buf2ptr; - GPRReg = GPRReg & 0x1F; - BitShiftArray(buf3, buf2ptr, 5, newPayloadSize); - GPRData = * (uint64_t *) buf3; - if(FPRWen){ - buf3ptr += 8; - FPRReg = * (uint8_t *) buf3ptr; - BitShiftArray(buf2, buf3ptr, 5, newPayloadSize - 8); - FPRReg = FPRReg & 0x1F; - FPRData = * (uint64_t *) buf2; - } - }else if(FPRWen){ - FPRReg = * (uint8_t *) buf2; - FPRReg = FPRReg & 0x1F; - BitShiftArray(buf3, buf2, 5, newPayloadSize); - FPRData = * (uint64_t *) buf3; - } - if(GPRWen ^ FPRWen){ - payload += 8; - Buf2Size = payloadsize - 38; - BitShiftArray(buf2, payload, 6, Buf2Size); - }else if(GPRWen & FPRWen){ - payload += 17; - Buf2Size = payloadsize - 47; - BitShiftArray(buf2, payload, 3, Buf2Size); - }else{ - Buf2Size = payloadsize - 30; - BitShiftArray(buf2, payload, 1, Buf2Size); - } - buf2ptr = buf2; - for(CSRIndex = 0; CSRIndex < CSRCount; CSRIndex++){ - CSRReg[CSRIndex] = (*(uint16_t *) buf2ptr) & 0xFFF; - Buf2Size -= 1; - BitShiftArray(buf3, buf2ptr + 1, 4, Buf2Size); - CSRValue[CSRIndex] = (*(uint64_t *) buf3); - CSRWen[CSRIndex] = 1; - buf2ptr = buf3; - } - } - InstructionData->PC = PC; - InstructionData->insn = insn; - InstructionData->Mcycle = Mcycle; - InstructionData->Minstret = Minstret; - InstructionData->Trap = Trap; - InstructionData->PrivilegeMode = PrivilegeMode; - InstructionData->GPREn = GPRWen; - InstructionData->FPREn = FPRWen; - InstructionData->CSRCount = CSRCount; - InstructionData->GPRReg = GPRReg; - InstructionData->GPRValue = GPRData; - InstructionData->FPRReg = FPRReg; - InstructionData->FPRValue = FPRData; - for(CSRIndex = 0; CSRIndex < 3; CSRIndex++){ - InstructionData->CSRWen[CSRIndex] = CSRWen[CSRIndex]; - InstructionData->CSRReg[CSRIndex] = CSRReg[CSRIndex]; - InstructionData->CSRValue[CSRIndex] = CSRValue[CSRIndex]; - } -} + + InstructionData->CSRReg[0] = FixedInstructionData->CSR0Wen; + if(InstructionData->CSRReg[0] != 0) InstructionData->CSRWen[0] = 1; + else InstructionData->CSRWen[0] = 0; + InstructionData->CSRValue[0] = FixedInstructionData->CSR0Value; + + InstructionData->CSRReg[1] = FixedInstructionData->CSR1Wen; + if(InstructionData->CSRReg[1] != 0) InstructionData->CSRWen[1] = 1; + else InstructionData->CSRWen[1] = 0; + InstructionData->CSRValue[1] = FixedInstructionData->CSR1Value; + + InstructionData->CSRReg[2] = FixedInstructionData->CSR2Wen; + if(InstructionData->CSRReg[2] != 0) InstructionData->CSRWen[2] = 1; + else InstructionData->CSRWen[2] = 0; + InstructionData->CSRValue[2] = FixedInstructionData->CSR2Value; + + //InstructionData->CSRReg[3] = FixedInstructionData->CSR3Wen; + InstructionData->CSRReg[3] = 0; + if(InstructionData->CSRReg[3] != 0) InstructionData->CSRWen[3] = 1; + else InstructionData->CSRWen[3] = 0; + InstructionData->CSRValue[3] = FixedInstructionData->CSR3Value; + + //InstructionData->CSRReg[4] = FixedInstructionData->CSR4Wen; + InstructionData->CSRReg[4] = 0; + if(InstructionData->CSRReg[4] != 0) InstructionData->CSRWen[4] = 1; + else InstructionData->CSRWen[4] = 0; + InstructionData->CSRValue[4] = FixedInstructionData->CSR4Value; +} void PrintInstructionData(RequiredRVVI_t *InstructionData){ int CSRIndex; @@ -468,33 +441,3 @@ void PrintInstructionData(RequiredRVVI_t *InstructionData){ } printf("\n"); } - -void BitShiftArray(uint8_t *dst, uint8_t *src, uint8_t ShiftAmount, int Length){ - // always shift right by ShiftAmount (0 to 7 bit positions). - // *** this implemenation is very inefficient. improve later. - if(ShiftAmount < 0 || ShiftAmount > 7) return; - /* Read the first source byte - Read the second source byte - Right Shift byte 1 by ShiftAmount - Right Rotate byte 2 by ShiftAmount - Mask byte 2 by ~(2^ShiftAmount -1) - OR together the two bytes to form the final next byte - - repeat this for each byte - On the last byte we don't do the last steps - */ - int Index; - for(Index = 0; Index < Length - 1; Index++){ - uint8_t byte1 = src[Index]; - uint8_t byte2 = src[Index+1]; - byte1 = byte1 >> ShiftAmount; - uint8_t byte2rot = (byte2 << (unsigned) (8 - ShiftAmount)) & 0xff; - uint8_t byte1final = byte2rot | byte1; - dst[Index] = byte1final; - } - // fence post - // For last one there is only one source byte - uint8_t byte1 = src[Length-1]; - byte1 = byte1 >> ShiftAmount; - dst[Length-1] = byte1; -} diff --git a/fpga/src/fpgaTopArtyA7.sv b/fpga/src/fpgaTopArtyA7.sv index 827ca1438..b06a23ced 100644 --- a/fpga/src/fpgaTopArtyA7.sv +++ b/fpga/src/fpgaTopArtyA7.sv @@ -1139,7 +1139,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 1) logic [P.XLEN-1:0] CSRArray [TOTAL_CSRS-1:0]; logic valid; - logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvvi; + logic [72+(5*P.XLEN) + MAX_CSRS*(P.XLEN+16)-1:0] rvvi; assign StallE = fpgaTop.wallypipelinedsoc.core.StallE; assign StallM = fpgaTop.wallypipelinedsoc.core.StallM; diff --git a/src/rvvi/packetizer.sv b/src/rvvi/packetizer.sv index cd3103fa4..77c58f467 100644 --- a/src/rvvi/packetizer.sv +++ b/src/rvvi/packetizer.sv @@ -32,7 +32,7 @@ module packetizer import cvw::*; #(parameter cvw_t P, parameter logic [31:0] RVVI_INIT_TIME_OUT = 32'd4, parameter logic [31:0] RVVI_PACKET_DELAY = 32'd2 )( - input logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvvi, + input logic [72+(5*P.XLEN) + MAX_CSRS*(P.XLEN+16)-1:0] rvvi, input logic valid, input logic m_axi_aclk, m_axi_aresetn, output logic RVVIStall, @@ -45,7 +45,9 @@ module packetizer import cvw::*; #(parameter cvw_t P, input logic RvviAxiWready ); - localparam TotalFrameLengthBits = 2*48+17+16+187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12); + localparam NearTotalFrameLengthBits = 2*48+16+72+(5*P.XLEN) + MAX_CSRS*(P.XLEN+16); + localparam WordPadLen = 32 - (NearTotalFrameLengthBits % 32); + localparam TotalFrameLengthBits = NearTotalFrameLengthBits + WordPadLen; localparam TotalFrameLengthBytes = TotalFrameLengthBits / 8; logic [9:0] WordCount; @@ -56,11 +58,11 @@ module packetizer import cvw::*; #(parameter cvw_t P, logic WordCountEnable; logic [47:0] SrcMac, DstMac; logic [15:0] EthType, Length; - logic [31:0] Tag; logic [TotalFrameLengthBits-1:0] TotalFrame; logic [31:0] TotalFrameWords [TotalFrameLengthBytes/4-1:0]; + logic [WordPadLen-1:0] WordPad; - logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvviDelay; + logic [72+(5*P.XLEN) + MAX_CSRS*(P.XLEN+16)-1:0] rvviDelay; typedef enum {STATE_RST, STATE_COUNT, STATE_RDY, STATE_WAIT, STATE_TRANS, STATE_TRANS_INSERT_DELAY} statetype; (* mark_debug = "true" *) statetype CurrState, NextState; @@ -109,7 +111,7 @@ module packetizer import cvw::*; #(parameter cvw_t P, counter #(32) framecounter(m_axi_aclk, ~m_axi_aresetn, (RvviAxiWready & RvviAxiWlast), FrameCount); - flopenr #(187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)) rvvireg(m_axi_aclk, ~m_axi_aresetn, valid, rvvi, rvviDelay); + flopenr #(72+(5*P.XLEN) + MAX_CSRS*(P.XLEN+16)) rvvireg(m_axi_aclk, ~m_axi_aresetn, valid, rvvi, rvviDelay); counter #(10) WordCounter(m_axi_aclk, WordCountReset, WordCountEnable, WordCount); @@ -124,12 +126,12 @@ module packetizer import cvw::*; #(parameter cvw_t P, end assign Length = {4'b0, BytesInFrame}; - assign TotalFrame = {17'b0, rvviDelay, EthType, DstMac, SrcMac}; + assign WordPad = '0; + assign TotalFrame = {WordPad, rvviDelay, EthType, DstMac, SrcMac}; // *** fix me later assign DstMac = 48'h8F54_0000_1654; // made something up assign SrcMac = 48'h4502_1111_6843; - assign Tag = 32'b0; assign EthType = 16'h005c; assign RvviAxiWdata = TotalFrameWords[WordCount[4:0]]; diff --git a/src/rvvi/rvvisynth.sv b/src/rvvi/rvvisynth.sv index 0c0214b3f..aa1c55aef 100644 --- a/src/rvvi/rvvisynth.sv +++ b/src/rvvi/rvvisynth.sv @@ -45,7 +45,7 @@ module rvvisynth import cvw::*; #(parameter cvw_t P, input logic [P.XLEN-1:0] GPRValue, FPRValue, input var logic [P.XLEN-1:0] CSRArray [TOTAL_CSRS-1:0], output logic valid, - output logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvvi + output logic [72+(5*P.XLEN) + MAX_CSRS*(P.XLEN+16)-1:0] rvvi ); // pipeline controlls @@ -65,9 +65,9 @@ module rvvisynth import cvw::*; #(parameter cvw_t P, logic [MAX_CSRS-1:0] EnabledCSRs; logic [MAX_CSRS-1:0] CSRCountShort; logic [11:0] CSRCount; - logic [177+P.XLEN-1:0] Required; - logic [10+2*P.XLEN-1:0] Registers; - logic [MAX_CSRS*(P.XLEN+12)-1:0] CSRs; + logic [56+3*P.XLEN-1:0] Required; + logic [16+2*P.XLEN-1:0] Registers; + logic [MAX_CSRS*(P.XLEN+16)-1:0] CSRs; assign XLENZeros = '0; @@ -82,10 +82,10 @@ module rvvisynth import cvw::*; #(parameter cvw_t P, flopenrc #(1) TrapWReg (clk, reset, 1'b0, ~StallW, TrapM, TrapW); assign valid = InstrValidW & ~StallW; - assign Required = {CSRCount, FPRWen, GPRWen, PrivilegeModeW, TrapW, Minstret, Mcycle, InstrRawW, PCW}; - assign Registers = {FPRWen, GPRWen} == 2'b11 ? {FPRValue, FPRAddr, GPRValue, GPRAddr} : - {FPRWen, GPRWen} == 2'b01 ? {XLENZeros, 5'b0, GPRValue, GPRAddr} : - {FPRWen, GPRWen} == 2'b10 ? {XLENZeros, 5'b0, FPRValue, FPRAddr} : + assign Required = {4'b0, CSRCount, 3'b0, FPRWen, GPRWen, PrivilegeModeW, TrapW, Minstret, Mcycle, InstrRawW, PCW}; + assign Registers = {FPRWen, GPRWen} == 2'b11 ? {FPRValue, 3'b0, FPRAddr, GPRValue, 3'b0, GPRAddr} : + {FPRWen, GPRWen} == 2'b01 ? {XLENZeros, 8'b0, GPRValue, 3'b0, GPRAddr} : + {FPRWen, GPRWen} == 2'b10 ? {FPRValue, 3'b0, FPRAddr, XLENZeros, 8'b0} : '0; /* verilator lint_off UNOPTFLAT */ @@ -116,7 +116,7 @@ module rvvisynth import cvw::*; #(parameter cvw_t P, for(index = 0; index < MAX_CSRS; index = index + 1) begin // step 3b csrindextoaddr #(TOTAL_CSRS) csrindextoaddr(CSRWenPriorityMatrix[index], CSRAddr[index]); - assign CSRs[(index+1) * (P.XLEN + 12)- 1: index * (P.XLEN + 12)] = {CSRValue[index], CSRAddr[index]}; + assign CSRs[(index+1) * (P.XLEN + 16)- 1: index * (P.XLEN + 16)] = {CSRValue[index], 4'b0, CSRAddr[index]}; assign EnabledCSRs[index] = |CSRWenPriorityMatrix[index]; end diff --git a/testbench/common/rvvitbwrapper.sv b/testbench/common/rvvitbwrapper.sv index 708cd0e7b..bd964d40d 100644 --- a/testbench/common/rvvitbwrapper.sv +++ b/testbench/common/rvvitbwrapper.sv @@ -41,7 +41,7 @@ module rvvitbwrapper import cvw::*; #(parameter cvw_t P, ); logic valid; - logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvvi; + logic [72+(5*P.XLEN) + MAX_CSRS*(P.XLEN+16)-1:0] rvvi; localparam TOTAL_CSRS = 36; From cc2a41045f2c60df90c46650dd5f4a46f19cabb9 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 22 Sep 2024 22:00:27 -0700 Subject: [PATCH 02/19] RV64 coverage configuration --- config/rv64gc/coverage.svh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index 855c1f6a9..c89b116c9 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -7,5 +7,6 @@ `include "RV64I_coverage.svh" `include "RV64M_coverage.svh" -//`include "RV64F_coverage.svh" +`include "RV64F_coverage.svh" `include "RV64Zicond_coverage.svh" +`include "RV64Zca_coverage.svh" From 468e48899aa6e5808a5245583eb8d55d3b03ea81 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 23 Sep 2024 06:06:26 -0700 Subject: [PATCH 03/19] Remove outdated code --- src/ieu/alu.sv | 1 - 1 file changed, 1 deletion(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index acd5b025d..b63123126 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -98,7 +98,6 @@ module alu import cvw::*; #(parameter cvw_t P) ( 3'b010: FullResult = {{(P.XLEN-1){1'b0}}, LT}; // slt 3'b011: FullResult = {{(P.XLEN-1){1'b0}}, LTU}; // sltu 3'b100: FullResult = A ^ CondMaskInvB; // xor, xnor, binv -// 3'b101: FullResult = (P.ZBS_SUPPORTED) ? {{(P.XLEN-1){1'b0}},{|(A & CondMaskInvB)}} : Shift; // bext (or IEU shift when BMU not supported) 3'b101: FullResult = (P.ZBS_SUPPORTED) ? {{(P.XLEN-1){1'b0}},{|(AndResult)}} : Shift; // bext (or IEU shift when BMU not supported) 3'b110: FullResult = A | CondMaskInvB; // or, orn, bset 3'b111: FullResult = AndResult; // and, bclr, czero.* From 4528a5cebced174f18737e18ca8059db4dc33cab Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 26 Sep 2024 08:08:59 -0700 Subject: [PATCH 04/19] Issue 963: VCS rv32gc lockstep simulation --- bin/wsim | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/bin/wsim b/bin/wsim index 88b0dd6c8..38213a332 100755 --- a/bin/wsim +++ b/bin/wsim @@ -86,11 +86,12 @@ if (args.tb == "testbench_fp"): # if lockstep is enabled, then we need to pass the Imperas lockstep arguments if(int(args.locksteplog) >= 1): EnableLog = 1 else: EnableLog = 0 -if((args.lockstep or args.lockstepverbose or args.fcov or args.fcovimp) and args.sim == "questa"): - prefix = "IMPERAS_TOOLS=" + WALLY + "/config/"+args.config+"/imperas.ic" - prefix = "MTI_VCO_MODE=64 " + prefix -else: - prefix = "" +prefix = "" +if (args.lockstep or args.lockstepverbose or args.fcov or args.fcovimp): + if (args.sim == "questa" or args.sim == "vcs"): + prefix = "IMPERAS_TOOLS=" + WALLY + "/config/"+args.config+"/imperas.ic" + if (args.sim == "questa"): + prefix = "MTI_VCO_MODE=64 " + prefix if (args.lockstep or args.lockstepverbose): if(args.locksteplog != 0): ImperasPlusArgs = " +IDV_TRACE2LOG=" + str(EnableLog) + " +IDV_TRACE2LOG_AFTER=" + str(args.locksteplog) From d9719ac9a08cff89fa741ee485766241749b14be Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Thu, 26 Sep 2024 10:24:06 -0500 Subject: [PATCH 05/19] Updated wsim to not run with invalid --lockstep options. --- bin/wsim | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/bin/wsim b/bin/wsim index 88b0dd6c8..7de45732e 100755 --- a/bin/wsim +++ b/bin/wsim @@ -66,7 +66,9 @@ if(args.testsuite.endswith('.elf') and args.elf == ""): # No --elf argument; che print("ELF file not found: " + args.testsuite) exit(1) - +if(args.lockstep and not args.testsuite.endswith('.elf')): + print(f"Invalid Options. Cannot run a testsuite, {args.testsuite} with lockstep. Must run a single elf.") + exit(1) # Validate arguments if (args.gui or args.ccov or args.fcov or args.fcovimp or args.fcovrvvi or args.lockstep or args.lockstepverbose): From bf0c7fba95e1d4ebfad6a3b963d710b3057c0f1c Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 28 Sep 2024 20:20:06 -0700 Subject: [PATCH 06/19] Update fp Makefile to generate softfloat --- tests/fp/testfloat/Makefile | 71 +++++++++++++++++++++++-------------- 1 file changed, 44 insertions(+), 27 deletions(-) diff --git a/tests/fp/testfloat/Makefile b/tests/fp/testfloat/Makefile index 2bc5854a2..2922ad695 100755 --- a/tests/fp/testfloat/Makefile +++ b/tests/fp/testfloat/Makefile @@ -8,40 +8,57 @@ .NOTPARALLEL: .SECONDEXPANSION: -TESTFLOATS := ieee riscv -SOFTFLOAT_BUILD_DIR := ${WALLY}/addins/berkeley-softfloat-3/build/Linux-x86_64-GCC/ -TESTFLOAT_BUILD_DIR := ${WALLY}/addins/berkeley-testfloat-3/build/Linux-x86_64-GCC/ +DIR := $(shell pwd) + +# SoftFloat variables +SOFTFLOAT_DIR := ${WALLY}/addins/berkeley-softfloat-3 +SOFTFLOAT_INCLUDE_DIR := source/include/ +SOFTFLOAT_BUILD_DIR := build/Linux-x86_64-GCC/ +SOFTFLOAT_ORIGINAL_BUILD_DIR := ${SOFTFLOAT_DIR}/${SOFTFLOAT_BUILD_DIR} +SOFTFLOAT_ORIGINAL_INCLUDE_DIR := ${SOFTFLOAT_DIR}/${SOFTFLOAT_INCLUDE_DIR} +SOFTFLOAT_LIB := softfloat.a +COPIED_SOFTFLOAT_LIB := softfloat/${SOFTFLOAT_BUILD_DIR}/${SOFTFLOAT_LIB} +ORIGINAL_SOFTFLOAT_LIB := ${SOFTFLOAT_ORIGINAL_BUILD_DIR}/${SOFTFLOAT_LIB} + +# TestFloat variables +TESTFLOAT_DIR := ${WALLY}/addins/berkeley-testfloat-3 +TESTFLOAT_BUILD_DIR := build/Linux-x86_64-GCC +TESTFLOAT_ORIGINAL_BUILD_DIR := ${TESTFLOAT_DIR}/${TESTFLOAT_BUILD_DIR} TESTFLOAT_EXECUTABLES := testfloat testfloat_gen testfloat_ver testsoftfloat timesoftfloat -ORIGINAL_TESTFLOAT_EXECUTABLES := $(foreach item,${TESTFLOAT_EXECUTABLES},$(patsubst %,${TESTFLOAT_BUILD_DIR}%,${item})) +ORIGINAL_TESTFLOAT_EXECUTABLES := $(foreach item,${TESTFLOAT_EXECUTABLES},$(patsubst %,${TESTFLOAT_ORIGINAL_BUILD_DIR}%,/${item})) -.PHONY: all ieee-softfloat riscv-softfloat ${TESTFLOATS} testfloat clean +.PHONY: all ieee riscv clean -all: riscv ieee +all: ieee riscv -${TESTFLOATS}: dir_$$@ $$@/testfloat_gen +ieee riscv: ieee-testfloat #$$@/testfloat/${TESTFLOAT_BUILD_DIR}/testfloat -.PRECIOUS: %/testfloat_gen -%/testfloat_gen: - $(MAKE) $*-softfloat - $(MAKE) testfloat - cp -r ${ORIGINAL_TESTFLOAT_EXECUTABLES} $*/ +ieee-testfloat: ieee/testfloat/${TESTFLOAT_BUILD_DIR}/testfloat +ieee-softfloat: ieee/$(COPIED_SOFTFLOAT_LIB) -ieee-softfloat: - $(MAKE) -C $(SOFTFLOAT_BUILD_DIR) clean - $(MAKE) -C $(SOFTFLOAT_BUILD_DIR) +# .PRECIOUS: %/testfloat +%/testfloat/${TESTFLOAT_BUILD_DIR}/testfloat: %/$(COPIED_SOFTFLOAT_LIB) + $(MAKE) -C $(TESTFLOAT_ORIGINAL_BUILD_DIR) clean + $(MAKE) SOFTFLOAT_DIR=${DIR}/$*/softfloat -C $(TESTFLOAT_ORIGINAL_BUILD_DIR) + cp -r ${ORIGINAL_TESTFLOAT_EXECUTABLES} $*/testfloat/${TESTFLOAT_BUILD_DIR}/ + $(MAKE) -C $(TESTFLOAT_ORIGINAL_BUILD_DIR) clean -riscv-softfloat: - $(MAKE) -C $(SOFTFLOAT_BUILD_DIR) clean - $(MAKE) SPECIALIZE_TYPE=RISCV -C $(SOFTFLOAT_BUILD_DIR) +# Build specified version of SoftFloat, either IEEE or RISCV +riscv/$(COPIED_SOFTFLOAT_LIB): SPECIALIZE_TYPE = SPECIALIZE_TYPE=RISCV +%/$(COPIED_SOFTFLOAT_LIB): %/${SOFTFLOAT_INCLUDE_DIR}/softfloat.h + $(MAKE) -C $(SOFTFLOAT_ORIGINAL_BUILD_DIR) clean + $(MAKE) $(SPECIALIZE_TYPE) -C $(SOFTFLOAT_ORIGINAL_BUILD_DIR) + cp ${ORIGINAL_SOFTFLOAT_LIB} $*/${COPIED_SOFTFLOAT_LIB} + $(MAKE) -C $(SOFTFLOAT_ORIGINAL_BUILD_DIR) clean -testfloat: - $(MAKE) -C $(TESTFLOAT_BUILD_DIR) clean - $(MAKE) -C $(TESTFLOAT_BUILD_DIR) - -dir_%: - mkdir -p $* +# Setup directories and link softfloat headers +%/${SOFTFLOAT_INCLUDE_DIR}/softfloat.h: + mkdir -p $*/softfloat/source/include + ln -sf ${SOFTFLOAT_ORIGINAL_INCLUDE_DIR}/* $*/softfloat/${SOFTFLOAT_INCLUDE_DIR} + mkdir -p $*/softfloat/build/Linux-x86_64-GCC + mkdir -p $*/testfloat/${TESTFLOAT_BUILD_DIR} clean: - $(MAKE) -C $(SOFTFLOAT_BUILD_DIR) clean - $(MAKE) -C $(TESTFLOAT_BUILD_DIR) clean - rm -f ieee/* riscv/* + $(MAKE) -C $(SOFTFLOAT_ORIGINAL_BUILD_DIR) clean + $(MAKE) -C $(TESTFLOAT_ORIGINAL_BUILD_DIR) clean + rm -rf ieee/* riscv/* From 0c2ce32c56d730dccc002ae506275f9443c9c9b9 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 28 Sep 2024 20:23:27 -0700 Subject: [PATCH 07/19] Update fp Makefile to generate softfloat --- tests/fp/testfloat/Makefile | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/tests/fp/testfloat/Makefile b/tests/fp/testfloat/Makefile index 2922ad695..6ca22c573 100755 --- a/tests/fp/testfloat/Makefile +++ b/tests/fp/testfloat/Makefile @@ -31,12 +31,8 @@ ORIGINAL_TESTFLOAT_EXECUTABLES := $(foreach item,${TESTFLOAT_EXECUTABLES},$(pats all: ieee riscv -ieee riscv: ieee-testfloat #$$@/testfloat/${TESTFLOAT_BUILD_DIR}/testfloat +ieee riscv: $$@/testfloat/${TESTFLOAT_BUILD_DIR}/testfloat -ieee-testfloat: ieee/testfloat/${TESTFLOAT_BUILD_DIR}/testfloat -ieee-softfloat: ieee/$(COPIED_SOFTFLOAT_LIB) - -# .PRECIOUS: %/testfloat %/testfloat/${TESTFLOAT_BUILD_DIR}/testfloat: %/$(COPIED_SOFTFLOAT_LIB) $(MAKE) -C $(TESTFLOAT_ORIGINAL_BUILD_DIR) clean $(MAKE) SOFTFLOAT_DIR=${DIR}/$*/softfloat -C $(TESTFLOAT_ORIGINAL_BUILD_DIR) @@ -59,6 +55,4 @@ riscv/$(COPIED_SOFTFLOAT_LIB): SPECIALIZE_TYPE = SPECIALIZE_TYPE=RISCV mkdir -p $*/testfloat/${TESTFLOAT_BUILD_DIR} clean: - $(MAKE) -C $(SOFTFLOAT_ORIGINAL_BUILD_DIR) clean - $(MAKE) -C $(TESTFLOAT_ORIGINAL_BUILD_DIR) clean rm -rf ieee/* riscv/* From 14b630a403f3500952a7df3eb73814cf7d92bfbe Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 28 Sep 2024 20:56:58 -0700 Subject: [PATCH 08/19] More testfloat fixups --- .gitignore | 3 ++- tests/fp/Makefile | 7 ++++--- tests/fp/{testfloat => berkeley-float}/Makefile | 0 tests/fp/vectors/ieee/Makefile | 4 ++-- tests/fp/vectors/riscv/Makefile | 4 ++-- 5 files changed, 10 insertions(+), 8 deletions(-) rename tests/fp/{testfloat => berkeley-float}/Makefile (100%) diff --git a/.gitignore b/.gitignore index bd3235578..4757d62cd 100644 --- a/.gitignore +++ b/.gitignore @@ -28,7 +28,8 @@ tests/riscof/riscof_work/ tests/wally-riscv-arch-test/riscv-test-suite/*/I/*/** tests/fp/vectors/**/*.tv tests/fp/vectors/**/sed* -tests/fp/testfloat/* +tests/fp/berkeley-float/* +!tests/fp/berkeley-float/Makefile tests/fp/combined_IF_vectors/IF_vectors/*.tv tests/custom/*/*/ tests/custom/*/*/*.memfile diff --git a/tests/fp/Makefile b/tests/fp/Makefile index 25057f490..d6359f249 100755 --- a/tests/fp/Makefile +++ b/tests/fp/Makefile @@ -2,7 +2,8 @@ # Floating Point Tests Makefile for CORE-V-Wally # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -TESTFLOATS := testfloat/ieee/testfloat_gen testfloat/riscv/testfloat_gen +TESTFLOAT := testfloat/build/Linux-x86_64-GCC/testfloat_gen +TESTFLOATS := berkeley-float/ieee/${TESTFLOAT} berkeley-float/riscv/${TESTFLOAT} .PHONY: all vectors combined_IF_vectors testfloat clean @@ -18,11 +19,11 @@ combined_IF_vectors: ${WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/M/src ve ${TESTFLOATS}: testfloat testfloat: - $(MAKE) -C testfloat + $(MAKE) -C berkeley-float clean: $(MAKE) -C vectors clean - $(MAKE) -C testfloat clean + $(MAKE) -C berkeley-float clean rm -f ${WALLY}/tests/fp/combined_IF_vectors/IF_vectors/*.tv ${WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/M/src: diff --git a/tests/fp/testfloat/Makefile b/tests/fp/berkeley-float/Makefile similarity index 100% rename from tests/fp/testfloat/Makefile rename to tests/fp/berkeley-float/Makefile diff --git a/tests/fp/vectors/ieee/Makefile b/tests/fp/vectors/ieee/Makefile index 1a37321d3..a44f54d5d 100755 --- a/tests/fp/vectors/ieee/Makefile +++ b/tests/fp/vectors/ieee/Makefile @@ -10,8 +10,8 @@ SHELL := /bin/bash VECTOR_TYPE := ieee -TESTFLOAT_DIR := ${WALLY}/tests/fp/testfloat -TESTFLOAT_GEN := ${TESTFLOAT_DIR}/${VECTOR_TYPE}/testfloat_gen +TESTFLOAT_DIR := ../../berkeley-float +TESTFLOAT_GEN := ${TESTFLOAT_DIR}/${VECTOR_TYPE}/testfloat/build/Linux-x86_64-GCC/testfloat_gen # List of testvectors to generate. Each rounding mode will be generated for each test. cvtint := ui32_to_f16 ui32_to_f32 ui32_to_f64 ui32_to_f128 \ diff --git a/tests/fp/vectors/riscv/Makefile b/tests/fp/vectors/riscv/Makefile index 91615a349..d3ed6d9a7 100755 --- a/tests/fp/vectors/riscv/Makefile +++ b/tests/fp/vectors/riscv/Makefile @@ -10,8 +10,8 @@ SHELL := /bin/bash VECTOR_TYPE := riscv -TESTFLOAT_DIR := ${WALLY}/tests/fp/testfloat -TESTFLOAT_GEN := ${TESTFLOAT_DIR}/${VECTOR_TYPE}/testfloat_gen +TESTFLOAT_DIR := ../../berkeley-float +TESTFLOAT_GEN := ${TESTFLOAT_DIR}/${VECTOR_TYPE}/testfloat/build/Linux-x86_64-GCC/testfloat_gen # List of testvectors to generate. Each rounding mode will be generated for each test. cvtint := ui32_to_f16 ui32_to_f32 ui32_to_f64 ui32_to_f128 \ From 495d1c71452d7d9c88add60c715290fc87e39dec Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 28 Sep 2024 21:43:41 -0700 Subject: [PATCH 09/19] Only generate RISCV version of softfloat --- tests/fp/Makefile | 26 +++++++---- tests/fp/berkeley-float/Makefile | 58 ----------------------- tests/fp/vectors/Makefile | 80 ++++++++++++++++++++++++++++---- tests/fp/vectors/ieee/Makefile | 78 ------------------------------- tests/fp/vectors/riscv/Makefile | 78 ------------------------------- 5 files changed, 87 insertions(+), 233 deletions(-) delete mode 100755 tests/fp/berkeley-float/Makefile mode change 100644 => 100755 tests/fp/vectors/Makefile delete mode 100755 tests/fp/vectors/ieee/Makefile delete mode 100755 tests/fp/vectors/riscv/Makefile diff --git a/tests/fp/Makefile b/tests/fp/Makefile index d6359f249..be0cce7d1 100755 --- a/tests/fp/Makefile +++ b/tests/fp/Makefile @@ -2,13 +2,17 @@ # Floating Point Tests Makefile for CORE-V-Wally # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -TESTFLOAT := testfloat/build/Linux-x86_64-GCC/testfloat_gen -TESTFLOATS := berkeley-float/ieee/${TESTFLOAT} berkeley-float/riscv/${TESTFLOAT} +SOFTFLOAT_DIR := ${WALLY}/addins/berkeley-softfloat-3/build/Linux-x86_64-GCC +TESTFLOAT_DIR := ${WALLY}/addins/berkeley-testfloat-3/build/Linux-x86_64-GCC -.PHONY: all vectors combined_IF_vectors testfloat clean +.PHONY: all softfloat testfloat vectors combined_IF_vectors clean all: vectors combined_IF_vectors +softfloat: ${SOFTFLOAT_DIR}/softfloat.a + +testfloat: ${TESTFLOAT_DIR}/testfloat + vectors: ${TESTFLOATS} $(MAKE) -C ${WALLY}/tests/fp/vectors @@ -16,15 +20,17 @@ combined_IF_vectors: ${WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/M/src ve cd ${WALLY}/tests/fp/combined_IF_vectors \ && ./create_IF_vectors.sh -${TESTFLOATS}: testfloat - -testfloat: - $(MAKE) -C berkeley-float - clean: - $(MAKE) -C vectors clean - $(MAKE) -C berkeley-float clean + $(MAKE) -C ${WALLY}/tests/fp/vectors clean + $(MAKE) -C ${SOFTFLOAT_DIR} clean + $(MAKE) -C ${TESTFLOAT_DIR} clean rm -f ${WALLY}/tests/fp/combined_IF_vectors/IF_vectors/*.tv ${WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/M/src: @$(error "riscv-arch-tests must be generated first. Run make from $$WALLY") + +${SOFTFLOAT_DIR}/softfloat.a: + $(MAKE) SPECIALIZE_TYPE=RISCV -C ${SOFTFLOAT_DIR} + +${TESTFLOAT_DIR}/testfloat: ${SOFTFLOAT_DIR}/softfloat.a + $(MAKE) -C ${TESTFLOAT_DIR} diff --git a/tests/fp/berkeley-float/Makefile b/tests/fp/berkeley-float/Makefile deleted file mode 100755 index 6ca22c573..000000000 --- a/tests/fp/berkeley-float/Makefile +++ /dev/null @@ -1,58 +0,0 @@ -# Jordan Carlin, jcarlin@hmc.edu, August 2024 -# Makefile to generate RISCV and IEEE varaints of Testfloat for CORE-V-Wally -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 - -# Makefile to build testfloat and softfloat executables for IEEE and RISC-V floating point variants - -# Disable parallel execution because both versions of softfloat/testfloat use the same build directory -.NOTPARALLEL: -.SECONDEXPANSION: - -DIR := $(shell pwd) - -# SoftFloat variables -SOFTFLOAT_DIR := ${WALLY}/addins/berkeley-softfloat-3 -SOFTFLOAT_INCLUDE_DIR := source/include/ -SOFTFLOAT_BUILD_DIR := build/Linux-x86_64-GCC/ -SOFTFLOAT_ORIGINAL_BUILD_DIR := ${SOFTFLOAT_DIR}/${SOFTFLOAT_BUILD_DIR} -SOFTFLOAT_ORIGINAL_INCLUDE_DIR := ${SOFTFLOAT_DIR}/${SOFTFLOAT_INCLUDE_DIR} -SOFTFLOAT_LIB := softfloat.a -COPIED_SOFTFLOAT_LIB := softfloat/${SOFTFLOAT_BUILD_DIR}/${SOFTFLOAT_LIB} -ORIGINAL_SOFTFLOAT_LIB := ${SOFTFLOAT_ORIGINAL_BUILD_DIR}/${SOFTFLOAT_LIB} - -# TestFloat variables -TESTFLOAT_DIR := ${WALLY}/addins/berkeley-testfloat-3 -TESTFLOAT_BUILD_DIR := build/Linux-x86_64-GCC -TESTFLOAT_ORIGINAL_BUILD_DIR := ${TESTFLOAT_DIR}/${TESTFLOAT_BUILD_DIR} -TESTFLOAT_EXECUTABLES := testfloat testfloat_gen testfloat_ver testsoftfloat timesoftfloat -ORIGINAL_TESTFLOAT_EXECUTABLES := $(foreach item,${TESTFLOAT_EXECUTABLES},$(patsubst %,${TESTFLOAT_ORIGINAL_BUILD_DIR}%,/${item})) - -.PHONY: all ieee riscv clean - -all: ieee riscv - -ieee riscv: $$@/testfloat/${TESTFLOAT_BUILD_DIR}/testfloat - -%/testfloat/${TESTFLOAT_BUILD_DIR}/testfloat: %/$(COPIED_SOFTFLOAT_LIB) - $(MAKE) -C $(TESTFLOAT_ORIGINAL_BUILD_DIR) clean - $(MAKE) SOFTFLOAT_DIR=${DIR}/$*/softfloat -C $(TESTFLOAT_ORIGINAL_BUILD_DIR) - cp -r ${ORIGINAL_TESTFLOAT_EXECUTABLES} $*/testfloat/${TESTFLOAT_BUILD_DIR}/ - $(MAKE) -C $(TESTFLOAT_ORIGINAL_BUILD_DIR) clean - -# Build specified version of SoftFloat, either IEEE or RISCV -riscv/$(COPIED_SOFTFLOAT_LIB): SPECIALIZE_TYPE = SPECIALIZE_TYPE=RISCV -%/$(COPIED_SOFTFLOAT_LIB): %/${SOFTFLOAT_INCLUDE_DIR}/softfloat.h - $(MAKE) -C $(SOFTFLOAT_ORIGINAL_BUILD_DIR) clean - $(MAKE) $(SPECIALIZE_TYPE) -C $(SOFTFLOAT_ORIGINAL_BUILD_DIR) - cp ${ORIGINAL_SOFTFLOAT_LIB} $*/${COPIED_SOFTFLOAT_LIB} - $(MAKE) -C $(SOFTFLOAT_ORIGINAL_BUILD_DIR) clean - -# Setup directories and link softfloat headers -%/${SOFTFLOAT_INCLUDE_DIR}/softfloat.h: - mkdir -p $*/softfloat/source/include - ln -sf ${SOFTFLOAT_ORIGINAL_INCLUDE_DIR}/* $*/softfloat/${SOFTFLOAT_INCLUDE_DIR} - mkdir -p $*/softfloat/build/Linux-x86_64-GCC - mkdir -p $*/testfloat/${TESTFLOAT_BUILD_DIR} - -clean: - rm -rf ieee/* riscv/* diff --git a/tests/fp/vectors/Makefile b/tests/fp/vectors/Makefile old mode 100644 new mode 100755 index d72748539..d3ed6d9a7 --- a/tests/fp/vectors/Makefile +++ b/tests/fp/vectors/Makefile @@ -1,16 +1,78 @@ # Jordan Carlin, jcarlin@hmc.edu, September 20 2024 -# Makefile to generate floating point testvectors for CORE-V-Wally +# Makefile to generate RISCV floating point testvectors for CORE-V-Wally # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -.PHONY: ieee riscv clean -all: ieee riscv +.DELETE_ON_ERROR: +.SECONDEXPANSION: +.ONESHELL: +# MAKEFLAGS += --no-print-directory -ieee: - $(MAKE) -C ieee +SHELL := /bin/bash -riscv: - $(MAKE) -C riscv +VECTOR_TYPE := riscv +TESTFLOAT_DIR := ../../berkeley-float +TESTFLOAT_GEN := ${TESTFLOAT_DIR}/${VECTOR_TYPE}/testfloat/build/Linux-x86_64-GCC/testfloat_gen + +# List of testvectors to generate. Each rounding mode will be generated for each test. +cvtint := ui32_to_f16 ui32_to_f32 ui32_to_f64 ui32_to_f128 \ + ui64_to_f16 ui64_to_f32 ui64_to_f64 ui64_to_f128 \ + i32_to_f16 i32_to_f32 i32_to_f64 i32_to_f128 \ + i64_to_f16 i64_to_f32 i64_to_f64 i64_to_f128 \ + f16_to_ui32 f32_to_ui32 f64_to_ui32 f128_to_ui32 \ + f16_to_ui64 f32_to_ui64 f64_to_ui64 f128_to_ui64 +cvtfp := f16_to_i32 f32_to_i32 f64_to_i32 f128_to_i32 \ + f16_to_i64 f32_to_i64 f64_to_i64 f128_to_i64 \ + f16_to_f32 f16_to_f64 f16_to_f128 \ + f32_to_f16 f32_to_f64 f32_to_f128 \ + f64_to_f16 f64_to_f32 f64_to_f128 \ + f128_to_f16 f128_to_f32 f128_to_f64 +add := f16_add f32_add f64_add f128_add +sub := f16_sub f32_sub f64_sub f128_sub +mul := f16_mul f32_mul f64_mul f128_mul +div := f16_div f32_div f64_div f128_div +sqrt := f16_sqrt f32_sqrt f64_sqrt f128_sqrt +eq := f16_eq f32_eq f64_eq f128_eq +le := f16_le f32_le f64_le f128_le +lt := f16_lt f32_lt f64_lt f128_lt +mulAdd := f16_mulAdd f32_mulAdd f64_mulAdd f128_mulAdd + +tests := $(cvtfp) $(cvtint) $(add) $(sub) $(mul) $(div) $(sqrt) $(eq) $(le) $(lt) $(mulAdd) + +# Set rounding modes and extensions +rne: ROUND_MODE := rnear_even +rne: ROUND_EXT := rne +rz: ROUND_MODE := rminMag +rz: ROUND_EXT := rz +ru: ROUND_MODE := rmax +ru: ROUND_EXT := ru +rd: ROUND_MODE := rmin +rd: ROUND_EXT := rd +rnm: ROUND_MODE := rnear_maxMag +rnm: ROUND_EXT := rnm + +.PHONY: all rne rz ru rd rnm clean + +all: rne rz ru rd rnm + +# Generate test vectors for each rounding mode +rne: $(addsuffix _rne.tv, $(tests)) +rz: $(addsuffix _rz.tv, $(tests)) +ru: $(addsuffix _ru.tv, $(tests)) +rd: $(addsuffix _rd.tv, $(tests)) +rnm: $(addsuffix _rnm.tv, $(tests)) + +# Rule to generate individual test vectors +%.tv: ${TESTFLOAT_GEN} + @echo "Creating $(VECTOR_TYPE) $@ vectors" + @if [[ "$*" =~ "to" ]] || [[ "$*" =~ "sqrt" ]] ; then level=2 ; else level=1 ; fi + @if [[ "$*" =~ "to_i" ]] || [[ "$*" =~ "to_u" ]] ; then exact="-exact" ; else exact="" ; fi + ${TESTFLOAT_GEN} -tininessafter -level $$level $$exact -$(ROUND_MODE) $(patsubst %_$(ROUND_EXT).tv, %, $@) > $@ + @sed -i 's/ /_/g' $@ + +# Appropriate testfloat_gen must exist +${TESTFLOAT_GEN}: + $(MAKE) -C ${TESTFLOAT_DIR} ${VECTOR_TYPE} clean: - $(MAKE) -C ieee clean - $(MAKE) -C riscv clean + rm -f *.tv + rm -f sed* diff --git a/tests/fp/vectors/ieee/Makefile b/tests/fp/vectors/ieee/Makefile deleted file mode 100755 index a44f54d5d..000000000 --- a/tests/fp/vectors/ieee/Makefile +++ /dev/null @@ -1,78 +0,0 @@ -# Jordan Carlin, jcarlin@hmc.edu, September 20 2024 -# Makefile to generate IEEE floating point testvectors for CORE-V-Wally -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 - -.DELETE_ON_ERROR: -.SECONDEXPANSION: -.ONESHELL: -# MAKEFLAGS += --no-print-directory - -SHELL := /bin/bash - -VECTOR_TYPE := ieee -TESTFLOAT_DIR := ../../berkeley-float -TESTFLOAT_GEN := ${TESTFLOAT_DIR}/${VECTOR_TYPE}/testfloat/build/Linux-x86_64-GCC/testfloat_gen - -# List of testvectors to generate. Each rounding mode will be generated for each test. -cvtint := ui32_to_f16 ui32_to_f32 ui32_to_f64 ui32_to_f128 \ - ui64_to_f16 ui64_to_f32 ui64_to_f64 ui64_to_f128 \ - i32_to_f16 i32_to_f32 i32_to_f64 i32_to_f128 \ - i64_to_f16 i64_to_f32 i64_to_f64 i64_to_f128 \ - f16_to_ui32 f32_to_ui32 f64_to_ui32 f128_to_ui32 \ - f16_to_ui64 f32_to_ui64 f64_to_ui64 f128_to_ui64 -cvtfp := f16_to_i32 f32_to_i32 f64_to_i32 f128_to_i32 \ - f16_to_i64 f32_to_i64 f64_to_i64 f128_to_i64 \ - f16_to_f32 f16_to_f64 f16_to_f128 \ - f32_to_f16 f32_to_f64 f32_to_f128 \ - f64_to_f16 f64_to_f32 f64_to_f128 \ - f128_to_f16 f128_to_f32 f128_to_f64 -add := f16_add f32_add f64_add f128_add -sub := f16_sub f32_sub f64_sub f128_sub -mul := f16_mul f32_mul f64_mul f128_mul -div := f16_div f32_div f64_div f128_div -sqrt := f16_sqrt f32_sqrt f64_sqrt f128_sqrt -eq := f16_eq f32_eq f64_eq f128_eq -le := f16_le f32_le f64_le f128_le -lt := f16_lt f32_lt f64_lt f128_lt -mulAdd := f16_mulAdd f32_mulAdd f64_mulAdd f128_mulAdd - -tests := $(cvtfp) $(cvtint) $(add) $(sub) $(mul) $(div) $(sqrt) $(eq) $(le) $(lt) $(mulAdd) - -# Set rounding modes and extensions -rne: ROUND_MODE := rnear_even -rne: ROUND_EXT := rne -rz: ROUND_MODE := rminMag -rz: ROUND_EXT := rz -ru: ROUND_MODE := rmax -ru: ROUND_EXT := ru -rd: ROUND_MODE := rmin -rd: ROUND_EXT := rd -rnm: ROUND_MODE := rnear_maxMag -rnm: ROUND_EXT := rnm - -.PHONY: all rne rz ru rd rnm clean - -all: rne rz ru rd rnm - -# Generate test vectors for each rounding mode -rne: $(addsuffix _rne.tv, $(tests)) -rz: $(addsuffix _rz.tv, $(tests)) -ru: $(addsuffix _ru.tv, $(tests)) -rd: $(addsuffix _rd.tv, $(tests)) -rnm: $(addsuffix _rnm.tv, $(tests)) - -# Rule to generate individual test vectors -%.tv: ${TESTFLOAT_GEN} - @echo "Creating $(VECTOR_TYPE) $@ vectors" - @if [[ "$*" =~ "to" ]] || [[ "$*" =~ "sqrt" ]] ; then level=2 ; else level=1 ; fi - @if [[ "$*" =~ "to_i" ]] || [[ "$*" =~ "to_u" ]] ; then exact="-exact" ; else exact="" ; fi - ${TESTFLOAT_GEN} -tininessafter -level $$level $$exact -$(ROUND_MODE) $(patsubst %_$(ROUND_EXT).tv, %, $@) > $@ - @sed -i 's/ /_/g' $@ - -# Appropriate testfloat_gen must exist -${TESTFLOAT_GEN}: - $(MAKE) -C ${TESTFLOAT_DIR} ${VECTOR_TYPE} - -clean: - rm -f *.tv - rm -f sed* diff --git a/tests/fp/vectors/riscv/Makefile b/tests/fp/vectors/riscv/Makefile deleted file mode 100755 index d3ed6d9a7..000000000 --- a/tests/fp/vectors/riscv/Makefile +++ /dev/null @@ -1,78 +0,0 @@ -# Jordan Carlin, jcarlin@hmc.edu, September 20 2024 -# Makefile to generate RISCV floating point testvectors for CORE-V-Wally -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 - -.DELETE_ON_ERROR: -.SECONDEXPANSION: -.ONESHELL: -# MAKEFLAGS += --no-print-directory - -SHELL := /bin/bash - -VECTOR_TYPE := riscv -TESTFLOAT_DIR := ../../berkeley-float -TESTFLOAT_GEN := ${TESTFLOAT_DIR}/${VECTOR_TYPE}/testfloat/build/Linux-x86_64-GCC/testfloat_gen - -# List of testvectors to generate. Each rounding mode will be generated for each test. -cvtint := ui32_to_f16 ui32_to_f32 ui32_to_f64 ui32_to_f128 \ - ui64_to_f16 ui64_to_f32 ui64_to_f64 ui64_to_f128 \ - i32_to_f16 i32_to_f32 i32_to_f64 i32_to_f128 \ - i64_to_f16 i64_to_f32 i64_to_f64 i64_to_f128 \ - f16_to_ui32 f32_to_ui32 f64_to_ui32 f128_to_ui32 \ - f16_to_ui64 f32_to_ui64 f64_to_ui64 f128_to_ui64 -cvtfp := f16_to_i32 f32_to_i32 f64_to_i32 f128_to_i32 \ - f16_to_i64 f32_to_i64 f64_to_i64 f128_to_i64 \ - f16_to_f32 f16_to_f64 f16_to_f128 \ - f32_to_f16 f32_to_f64 f32_to_f128 \ - f64_to_f16 f64_to_f32 f64_to_f128 \ - f128_to_f16 f128_to_f32 f128_to_f64 -add := f16_add f32_add f64_add f128_add -sub := f16_sub f32_sub f64_sub f128_sub -mul := f16_mul f32_mul f64_mul f128_mul -div := f16_div f32_div f64_div f128_div -sqrt := f16_sqrt f32_sqrt f64_sqrt f128_sqrt -eq := f16_eq f32_eq f64_eq f128_eq -le := f16_le f32_le f64_le f128_le -lt := f16_lt f32_lt f64_lt f128_lt -mulAdd := f16_mulAdd f32_mulAdd f64_mulAdd f128_mulAdd - -tests := $(cvtfp) $(cvtint) $(add) $(sub) $(mul) $(div) $(sqrt) $(eq) $(le) $(lt) $(mulAdd) - -# Set rounding modes and extensions -rne: ROUND_MODE := rnear_even -rne: ROUND_EXT := rne -rz: ROUND_MODE := rminMag -rz: ROUND_EXT := rz -ru: ROUND_MODE := rmax -ru: ROUND_EXT := ru -rd: ROUND_MODE := rmin -rd: ROUND_EXT := rd -rnm: ROUND_MODE := rnear_maxMag -rnm: ROUND_EXT := rnm - -.PHONY: all rne rz ru rd rnm clean - -all: rne rz ru rd rnm - -# Generate test vectors for each rounding mode -rne: $(addsuffix _rne.tv, $(tests)) -rz: $(addsuffix _rz.tv, $(tests)) -ru: $(addsuffix _ru.tv, $(tests)) -rd: $(addsuffix _rd.tv, $(tests)) -rnm: $(addsuffix _rnm.tv, $(tests)) - -# Rule to generate individual test vectors -%.tv: ${TESTFLOAT_GEN} - @echo "Creating $(VECTOR_TYPE) $@ vectors" - @if [[ "$*" =~ "to" ]] || [[ "$*" =~ "sqrt" ]] ; then level=2 ; else level=1 ; fi - @if [[ "$*" =~ "to_i" ]] || [[ "$*" =~ "to_u" ]] ; then exact="-exact" ; else exact="" ; fi - ${TESTFLOAT_GEN} -tininessafter -level $$level $$exact -$(ROUND_MODE) $(patsubst %_$(ROUND_EXT).tv, %, $@) > $@ - @sed -i 's/ /_/g' $@ - -# Appropriate testfloat_gen must exist -${TESTFLOAT_GEN}: - $(MAKE) -C ${TESTFLOAT_DIR} ${VECTOR_TYPE} - -clean: - rm -f *.tv - rm -f sed* From 478ed242adc6a7c40cc35cefb8e491f60b58fdef Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 29 Sep 2024 00:32:18 -0700 Subject: [PATCH 10/19] More testfloat gen updates to switch to just riscv vectors --- tests/fp/Makefile | 6 +++--- tests/fp/vectors/Makefile | 15 ++++++--------- 2 files changed, 9 insertions(+), 12 deletions(-) diff --git a/tests/fp/Makefile b/tests/fp/Makefile index be0cce7d1..c98c37d8b 100755 --- a/tests/fp/Makefile +++ b/tests/fp/Makefile @@ -11,9 +11,9 @@ all: vectors combined_IF_vectors softfloat: ${SOFTFLOAT_DIR}/softfloat.a -testfloat: ${TESTFLOAT_DIR}/testfloat +testfloat: ${TESTFLOAT_DIR}/testfloat_gen -vectors: ${TESTFLOATS} +vectors: testfloat $(MAKE) -C ${WALLY}/tests/fp/vectors combined_IF_vectors: ${WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/M/src vectors @@ -32,5 +32,5 @@ ${WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/M/src: ${SOFTFLOAT_DIR}/softfloat.a: $(MAKE) SPECIALIZE_TYPE=RISCV -C ${SOFTFLOAT_DIR} -${TESTFLOAT_DIR}/testfloat: ${SOFTFLOAT_DIR}/softfloat.a +${TESTFLOAT_DIR}/testfloat_gen: ${SOFTFLOAT_DIR}/softfloat.a $(MAKE) -C ${TESTFLOAT_DIR} diff --git a/tests/fp/vectors/Makefile b/tests/fp/vectors/Makefile index d3ed6d9a7..5db3aa5ab 100755 --- a/tests/fp/vectors/Makefile +++ b/tests/fp/vectors/Makefile @@ -3,15 +3,11 @@ # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 .DELETE_ON_ERROR: -.SECONDEXPANSION: .ONESHELL: -# MAKEFLAGS += --no-print-directory - SHELL := /bin/bash -VECTOR_TYPE := riscv -TESTFLOAT_DIR := ../../berkeley-float -TESTFLOAT_GEN := ${TESTFLOAT_DIR}/${VECTOR_TYPE}/testfloat/build/Linux-x86_64-GCC/testfloat_gen +TESTFLOAT_DIR := ${WALLY}/addins/berkeley-testfloat-3/build/Linux-x86_64-GCC +TESTFLOAT_GEN := ${TESTFLOAT_DIR}/testfloat_gen # List of testvectors to generate. Each rounding mode will be generated for each test. cvtint := ui32_to_f16 ui32_to_f32 ui32_to_f64 ui32_to_f128 \ @@ -52,6 +48,7 @@ rnm: ROUND_EXT := rnm .PHONY: all rne rz ru rd rnm clean +# Generate all test vectors all: rne rz ru rd rnm # Generate test vectors for each rounding mode @@ -63,15 +60,15 @@ rnm: $(addsuffix _rnm.tv, $(tests)) # Rule to generate individual test vectors %.tv: ${TESTFLOAT_GEN} - @echo "Creating $(VECTOR_TYPE) $@ vectors" + @echo Creating $@ vectors @if [[ "$*" =~ "to" ]] || [[ "$*" =~ "sqrt" ]] ; then level=2 ; else level=1 ; fi @if [[ "$*" =~ "to_i" ]] || [[ "$*" =~ "to_u" ]] ; then exact="-exact" ; else exact="" ; fi ${TESTFLOAT_GEN} -tininessafter -level $$level $$exact -$(ROUND_MODE) $(patsubst %_$(ROUND_EXT).tv, %, $@) > $@ @sed -i 's/ /_/g' $@ -# Appropriate testfloat_gen must exist +# Generate TestFloat first if necessary ${TESTFLOAT_GEN}: - $(MAKE) -C ${TESTFLOAT_DIR} ${VECTOR_TYPE} + $(MAKE) -C ${WALLY}/tests/fp testfloat clean: rm -f *.tv From ad09edd17d87d419a5ff4fd289eba5f4390570e2 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 29 Sep 2024 00:37:26 -0700 Subject: [PATCH 11/19] Remove remaining ieee testcase --- bin/regression-wally | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index d3cbd0b41..c6c8ab523 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -438,13 +438,12 @@ if (args.testfloat): # for testfloat alone, just run testfloat tests if (args.testfloat or args.nightly): # for nightly, run testfloat along with others testfloatsim = "questa" # change to Verilator when Issue #707 about testfloat not running Verilator is resolved testfloatconfigs = ["fdqh_rv64gc", "fdq_rv64gc", "fdh_rv64gc", "fd_rv64gc", "fh_rv64gc", "f_rv64gc", "fdqh_rv32gc", "f_rv32gc"] - testfloatconfigs.append("fdqh_ieee_rv64gc") # run IEEE tests for single config for config in testfloatconfigs: tests = ["div", "sqrt", "add", "sub", "mul", "cvtint", "cvtfp", "fma", "cmp"] if ("f_" in config): tests.remove("cvtfp") for test in tests: - sim_log = WALLY + "/sim/" + testfloatsim + "/logs/"+config+"_"+test+".log" + sim_log = WALLY + "/sim/" + testfloatsim + "/logs/"+config+"_"+test+".log" tc = TestCase( name=test, variant=config, From a3214e168212c19083a42a0aa6781785e334fcf7 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 29 Sep 2024 00:40:31 -0700 Subject: [PATCH 12/19] Remove remaining ieee derived config --- config/derivlist.txt | 5 ----- 1 file changed, 5 deletions(-) diff --git a/config/derivlist.txt b/config/derivlist.txt index 91b062252..7e6cd6909 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -880,11 +880,6 @@ deriv fdqh_rv64gc rv64gc Q_SUPPORTED 1 ZFH_SUPPORTED 1 -# IEEE compatible FPU - -deriv fdqh_ieee_rv64gc fdqh_rv64gc -IEEE754 1 - #### MORE DIVIDER variants #### F_only, RK variable From 716bee3d2614e9cbf55a2ab67785e9055782d570 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 29 Sep 2024 00:57:41 -0700 Subject: [PATCH 13/19] Restore testbench_fp to load from vectors directory --- testbench/testbench_fp.sv | 20 +++----------------- testbench/tests_fp.vh | 1 + 2 files changed, 4 insertions(+), 17 deletions(-) diff --git a/testbench/testbench_fp.sv b/testbench/testbench_fp.sv index 43b8becff..48d4a293d 100644 --- a/testbench/testbench_fp.sv +++ b/testbench/testbench_fp.sv @@ -33,22 +33,7 @@ module testbench_fp; parameter string TEST="none"; // choices are cvtint, cvtfp, cmp, add, sub, mul, div, sqrt, fma; all does not check properly parameter string TEST_SIZE="all"; - `include "parameter-defs.vh" - -`ifdef VERILATOR - import "DPI-C" function string getenvval(input string env_name); - string WALLY_DIR = getenvval("WALLY"); -`elsif VCS - import "DPI-C" function string getenv(input string env_name); - string WALLY_DIR = getenv("WALLY"); -`else - string WALLY_DIR = "$WALLY"; -`endif - - string FP_TESTS = {WALLY_DIR, "/tests/fp/vectors"}; - string pp; - if (P.IEEE754) assign pp = {FP_TESTS, "/ieee/"}; - else assign pp = {FP_TESTS, "/riscv/"}; + `include "parameter-defs.vh" parameter MAXVECTORS = 8388610; @@ -671,6 +656,7 @@ module testbench_fp; // Read the first test initial begin + static string pp = `PATH; string testname; string tt0; tt0 = $sformatf("%s", Tests[TestNum]); @@ -1009,7 +995,7 @@ module testbench_fp; // clear the vectors for(int i=0; i Date: Sun, 29 Sep 2024 01:02:06 -0700 Subject: [PATCH 14/19] Update gitignore --- .gitignore | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/.gitignore b/.gitignore index 4757d62cd..1aa2b562d 100644 --- a/.gitignore +++ b/.gitignore @@ -26,10 +26,8 @@ tests/riscof/config32e.ini tests/riscof/config64.ini tests/riscof/riscof_work/ tests/wally-riscv-arch-test/riscv-test-suite/*/I/*/** -tests/fp/vectors/**/*.tv -tests/fp/vectors/**/sed* -tests/fp/berkeley-float/* -!tests/fp/berkeley-float/Makefile +tests/fp/vectors/*.tv +tests/fp/vectors/sed* tests/fp/combined_IF_vectors/IF_vectors/*.tv tests/custom/*/*/ tests/custom/*/*/*.memfile From 4cacc6b80ccd986366d5d6b21d483c18b88b0ab8 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 29 Sep 2024 01:05:38 -0700 Subject: [PATCH 15/19] More testfloat makefile cleanup --- tests/fp/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/fp/Makefile b/tests/fp/Makefile index c98c37d8b..750492605 100755 --- a/tests/fp/Makefile +++ b/tests/fp/Makefile @@ -26,11 +26,11 @@ clean: $(MAKE) -C ${TESTFLOAT_DIR} clean rm -f ${WALLY}/tests/fp/combined_IF_vectors/IF_vectors/*.tv -${WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/M/src: - @$(error "riscv-arch-tests must be generated first. Run make from $$WALLY") - ${SOFTFLOAT_DIR}/softfloat.a: $(MAKE) SPECIALIZE_TYPE=RISCV -C ${SOFTFLOAT_DIR} ${TESTFLOAT_DIR}/testfloat_gen: ${SOFTFLOAT_DIR}/softfloat.a $(MAKE) -C ${TESTFLOAT_DIR} + +${WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/M/src: + @$(error "riscv-arch-tests must be generated first. Run make from $$WALLY") From d4788c2f6a870b953c2c895252c9628e6ae74725 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 29 Sep 2024 01:30:37 -0700 Subject: [PATCH 16/19] Update softfloat_demo Makefile --- examples/fp/softfloat_demo/Makefile | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/examples/fp/softfloat_demo/Makefile b/examples/fp/softfloat_demo/Makefile index edfebb03a..009a08e17 100644 --- a/examples/fp/softfloat_demo/Makefile +++ b/examples/fp/softfloat_demo/Makefile @@ -1,22 +1,17 @@ -# Makefile +# softfloat_demo Makefile CC = gcc CFLAGS = -O3 LFLAGS = -L. -# Link against the riscv-isa-sim version of SoftFloat rather than -# the regular version to get RISC-V NaN behavior -#IFLAGS = -I$(RISCV)/riscv-isa-sim/softfloat -#LIBS = $(RISCV)/riscv-isa-sim/build/libsoftfloat.a -lm -lquadmath -IFLAGS = -I../../../addins/berkeley-softfloat-3/source/include/ -LIBS = ../../../addins/berkeley-softfloat-3/build/Linux-x86_64-GCC/softfloat.a -lm -lquadmath +IFLAGS = -I$(WALLY)/addins/berkeley-softfloat-3/source/include/ +LIBS = $(WALLY)/addins/berkeley-softfloat-3/build/Linux-x86_64-GCC/softfloat.a -lm -lquadmath SRCS = $(wildcard *.c) - -PROGS = $(patsubst %.c,%,$(SRCS)) +PROGS = $(patsubst %.c,%,$(SRCS)) all: $(PROGS) %: %.c $(CC) $(CFLAGS) -DSOFTFLOAT_FAST_INT64 $(IFLAGS) $(LFLAGS) -o $@ $< $(LIBS) -clean: +clean: rm -f $(PROGS) From e3e205ad79f22553af179153ca7101c441bf532f Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 29 Sep 2024 01:35:49 -0700 Subject: [PATCH 17/19] Update sqrttest Makefile --- examples/fp/sqrttest/Makefile | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/examples/fp/sqrttest/Makefile b/examples/fp/sqrttest/Makefile index 52d22c438..bc07f2939 100644 --- a/examples/fp/sqrttest/Makefile +++ b/examples/fp/sqrttest/Makefile @@ -4,14 +4,9 @@ CC = gcc CFLAGS = -O3 LIBS = -lm LFLAGS = -L. -# Link against the riscv-isa-sim version of SoftFloat rather than -# the regular version to get RISC-V NaN behavior -IFLAGS = -I$(RISCV)/riscv-isa-sim/softfloat -LIBS = $(RISCV)/riscv-isa-sim/build/libsoftfloat.a -#IFLAGS = -I../../../addins/berkeley-softfloat-3/source/include/ -#LIBS = ../../../addins/berkeley-softfloat-3/build/Linux-x86_64-GCC/softfloat.a +IFLAGS = -I$(WALLY)/addins/berkeley-softfloat-3/source/include/ +LIBS = $(WALLY)/addins/berkeley-softfloat-3/build/Linux-x86_64-GCC/softfloat.a -lm -lquadmath SRCS = $(wildcard *.c) - PROGS = $(patsubst %.c,%,$(SRCS)) all: $(PROGS) From 7fea22e48a8cac58fc80df17986d30dc3e7ca621 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 29 Sep 2024 01:39:04 -0700 Subject: [PATCH 18/19] Update fpcalc Makefile --- examples/fp/fpcalc/Makefile | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/examples/fp/fpcalc/Makefile b/examples/fp/fpcalc/Makefile index 2f5751ffa..f3fc4bdcf 100644 --- a/examples/fp/fpcalc/Makefile +++ b/examples/fp/fpcalc/Makefile @@ -1,15 +1,10 @@ -# Makefile +# fpcalc Makefile CC = gcc CFLAGS = -O3 -Wno-format-overflow -# Link against the riscv-isa-sim version of SoftFloat rather than -# the regular version to get RISC-V NaN behavior -IFLAGS = -I$(RISCV)/riscv-isa-sim/softfloat -LIBS = $(RISCV)/riscv-isa-sim/build/libsoftfloat.a -lm -lquadmath -#IFLAGS = -I../../../addins/berkeley-softfloat-3/source/include/ -#LIBS = ../../../addins/berkeley-softfloat-3/build/Linux-x86_64-GCC/softfloat.a -lm -lquadmath +IFLAGS = -I$(WALLY)/addins/berkeley-softfloat-3/source/include/ +LIBS = $(WALLY)/addins/berkeley-softfloat-3/build/Linux-x86_64-GCC/softfloat.a -lm -lquadmath SRCS = $(wildcard *.c) - PROGS = $(patsubst %.c,%,$(SRCS)) all: $(PROGS) @@ -17,5 +12,5 @@ all: $(PROGS) %: %.c $(CC) $(CFLAGS) -DSOFTFLOAT_FAST_INT64 $(IFLAGS) $(LFLAGS) -o $@ $< $(LIBS) -clean: +clean: rm -f $(PROGS) From 5118a1ff9f763053dc63c346600764cd88b3d90e Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 29 Sep 2024 17:03:00 -0700 Subject: [PATCH 19/19] Pin GCC to 13.2.0 to avoid GCC 14 issue with Q extension --- bin/wally-tool-chain-install.sh | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 88600ba26..474cbe9b5 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -208,9 +208,10 @@ fi section_header "Installing/Updating RISC-V GNU Toolchain" STATUS="RISC-V GNU Toolchain" cd "$RISCV" -if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2"; then +# Temporarily pin riscv-gnu-toolchain to use GCC 13.2.0. GCC 14 does not work with the Q extension. +if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2" "b488ddb"; then cd riscv-gnu-toolchain - git reset --hard && git clean -f && git checkout master && git pull + git reset --hard && git clean -f && git checkout b488ddb #&& git pull ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" make -j "${NUM_THREADS}" 2>&1 | logger riscv-gnu-toolchain; [ "${PIPESTATUS[0]}" == 0 ] if [ "$clean" ]; then