diff --git a/examples/exercises/11p6/Makefile b/examples/exercises/11p6/Makefile index ffc37df98..ef232df94 100644 --- a/examples/exercises/11p6/Makefile +++ b/examples/exercises/11p6/Makefile @@ -7,7 +7,7 @@ $(TARGET).elf: $(TARGET).S Makefile riscv64-unknown-elf-gcc -g -o $(TARGET) -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany \ -nostartfiles -T../../link/link.ld $(TARGET).S -o $(TARGET).elf -# simulate in lockstep with ImperasDV +# simulate in Spike sim: $(TARGET).elf.objdump wsim rv32gc $(TARGET).elf --lockstepverbose diff --git a/examples/exercises/8p3/Makefile b/examples/exercises/8p3/Makefile index 6764fac1b..0a41b30ee 100644 --- a/examples/exercises/8p3/Makefile +++ b/examples/exercises/8p3/Makefile @@ -7,7 +7,7 @@ $(TARGET).elf: $(TARGET).S Makefile riscv64-unknown-elf-gcc -g -o $(TARGET) -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany \ -nostartfiles -T../../link/link.ld $(TARGET).S -o $(TARGET).elf -# simulate in lockstep with ImperasDV +# simulate in Spike sim: $(TARGET).elf.objdump wsim rv32gc $(TARGET).elf --lockstepverbose diff --git a/examples/exercises/8p4/Makefile b/examples/exercises/8p4/Makefile index b4cc1c41e..df1e64ac2 100644 --- a/examples/exercises/8p4/Makefile +++ b/examples/exercises/8p4/Makefile @@ -7,7 +7,7 @@ $(TARGET).elf: $(TARGET).S Makefile riscv64-unknown-elf-gcc -g -o $(TARGET) -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany \ -nostartfiles -T../../link/link.ld $(TARGET).S -o $(TARGET).elf -# simulate in lockstep with ImperasDV +# simulate in Spike sim: $(TARGET).elf.objdump wsim rv32gc $(TARGET).elf --lockstepverbose diff --git a/examples/exercises/8p5/Makefile b/examples/exercises/8p5/Makefile index f28fc2c57..432812826 100644 --- a/examples/exercises/8p5/Makefile +++ b/examples/exercises/8p5/Makefile @@ -7,7 +7,7 @@ $(TARGET).elf: $(TARGET).S Makefile riscv64-unknown-elf-gcc -g -o $(TARGET) -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany \ -nostartfiles -T../../link/link.ld $(TARGET).S -o $(TARGET).elf -# simulate in lockstep with ImperasDV +# simulate in Spike sim: $(TARGET).elf.objdump wsim rv32gc $(TARGET).elf --lockstepverbose diff --git a/examples/exercises/8p7/Makefile b/examples/exercises/8p7/Makefile index 38f3d4705..8fb8eaee1 100644 --- a/examples/exercises/8p7/Makefile +++ b/examples/exercises/8p7/Makefile @@ -7,7 +7,7 @@ $(TARGET).elf: $(TARGET).S Makefile riscv64-unknown-elf-gcc -g -o $(TARGET) -march=rv32im_zicsr -mabi=ilp32 -mcmodel=medany \ -nostartfiles -T../../link/link.ld $(TARGET).S -o $(TARGET).elf -# simulate in lockstep with ImperasDV +# simulate with Spike sim: $(TARGET).elf.objdump spike --isa=rv32i_zicsr -d $(TARGET).elf diff --git a/examples/exercises/8p8/Makefile b/examples/exercises/8p8/Makefile index d86276a04..731182993 100644 --- a/examples/exercises/8p8/Makefile +++ b/examples/exercises/8p8/Makefile @@ -7,7 +7,7 @@ $(TARGET).elf: $(TARGET).S Makefile riscv64-unknown-elf-gcc -g -o $(TARGET) -march=rv32im_zicsr -mabi=ilp32 -mcmodel=medany \ -nostartfiles -T../../link/link.ld $(TARGET).S -o $(TARGET).elf -# simulate in lockstep with ImperasDV +# simulate in Spike sim: $(TARGET).elf.objdump spike --isa=rv32i_zicsr -d $(TARGET).elf diff --git a/examples/exercises/8p9/Makefile b/examples/exercises/8p9/Makefile index eaffe9595..6a4d18c85 100644 --- a/examples/exercises/8p9/Makefile +++ b/examples/exercises/8p9/Makefile @@ -7,7 +7,7 @@ $(TARGET).elf: $(TARGET).S Makefile riscv64-unknown-elf-gcc -g -o $(TARGET) -march=rv32im_zicsr -mabi=ilp32 -mcmodel=medany \ -nostartfiles -T../../link/link.ld $(TARGET).S -o $(TARGET).elf -# simulate in lockstep with ImperasDV +# simulate in Spike sim: $(TARGET).elf.objdump wsim rv32gc 8p9.elf --lockstepverbose > log diff --git a/src/mmu/pmpadrdec.sv b/src/mmu/pmpadrdec.sv index 52f08aeab..1b2ee4c98 100644 --- a/src/mmu/pmpadrdec.sv +++ b/src/mmu/pmpadrdec.sv @@ -49,17 +49,13 @@ module pmpadrdec import cvw::*; #(parameter cvw_t P) ( logic TORMatch, NAMatch; logic PAltPMPAdr; - logic [P.PA_BITS-1:0] PMPAdrFull; logic [1:0] AdrMode; assign AdrMode = PMPCfg[4:3]; - // Bottom two bits of PMPAdr are 00 - assign PMPAdrFull = {PMPAdr, 2'b00}; - // Top-of-range (TOR) // Append two implicit trailing 0's to PMPAdr value - assign PAltPMPAdr = {1'b0, PhysicalAddress} < {1'b0, PMPAdrFull}; // unsigned comparison + assign PAltPMPAdr = {1'b0, PhysicalAddress} < {1'b0, PMPAdr, 2'b00}; // unsigned comparison assign PAgePMPAdrOut = ~PAltPMPAdr; assign TORMatch = PAgePMPAdrIn & PAltPMPAdr; // exclusion-tag: PAgePMPAdrIn diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index 72660846a..9a86974e5 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -224,7 +224,7 @@ module csrm import cvw::*; #(parameter cvw_t P) ( always_comb begin logic [P.XLEN-1:0] pmpaddr; pmpaddr = {{(P.XLEN-(P.PA_BITS-2)){1'b0}}, PMPADDR_ARRAY_PREGRAIN_REGW[i]}; // raw value in PMP registers - if (PMPCFG_ARRAY_REGW[i][4]) PMPADDR_ARRAY_REGW[i] = {pmpaddr[P.PA_BITS-3:Gm1], {Gm1 {1'b1}}}; // in NAPOT, bottom G-1 bits read as all 1s + if (PMPCFG_ARRAY_REGW[i][4]) PMPADDR_ARRAY_REGW[i] = {pmpaddr[P.PA_BITS-3:Gm1], {Gm1 {1'b1}}}; // in NAPOT/NA4, bottom G-1 bits read as all 1s (but no bits affected for NA4) else PMPADDR_ARRAY_REGW[i] = {pmpaddr[P.PA_BITS-3:P.PMP_G], {P.PMP_G{1'b0}}}; // in TOR/OFF, bottom G bits read as 0s end diff --git a/src/uncore/trickbox_apb.sv b/src/uncore/trickbox_apb.sv index 52b97354e..f92b83c46 100644 --- a/src/uncore/trickbox_apb.sv +++ b/src/uncore/trickbox_apb.sv @@ -28,23 +28,23 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module trickbox_apb import cvw::*; #(parameter cvw_t P, NUM_HARTS = 1) ( +module trickbox_apb import cvw::*; #(parameter XLEN = 64, NUM_HARTS = 1) ( input logic PCLK, PRESETn, input logic PSEL, input logic [15:0] PADDR, - input logic [P.XLEN-1:0] PWDATA, - input logic [P.XLEN/8-1:0] PSTRB, + input logic [XLEN-1:0] PWDATA, + input logic [XLEN/8-1:0] PSTRB, input logic PWRITE, input logic PENABLE, - output logic [P.XLEN-1:0] PRDATA, + output logic [XLEN-1:0] PRDATA, output logic PREADY, input logic [63:0] MTIME_IN, input logic [NUM_HARTS-1:0] MTIP_IN, MSIP_IN, SSIP_IN, MEIP_IN, SEIP_IN, - input var logic [P.XLEN-1:0] HGEIP_IN[NUM_HARTS-1:0], + input var logic [XLEN-1:0] HGEIP_IN[NUM_HARTS-1:0], output logic [63:0] MTIME_OUT, output logic [NUM_HARTS-1:0] MTIP_OUT, MSIP_OUT, SSIP_OUT, MEIP_OUT, SEIP_OUT, - output var logic [P.XLEN-1:0] HGEIP_OUT[NUM_HARTS-1:0], - output logic [P.XLEN-1:0] TOHOST_OUT + output var logic [XLEN-1:0] HGEIP_OUT[NUM_HARTS-1:0], + output logic [XLEN-1:0] TOHOST_OUT ); // register map @@ -56,8 +56,8 @@ module trickbox_apb import cvw::*; #(parameter cvw_t P, NUM_HARTS = 1) ( logic [7:0] TRICKEN; logic [63:0] MTIME; logic [NUM_HARTS-1:0] MTIP, MSIP, SSIP, MEIP, SEIP; - logic [P.XLEN-1:0] TOHOST; - logic [P.XLEN-1:0] HGEIP[NUM_HARTS-1:0]; + logic [XLEN-1:0] TOHOST; + logic [XLEN-1:0] HGEIP[NUM_HARTS-1:0]; logic [15:0] entry; logic [9:0] hart; // which hart is being accessed logic memwrite; @@ -82,16 +82,16 @@ module trickbox_apb import cvw::*; #(parameter cvw_t P, NUM_HARTS = 1) ( 10'b0000000001: RD <= '0; // Reading COM1 has no effect; busy bit not yet implemented. Later add busy bit 10'b0000000010: RD <= {56'b0, TRICKEN}; 10'b1111111111: RD <= MTIME; - default: RD = '0; + default: RD <= '0; endcase - 3'b110: RD = HGEIP[hart]; - default: RD = '0; + 3'b110: RD <= HGEIP[hart]; + default: RD <= '0; endcase end // word aligned reads - if (P.XLEN == 64) assign PRDATA = RD; - else assign PRDATA = RD[PADDR[2]*32 +: 32]; // 32-bit register access to upper or lower half + if (XLEN == 64) assign PRDATA = RD; + else assign PRDATA = RD[PADDR[2]*32 +: 32]; // 32-bit register access to upper or lower half // write circuitry always_ff @(posedge PCLK) @@ -123,8 +123,8 @@ module trickbox_apb import cvw::*; #(parameter cvw_t P, NUM_HARTS = 1) ( HGEIP[i] <= 0; end else if (memwrite & (hart == i)) begin if (PADDR[15:13] == 3'b010) begin - if (P.XLEN == 64) MTIMECMP[hart] <= PWDATA; // 64-bit write - else MTIMECMP[hart][PADDR[2]*32 +: 32] <= PWDATA; // 32-bit write + if (XLEN == 64) MTIMECMP[hart] <= PWDATA; // 64-bit write + else MTIMECMP[hart][PADDR[2]*32 +: 32] <= PWDATA; // 32-bit write end else if (PADDR[15:13] == 3'b110) begin HGEIP[hart] <= PWDATA; end @@ -134,11 +134,10 @@ module trickbox_apb import cvw::*; #(parameter cvw_t P, NUM_HARTS = 1) ( always_ff @(posedge PCLK) if (~PRESETn) begin MTIME <= '0; - // MTIMECMP is not reset end else if (memwrite & (PADDR[15:13] == 3'b101 && hart == 10'b1111111111)) begin - if (P.XLEN == 64) MTIME <= PWDATA; // 64-bit write - else MTIME <= MTIME[PADDR[2]*32 +: 32]; // 32-bit write - end else MTIME <= MTIME + 1; + if (XLEN == 64) MTIME <= PWDATA; // 64-bit write + else MTIME <= MTIME[PADDR[2]*32 +: 32]; // 32-bit write + end else MTIME <= MTIME + 1; // timer interrupt when MTIME >= MTIMECMP (unsigned) for (i=0;i