From ca96ed48ae03c8dd403ee8c91deb6922911da424 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 27 May 2025 03:55:28 -0700 Subject: [PATCH] cleanup --- testbench/common/riscvassertions.sv | 1 - 1 file changed, 1 deletion(-) diff --git a/testbench/common/riscvassertions.sv b/testbench/common/riscvassertions.sv index 78918e0d9..0d90a6de7 100644 --- a/testbench/common/riscvassertions.sv +++ b/testbench/common/riscvassertions.sv @@ -21,7 +21,6 @@ module riscvassertions import cvw::*; #(parameter cvw_t P); initial begin - //$display("PMPG = %d LLEN = %d !ZCA = %b PMPENTRIES = %d !ICS = %b", P.PMP_G, P.ICACHE_LINELENINBITS, !P.ZCA_SUPPORTED, P.PMP_ENTRIES, !P.ICACHE_SUPPORTED); assert (P.PMP_ENTRIES == 0 | P.PMP_ENTRIES==16 | P.PMP_ENTRIES==64) else $fatal(1, "Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64"); assert (P.PMP_G > 0 | P.XLEN == 32 | P.PMP_ENTRIES == 0) else $fatal(1, "RV64 requires PMP_G at least 1 to avoid checking for 8-byte accesses to 4-byte region"); assert ((P.PMP_G >= $clog2(P.DCACHE_LINELENINBITS/8)-2) | !P.ZICCLSM_SUPPORTED | P.PMP_ENTRIES == 0) else $fatal(1, "Systems that support misaligned data with PMP must have grain size of at least one cache line so accesses that span grains will also cause spills");