diff --git a/.gitignore b/.gitignore index bd3235578..1aa2b562d 100644 --- a/.gitignore +++ b/.gitignore @@ -26,9 +26,8 @@ tests/riscof/config32e.ini tests/riscof/config64.ini tests/riscof/riscof_work/ tests/wally-riscv-arch-test/riscv-test-suite/*/I/*/** -tests/fp/vectors/**/*.tv -tests/fp/vectors/**/sed* -tests/fp/testfloat/* +tests/fp/vectors/*.tv +tests/fp/vectors/sed* tests/fp/combined_IF_vectors/IF_vectors/*.tv tests/custom/*/*/ tests/custom/*/*/*.memfile diff --git a/bin/regression-wally b/bin/regression-wally index d3cbd0b41..c6c8ab523 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -438,13 +438,12 @@ if (args.testfloat): # for testfloat alone, just run testfloat tests if (args.testfloat or args.nightly): # for nightly, run testfloat along with others testfloatsim = "questa" # change to Verilator when Issue #707 about testfloat not running Verilator is resolved testfloatconfigs = ["fdqh_rv64gc", "fdq_rv64gc", "fdh_rv64gc", "fd_rv64gc", "fh_rv64gc", "f_rv64gc", "fdqh_rv32gc", "f_rv32gc"] - testfloatconfigs.append("fdqh_ieee_rv64gc") # run IEEE tests for single config for config in testfloatconfigs: tests = ["div", "sqrt", "add", "sub", "mul", "cvtint", "cvtfp", "fma", "cmp"] if ("f_" in config): tests.remove("cvtfp") for test in tests: - sim_log = WALLY + "/sim/" + testfloatsim + "/logs/"+config+"_"+test+".log" + sim_log = WALLY + "/sim/" + testfloatsim + "/logs/"+config+"_"+test+".log" tc = TestCase( name=test, variant=config, diff --git a/config/derivlist.txt b/config/derivlist.txt index 91b062252..7e6cd6909 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -880,11 +880,6 @@ deriv fdqh_rv64gc rv64gc Q_SUPPORTED 1 ZFH_SUPPORTED 1 -# IEEE compatible FPU - -deriv fdqh_ieee_rv64gc fdqh_rv64gc -IEEE754 1 - #### MORE DIVIDER variants #### F_only, RK variable diff --git a/examples/fp/fpcalc/Makefile b/examples/fp/fpcalc/Makefile index 2f5751ffa..f3fc4bdcf 100644 --- a/examples/fp/fpcalc/Makefile +++ b/examples/fp/fpcalc/Makefile @@ -1,15 +1,10 @@ -# Makefile +# fpcalc Makefile CC = gcc CFLAGS = -O3 -Wno-format-overflow -# Link against the riscv-isa-sim version of SoftFloat rather than -# the regular version to get RISC-V NaN behavior -IFLAGS = -I$(RISCV)/riscv-isa-sim/softfloat -LIBS = $(RISCV)/riscv-isa-sim/build/libsoftfloat.a -lm -lquadmath -#IFLAGS = -I../../../addins/berkeley-softfloat-3/source/include/ -#LIBS = ../../../addins/berkeley-softfloat-3/build/Linux-x86_64-GCC/softfloat.a -lm -lquadmath +IFLAGS = -I$(WALLY)/addins/berkeley-softfloat-3/source/include/ +LIBS = $(WALLY)/addins/berkeley-softfloat-3/build/Linux-x86_64-GCC/softfloat.a -lm -lquadmath SRCS = $(wildcard *.c) - PROGS = $(patsubst %.c,%,$(SRCS)) all: $(PROGS) @@ -17,5 +12,5 @@ all: $(PROGS) %: %.c $(CC) $(CFLAGS) -DSOFTFLOAT_FAST_INT64 $(IFLAGS) $(LFLAGS) -o $@ $< $(LIBS) -clean: +clean: rm -f $(PROGS) diff --git a/examples/fp/softfloat_demo/Makefile b/examples/fp/softfloat_demo/Makefile index edfebb03a..009a08e17 100644 --- a/examples/fp/softfloat_demo/Makefile +++ b/examples/fp/softfloat_demo/Makefile @@ -1,22 +1,17 @@ -# Makefile +# softfloat_demo Makefile CC = gcc CFLAGS = -O3 LFLAGS = -L. -# Link against the riscv-isa-sim version of SoftFloat rather than -# the regular version to get RISC-V NaN behavior -#IFLAGS = -I$(RISCV)/riscv-isa-sim/softfloat -#LIBS = $(RISCV)/riscv-isa-sim/build/libsoftfloat.a -lm -lquadmath -IFLAGS = -I../../../addins/berkeley-softfloat-3/source/include/ -LIBS = ../../../addins/berkeley-softfloat-3/build/Linux-x86_64-GCC/softfloat.a -lm -lquadmath +IFLAGS = -I$(WALLY)/addins/berkeley-softfloat-3/source/include/ +LIBS = $(WALLY)/addins/berkeley-softfloat-3/build/Linux-x86_64-GCC/softfloat.a -lm -lquadmath SRCS = $(wildcard *.c) - -PROGS = $(patsubst %.c,%,$(SRCS)) +PROGS = $(patsubst %.c,%,$(SRCS)) all: $(PROGS) %: %.c $(CC) $(CFLAGS) -DSOFTFLOAT_FAST_INT64 $(IFLAGS) $(LFLAGS) -o $@ $< $(LIBS) -clean: +clean: rm -f $(PROGS) diff --git a/examples/fp/sqrttest/Makefile b/examples/fp/sqrttest/Makefile index 52d22c438..bc07f2939 100644 --- a/examples/fp/sqrttest/Makefile +++ b/examples/fp/sqrttest/Makefile @@ -4,14 +4,9 @@ CC = gcc CFLAGS = -O3 LIBS = -lm LFLAGS = -L. -# Link against the riscv-isa-sim version of SoftFloat rather than -# the regular version to get RISC-V NaN behavior -IFLAGS = -I$(RISCV)/riscv-isa-sim/softfloat -LIBS = $(RISCV)/riscv-isa-sim/build/libsoftfloat.a -#IFLAGS = -I../../../addins/berkeley-softfloat-3/source/include/ -#LIBS = ../../../addins/berkeley-softfloat-3/build/Linux-x86_64-GCC/softfloat.a +IFLAGS = -I$(WALLY)/addins/berkeley-softfloat-3/source/include/ +LIBS = $(WALLY)/addins/berkeley-softfloat-3/build/Linux-x86_64-GCC/softfloat.a -lm -lquadmath SRCS = $(wildcard *.c) - PROGS = $(patsubst %.c,%,$(SRCS)) all: $(PROGS) diff --git a/testbench/testbench_fp.sv b/testbench/testbench_fp.sv index 43b8becff..48d4a293d 100644 --- a/testbench/testbench_fp.sv +++ b/testbench/testbench_fp.sv @@ -33,22 +33,7 @@ module testbench_fp; parameter string TEST="none"; // choices are cvtint, cvtfp, cmp, add, sub, mul, div, sqrt, fma; all does not check properly parameter string TEST_SIZE="all"; - `include "parameter-defs.vh" - -`ifdef VERILATOR - import "DPI-C" function string getenvval(input string env_name); - string WALLY_DIR = getenvval("WALLY"); -`elsif VCS - import "DPI-C" function string getenv(input string env_name); - string WALLY_DIR = getenv("WALLY"); -`else - string WALLY_DIR = "$WALLY"; -`endif - - string FP_TESTS = {WALLY_DIR, "/tests/fp/vectors"}; - string pp; - if (P.IEEE754) assign pp = {FP_TESTS, "/ieee/"}; - else assign pp = {FP_TESTS, "/riscv/"}; + `include "parameter-defs.vh" parameter MAXVECTORS = 8388610; @@ -671,6 +656,7 @@ module testbench_fp; // Read the first test initial begin + static string pp = `PATH; string testname; string tt0; tt0 = $sformatf("%s", Tests[TestNum]); @@ -1009,7 +995,7 @@ module testbench_fp; // clear the vectors for(int i=0; i $@ + @sed -i 's/ /_/g' $@ + +# Generate TestFloat first if necessary +${TESTFLOAT_GEN}: + $(MAKE) -C ${WALLY}/tests/fp testfloat clean: - $(MAKE) -C ieee clean - $(MAKE) -C riscv clean + rm -f *.tv + rm -f sed* diff --git a/tests/fp/vectors/ieee/Makefile b/tests/fp/vectors/ieee/Makefile deleted file mode 100755 index 1a37321d3..000000000 --- a/tests/fp/vectors/ieee/Makefile +++ /dev/null @@ -1,78 +0,0 @@ -# Jordan Carlin, jcarlin@hmc.edu, September 20 2024 -# Makefile to generate IEEE floating point testvectors for CORE-V-Wally -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 - -.DELETE_ON_ERROR: -.SECONDEXPANSION: -.ONESHELL: -# MAKEFLAGS += --no-print-directory - -SHELL := /bin/bash - -VECTOR_TYPE := ieee -TESTFLOAT_DIR := ${WALLY}/tests/fp/testfloat -TESTFLOAT_GEN := ${TESTFLOAT_DIR}/${VECTOR_TYPE}/testfloat_gen - -# List of testvectors to generate. Each rounding mode will be generated for each test. -cvtint := ui32_to_f16 ui32_to_f32 ui32_to_f64 ui32_to_f128 \ - ui64_to_f16 ui64_to_f32 ui64_to_f64 ui64_to_f128 \ - i32_to_f16 i32_to_f32 i32_to_f64 i32_to_f128 \ - i64_to_f16 i64_to_f32 i64_to_f64 i64_to_f128 \ - f16_to_ui32 f32_to_ui32 f64_to_ui32 f128_to_ui32 \ - f16_to_ui64 f32_to_ui64 f64_to_ui64 f128_to_ui64 -cvtfp := f16_to_i32 f32_to_i32 f64_to_i32 f128_to_i32 \ - f16_to_i64 f32_to_i64 f64_to_i64 f128_to_i64 \ - f16_to_f32 f16_to_f64 f16_to_f128 \ - f32_to_f16 f32_to_f64 f32_to_f128 \ - f64_to_f16 f64_to_f32 f64_to_f128 \ - f128_to_f16 f128_to_f32 f128_to_f64 -add := f16_add f32_add f64_add f128_add -sub := f16_sub f32_sub f64_sub f128_sub -mul := f16_mul f32_mul f64_mul f128_mul -div := f16_div f32_div f64_div f128_div -sqrt := f16_sqrt f32_sqrt f64_sqrt f128_sqrt -eq := f16_eq f32_eq f64_eq f128_eq -le := f16_le f32_le f64_le f128_le -lt := f16_lt f32_lt f64_lt f128_lt -mulAdd := f16_mulAdd f32_mulAdd f64_mulAdd f128_mulAdd - -tests := $(cvtfp) $(cvtint) $(add) $(sub) $(mul) $(div) $(sqrt) $(eq) $(le) $(lt) $(mulAdd) - -# Set rounding modes and extensions -rne: ROUND_MODE := rnear_even -rne: ROUND_EXT := rne -rz: ROUND_MODE := rminMag -rz: ROUND_EXT := rz -ru: ROUND_MODE := rmax -ru: ROUND_EXT := ru -rd: ROUND_MODE := rmin -rd: ROUND_EXT := rd -rnm: ROUND_MODE := rnear_maxMag -rnm: ROUND_EXT := rnm - -.PHONY: all rne rz ru rd rnm clean - -all: rne rz ru rd rnm - -# Generate test vectors for each rounding mode -rne: $(addsuffix _rne.tv, $(tests)) -rz: $(addsuffix _rz.tv, $(tests)) -ru: $(addsuffix _ru.tv, $(tests)) -rd: $(addsuffix _rd.tv, $(tests)) -rnm: $(addsuffix _rnm.tv, $(tests)) - -# Rule to generate individual test vectors -%.tv: ${TESTFLOAT_GEN} - @echo "Creating $(VECTOR_TYPE) $@ vectors" - @if [[ "$*" =~ "to" ]] || [[ "$*" =~ "sqrt" ]] ; then level=2 ; else level=1 ; fi - @if [[ "$*" =~ "to_i" ]] || [[ "$*" =~ "to_u" ]] ; then exact="-exact" ; else exact="" ; fi - ${TESTFLOAT_GEN} -tininessafter -level $$level $$exact -$(ROUND_MODE) $(patsubst %_$(ROUND_EXT).tv, %, $@) > $@ - @sed -i 's/ /_/g' $@ - -# Appropriate testfloat_gen must exist -${TESTFLOAT_GEN}: - $(MAKE) -C ${TESTFLOAT_DIR} ${VECTOR_TYPE} - -clean: - rm -f *.tv - rm -f sed* diff --git a/tests/fp/vectors/riscv/Makefile b/tests/fp/vectors/riscv/Makefile deleted file mode 100755 index 91615a349..000000000 --- a/tests/fp/vectors/riscv/Makefile +++ /dev/null @@ -1,78 +0,0 @@ -# Jordan Carlin, jcarlin@hmc.edu, September 20 2024 -# Makefile to generate RISCV floating point testvectors for CORE-V-Wally -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 - -.DELETE_ON_ERROR: -.SECONDEXPANSION: -.ONESHELL: -# MAKEFLAGS += --no-print-directory - -SHELL := /bin/bash - -VECTOR_TYPE := riscv -TESTFLOAT_DIR := ${WALLY}/tests/fp/testfloat -TESTFLOAT_GEN := ${TESTFLOAT_DIR}/${VECTOR_TYPE}/testfloat_gen - -# List of testvectors to generate. Each rounding mode will be generated for each test. -cvtint := ui32_to_f16 ui32_to_f32 ui32_to_f64 ui32_to_f128 \ - ui64_to_f16 ui64_to_f32 ui64_to_f64 ui64_to_f128 \ - i32_to_f16 i32_to_f32 i32_to_f64 i32_to_f128 \ - i64_to_f16 i64_to_f32 i64_to_f64 i64_to_f128 \ - f16_to_ui32 f32_to_ui32 f64_to_ui32 f128_to_ui32 \ - f16_to_ui64 f32_to_ui64 f64_to_ui64 f128_to_ui64 -cvtfp := f16_to_i32 f32_to_i32 f64_to_i32 f128_to_i32 \ - f16_to_i64 f32_to_i64 f64_to_i64 f128_to_i64 \ - f16_to_f32 f16_to_f64 f16_to_f128 \ - f32_to_f16 f32_to_f64 f32_to_f128 \ - f64_to_f16 f64_to_f32 f64_to_f128 \ - f128_to_f16 f128_to_f32 f128_to_f64 -add := f16_add f32_add f64_add f128_add -sub := f16_sub f32_sub f64_sub f128_sub -mul := f16_mul f32_mul f64_mul f128_mul -div := f16_div f32_div f64_div f128_div -sqrt := f16_sqrt f32_sqrt f64_sqrt f128_sqrt -eq := f16_eq f32_eq f64_eq f128_eq -le := f16_le f32_le f64_le f128_le -lt := f16_lt f32_lt f64_lt f128_lt -mulAdd := f16_mulAdd f32_mulAdd f64_mulAdd f128_mulAdd - -tests := $(cvtfp) $(cvtint) $(add) $(sub) $(mul) $(div) $(sqrt) $(eq) $(le) $(lt) $(mulAdd) - -# Set rounding modes and extensions -rne: ROUND_MODE := rnear_even -rne: ROUND_EXT := rne -rz: ROUND_MODE := rminMag -rz: ROUND_EXT := rz -ru: ROUND_MODE := rmax -ru: ROUND_EXT := ru -rd: ROUND_MODE := rmin -rd: ROUND_EXT := rd -rnm: ROUND_MODE := rnear_maxMag -rnm: ROUND_EXT := rnm - -.PHONY: all rne rz ru rd rnm clean - -all: rne rz ru rd rnm - -# Generate test vectors for each rounding mode -rne: $(addsuffix _rne.tv, $(tests)) -rz: $(addsuffix _rz.tv, $(tests)) -ru: $(addsuffix _ru.tv, $(tests)) -rd: $(addsuffix _rd.tv, $(tests)) -rnm: $(addsuffix _rnm.tv, $(tests)) - -# Rule to generate individual test vectors -%.tv: ${TESTFLOAT_GEN} - @echo "Creating $(VECTOR_TYPE) $@ vectors" - @if [[ "$*" =~ "to" ]] || [[ "$*" =~ "sqrt" ]] ; then level=2 ; else level=1 ; fi - @if [[ "$*" =~ "to_i" ]] || [[ "$*" =~ "to_u" ]] ; then exact="-exact" ; else exact="" ; fi - ${TESTFLOAT_GEN} -tininessafter -level $$level $$exact -$(ROUND_MODE) $(patsubst %_$(ROUND_EXT).tv, %, $@) > $@ - @sed -i 's/ /_/g' $@ - -# Appropriate testfloat_gen must exist -${TESTFLOAT_GEN}: - $(MAKE) -C ${TESTFLOAT_DIR} ${VECTOR_TYPE} - -clean: - rm -f *.tv - rm -f sed*