diff --git a/benchmarks/embench/Makefile b/benchmarks/embench/Makefile index 538fb64f9..3dba4daaa 100644 --- a/benchmarks/embench/Makefile +++ b/benchmarks/embench/Makefile @@ -16,10 +16,18 @@ buildsize: build_speedopt_size build_sizeopt_size # uses the build_all.py python file to build the tests in addins/embench-iot/bd_speed/ optimized for speed and size build_speedopt_speed: $(embench_dir)/build_all.py --builddir=bd_speedopt_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S" --cflags="-O2 -nostartfiles" + # remove files not used in embench1.0 When changing to 2.0, restore these files + #rm -rf $(embench_dir)/bd_speedopt_speed/src/md5sum + #rm -rf $(embench_dir)/bd_speedopt_speed/src/tarfind + #rm -rf $(embench_dir)/bd_speedopt_speed/src/primecount find $(embench_dir)/bd_speedopt_speed/ -type f ! -name "*.*" | while read f; do cp "$$f" "$$f.elf"; done build_sizeopt_speed: $(embench_dir)/build_all.py --builddir=bd_sizeopt_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S" --cflags="-Os -nostartfiles" + # remove files not used in embench1.0 When changing to 2.0, restore these files + #rm -rf $(embench_dir)/bd_sizeopt_speed/src/md5sum + #rm -rf $(embench_dir)/bd_sizeopt_speed/src/tarfind + #rm -rf $(embench_dir)/bd_sizeopt_speed/src/primecount find $(embench_dir)/bd_sizeopt_speed/ -type f ! -name "*.*" | while read f; do cp "$$f" "$$f.elf"; done # uses the build_all.py python file to build the tests in addins/embench-iot/bd_speed/ optimized for speed and size diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 2314cb81e..838560ed1 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -339,5 +339,6 @@ module controller import cvw::*; #(parameter cvw_t P) ( // the synchronous DTIM cannot read immediately after write // a cache cannot read or write immediately after a write - assign StoreStallD = MemRWE[0] & ((MemRWD[1] | (MemRWD[0] & P.DCACHE_SUPPORTED)) | (|AtomicD)); + // atomic operations are also detected as MemRWD[1] + assign StoreStallD = MemRWE[0] & ((MemRWD[1] | (MemRWD[0] & P.DCACHE_SUPPORTED))); endmodule diff --git a/testbench/common/riscvassertions.sv b/testbench/common/riscvassertions.sv index 24a7e223c..50577c37d 100644 --- a/testbench/common/riscvassertions.sv +++ b/testbench/common/riscvassertions.sv @@ -56,6 +56,8 @@ module riscvassertions import cvw::*; #(parameter cvw_t P); assert (P.IDIV_ON_FPU == 0 || P.F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED"); assert (P.SSTC_SUPPORTED == 0 || (P.S_SUPPORTED)) else $error("SSTC requires S_SUPPORTED"); assert ((P.ZMMUL_SUPPORTED == 0) || (P.M_SUPPORTED ==0)) else $error("At most one of ZMMUL_SUPPORTED and M_SUPPORTED can be enabled"); + assert ((P.ZICNTR_SUPPORTED == 0) || (P.ZICSR_SUPPORTED == 1)) else $error("ZICNTR_SUPPORTED requires ZICSR_SUPPORTED"); + assert ((P.ZIHPM_SUPPORTED == 0) || (P.ZICNTR_SUPPORTED == 1)) else $error("ZIPHM_SUPPORTED requires ZICNTR_SUPPORTED"); end endmodule diff --git a/testbench/tests.vh b/testbench/tests.vh index 54167f73c..f38f28056 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -75,26 +75,26 @@ string tvpaths[] = '{ string embench[] = '{ `EMBENCH, - "bd_speedopt_speed/src/nsichneu/nsichneu", - "bd_speedopt_speed/src/cubic/cubic", // cubic is likely going to removed when embench 2.0 launches "bd_speedopt_speed/src/aha-mont64/aha-mont64", "bd_speedopt_speed/src/crc32/crc32", + "bd_speedopt_speed/src/cubic/cubic", // cubic is likely going to removed when embench 2.0 launches "bd_speedopt_speed/src/edn/edn", "bd_speedopt_speed/src/huffbench/huffbench", "bd_speedopt_speed/src/matmult-int/matmult-int", - // "bd_speedopt_speed/src/md5sum/md5sum", //commenting out tests from embench 2.0. When embench 2.0 launches stabilty, add these tests back + "bd_speedopt_speed/src/md5sum/md5sum", //commenting out tests from embench 2.0. When embench 2.0 launches stabilty, add these tests back "bd_speedopt_speed/src/minver/minver", "bd_speedopt_speed/src/nettle-aes/nettle-aes", "bd_speedopt_speed/src/nettle-sha256/nettle-sha256", + "bd_speedopt_speed/src/nsichneu/nsichneu", "bd_speedopt_speed/src/nbody/nbody", "bd_speedopt_speed/src/picojpeg/picojpeg", - // "bd_speedopt_speed/src/primecount/primecount", + "bd_speedopt_speed/src/primecount/primecount", "bd_speedopt_speed/src/qrduino/qrduino", "bd_speedopt_speed/src/sglib-combined/sglib-combined", "bd_speedopt_speed/src/slre/slre", "bd_speedopt_speed/src/st/st", "bd_speedopt_speed/src/statemate/statemate", - // "bd_speedopt_speed/src/tarfind/tarfind", + "bd_speedopt_speed/src/tarfind/tarfind", "bd_speedopt_speed/src/ud/ud", "bd_speedopt_speed/src/wikisort/wikisort", "bd_sizeopt_speed/src/aha-mont64/aha-mont64", @@ -103,20 +103,20 @@ string tvpaths[] = '{ "bd_sizeopt_speed/src/edn/edn", "bd_sizeopt_speed/src/huffbench/huffbench", "bd_sizeopt_speed/src/matmult-int/matmult-int", - // "bd_sizeopt_speed/src/md5sum/md5sum", + "bd_sizeopt_speed/src/md5sum/md5sum", "bd_sizeopt_speed/src/minver/minver", "bd_sizeopt_speed/src/nbody/nbody", "bd_sizeopt_speed/src/nettle-aes/nettle-aes", "bd_sizeopt_speed/src/nettle-sha256/nettle-sha256", "bd_sizeopt_speed/src/nsichneu/nsichneu", "bd_sizeopt_speed/src/picojpeg/picojpeg", - // "bd_sizeopt_speed/src/primecount/primecount", + "bd_sizeopt_speed/src/primecount/primecount", "bd_sizeopt_speed/src/qrduino/qrduino", "bd_sizeopt_speed/src/sglib-combined/sglib-combined", "bd_sizeopt_speed/src/slre/slre", "bd_sizeopt_speed/src/st/st", "bd_sizeopt_speed/src/statemate/statemate", - // "bd_sizeopt_speed/src/tarfind/tarfind", + "bd_sizeopt_speed/src/tarfind/tarfind", "bd_sizeopt_speed/src/ud/ud", "bd_sizeopt_speed/src/wikisort/wikisort" }; @@ -1466,7 +1466,7 @@ string arch64zbb[] = '{ "rv64i_m/B/src/andn-01.S", "rv64i_m/B/src/orn-01.S", "rv64i_m/B/src/xnor-01.S", - "rv64i_m/B/src/zext.h-01.S", + "rv64i_m/B/src/zext.h_64-01.S", "rv64i_m/B/src/sext.b-01.S", "rv64i_m/B/src/sext.h-01.S", "rv64i_m/B/src/clz-01.S",