diff --git a/pipelined/src/ppa/ppa.sv b/pipelined/src/ppa/ppa.sv
new file mode 100644
index 000000000..3662c9b90
--- /dev/null
+++ b/pipelined/src/ppa/ppa.sv
@@ -0,0 +1,66 @@
+// ppa.sv
+// Teo Ene & David_Harris@hmc.edu 25 Feb 2021
+// Measure PPA of various building blocks
+
+/*
+module top(
+    input  logic       a1,
+    input  logic [7:0] a8, b8,
+    input  logic [15:0] a16, b16,
+    input  logic [31:0] a32, b32,
+    input  logic [63:0] a64, b64,
+    output logic        yinv,
+    output logic [63:0] y1, y2, y3, y4
+);
+
+  // fo4 inverter
+  myinv myinv(a1, yinv);)
+
+    // adders
+  add #(8) add8(a8, b8, yadd8);
+  add #(16) add16(a16, b16, yadd16);
+  add #(32) add32(a32, b32, yadd32);
+  add #(64) add64(a64, b64, yadd64);
+
+  // mux2, mux3, mux4 of 1, 8, 16, 32, 64
+  
+endmodule
+ */
+
+module ppa_inv(input a, output y);
+  assign out = ~in;
+endmodule
+
+module ppa_add #(parameter WIDTH=8) (
+    input logic [7:0] a, b,
+    output logic [7:0] y
+);
+
+   assign out = a + b;
+endmodule
+
+
+/*module inv4(input logic a, output logic y);
+  logic [3:0] b
+  INVX2 i0(a, b[0]);
+  INVX2 i1(a, b[1]);
+  INVX2 i2(a, b[2]);
+  INVX2 i3(a, b[3]);
+  INVX2 i00(b[0], y;
+  INVX2 i01(b[0], y);
+  INVX2 i02(b[0], y);
+  INVX2 i03(b[0], y);
+  INVX2 i10(b[1], y;
+  INVX2 i11(b[1], y);
+  INVX2 i12(b[1], y);
+  INVX2 i13(b[1], y);
+  INVX2 i20(b[2], y;
+  INVX2 i21(b[2], y);
+  INVX2 i22(b[2], y);
+  INVX2 i23(b[2], y);
+  INVX2 i30(b[3], y;
+  INVX2 i31(b[3], y);
+  INVX2 i32(b[3], y);
+  INVX2 i33(b[3], y);
+endmodule
+*/
diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl
index d79009fe1..3feb5f123 100755
--- a/synthDC/scripts/synth.tcl
+++ b/synthDC/scripts/synth.tcl
@@ -21,6 +21,7 @@ set hdl_src "../pipelined/src"
 set cfg "${hdl_src}/../config/${cfgName}/wally-config.vh"
 set saifpower $::env(SAIFPOWER)
 set maxopt $::env(MAXOPT)
+set drive $::env(DRIVE)
 
 eval file copy -force ${cfg} {hdl/}
 eval file copy -force ${cfg} $outputDir
@@ -111,7 +112,11 @@ set all_in_ex_clk [remove_from_collection [all_inputs] [get_ports $my_clk]]
 if {$tech == "sky130"} {
     set_driving_cell  -lib_cell sky130_osu_sc_12T_ms__dff_1 -pin Q $all_in_ex_clk
 } elseif {$tech == "sky90"} {
-    set_driving_cell  -lib_cell scc9gena_dfxbp_1 -pin Q $all_in_ex_clk
+    if ($drive == "INV") {
+	set_driving_cell -lib_cell scc9gena_inv_1 -pin Y $all_in_ex_clk
+    } else {
+	set_driving_cell  -lib_cell scc9gena_dfxbp_1 -pin Q $all_in_ex_clk
+    }
 }
 
 # Set input/output delay
@@ -122,7 +127,11 @@ set_output_delay 0.1 -max -clock $my_clk [all_outputs]
 if {$tech == "sky130"} {
     set_load [expr [load_of sky130_osu_sc_12T_ms_TT_1P8_25C.ccs/sky130_osu_sc_12T_ms__dff_1/D] * 1] [all_outputs]
 } elseif {$tech == "sky90"} {
-    set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_dfxbp_1/D] * 1] [all_outputs]
+    if ($drive == "INV") {
+	set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_inv_4/A] * 1] [all_outputs]
+    } else {
+        set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_dfxbp_1/D] * 1] [all_outputs]
+    }
 }
 
 # Set the wire load model