From d9d5fc0827c50d7cbfa6711ca06a57199d08b088 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 15 Aug 2024 11:14:22 -0700 Subject: [PATCH] Refactor gitignore --- .gitignore | 300 ++++++++++++++++++++--------------------------------- 1 file changed, 112 insertions(+), 188 deletions(-) diff --git a/.gitignore b/.gitignore index 85d753d82..ec5520c64 100644 --- a/.gitignore +++ b/.gitignore @@ -1,78 +1,46 @@ +# General file extensions to ignore +.nfs* +*.objdump* +*.o +*.d +*.a +*.vstf +*.vcd +*.signature.output +*.dtb +*.log +*.map +*.elf* +*.list + +# General directories to ignore +.vscode/ +__pycache__/ **/work* -**/wally_*.log /**/obj_dir* /**/gmon* -.nfs* - -__pycache__/ -.vscode/ - #External repos addins/riscv-arch-test/Makefile.include addins/riscv-tests/target addins/TestFloat-3e/build/Linux-x86_64-GCC/* - -#vsim work files to ignore -transcript -vsim.wlf -wlft* -wlft* -/imperas-riscv-tests/FunctionRadix_32.addr -/imperas-riscv-tests/FunctionRadix_64.addr -/imperas-riscv-tests/FunctionRadix.addr -/imperas-riscv-tests/ProgramMap.txt -/imperas-riscv-tests/logs -*.o -*.d -*.vstf -testsBP/*/*/*.elf* -testsBP/*/OBJ/* -testsBP/*/*.a -tests/wally-riscv-arch-test/riscv-test-suite/*/I/*/* -tests/riscof/riscof_work/ +# Tests tests/riscof/config32.ini tests/riscof/config32e.ini tests/riscof/config64.ini -tests/linux-testgen/linux-testvectors/* -!tests/linux-testgen/linux-testvectors/tvCopier.py -!tests/linux-testgen/linux-testvectors/tvLinker.sh -!tests/linux-testgen/linux-testvectors/tvUnlinker.sh -tests/linux-testgen/buildroot -tests/linux-testgen/buildroot-image-output -tests/linux-testgen/buildroot-config-src/main.config.old -tests/linux-testgen/buildroot-config-src/linux.config.old -tests/linux-testgen/buildroot-config-src/busybox.config.old +tests/riscof/riscof_work/ +tests/wally-riscv-arch-test/riscv-test-suite/*/I/*/** +tests/fp/vectors/*.tv +tests/fp/combined_IF_vectors/IF_vectors/*.tv +tests/custom/*/*/ +tests/custom/*/*/*.memfile +tests/riscvdv +tests/functcov + +# Linux linux/buildroot linux/testvector-generation/boottrace.S -linux/testvector-generation/boottrace_disasm.log -sim/slack-notifier/slack-webhook-url.txt -fpga/generator/IP -fpga/generator/vivado.* -fpga/generator/.Xil/* -fpga/generator/WallyFPGA* -fpga/generator/reports/ -fpga/generator/*.log -fpga/generator/*.jou -*.objdump* -*.signature.output -examples/asm/sumtest/sumtest -examples/asm/example/example -examples/C/sum/sum -examples/C/fir/fir -examples/fp/softfloat_demo/softfloat_demo -examples/fp/softfloat_demo/softfloat_demoDP -examples/fp/softfloat_demo/softfloat_demoQP -examples/fp/softfloat_demo/softfloat_demoSP -examples/fp/fpcalc/fpcalc -examples/fp/sqrttest/sqrttest -examples/C/inline/inline -examples/C/mcmodel/mcmodel -examples/C/sum_mixed/sum_mixed -examples/asm/trap/trap -examples/asm/etc/pause -src/fma/fma16_testgen linux/devicetree/debug/* !linux/devicetree/debug/dump-dts.sh linux/testvector-generation/genCheckpoint.gdb @@ -80,10 +48,30 @@ linux/testvector-generation/silencePipe linux/testvector-generation/silencePipe.control linux/testvector-generation/fixBinMem linux/testvector-generation/qemu-serial -*.dtb + +# FPGA +fpga/generator/IP +fpga/generator/vivado.* +fpga/generator/.Xil/* +fpga/generator/WallyFPGA* +fpga/generator/reports/ +fpga/generator/*.jou +fpga/src/sdc/* +fpga/src/sdc.tar.gz +fpga/src/CopiedFiles_do_not_add_to_repo/* +fpga/generator/sim/imp-funcsim.v +fpga/generator/sim/imp-timesim.sdf +fpga/generator/sim/imp-timesim.v +fpga/generator/sim/syn-funcsim.v +fpga/rvvidaemon/rvvidaemon +fpga/zsbl/OBJ/* +fpga/zsbl/bin/* +fpga/src/boot.mem +fpga/src/data.mem + +# Synthesis synthDC/WORK synthDC/alib-52 -synthDC/*.log synthDC/*.svf synthDC/runs/ synthDC/newRuns @@ -92,128 +80,51 @@ synthDC/ppa/plots synthDC/wallyplots/ synthDC/runArchive synthDC/hdl -sim/power.saif -tests/fp/vectors synthDC/Summary.csv -tests/custom/work -tests/custom/*/*/*.list -tests/custom/*/*/*.elf -tests/custom/*/*/*.map -tests/custom/*/*/*.memfile -tests/custom/crt0/*.a -tests/custom/*/*.elf* -sim/sd_model.log -fpga/src/sdc/* -fpga/src/sdc.tar.gz -fpga/src/CopiedFiles_do_not_add_to_repo/* -fpga/src/boot.mem -fpga/src/data.mem -sim/branch.log -/fpga/generator/sim/imp-funcsim.v -/fpga/generator/sim/imp-timesim.sdf -/fpga/generator/sim/imp-timesim.v -/fpga/generator/sim/syn-funcsim.v -external -sim/results -tests/wally-riscv-arch-test/riscv-test-suite/rv*i_m/I/src/*.S -tests/wally-riscv-arch-test/riscv-test-suite/rv*i_m/I/Makefrag -sim/branch_BP_GSHARE10.log -sim/branch_BP_GSHARE16.log -sim/questa/imperas.log -sim/results-error/ -sim/test1.rep -sim/questa/vsim.log -tests/coverage/*.elf -*.elf.memfile -sim/*Cache.log -sim/branch -tests/fp/combined_IF_vectors/IF_vectors/*.tv -/sim/branch-march14.tar.gz -/sim/gshareforward-no-class -/sim/lint-wally_32 -/sim/lint-wally_32e -/sim/local16.txt -/sim/localhistory_m6k10_results_april24.txt -/sim/log.log -/sim/obj_dir/Vtestbench.cpp -/sim/obj_dir/Vtestbench.h -/sim/obj_dir/Vtestbench.mk -/sim/obj_dir/Vtestbench__ConstPool_0.cpp -/sim/obj_dir/Vtestbench__Syms.cpp -/sim/obj_dir/Vtestbench__Syms.h -/sim/obj_dir/Vtestbench___024root.h -/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__0.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__0__Slow.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__1.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__10.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__11.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__1__Slow.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__2.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__2__Slow.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__3.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__3__Slow.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__4.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__4__Slow.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__5.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__5__Slow.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__6.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__7.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__8.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__9.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hfc24d085__0.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hfc24d085__0__Slow.cpp -/sim/obj_dir/Vtestbench___024root__Slow.cpp -/sim/obj_dir/Vtestbench___024unit.h -/sim/obj_dir/Vtestbench___024unit__DepSet_hf87c9ffd__0__Slow.cpp -/sim/obj_dir/Vtestbench___024unit__Slow.cpp -/sim/obj_dir/Vtestbench__verFiles.dat -/sim/obj_dir/Vtestbench_classes.mk -/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9.h -/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h34d4af8f__0.cpp -/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h34d4af8f__0__Slow.cpp -/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h845a114e__0.cpp -/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h845a114e__0__Slow.cpp -/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h845a114e__1.cpp -/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__Slow.cpp -/sim/obj_dir/Vtestbench_tlbram__Pz1_T20.h -/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__DepSet_h3df7cb71__0.cpp -/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__DepSet_hab70f5b0__0.cpp -/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__DepSet_hab70f5b0__0__Slow.cpp -/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__Slow.cpp -sim/bp-results/*.log -sim/branch*.log -/tests/custom/fpga-test-sdc/bin/fpga-test-sdc + +# Benchmarks benchmarks/embench/wally*.json benchmarks/embench/run* -sim/cfi.log +benchmarks/coremark/coremark_results.csv + +# Simulation +sim/*.svg +sim/power.saif +sim/results +sim/results-error/ +sim/test1.rep +sim/branch +sim/branch-march14.tar.gz +sim/gshareforward-no-class +sim/local16.txt +sim/localhistory_m6k10_results_april24.txt sim/cfi/* sim/branch/* -sim/obj_dir -examples/verilog/fulladder/obj_dir -examples/verilog/fulladder/fulladder.vcd -config/deriv -docs/docker/buildroot-config-src -docs/docker/testvector-generation -sim/questa/cov -sim/questa/fcovrvvi -sim/questa/fcovrvvi_logs -sim/questa/fcovrvvi_ucdb sim/covhtmlreport/ + +# Questa sim/questa/logs sim/questa/wkdir sim/questa/ucdb -sim/questa/fcov +sim/questa/cov +sim/questa/fcov +sim/questa/fcovrvvi +sim/questa/fcovrvvi_logs +sim/questa/fcovrvvi_ucdb sim/questa/fcov_logs sim/questa/fcov_ucdb -sim/verilator/logs -sim/verilator/wkdir +sim/questa/functcov_logs +sim/questa/functcov_ucdbs +sim/questa/functcov +sim/questa/riscv.ucdb +transcript +vsim.wlf +wlft* + +# VCS sim/vcs/logs sim/vcs/wkdir sim/vcs/ucdb -benchmarks/coremark/coremark_results.csv -fpga/zsbl/OBJ/* -fpga/zsbl/bin/* -sim/*.svg sim/vcs/csrc sim/vcs/profileReport* sim/vcs/program.out @@ -222,17 +133,13 @@ sim/vcs/simprofile_dir sim/vcs/ucli.key sim/vcs/verdi_config_file sim/vcs/vcdplus.vpd -sim/*/testbench.vcd -sim/questa/imperas.log -sim/questa/functcov.log -sim/questa/functcov_logs/* -sim/questa/functcov_ucdbs/* -sim/questa/functcov -sim/questa/riscv.ucdb -sim/questa/riscv.ucdb.log -sim/questa/riscv.ucdb.summary.log -sim/questa/riscv.ucdb.testdetails.log -tests/riscvdv +sim/vcs/simprofile* + +# Verilator +sim/verilator/logs +sim/verilator/wkdir + +# Examples examples/verilog/fulladder/csrc/ examples/verilog/fulladder/profileReport.html examples/verilog/fulladder/profileReport.json @@ -242,10 +149,27 @@ examples/verilog/fulladder/simprofile_dir/ examples/verilog/fulladder/simv.daidir/ examples/verilog/fulladder/ucli.key examples/verilog/fulladder/verdi_config_file +examples/fp/softfloat_demo/softfloat_demo +examples/fp/softfloat_demo/softfloat_demoDP +examples/fp/softfloat_demo/softfloat_demoQP +examples/fp/softfloat_demo/softfloat_demoSP +examples/fp/fpcalc/fpcalc +examples/fp/sqrttest/sqrttest examples/crypto/gfmul/gfmul -tests/functcov -tests/functcov/* -tests/functcov/*/* -sim/vcs/simprofile* -sim/verilator/verilator.log -/fpga/rvvidaemon/rvvidaemon +examples/C/fir/fir +examples/C/inline/inline +examples/C/mcmodel/mcmodel_medany +examples/C/mcmodel/mcmodel_medlow +examples/C/sum/sum +examples/C/sum_mixed/sum_mixed +examples/asm/sumtest/sumtest +examples/asm/example/example +examples/asm/trap/trap +examples/asm/etc/pause + +# Other +external +config/deriv +sim/slack-notifier/slack-webhook-url.txt +docs/docker/buildroot-config-src +docs/docker/testvector-generation