From d9e8d16bbe87e5c51a8438259d68715fefdd8ef9 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 15 Jan 2022 00:24:16 +0000
Subject: [PATCH] Renamed LSUStall to LSUStallM

---
 fpga/constraints/debug2.xdc               |  2 +-
 pipelined/regression/fpga-wave.do         |  2 +-
 pipelined/regression/linux-wave.do        |  4 +-
 pipelined/regression/sim-wally-batch      |  2 +-
 pipelined/regression/wave-coremark.do     |  2 +-
 pipelined/regression/wave.do              |  4 +-
 pipelined/src/hazard/hazard.sv            |  4 +-
 pipelined/src/lsu/lsu.sv                  | 53 ++++++-----------------
 pipelined/src/wally/wallypipelinedhart.sv |  6 +--
 9 files changed, 26 insertions(+), 53 deletions(-)

diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc
index 8f4077b80..9916030af 100644
--- a/fpga/constraints/debug2.xdc
+++ b/fpga/constraints/debug2.xdc
@@ -350,7 +350,7 @@ connect_debug_port u_ila_0/probe79 [get_nets [list wallypipelinedsoc/hart/hzu/CS
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe80]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe80]
-connect_debug_port u_ila_0/probe80 [get_nets [list wallypipelinedsoc/hart/hzu/LSUStall ]]
+connect_debug_port u_ila_0/probe80 [get_nets [list wallypipelinedsoc/hart/hzu/LSUStallM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe81]
diff --git a/pipelined/regression/fpga-wave.do b/pipelined/regression/fpga-wave.do
index 43585e873..6fb4effc2 100644
--- a/pipelined/regression/fpga-wave.do
+++ b/pipelined/regression/fpga-wave.do
@@ -38,7 +38,7 @@ add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/ha
 add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/hart/hzu/LoadStallD
 add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/hart/hzu/StoreStallD
 add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/hart/hzu/ICacheStallF
-add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/hart/hzu/LSUStall
+add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/hart/hzu/LSUStallM
 add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/hart/MulDivStallD
 add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/wallypipelinedsoc/hart/hzu/FlushF
 add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/wallypipelinedsoc/hart/FlushD
diff --git a/pipelined/regression/linux-wave.do b/pipelined/regression/linux-wave.do
index 02cd3e475..ce3c6a470 100644
--- a/pipelined/regression/linux-wave.do
+++ b/pipelined/regression/linux-wave.do
@@ -13,7 +13,7 @@ add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/Ret
 add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/hart/hzu/TrapM
 add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
 add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/StoreStallD
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStallM
 add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DivBusyE
 add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/trap/ExceptionM
 add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/trap/InstrMisalignedFaultM
@@ -204,7 +204,7 @@ add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/amo/amoalu/width
 add wave -noupdate -expand -group lsu -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/interlockfsm/InterlockCurrState
 add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/SelHPTW
 add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/InterlockStall
-add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/LSUStall
+add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/LSUStallM
 add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataM
 add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WriteDataM
 add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcache/cachefsm/CurrState
diff --git a/pipelined/regression/sim-wally-batch b/pipelined/regression/sim-wally-batch
index 7db25e6cf..fdaec1d1b 100755
--- a/pipelined/regression/sim-wally-batch
+++ b/pipelined/regression/sim-wally-batch
@@ -1,3 +1,3 @@
 vsim -c <<!
-do wally-pipelined-batch.do rv32gc arch32f
+do wally-pipelined-batch.do rv64gc wally64priv
 !
diff --git a/pipelined/regression/wave-coremark.do b/pipelined/regression/wave-coremark.do
index 4d7740465..7bea0645f 100644
--- a/pipelined/regression/wave-coremark.do
+++ b/pipelined/regression/wave-coremark.do
@@ -38,7 +38,7 @@ add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart
 add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
 add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/StoreStallD
 add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStallM
 add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
 add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
 add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD
diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do
index d9e0104b8..be9074b5e 100644
--- a/pipelined/regression/wave.do
+++ b/pipelined/regression/wave.do
@@ -11,7 +11,7 @@ add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/Ret
 add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/hart/hzu/TrapM
 add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
 add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/StoreStallD
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStallM
 add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MDUStallD
 add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DivBusyE
 add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/trap/InstrMisalignedFaultM
@@ -180,7 +180,7 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
 add wave -noupdate -group lsu -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/interlockfsm/InterlockCurrState
 add wave -noupdate -group lsu /testbench/dut/hart/lsu/SelHPTW
 add wave -noupdate -group lsu /testbench/dut/hart/lsu/InterlockStall
-add wave -noupdate -group lsu /testbench/dut/hart/lsu/LSUStall
+add wave -noupdate -group lsu /testbench/dut/hart/lsu/LSUStallM
 add wave -noupdate -group lsu /testbench/dut/hart/lsu/ReadDataWordMuxM
 add wave -noupdate -group lsu /testbench/dut/hart/lsu/ReadDataM
 add wave -noupdate -group lsu /testbench/dut/hart/lsu/WriteDataM
diff --git a/pipelined/src/hazard/hazard.sv b/pipelined/src/hazard/hazard.sv
index d369bd43b..0fa6706de 100644
--- a/pipelined/src/hazard/hazard.sv
+++ b/pipelined/src/hazard/hazard.sv
@@ -34,7 +34,7 @@ module hazard(
   // Detect hazards
 (* mark_debug = "true" *)	      input logic  BPPredWrongE, CSRWritePendingDEM, RetM, TrapM,
 (* mark_debug = "true" *)	      input logic  LoadStallD, StoreStallD, MDUStallD, CSRRdStallD,
-(* mark_debug = "true" *)	      input logic  LSUStall, IFUStallF,
+(* mark_debug = "true" *)	      input logic  LSUStallM, IFUStallF,
 (* mark_debug = "true" *)              input logic  FPUStallD, FStallD,
 (* mark_debug = "true" *)	      input logic  DivBusyE,FDivBusyE,
 (* mark_debug = "true" *)	      input logic  EcallFaultM, BreakpointFaultM,
@@ -64,7 +64,7 @@ module hazard(
   assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FPUStallD | FStallD) & ~(TrapM | RetM | BPPredWrongE);    // stall in decode if instruction is a load/mul/csr dependent on previous
   assign StallECause = (DivBusyE | FDivBusyE) & ~(TrapM);
   assign StallMCause = 0; 
-  assign StallWCause = LSUStall | IFUStallF;
+  assign StallWCause = LSUStallM | IFUStallF;
 
   assign StallF = StallFCause | StallD;
   assign StallD = StallDCause | StallE;
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index 1a4056f12..2a9025230 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -36,7 +36,7 @@ module lsu
   (
    input logic 				   clk, reset,
    input logic 				   StallM, FlushM, StallW, FlushW,
-   output logic 			   LSUStall,
+   output logic 			   LSUStallM,
    // Memory Stage
 
    // connected to cpu (controls)
@@ -122,14 +122,14 @@ module lsu
   logic 					   BusCommittedM, DCacheCommittedM;
   
 
-  flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
-  assign IEUAdrExtM = {2'b00, IEUAdrM}; // *** probably needs to connect to external bus too, make external bus PADDRBITS
- 
   ////////////////////////////////////////////////////////////////////////////////////////////////
   // HPTW and Interlock FSM (only needed if VM supported)
   // MMU include PMP and is needed if any privileged supported
   ////////////////////////////////////////////////////////////////////////////////////////////////
 
+  flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
+  assign IEUAdrExtM = {2'b00, IEUAdrM}; 
+ 
   if(`MEM_VIRTMEM) begin : MEM_VIRTMEM
     logic 					   AnyCPUReqM;
     logic [`PA_BITS-1:0] 		   HPTWAdr;
@@ -167,37 +167,17 @@ module lsu
     // always block interrupts when using the hardware page table walker.
     assign CPUBusy = StallW & ~SelHPTW;
     
-    // It is not possible to pipeline hptw as the following load will depend on the previous load's
-    // data. Therefore we don't need a pipeline register
-    //flop #(`PA_BITS) HPTWAdrMReg(clk, HPTWAdr, HPTWAdrM);   // delay HPTWAdrM by a cycle
-
     // Specify which type of page fault is occurring
     assign DTLBLoadPageFaultM = DTLBPageFaultM & PreLSURWM[1];
     assign DTLBStorePageFaultM = DTLBPageFaultM & PreLSURWM[0];
   end // if (`MEM_VIRTMEM)
   else begin
-    assign InterlockStall = 1'b0;
-    
-    assign LSUAdrE = PreLSUAdrE;
-    assign SelHPTW = 1'b0;
-    assign IgnoreRequest = 1'b0;
-
-    assign PTE = '0;
-    assign PageType = '0;
-    assign DTLBWriteM = 1'b0;
-    assign ITLBWriteF = 1'b0;	  
-    
-    assign PreLSURWM = MemRWM;
-    assign LSUFunct3M = Funct3M;
-    assign LSUFunct7M = Funct7M;
-    assign LSUAtomicM = AtomicM;
-    assign PreLSUAdrE = IEUAdrE[11:0];
-    assign PreLSUPAdrM = IEUAdrExtM;
+    assign {InterlockStall, SelHPTW, IgnoreRequest, PTE, PageType, DTLBWriteM, ITLBWriteF} = '0;
+    assign {DTLBLoadPageFaultM, DTLBStorePageFaultM} = '0;
     assign CPUBusy = StallW;
-    
-    assign DTLBLoadPageFaultM = 1'b0;
-    assign DTLBStorePageFaultM = 1'b0;
-  end
+    assign LSUAdrE = PreLSUAdrE; assign LSUFunct3M = Funct3M;  assign LSUFunct7M = Funct7M; assign LSUAtomicM = AtomicM;
+    assign PreLSURWM = MemRWM; assign PreLSUAdrE = IEUAdrE[11:0]; assign PreLSUPAdrM = IEUAdrExtM;
+   end
 
 
   // **** look into this confusing signal.
@@ -210,8 +190,6 @@ module lsu
   // to flush the memory operation at that time.
   assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM;
 
-  // Outside Pipeline Logic
-
   // MMU and Misalignment fault logic required if privileged unit exists
   if(`ZICSR_SUPPORTED == 1) begin : dmmu
     logic 					   DataMisalignedM;
@@ -235,8 +213,9 @@ module lsu
       .AtomicAccessM(1'b0), .ExecuteAccessF(1'b0),  ///  atomicaccessm is probably a bug
       .WriteAccessM(PreLSURWM[0]), .ReadAccessM(PreLSURWM[1]),
       .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW
-      ); // *** the pma/pmp instruction access faults don't really matter here. is it possible to parameterize which outputs exist?
+      );
 
+    // *** lsumisaligned lsumisaligned(Funct3M, IEUAdrM, MemRW, LoadMisalignedFaultM, StoreMisalignedFaultM);
     // *** lump into lsumislaigned module
     // Determine if an Unaligned access is taking place
     // hptw guarantees alignment, only check inputs from IEU.
@@ -253,17 +232,11 @@ module lsu
     assign StoreMisalignedFaultM = DataMisalignedM & MemRWM[0];
     
   end else begin
+    assign {DTLBMissM, DTLBPageFaultM, LoadAccessFaultM, StoreAccessFaultM, LoadMisalignedFaultM, StoreMisalignedFaultM} = '0;
     assign LSUPAdrM = PreLSUPAdrM;
-    assign DTLBMissM = 0;
     assign CacheableM = 1;
-    assign DTLBPageFaultM = 0;
-    assign LoadAccessFaultM = 0;
-    assign StoreAccessFaultM = 0;
-    assign LoadMisalignedFaultM = 0;
-    assign StoreMisalignedFaultM = 0;
   end
-  // *** rename these to LSUStallM
-  assign LSUStall = DCacheStall | InterlockStall | BusStall;
+  assign LSUStallM = DCacheStall | InterlockStall | BusStall;
   
   ////////////////////////////////////////////////////////////////////////////////////////////////
   // Hart Memory System
diff --git a/pipelined/src/wally/wallypipelinedhart.sv b/pipelined/src/wally/wallypipelinedhart.sv
index f11f5384d..ddaff6933 100644
--- a/pipelined/src/wally/wallypipelinedhart.sv
+++ b/pipelined/src/wally/wallypipelinedhart.sv
@@ -120,7 +120,7 @@ module wallypipelinedhart (
 
   // IMem stalls
   logic 		    IFUStallF;
-  logic 		    LSUStall;
+  logic 		    LSUStallM;
 
   
 
@@ -278,7 +278,7 @@ module wallypipelinedhart (
 	.StoreAccessFaultM,     // connects to privilege
     
 	.PCF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF,
-	.LSUStall);                     // change to LSUStall
+	.LSUStallM);                     // change to LSUStallM
 
 
    // *** Ross: please make EBU conditional when only supporting internal memories
@@ -303,7 +303,7 @@ module wallypipelinedhart (
    hazard     hzu(
      .BPPredWrongE, .CSRWritePendingDEM, .RetM, .TrapM,
      .LoadStallD, .StoreStallD, .MDUStallD, .CSRRdStallD,
-     .LSUStall, .IFUStallF,
+     .LSUStallM, .IFUStallF,
      .FPUStallD, .FStallD,
 	.DivBusyE, .FDivBusyE,
 	.EcallFaultM, .BreakpointFaultM,