From 23775c6d6755bc29039f4143dca67cebae05cde1 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 1 Mar 2023 11:18:00 -0800 Subject: [PATCH 1/3] Renamed I/D TLBMissOrDAFault to TLBMissOrUpdateDA for consistency with UpdateDA --- src/mmu/hptw.sv | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index f2df8ea92..2fcf469de 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -91,8 +91,8 @@ module hptw ( logic [`PA_BITS-1:0] HPTWReadAdr; logic SelHPTWAdr; logic [`XLEN+1:0] HPTWAdrExt; - logic ITLBMissOrDAFaultF; - logic DTLBMissOrDAFaultM; + logic ITLBMissOrUpdateDAF; + logic DTLBMissOrUpdateDAM; logic LSUAccessFaultM; logic [`PA_BITS-1:0] HPTWAdr; logic [1:0] HPTWRW; @@ -108,14 +108,14 @@ module hptw ( // Extract bits from CSRs and inputs assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]; assign BasePageTablePPN = SATP_REGW[`PPN_BITS-1:0]; - assign TLBMiss = (DTLBMissOrDAFaultM | ITLBMissOrDAFaultF); + assign TLBMiss = (DTLBMissOrUpdateDAM | ITLBMissOrUpdateDAF); // Determine which address to translate mux2 #(`XLEN) vadrmux(PCFSpill, IEUAdrExtM[`XLEN-1:0], DTLBWalk, TranslationVAdr); assign CurrentPPN = PTE[`PPN_BITS+9:10]; // State flops - flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissOrDAFaultM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB) + flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissOrUpdateDAM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB) assign PRegEn = HPTWRW[1] & ~DCacheStallM | UpdatePTE; flopenr #(`XLEN) PTEReg(clk, reset, PRegEn, NextPTE, PTE); // Capture page table entry from data cache @@ -275,8 +275,8 @@ module hptw ( assign SelHPTW = WalkerState != IDLE; assign HPTWStall = (WalkerState != IDLE) | (WalkerState == IDLE & TLBMiss); - assign ITLBMissOrDAFaultF = ITLBMissF | (`SVADU_SUPPORTED & InstrUpdateDAF); - assign DTLBMissOrDAFaultM = DTLBMissM | (`SVADU_SUPPORTED & DataUpdateDAM); + assign ITLBMissOrUpdateDAF = ITLBMissF | (`SVADU_SUPPORTED & InstrUpdateDAF); + assign DTLBMissOrUpdateDAM = DTLBMissM | (`SVADU_SUPPORTED & DataUpdateDAM); // HTPW address/data/control muxing From 316b8b2250de540d9e4342b0db0e2d17f92e7eab Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 2 Mar 2023 20:00:47 -0800 Subject: [PATCH 2/3] Refactored Floating point division special case detection to avoid spurious trigger on Y for sqrt) --- src/fpu/fdivsqrt/fdivsqrtfsm.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/src/fpu/fdivsqrt/fdivsqrtfsm.sv index 81f6a5eed..da13813fe 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfsm.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfsm.sv @@ -60,9 +60,9 @@ module fdivsqrtfsm( assign IFDivStartE = (FDivStartE | (IDivStartE & `IDIV_ON_FPU)) & (state == IDLE) & ~StallM; assign FDivDoneE = (state == DONE); assign FDivBusyE = (state == BUSY) | IFDivStartE; - + // terminate immediately on special cases - assign FSpecialCaseE = XZeroE | (YZeroE&~SqrtE) | XInfE | YInfE | XNaNE | YNaNE | (XsE&SqrtE); + assign FSpecialCaseE = XZeroE | | XInfE | XNaNE | (XsE&SqrtE) | (YZeroE | YInfE | YNaNE)&~SqrtE; if (`IDIV_ON_FPU) assign SpecialCaseE = IntDivE ? ISpecialCaseE : FSpecialCaseE; else assign SpecialCaseE = FSpecialCaseE; flopenr #(1) SpecialCaseReg(clk, reset, IFDivStartE, SpecialCaseE, SpecialCaseM); // save SpecialCase for checking in fdivsqrtpostproc From a49f45f2f37e663c8517d1f87190d1768424b3f2 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 3 Mar 2023 15:54:35 -0800 Subject: [PATCH 3/3] Setup ImperasDV if available --- setup.sh | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/setup.sh b/setup.sh index af4bac3b5..f6cbac6ba 100755 --- a/setup.sh +++ b/setup.sh @@ -16,15 +16,15 @@ echo \$WALLY set to ${WALLY} # Must edit these based on your local environment. Ask your sysadmin. export MGLS_LICENSE_FILE=27002@zircon.eng.hmc.edu # Change this to your Siemens license server export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server -export QUESTAPATH=/cad/mentor/questa_sim-2022.4_2/questasim/bin # Change this for your path to Questa -export SNPSPATH=/cad/synopsys/SYN/bin # Change this for your path to Design Compiler +export QUESTA_HOME=/cad/mentor/questa_sim-2022.4_2/questasim # Change this for your path to Questa, excluding bin +export SNPS_HOME=/cad/synopsys/SYN # Change this for your path to Design Compiler, excluding bin # Path to RISC-V Tools export RISCV=/opt/riscv # change this if you installed the tools in a different location # Tools # Questa and Synopsys -export PATH=$QUESTAPATH:$SNPSPATH:$PATH +export PATH=$QUESTA_HOME/bin:$SNPS_HOME/bin:$PATH # GCC export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$RISCV/riscv-gnu-toolchain/lib:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib export PATH=$PATH:$RISCV/riscv-gnu-toolchain/bin:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/bin # GCC tools @@ -42,4 +42,15 @@ export PATH=/usr/local/bin/verilator:$PATH # Change this for your path to Verila #export PATH=$RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64:$PATH #export LD_LIBRARY_PATH=$RISCV/imperas_riscv_tests/riscv-ovpsim-plus/bin/Linux64:$LD_LIBRARY_PATH # remove if no imperas +export IDV=$RISCV/ImperasDV-OpenHW +if [ -e "$IDV" ]; then +# echo "Imperas exists" + export IMPERAS_HOME=$IDV/Imperas + export IMPERAS_PERSONALITY=CPUMAN_DV_ASYNC + export ROOTDIR=~/ + source ${IDV}/Imperas/bin/setup.sh + setupImperas ${IDV}/Imperas +fi + + echo "setup done" \ No newline at end of file