From dc09e1c0c5f9ef0c64e458b7e2d36c9ebce76046 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Fri, 24 May 2024 16:38:47 -0500 Subject: [PATCH] Modified names so they don't conflict with FPGA's axi signals. --- sim/questa/wave.do | 10 +++++----- src/rvvi/packetizer.sv | 20 ++++++++++---------- testbench/testbench.sv | 16 ++++++++-------- 3 files changed, 23 insertions(+), 23 deletions(-) diff --git a/sim/questa/wave.do b/sim/questa/wave.do index ec8dd82b3..8ce781d18 100644 --- a/sim/questa/wave.do +++ b/sim/questa/wave.do @@ -667,11 +667,11 @@ add wave -noupdate -group packetizer -color Gold /testbench/rvvi_synth/packetize add wave -noupdate -group packetizer -radix unsigned /testbench/rvvi_synth/packetizer/WordCount add wave -noupdate -group packetizer /testbench/rvvi_synth/packetizer/RVVIStall add wave -noupdate -group packetizer /testbench/rvvi_synth/packetizer/rvviDelay -add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/m_axi_wdata -add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/m_axi_wlast -add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/m_axi_wstrb -add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/m_axi_wvalid -add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/m_axi_wready +add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/RvviAxiWdata +add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/RvviAxiWlast +add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/RvviAxiWstrb +add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/RvviAxiWvalid +add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/RvviAxiWready add wave -noupdate -expand -group eth /testbench/rvvi_synth/ethernet/mii_tx_clk add wave -noupdate -expand -group eth /testbench/rvvi_synth/ethernet/mii_txd add wave -noupdate -expand -group eth /testbench/rvvi_synth/ethernet/mii_tx_en diff --git a/src/rvvi/packetizer.sv b/src/rvvi/packetizer.sv index b5a2cb695..93390d03b 100644 --- a/src/rvvi/packetizer.sv +++ b/src/rvvi/packetizer.sv @@ -35,11 +35,11 @@ module packetizer import cvw::*; #(parameter cvw_t P, output logic RVVIStall, // axi 4 write address channel // axi 4 write data channel - output logic [31:0] m_axi_wdata, - output logic [3:0] m_axi_wstrb, - output logic m_axi_wlast, - output logic m_axi_wvalid, - input logic m_axi_wready + output logic [31:0] RvviAxiWdata, + output logic [3:0] RvviAxiWstrb, + output logic RvviAxiWlast, + output logic RvviAxiWvalid, + input logic RvviAxiWready ); localparam TotalFrameLengthBits = 2*48+32+16+187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12); @@ -80,7 +80,7 @@ module packetizer import cvw::*; #(parameter cvw_t P, end assign RVVIStall = CurrState != STATE_RDY; - assign TransReady = m_axi_wready; + assign TransReady = RvviAxiWready; assign WordCountEnable = (CurrState == STATE_RDY & valid) | (CurrState == STATE_TRANS & TransReady); assign WordCountReset = CurrState == STATE_RDY; @@ -106,10 +106,10 @@ module packetizer import cvw::*; #(parameter cvw_t P, assign Tag = '0; assign Length = BytesInFrame + 16'd6 + 16'd6 + 16'd4 + 16'd2; - assign m_axi_wdata = TotalFrameWords[WordCount]; - assign m_axi_wstrb = '1; - assign m_axi_wlast = BurstDone; - assign m_axi_wvalid = (CurrState == STATE_TRANS); + assign RvviAxiWdata = TotalFrameWords[WordCount]; + assign RvviAxiWstrb = '1; + assign RvviAxiWlast = BurstDone; + assign RvviAxiWvalid = (CurrState == STATE_TRANS); endmodule diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 3895a157a..6020088e6 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -598,11 +598,11 @@ module testbench; rvvisynth #(P, MAX_CSRS) rvvisynth(.clk, .reset, .valid, .rvvi); // axi 4 write data channel - logic [31:0] m_axi_wdata; - logic [3:0] m_axi_wstrb; - logic m_axi_wlast; - logic m_axi_wvalid; - logic m_axi_wready; + logic [31:0] RvviAxiWdata; + logic [3:0] RvviAxiWstrb; + logic RvviAxiWlast; + logic RvviAxiWvalid; + logic RvviAxiWready; logic [3:0] mii_txd; logic mii_tx_en, mii_tx_er; @@ -611,11 +611,11 @@ module testbench; logic rx_error_bad_fcs, rx_fifo_overflow, rx_fifo_bad_frame, rx_fifo_good_frame; packetizer #(P, MAX_CSRS) packetizer(.rvvi, .valid, .m_axi_aclk(clk), .m_axi_aresetn(~reset), .RVVIStall, - .m_axi_wdata, .m_axi_wstrb, .m_axi_wlast, .m_axi_wvalid, .m_axi_wready); + .RvviAxiWdata, .RvviAxiWstrb, .RvviAxiWlast, .RvviAxiWvalid, .RvviAxiWready); eth_mac_mii_fifo #("GENERIC", "BUFG", 32) ethernet(.rst(reset), .logic_clk(clk), .logic_rst(reset), - .tx_axis_tdata(m_axi_wdata), .tx_axis_tkeep(m_axi_wstrb), .tx_axis_tvalid(m_axi_wvalid), .tx_axis_tready(m_axi_wready), - .tx_axis_tlast(m_axi_wlast), .tx_axis_tuser('0), .rx_axis_tdata(), .rx_axis_tkeep(), .rx_axis_tvalid(), .rx_axis_tready(1'b1), + .tx_axis_tdata(RvviAxiWdata), .tx_axis_tkeep(RvviAxiWstrb), .tx_axis_tvalid(RvviAxiWvalid), .tx_axis_tready(RvviAxiWready), + .tx_axis_tlast(RvviAxiWlast), .tx_axis_tuser('0), .rx_axis_tdata(), .rx_axis_tkeep(), .rx_axis_tvalid(), .rx_axis_tready(1'b1), .rx_axis_tlast(), .rx_axis_tuser(), // *** update these