From b2958f228f99f34ae84e9b225aa4a902ef37f273 Mon Sep 17 00:00:00 2001 From: SadhviNarayanan Date: Sat, 26 Apr 2025 01:32:29 -0700 Subject: [PATCH 01/43] added benchmarking scripts to check for performance hits --- benchmarks/coremark/coremark_sweep.py | 10 +- .../coremark/expected_coremark_results.csv | 13 ++ bin/expected_results.json | 23 +++ bin/regression-wally | 41 ++++- bin/validate_performance.py | 173 ++++++++++++++++++ 5 files changed, 257 insertions(+), 3 deletions(-) create mode 100644 benchmarks/coremark/expected_coremark_results.csv create mode 100644 bin/expected_results.json create mode 100755 bin/validate_performance.py diff --git a/benchmarks/coremark/coremark_sweep.py b/benchmarks/coremark/coremark_sweep.py index 2e2ab4555..5e6b099e7 100755 --- a/benchmarks/coremark/coremark_sweep.py +++ b/benchmarks/coremark/coremark_sweep.py @@ -33,6 +33,13 @@ import csv import os import re +WALLY = os.environ.get("WALLY") + +# Set working directory to where the Makefile is +coremark_dir = os.path.join(WALLY, "benchmarks/coremark") +os.chdir(coremark_dir) + + # list of architectures to run. arch_list = [ "rv32i_zicsr", @@ -54,7 +61,8 @@ mt_regex = r"Elapsed MTIME: (\d+).*?Elapsed MINSTRET: (\d+).*?COREMARK/MHz Score #cpi_regex = r"CPI: \d+ / \d+ = (\d+\.\d+)" #cmhz_regex = r"COREMARK/MHz Score: [\d,]+ / [\d,]+ = (\d+\.\d+)" # Open a CSV file to write the results -resultfile = 'coremark_results.csv' +resultfile = os.path.join(coremark_dir, 'coremark_results.csv') +# resultfile = 'coremark_results.csv' with open(resultfile, mode='w', newline='') as csvfile: fieldnames = ['Architecture', 'CM / MHz','CPI','MTIME','MINSTRET','Load Stalls','Store Stalls','D$ Accesses', 'D$ Misses','I$ Accesses','I$ Misses','Branches','Branch Mispredicts','BTB Misses', diff --git a/benchmarks/coremark/expected_coremark_results.csv b/benchmarks/coremark/expected_coremark_results.csv new file mode 100644 index 000000000..fff7b0055 --- /dev/null +++ b/benchmarks/coremark/expected_coremark_results.csv @@ -0,0 +1,13 @@ +Architecture,CM / MHz,CPI,MTIME,MINSTRET,Load Stalls,Store Stalls,D$ Accesses,D$ Misses,I$ Accesses,I$ Misses,Branches,Branch Mispredicts,BTB Misses,Jump/JR,RAS Wrong,Returns,BP Class Pred Wrong +rv32i_zicsr,1.20,1.16,8269385,7124630,261886,22307,716317,73,7827908,1040,2009578,443447,5476,122015,3468,113645,20699 +rv32im_zicsr,3.26,1.12,3061233,2716910,264489,22198,690506,73,2975498,827,543885,45067,5483,30033,69,15237,20898 +rv32imc_zicsr,3.24,1.13,3085767,2716550,264404,23853,690507,75,3011253,285,543761,44223,5615,29675,171,15237,20295 +rv32im_zicsr_zba_zbb_zbs,3.38,1.12,2954414,2624181,266850,22258,689232,75,2878922,494,544408,42375,4295,29685,18,15249,14980 +rv32gc,3.24,1.13,3085783,2716550,264134,23852,690500,74,3010201,286,543485,44182,5563,29668,162,15230,20108 +rv32gc_zba_zbb_zbs,3.32,1.14,3003843,2624181,272635,22141,689226,74,2929468,280,543245,44490,6087,29680,23,15242,22189 +rv64i_zicsr,1.02,1.13,9731538,8559698,273929,22198,720375,85,9242621,588,2340171,459594,4842,128954,178,109383,15941 +rv64im_zicsr,2.86,1.10,3493939,3156218,271101,22149,691714,83,3406099,340,547671,42901,4651,34669,14,15099,15726 +rv64imc_zicsr,2.82,1.12,3545301,3156218,271029,25304,691715,86,3457798,263,547535,43990,4970,34671,5,15099,15889 +rv64im_zicsr_zba_zbb_zbs,3.08,1.11,3241375,2901479,273442,24665,689242,85,3150626,424,547796,41798,4635,34680,43,15111,16143 +rv64gc,2.82,1.12,3545281,3156218,270740,25304,691708,86,3456812,264,547229,43969,4970,34664,5,15092,15889 +rv64gc_zba_zbb_zbs,3.03,1.13,3297540,2901479,273107,26696,689236,83,3200848,250,547359,46238,6197,34675,73,15104,21328 diff --git a/bin/expected_results.json b/bin/expected_results.json new file mode 100644 index 000000000..8ffd582a8 --- /dev/null +++ b/bin/expected_results.json @@ -0,0 +1,23 @@ +{ + "coremark": { + "coremark/mhz": 3.38 + }, + "embench_rv32imc": { + "wallySizeOpt_size": { + "size geometric mean": 1.04, + "size geometric standard deviation": 1.26 + }, + "wallySizeOpt_speed": { + "size geometric mean": 1.07, + "size geometric standard deviation": 1.51 + }, + "wallySpeedOpt_size": { + "size geometric mean": 1.21, + "size geometric standard deviation": 1.28 + }, + "wallySpeedOpt_speed": { + "size geometric mean": 1.15, + "size geometric standard deviation": 1.61 + } + } +} \ No newline at end of file diff --git a/bin/regression-wally b/bin/regression-wally index 88b88a000..ae12761e8 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -395,6 +395,8 @@ def parse_args(): parser.add_argument("--fp", help="Include floating-point tests in coverage (slower runtime)", action="store_true") # Currently not used parser.add_argument("--breker", help="Run Breker tests", action="store_true") # Requires a license for the breker tool. See tests/breker/README.md for details parser.add_argument("--dryrun", help="Print commands invoked to console without running regression", action="store_true") + + parser.add_argument("--performance", help="Check for performance changes or discrepencies in embench and coremark", action="store_true") return parser.parse_args() @@ -415,7 +417,7 @@ def process_args(args): TIMEOUT_DUR = 30*60 shutil.rmtree(f"{regressionDir}/questa/fcov_ucdb", ignore_errors=True) os.makedirs(f"{regressionDir}/questa/fcov_ucdb", exist_ok=True) - elif args.buildroot: + elif args.buildroot or args.performance: # TODO: fix timing on this bc performance shodl also be limit on nightly TIMEOUT_DUR = 60*3600 # 2.5 days elif args.testfloat: sims = [testfloatsim] @@ -423,7 +425,7 @@ def process_args(args): elif args.branch: TIMEOUT_DUR = 120*60 # seconds elif args.nightly: - TIMEOUT_DUR = 30*60 # seconds + TIMEOUT_DUR = 5*3600 # seconds # NOTE: changed this to 5 hours for nightly regression else: TIMEOUT_DUR = 10*60 # seconds @@ -505,6 +507,41 @@ def selectTests(args, sims, coverStr): grepstr="All Tests completed with 0 errors", grepfile = sim_log) configs.append(tc) + + if (args.performance or args.nightly): + # RUNNING THE EMBENCH TEST + embench_test = TestCase( + name="embench", + variant="rv32gc", # is this the correct variant here? or rv32imac_zicsr + cmd="cd $WALLY/benchmarks/embench && make run | tee run.log", # do we want to pipe result out? | tee run.log + grepstr="SUCCESS", # not sure what keyword to put here + grepfile=os.path.expandvars("$WALLY/benchmarks/embench/run.log") + ) + configs.append(embench_test) + + validation_log = f"{WALLY}/bin/logs/validation.log" + os.makedirs(os.path.dirname(validation_log), exist_ok=True) + + validate_test_dir = f"{WALLY}/bin/validate_performance.py" + coremark_sweep_test_dir = f"{WALLY}/benchmarks/coremark/coremark_sweep.py" + + # Remove './' since you're using full paths + # Ensure the log file exists before writing (with `touch`) + # Also chain commands properly and safely + performance_test = TestCase( + name="validate_performance", + variant="performance check", + cmd=( + f"touch {validation_log} && " + f"python3 {coremark_sweep_test_dir} && " + f"python3 {validate_test_dir} | tee {validation_log}" + ), + grepstr="Validation Tests completed with 0 errors", # adjust if message differs + grepfile=validation_log + ) + + configs.append(performance_test) + return configs diff --git a/bin/validate_performance.py b/bin/validate_performance.py new file mode 100755 index 000000000..ea5598215 --- /dev/null +++ b/bin/validate_performance.py @@ -0,0 +1,173 @@ +#!/usr/bin/env python3 +import csv +import json +import os + +# global variables +WALLY = os.environ.get('WALLY') +coremarkDir = f'{WALLY}/benchmarks/coremark/coremark_results.csv' +coremarkDir_expected = f'{WALLY}/benchmarks/coremark/expected_coremark_results.csv' +embenchDir = f'{WALLY}/benchmarks/embench' + + +def create_expected_results_json(): + # Create a dictionary to hold the expected results + validation_data = { + "coremark": { + "coremark/mhz": 3.38 + }, + "embench_rv32imc": { + "wallySizeOpt_size": { + "size geometric mean": 1.04, + "size geometric standard deviation": 1.26 + }, + "wallySizeOpt_speed": { + "size geometric mean": 1.07, + "size geometric standard deviation": 1.51 + }, + "wallySpeedOpt_size": { + "size geometric mean": 1.21, + "size geometric standard deviation": 1.28 + }, + "wallySpeedOpt_speed": { + "size geometric mean": 1.15, + "size geometric standard deviation": 1.61 + } + } + } + + # Write the data to a JSON file + with open('expected_results.json', 'w') as json_file: + json.dump(validation_data, json_file, indent=4) # Use validation_data instead of 'data' + +def validate_results(): + # EMBENCH VALIDATION + failing_value = "" + # Create a list to keep track of all the csv files generated by embench + embench_csv_files = ["wallySizeOpt_size", "wallySizeOpt_speed", "wallySpeedOpt_size", "wallySpeedOpt_speed"] + + for json_file in embench_csv_files: + directory = f"{embenchDir}/{json_file}.json" + # Open and read the JSON file + with open(directory) as file: + embench_log_csv_data = json.load(file) + + # Extract whether the file is a speed or size test (based on the filename) + type_speed_sound = json_file.split("_")[1] + + # Create the keys for the JSON data + level1 = f"{type_speed_sound} results" + key_level2_mean = f"{type_speed_sound} geometric mean" + key_level2_std_dev = f"{type_speed_sound} geometric standard deviation" + + # Extract the actual size geometric mean and std. dev. from the JSON data + actual_size_geometric_mean = embench_log_csv_data[level1][key_level2_mean] + actual_size_geometric_std_dev = embench_log_csv_data[level1][key_level2_std_dev] + + # Load the expected results from the expected_results.json file + expected_results_path = f"{WALLY}/bin/expected_results.json" + with open(expected_results_path) as file: + expected_data = json.load(file) + + # Extract geometric means from the expected results for comparison + expected_wally_geometric_mean = expected_data['embench_rv32imc'][json_file]['size geometric mean'] + expected_wally_geometric_std_dev = expected_data['embench_rv32imc'][json_file]['size geometric standard deviation'] + + # Compare the actual and expected results + if (actual_size_geometric_mean != expected_wally_geometric_mean): + failing_value += f"embench {json_file}'s geometric mean of {actual_size_geometric_mean} does not match expected value of {expected_wally_geometric_mean}\n" + + # # Update expected results file if smaller / better results + # if actual_size_geometric_mean < expected_wally_geometric_mean: + # updated_expected_json = True + # expected_data['embench_rv32imc'][json_file]['size geometric mean'] = actual_size_geometric_mean + # print(f"Updated expected geometric mean for {json_file} to {actual_size_geometric_mean}") + + + if (actual_size_geometric_std_dev != expected_wally_geometric_std_dev): + failing_value += f"embench {json_file}'s geometric std. dev. of {actual_size_geometric_std_dev} does not match expected value of {expected_wally_geometric_std_dev}\n" + + # # Update expected results file if smaller / better results + # if actual_size_geometric_std_dev < expected_wally_geometric_std_dev: + # updated_expected_json = True + # expected_data['embench_rv32imc'][json_file]['size geometric standard deviation'] = actual_size_geometric_std_dev + # print(f"Updated expected std. dev. for {json_file} to {actual_size_geometric_std_dev}") + + # if (updated_expected_json): + # with open(expected_results_path, 'w') as f: + # json.dump(expected_data, f, indent=4) + + # # automatically push the expected_results.json file to github + # subprocess.run(["git", "add", expected_results_path]) + # subprocess.run(["git", "commit", "-m", "Update expected results with improved metrics"]) + # subprocess.run(["git", "push"]) + + # COREMARK VALIDATION + # coremark_run = {} + # with open(coremarkDir, newline='') as csvfile: + # reader = csv.DictReader(csvfile) + # for row in reader: + # arch = row["Architecture"] + # coremark_run[arch] = row + # Now you can directly index into it + # actual_CM_MHz = coremark_run["rv32im_zicsr_zba_zbb_zbs"]["CM / MHz"] + # expected_wally_CM_Mhz = expected_data['coremark']['coremark/mhz'] + # if (str(actual_CM_MHz) != str(expected_wally_CM_Mhz)): + # failure = True + # failing_value += f"coremark's actual CM/MHz of {actual_CM_MHz} does not match expected value of {expected_wally_CM_Mhz}\n" + + + # Read in the expected results from the expected_coremark_results.csv file, + # as well as the new one created by the test + actual_results = read_csv_as_sorted_list(coremarkDir) + expected_results = read_csv_as_sorted_list(coremarkDir_expected) + + # Compare the two CSV files + if actual_results != expected_results: + failing_value = "Coremark results do not match expected results.\n" + print(failing_value) + failing_value += f"Coremark results:\n{actual_results}\n" + failing_value += f"Expected results:\n{expected_results}\n" + exit(1) + + # Check if there were any failures + if (failing_value == ""): + print("Validation Tests completed with 0 errors") + else: + print(failing_value) + exit(1) + + +def read_csv_as_sorted_list(filename): + with open(filename, newline='') as f: + reader = csv.reader(f) + rows = list(reader) + rows.sort() # sort rows for consistent ordering + return rows + +def main(): + create_expected_results_json() # NOTE: need to uncomment this line to create the expected_results.json file + validate_results() + +if __name__ == "__main__": + main() + + +# do we only want to trigger with nightly - yes +# is there a reason we only care about the 3.38 from the rv32im_zicsr_zba_zbb_zbs arch - most complete +# how do i know if the two testss that produce the results i scrape from are running - just running these default + # cd $WALLY/benchmarks/coremark + # ./coremark_sweep.py + + # cd $WALLY/benchmarks/embench + # make run + +# automatically push to github if better results? + +# coremark sweep - creates the csv of values fro diff arch +# embench benchmark - creates the 4 json files for speed/size + +# check if there are differences between runs of coremark sweep on the csv --> done +# need to standardize timoeout duration between performance flag and nightly +# need to make syre it is failing when different +# need to check if i need to validate more values in this file (maybe do a diff for the csv) --> done this part (more to come in future liekly) From becb11e752207659a467cebb1ba6c2123b38668b Mon Sep 17 00:00:00 2001 From: SadhviNarayanan Date: Sat, 26 Apr 2025 01:45:21 -0700 Subject: [PATCH 02/43] updated to upstream --- bin/regression-wally | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index 1f422de4f..ada773558 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -518,15 +518,13 @@ def selectTests(args, sims, coverStr): ) configs.append(embench_test) + # RUNNING THE COREMARK TEST validation_log = f"{WALLY}/bin/logs/validation.log" os.makedirs(os.path.dirname(validation_log), exist_ok=True) validate_test_dir = f"{WALLY}/bin/validate_performance.py" coremark_sweep_test_dir = f"{WALLY}/benchmarks/coremark/coremark_sweep.py" - - # Remove './' since you're using full paths - # Ensure the log file exists before writing (with `touch`) - # Also chain commands properly and safely + performance_test = TestCase( name="validate_performance", variant="performance check", From 3847b9cd1e10a76b99123bc48d4057c1be68af0b Mon Sep 17 00:00:00 2001 From: SadhviNarayanan Date: Sat, 26 Apr 2025 05:16:33 -0700 Subject: [PATCH 03/43] new version implemented through grep in regression --- bin/regression-wally | 43 +++++++++++++++++++++++++++++++++++++------ 1 file changed, 37 insertions(+), 6 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index ada773558..ffa6c863e 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -372,8 +372,12 @@ def run_test_case(config, dryrun: bool = False): print(f"Executing {cmd}", flush=True) return 0 else: - os.system(cmd) - if search_log_for_text(config.grepstr, grepfile): + ret_code = os.system(cmd) + if ret_code != 0: + print(f"{bcolors.FAIL}{cmd}: Failed to execute{bcolors.ENDC}", flush=True) + print(f" Check {grepfile} for more details.", flush=True) + return 1 + elif search_log_for_text(config.grepstr, grepfile): # Flush is needed to flush output to stdout when running in multiprocessing Pool print(f"{bcolors.OKGREEN}{cmd}: Success{bcolors.ENDC}", flush=True) return 0 @@ -509,10 +513,29 @@ def selectTests(args, sims, coverStr): if (args.performance or args.nightly): # RUNNING THE EMBENCH TEST + json_dir_1 = f"{WALLY}/benchmarks/embench/wallySizeOpt_size.json" + json_dir_2 = f"{WALLY}/benchmarks/embench/wallySizeOpt_speed.json" + json_dir_3 = f"{WALLY}/benchmarks/embench/wallySpeedOpt_size.json" + json_dir_4 = f"{WALLY}/benchmarks/embench/wallySpeedOpt_speed.json" + embench_test = TestCase( name="embench", variant="rv32gc", # is this the correct variant here? or rv32imac_zicsr - cmd="cd $WALLY/benchmarks/embench && make run | tee run.log", # do we want to pipe result out? | tee run.log + cmd=( + f"touch $WALLY/benchmarks/embench/run.log && (" + f"cd $WALLY/benchmarks/embench && make run | tee run.log && " + f"grep -q 'size geometric mean.*1.04' {json_dir_1} && " + f"grep -q 'size geometric standard deviation.*1.26' {json_dir_1} && " + f"grep -q 'speed geometric mean.*1.07' {json_dir_2} && " + f"grep -q 'speed geometric standard deviation.*1.51' {json_dir_2} && " + f"grep -q 'size geometric mean.*1.21' {json_dir_3} && " + f"grep -q 'size geometric standard deviation.*1.28' {json_dir_3} && " + f"grep -q 'speed geometric mean.*1.15' {json_dir_4} && " + f"grep -q 'speed geometric standard deviation.*1.61' {json_dir_4}" + f") && echo 'EMBENCH_TEST_PASSED' >> $WALLY/benchmarks/embench/run.log " + f"|| (echo 'EMBENCH_TEST_FAILED: Values did not match expected metrics' >> $WALLY/benchmarks/embench/run.log && exit 1)" + ), + grepstr="SUCCESS", # not sure what keyword to put here grepfile=os.path.expandvars("$WALLY/benchmarks/embench/run.log") ) @@ -522,16 +545,24 @@ def selectTests(args, sims, coverStr): validation_log = f"{WALLY}/bin/logs/validation.log" os.makedirs(os.path.dirname(validation_log), exist_ok=True) - validate_test_dir = f"{WALLY}/bin/validate_performance.py" coremark_sweep_test_dir = f"{WALLY}/benchmarks/coremark/coremark_sweep.py" - + + actual_coremark_values_csv = f"{WALLY}/benchmarks/coremark/coremark_results.csv" + expected_coremark_values_csv = f"{WALLY}/benchmarks/coremark/expected_coremark_results.csv" + performance_test = TestCase( name="validate_performance", variant="performance check", cmd=( + "set -e && " f"touch {validation_log} && " f"python3 {coremark_sweep_test_dir} && " - f"python3 {validate_test_dir} | tee {validation_log}" + f"if diff -q {actual_coremark_values_csv} {expected_coremark_values_csv}; then " + f" echo 'Coremark Validation Tests completed with 0 errors' | tee {validation_log}; " + f"else " + f" echo 'ERROR: CSV files differ' | tee {validation_log}; " + f" exit 1; " + f"fi" ), grepstr="Validation Tests completed with 0 errors", # adjust if message differs grepfile=validation_log From fd77120eb24c667d9ab6c7ca38408346aebbf1cd Mon Sep 17 00:00:00 2001 From: SadhviNarayanan Date: Sat, 26 Apr 2025 05:22:13 -0700 Subject: [PATCH 04/43] new version implemented through grep in regression --- bin/regression-wally | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/regression-wally b/bin/regression-wally index ffa6c863e..6b6ac6fc0 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -520,7 +520,7 @@ def selectTests(args, sims, coverStr): embench_test = TestCase( name="embench", - variant="rv32gc", # is this the correct variant here? or rv32imac_zicsr + variant="rv32gc", # is this the correct variant here? or rv32imac_zicsr cmd=( f"touch $WALLY/benchmarks/embench/run.log && (" f"cd $WALLY/benchmarks/embench && make run | tee run.log && " From 9bb392ae5ae1417ed8d210fb96ff55644e11b9b4 Mon Sep 17 00:00:00 2001 From: SadhviNarayanan Date: Sat, 26 Apr 2025 05:35:31 -0700 Subject: [PATCH 05/43] updated grepstr --- bin/regression-wally | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/regression-wally b/bin/regression-wally index 6b6ac6fc0..5a557746e 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -536,7 +536,7 @@ def selectTests(args, sims, coverStr): f"|| (echo 'EMBENCH_TEST_FAILED: Values did not match expected metrics' >> $WALLY/benchmarks/embench/run.log && exit 1)" ), - grepstr="SUCCESS", # not sure what keyword to put here + grepstr="EMBENCH_TEST_PASSED", # not sure what keyword to put here --> could also put success which comes from the simulation grepfile=os.path.expandvars("$WALLY/benchmarks/embench/run.log") ) configs.append(embench_test) From 2800ac64d72261e489f13cb6e1dcd83390fe2ee3 Mon Sep 17 00:00:00 2001 From: SadhviNarayanan Date: Sat, 26 Apr 2025 16:42:28 -0700 Subject: [PATCH 06/43] cleaned up script here as well --- bin/validate_performance.py | 21 +-------------------- 1 file changed, 1 insertion(+), 20 deletions(-) diff --git a/bin/validate_performance.py b/bin/validate_performance.py index ea5598215..4ce6a21e0 100755 --- a/bin/validate_performance.py +++ b/bin/validate_performance.py @@ -9,6 +9,7 @@ coremarkDir = f'{WALLY}/benchmarks/coremark/coremark_results.csv' coremarkDir_expected = f'{WALLY}/benchmarks/coremark/expected_coremark_results.csv' embenchDir = f'{WALLY}/benchmarks/embench' +# NOTE: This script is not used in this branch's implementation, however it is kept here for reference def create_expected_results_json(): # Create a dictionary to hold the expected results @@ -151,23 +152,3 @@ def main(): if __name__ == "__main__": main() - - -# do we only want to trigger with nightly - yes -# is there a reason we only care about the 3.38 from the rv32im_zicsr_zba_zbb_zbs arch - most complete -# how do i know if the two testss that produce the results i scrape from are running - just running these default - # cd $WALLY/benchmarks/coremark - # ./coremark_sweep.py - - # cd $WALLY/benchmarks/embench - # make run - -# automatically push to github if better results? - -# coremark sweep - creates the csv of values fro diff arch -# embench benchmark - creates the 4 json files for speed/size - -# check if there are differences between runs of coremark sweep on the csv --> done -# need to standardize timoeout duration between performance flag and nightly -# need to make syre it is failing when different -# need to check if i need to validate more values in this file (maybe do a diff for the csv) --> done this part (more to come in future liekly) From bcf81e5aad86fcbb028d0492cbaf9077f9e03a5d Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Sun, 27 Apr 2025 13:13:24 -0500 Subject: [PATCH 07/43] Created test to force ebu arbitration. --- tests/coverage/ebuArb.S | 135 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 135 insertions(+) create mode 100644 tests/coverage/ebuArb.S diff --git a/tests/coverage/ebuArb.S b/tests/coverage/ebuArb.S new file mode 100644 index 000000000..14ae573af --- /dev/null +++ b/tests/coverage/ebuArb.S @@ -0,0 +1,135 @@ +/////////////////////////////////////////// +// ebuArb.S +// +// Written: Rose Thompson rose@rosethompson.net +// +// Purpose: Force EBU arbitration. +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-25 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate + +#include "WALLY-init-lib.h" + + # run-elf.bash find this in project description + # cannot do this with a loop +main: + la x31, data + addi x30, x31, 0x40 + addi x29, x31, 0x80 + addi x28, x31, 0xc0 + addi x27, x31, 0x100 + addi x26, x31, 0x140 + addi x25, x31, 0x180 + addi x24, x31, 0x1c0 + + ld x0, 0(x31) + cbo.inval (x31) + ld x1, 8(x31) + ld x2, 0x10(x31) + ld x3, 0x18(x31) + ld x4, 0x20(x31) + ld x5, 0x28(x31) + ld x6, 0x30(x31) + ld x7, 0x38(x31) + ld x8, 0x40(x31) + cbo.inval (x30) + ld x9, 0x48(x31) + ld x10, 0x50(x31) + ld x11, 0x58(x31) + ld x12, 0x60(x31) + ld x13, 0x68(x31) + ld x14, 0x70(x31) + ld x15, 0x78(x31) + ld x16, 0x80(x31) + cbo.inval (x29) + ld x17, 0x88(x31) + ld x18, 0x90(x31) + ld x19, 0x98(x31) + ld x20, 0xa0(x31) + ld x21, 0xa8(x31) + ld x22, 0xb0(x31) + ld x23, 0xb8(x31) + ld x23, 0xc0(x31) + cbo.inval (x28) + ld x23, 0xc8(x31) + ld x23, 0xd0(x31) + ld x23, 0xd8(x31) + ld x23, 0xe0(x31) + ld x23, 0xe8(x31) + ld x23, 0xf0(x31) + ld x0, 0xf8(x31) + ld x1, 0x100(x31) + cbo.inval (x27) + ld x1, 0x108(x31) + ld x1, 0x110(x31) + ld x1, 0x118(x31) + ld x1, 0x120(x31) + ld x1, 0x128(x31) + ld x1, 0x130(x31) + ld x1, 0x138(x31) + ld x1, 0x140(x31) + cbo.inval (x26) + ld x1, 0x148(x31) + ld x1, 0x150(x31) + ld x1, 0x158(x31) + ld x1, 0x160(x31) + ld x1, 0x168(x31) + ld x1, 0x170(x31) + ld x1, 0x178(x31) + ld x1, 0x180(x31) + cbo.inval (x25) + ld x1, 0x188(x31) + ld x1, 0x190(x31) + ld x1, 0x198(x31) + ld x1, 0x1a0(x31) + ld x1, 0x1a8(x31) + ld x1, 0x1b0(x31) + ld x1, 0x1b8(x31) + ld x1, 0x1c0(x31) + cbo.inval (x24) + ld x1, 0x1c8(x31) + ld x1, 0x1d0(x31) + ld x1, 0x1d8(x31) + ld x1, 0x1e0(x31) + ld x1, 0x1e8(x31) + ld x1, 0x1f0(x31) + ld x1, 0x1f8(x31) + + + +finished: + j done + +.data + +.align 3 +# Page table situated at 0x80010000 +data: + .8byte 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7 + .8byte 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf + .8byte 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17 + .8byte 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f + .8byte 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27 + .8byte 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f + .8byte 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37 + .8byte 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f + .8byte 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47 + .8byte 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f From cd0b44dd8b132665134d0a4f7bd3faa55b5c077b Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Sun, 27 Apr 2025 13:18:52 -0500 Subject: [PATCH 08/43] Cleaned up ebuArb test. --- tests/coverage/ebuArb.S | 61 +++++++++++++++++++++++++++++++++++++---- 1 file changed, 56 insertions(+), 5 deletions(-) diff --git a/tests/coverage/ebuArb.S b/tests/coverage/ebuArb.S index 14ae573af..a811b7754 100644 --- a/tests/coverage/ebuArb.S +++ b/tests/coverage/ebuArb.S @@ -28,8 +28,7 @@ #include "WALLY-init-lib.h" - # run-elf.bash find this in project description - # cannot do this with a loop + # cannot do this with a loop, must invalidate frequently to force as many possible lsu bus requests. main: la x31, data addi x30, x31, 0x40 @@ -43,74 +42,129 @@ main: ld x0, 0(x31) cbo.inval (x31) ld x1, 8(x31) + cbo.inval (x31) ld x2, 0x10(x31) + cbo.inval (x31) ld x3, 0x18(x31) + cbo.inval (x31) ld x4, 0x20(x31) + cbo.inval (x31) ld x5, 0x28(x31) + cbo.inval (x31) ld x6, 0x30(x31) + cbo.inval (x31) ld x7, 0x38(x31) + cbo.inval (x31) ld x8, 0x40(x31) cbo.inval (x30) ld x9, 0x48(x31) + cbo.inval (x30) ld x10, 0x50(x31) + cbo.inval (x30) ld x11, 0x58(x31) + cbo.inval (x30) ld x12, 0x60(x31) + cbo.inval (x30) ld x13, 0x68(x31) + cbo.inval (x30) ld x14, 0x70(x31) + cbo.inval (x30) ld x15, 0x78(x31) + cbo.inval (x30) ld x16, 0x80(x31) cbo.inval (x29) ld x17, 0x88(x31) + cbo.inval (x29) ld x18, 0x90(x31) + cbo.inval (x29) ld x19, 0x98(x31) + cbo.inval (x29) ld x20, 0xa0(x31) + cbo.inval (x29) ld x21, 0xa8(x31) + cbo.inval (x29) ld x22, 0xb0(x31) + cbo.inval (x29) ld x23, 0xb8(x31) + cbo.inval (x29) ld x23, 0xc0(x31) cbo.inval (x28) ld x23, 0xc8(x31) + cbo.inval (x28) ld x23, 0xd0(x31) + cbo.inval (x28) ld x23, 0xd8(x31) + cbo.inval (x28) ld x23, 0xe0(x31) + cbo.inval (x28) ld x23, 0xe8(x31) + cbo.inval (x28) ld x23, 0xf0(x31) + cbo.inval (x28) ld x0, 0xf8(x31) + cbo.inval (x28) ld x1, 0x100(x31) cbo.inval (x27) ld x1, 0x108(x31) + cbo.inval (x27) ld x1, 0x110(x31) + cbo.inval (x27) ld x1, 0x118(x31) + cbo.inval (x27) ld x1, 0x120(x31) + cbo.inval (x27) ld x1, 0x128(x31) + cbo.inval (x27) ld x1, 0x130(x31) + cbo.inval (x27) ld x1, 0x138(x31) + cbo.inval (x27) ld x1, 0x140(x31) cbo.inval (x26) ld x1, 0x148(x31) + cbo.inval (x26) ld x1, 0x150(x31) + cbo.inval (x26) ld x1, 0x158(x31) + cbo.inval (x26) ld x1, 0x160(x31) + cbo.inval (x26) ld x1, 0x168(x31) + cbo.inval (x26) ld x1, 0x170(x31) + cbo.inval (x26) ld x1, 0x178(x31) + cbo.inval (x26) ld x1, 0x180(x31) cbo.inval (x25) ld x1, 0x188(x31) + cbo.inval (x25) ld x1, 0x190(x31) + cbo.inval (x25) ld x1, 0x198(x31) + cbo.inval (x25) ld x1, 0x1a0(x31) + cbo.inval (x25) ld x1, 0x1a8(x31) + cbo.inval (x25) ld x1, 0x1b0(x31) + cbo.inval (x25) ld x1, 0x1b8(x31) + cbo.inval (x25) ld x1, 0x1c0(x31) cbo.inval (x24) ld x1, 0x1c8(x31) + cbo.inval (x24) ld x1, 0x1d0(x31) + cbo.inval (x24) ld x1, 0x1d8(x31) + cbo.inval (x24) ld x1, 0x1e0(x31) + cbo.inval (x24) ld x1, 0x1e8(x31) + cbo.inval (x24) ld x1, 0x1f0(x31) + cbo.inval (x24) ld x1, 0x1f8(x31) @@ -121,7 +175,6 @@ finished: .data .align 3 -# Page table situated at 0x80010000 data: .8byte 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7 .8byte 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf @@ -131,5 +184,3 @@ data: .8byte 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f .8byte 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37 .8byte 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f - .8byte 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47 - .8byte 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f From a03691498cb9df26d309c14665ef3a54814a322f Mon Sep 17 00:00:00 2001 From: SadhviNarayanan Date: Mon, 28 Apr 2025 02:05:57 -0700 Subject: [PATCH 09/43] updated the script --- bin/regression-wally | 113 ++++++++++++++++++++++++++----------------- 1 file changed, 68 insertions(+), 45 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index 5a557746e..370eaa142 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -278,7 +278,7 @@ lockstepwaivers = [ # Data Types & Functions ################################## -TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr', 'grepfile']) +TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr', 'grepfile', 'diffcommand', 'simlog']) # name: the name of this test configuration (used in printing human-readable # output and picking logfile names) # cmd: the command to run to test (should include the logfile as '{}', and @@ -287,7 +287,10 @@ TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr', 'grepfil # grep finds that string in the logfile (is used by grep, so it may # be any pattern grep accepts, see `man 1 grep` for more info). # grepfile: a string containing the location of the file to be searched for output - +# diffcommand: the command to run, if enabled, to check the output of the CoreMark benchmark +# against the expected output. The command should write to the +# validation log file. If None, no diff command is run. +# simlog: the name of the logfile to be used for this test. class bcolors: HEADER = '\033[95m' OKBLUE = '\033[94m' @@ -316,7 +319,9 @@ def addTests(testList, sim, coverStr, configs): variant=config, cmd=f"{cmdPrefix} {t} > {sim_log}", grepstr=gs, - grepfile = grepfile) + grepfile = grepfile, + diffcommand=None, + simlog=sim_log) configs.append(tc) @@ -352,7 +357,9 @@ def addTestsByDir(testDir, config, sim, coverStr, configs, lockstepMode=0, breke variant=config, cmd=f"{cmdPrefix} {fullfile} > {sim_log}", grepstr=gs, - grepfile = sim_log) + grepfile = sim_log, + diffcommand=None, + simlog=sim_log) configs.append(tc) def search_log_for_text(text, grepfile): @@ -368,6 +375,7 @@ def search_log_for_text(text, grepfile): def run_test_case(config, dryrun: bool = False): grepfile = config.grepfile cmd = config.cmd + diffcommand = config.diffcommand if dryrun: print(f"Executing {cmd}", flush=True) return 0 @@ -377,6 +385,20 @@ def run_test_case(config, dryrun: bool = False): print(f"{bcolors.FAIL}{cmd}: Failed to execute{bcolors.ENDC}", flush=True) print(f" Check {grepfile} for more details.", flush=True) return 1 + elif diffcommand: + sim_log = config.simlog + check_ret_code = os.system(diffcommand) + with open(sim_log, 'a') as f: + if check_ret_code == 0: + # Success message + print(f"{bcolors.OKGREEN}{cmd}: Success{bcolors.ENDC}", flush=True) + f.write("Coremark Validation Tests completed with 0 errors\n") # Write success message to the log + return 0 + else: + # Failure message + print(f"{bcolors.FAIL}{cmd}: Failures detected in output: there is a difference in the coremark csv files. Check {sim_log}.{bcolors.ENDC}", flush=True) + f.write("ERROR: There is a difference in the coremark CSV files\n") # Write failure message to the log + return 1 elif search_log_for_text(config.grepstr, grepfile): # Flush is needed to flush output to stdout when running in multiprocessing Pool print(f"{bcolors.OKGREEN}{cmd}: Success{bcolors.ENDC}", flush=True) @@ -399,7 +421,7 @@ def parse_args(): parser.add_argument("--breker", help="Run Breker tests", action="store_true") # Requires a license for the breker tool. See tests/breker/README.md for details parser.add_argument("--dryrun", help="Print commands invoked to console without running regression", action="store_true") - parser.add_argument("--performance", help="Check for performance changes or discrepencies in embench and coremark", action="store_true") + parser.add_argument("--performance", help="Check for performance changes or discrepancies in embench and coremark", action="store_true") return parser.parse_args() @@ -420,15 +442,15 @@ def process_args(args): TIMEOUT_DUR = 30*60 shutil.rmtree(f"{regressionDir}/questa/fcov_ucdb", ignore_errors=True) os.makedirs(f"{regressionDir}/questa/fcov_ucdb", exist_ok=True) - elif args.buildroot or args.performance: # TODO: fix timing on this bc performance shodl also be limit on nightly + elif args.buildroot: TIMEOUT_DUR = 60*3600 # 2.5 days elif args.testfloat: sims = [testfloatsim] TIMEOUT_DUR = 30*60 # seconds elif args.branch: TIMEOUT_DUR = 120*60 # seconds - elif args.nightly: - TIMEOUT_DUR = 5*3600 # seconds # NOTE: changed this to 5 hours for nightly regression + elif args.nightly or args.performance: + TIMEOUT_DUR = 5*3600 # seconds else: TIMEOUT_DUR = 10*60 # seconds @@ -443,7 +465,9 @@ def selectTests(args, sims, coverStr): variant="all", cmd=f"lint-wally {'--nightly' if args.nightly else ''} | tee {regressionDir}/verilator/logs/all_lints.log", grepstr="lints run with no errors or warnings", - grepfile = f"{regressionDir}/verilator/logs/all_lints.log") + grepfile = f"{regressionDir}/verilator/logs/all_lints.log", + diffcommand=None, + simlog=f"{regressionDir}/verilator/logs/all_lints.log"), ] # run full buildroot boot simulation (slow) if buildroot flag is set. Start it early to overlap with other tests @@ -508,15 +532,17 @@ def selectTests(args, sims, coverStr): variant=config, cmd=f"wsim --tb testbench_fp --sim {testfloatsim} {config} {test} > {sim_log}", grepstr="All Tests completed with 0 errors", - grepfile = sim_log) + grepfile = sim_log, + diffcommand=None, + simlog=sim_log) configs.append(tc) if (args.performance or args.nightly): # RUNNING THE EMBENCH TEST - json_dir_1 = f"{WALLY}/benchmarks/embench/wallySizeOpt_size.json" - json_dir_2 = f"{WALLY}/benchmarks/embench/wallySizeOpt_speed.json" - json_dir_3 = f"{WALLY}/benchmarks/embench/wallySpeedOpt_size.json" - json_dir_4 = f"{WALLY}/benchmarks/embench/wallySpeedOpt_speed.json" + wallySizeOpt_size_json = f"{WALLY}/benchmarks/embench/wallySizeOpt_size.json" + wallySizeOpt_speed_json = f"{WALLY}/benchmarks/embench/wallySizeOpt_speed.json" + wallySpeedOpt_size_json = f"{WALLY}/benchmarks/embench/wallySpeedOpt_size.json" + wallySpeedOpt_speed_json = f"{WALLY}/benchmarks/embench/wallySpeedOpt_speed.json" embench_test = TestCase( name="embench", @@ -524,51 +550,48 @@ def selectTests(args, sims, coverStr): cmd=( f"touch $WALLY/benchmarks/embench/run.log && (" f"cd $WALLY/benchmarks/embench && make run | tee run.log && " - f"grep -q 'size geometric mean.*1.04' {json_dir_1} && " - f"grep -q 'size geometric standard deviation.*1.26' {json_dir_1} && " - f"grep -q 'speed geometric mean.*1.07' {json_dir_2} && " - f"grep -q 'speed geometric standard deviation.*1.51' {json_dir_2} && " - f"grep -q 'size geometric mean.*1.21' {json_dir_3} && " - f"grep -q 'size geometric standard deviation.*1.28' {json_dir_3} && " - f"grep -q 'speed geometric mean.*1.15' {json_dir_4} && " - f"grep -q 'speed geometric standard deviation.*1.61' {json_dir_4}" + f"grep -q 'size geometric mean.*1.04' {wallySizeOpt_size_json} && " + f"grep -q 'size geometric standard deviation.*1.26' {wallySizeOpt_size_json} && " + f"grep -q 'speed geometric mean.*1.07' {wallySizeOpt_speed_json} && " + f"grep -q 'speed geometric standard deviation.*1.51' {wallySizeOpt_speed_json} && " + f"grep -q 'size geometric mean.*1.21' {wallySpeedOpt_size_json} && " + f"grep -q 'size geometric standard deviation.*1.28' {wallySpeedOpt_size_json} && " + f"grep -q 'speed geometric mean.*1.15' {wallySpeedOpt_speed_json} && " + f"grep -q 'speed geometric standard deviation.*1.61' {wallySpeedOpt_speed_json}" f") && echo 'EMBENCH_TEST_PASSED' >> $WALLY/benchmarks/embench/run.log " f"|| (echo 'EMBENCH_TEST_FAILED: Values did not match expected metrics' >> $WALLY/benchmarks/embench/run.log && exit 1)" ), - grepstr="EMBENCH_TEST_PASSED", # not sure what keyword to put here --> could also put success which comes from the simulation - grepfile=os.path.expandvars("$WALLY/benchmarks/embench/run.log") + grepstr="EMBENCH_TEST_PASSED", # make sure this matches the grep string in the command + grepfile=os.path.expandvars("$WALLY/benchmarks/embench/run.log"), + diffcommand=None, + simlog=os.path.expandvars("$WALLY/benchmarks/embench/run.log") ) configs.append(embench_test) # RUNNING THE COREMARK TEST - validation_log = f"{WALLY}/bin/logs/validation.log" - os.makedirs(os.path.dirname(validation_log), exist_ok=True) + sim_log = f"{regressionDir}/{defaultsim}/logs/validation.log" + # Create the directory if it doesn't exist + os.makedirs(os.path.dirname(sim_log), exist_ok=True) + + # Clear the file contents for a fresh start + with open(sim_log, 'w') as f: + f.write('') # clears the file coremark_sweep_test_dir = f"{WALLY}/benchmarks/coremark/coremark_sweep.py" - actual_coremark_values_csv = f"{WALLY}/benchmarks/coremark/coremark_results.csv" expected_coremark_values_csv = f"{WALLY}/benchmarks/coremark/expected_coremark_results.csv" - - performance_test = TestCase( - name="validate_performance", - variant="performance check", - cmd=( - "set -e && " - f"touch {validation_log} && " - f"python3 {coremark_sweep_test_dir} && " - f"if diff -q {actual_coremark_values_csv} {expected_coremark_values_csv}; then " - f" echo 'Coremark Validation Tests completed with 0 errors' | tee {validation_log}; " - f"else " - f" echo 'ERROR: CSV files differ' | tee {validation_log}; " - f" exit 1; " - f"fi" - ), - grepstr="Validation Tests completed with 0 errors", # adjust if message differs - grepfile=validation_log + coremark_test = TestCase( + name="validate_coremark_sweep", + variant="coremark check", + cmd=(f"python3 {coremark_sweep_test_dir}"), + grepstr=None, + grepfile=None, + diffcommand=f"diff -q {actual_coremark_values_csv} {expected_coremark_values_csv}", + simlog=sim_log ) - configs.append(performance_test) + configs.append(coremark_test) return configs From 82ccb0c0ae8352a495fb302e766c1a7ce7995a36 Mon Sep 17 00:00:00 2001 From: SadhviNarayanan Date: Mon, 28 Apr 2025 02:08:18 -0700 Subject: [PATCH 10/43] updated the script --- bin/regression-wally | 1 + 1 file changed, 1 insertion(+) diff --git a/bin/regression-wally b/bin/regression-wally index 370eaa142..d8af9ffaa 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -5,6 +5,7 @@ # David_Harris@Hmc.edu 25 January 2021 # Modified by Jarred Allen and many others # jcarlin@hmc.edu December 2024 +# sanarayanan@hmc.edu April 2025 # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 # # Run a regression with multiple configurations in parallel and exit with From 381bb34879093b80fcad5bff4e737b6697d0dff8 Mon Sep 17 00:00:00 2001 From: SadhviNarayanan Date: Mon, 28 Apr 2025 02:10:08 -0700 Subject: [PATCH 11/43] removed external script --- bin/validate_performance.py | 154 ------------------------------------ 1 file changed, 154 deletions(-) delete mode 100755 bin/validate_performance.py diff --git a/bin/validate_performance.py b/bin/validate_performance.py deleted file mode 100755 index 4ce6a21e0..000000000 --- a/bin/validate_performance.py +++ /dev/null @@ -1,154 +0,0 @@ -#!/usr/bin/env python3 -import csv -import json -import os - -# global variables -WALLY = os.environ.get('WALLY') -coremarkDir = f'{WALLY}/benchmarks/coremark/coremark_results.csv' -coremarkDir_expected = f'{WALLY}/benchmarks/coremark/expected_coremark_results.csv' -embenchDir = f'{WALLY}/benchmarks/embench' - -# NOTE: This script is not used in this branch's implementation, however it is kept here for reference - -def create_expected_results_json(): - # Create a dictionary to hold the expected results - validation_data = { - "coremark": { - "coremark/mhz": 3.38 - }, - "embench_rv32imc": { - "wallySizeOpt_size": { - "size geometric mean": 1.04, - "size geometric standard deviation": 1.26 - }, - "wallySizeOpt_speed": { - "size geometric mean": 1.07, - "size geometric standard deviation": 1.51 - }, - "wallySpeedOpt_size": { - "size geometric mean": 1.21, - "size geometric standard deviation": 1.28 - }, - "wallySpeedOpt_speed": { - "size geometric mean": 1.15, - "size geometric standard deviation": 1.61 - } - } - } - - # Write the data to a JSON file - with open('expected_results.json', 'w') as json_file: - json.dump(validation_data, json_file, indent=4) # Use validation_data instead of 'data' - -def validate_results(): - # EMBENCH VALIDATION - failing_value = "" - # Create a list to keep track of all the csv files generated by embench - embench_csv_files = ["wallySizeOpt_size", "wallySizeOpt_speed", "wallySpeedOpt_size", "wallySpeedOpt_speed"] - - for json_file in embench_csv_files: - directory = f"{embenchDir}/{json_file}.json" - # Open and read the JSON file - with open(directory) as file: - embench_log_csv_data = json.load(file) - - # Extract whether the file is a speed or size test (based on the filename) - type_speed_sound = json_file.split("_")[1] - - # Create the keys for the JSON data - level1 = f"{type_speed_sound} results" - key_level2_mean = f"{type_speed_sound} geometric mean" - key_level2_std_dev = f"{type_speed_sound} geometric standard deviation" - - # Extract the actual size geometric mean and std. dev. from the JSON data - actual_size_geometric_mean = embench_log_csv_data[level1][key_level2_mean] - actual_size_geometric_std_dev = embench_log_csv_data[level1][key_level2_std_dev] - - # Load the expected results from the expected_results.json file - expected_results_path = f"{WALLY}/bin/expected_results.json" - with open(expected_results_path) as file: - expected_data = json.load(file) - - # Extract geometric means from the expected results for comparison - expected_wally_geometric_mean = expected_data['embench_rv32imc'][json_file]['size geometric mean'] - expected_wally_geometric_std_dev = expected_data['embench_rv32imc'][json_file]['size geometric standard deviation'] - - # Compare the actual and expected results - if (actual_size_geometric_mean != expected_wally_geometric_mean): - failing_value += f"embench {json_file}'s geometric mean of {actual_size_geometric_mean} does not match expected value of {expected_wally_geometric_mean}\n" - - # # Update expected results file if smaller / better results - # if actual_size_geometric_mean < expected_wally_geometric_mean: - # updated_expected_json = True - # expected_data['embench_rv32imc'][json_file]['size geometric mean'] = actual_size_geometric_mean - # print(f"Updated expected geometric mean for {json_file} to {actual_size_geometric_mean}") - - - if (actual_size_geometric_std_dev != expected_wally_geometric_std_dev): - failing_value += f"embench {json_file}'s geometric std. dev. of {actual_size_geometric_std_dev} does not match expected value of {expected_wally_geometric_std_dev}\n" - - # # Update expected results file if smaller / better results - # if actual_size_geometric_std_dev < expected_wally_geometric_std_dev: - # updated_expected_json = True - # expected_data['embench_rv32imc'][json_file]['size geometric standard deviation'] = actual_size_geometric_std_dev - # print(f"Updated expected std. dev. for {json_file} to {actual_size_geometric_std_dev}") - - # if (updated_expected_json): - # with open(expected_results_path, 'w') as f: - # json.dump(expected_data, f, indent=4) - - # # automatically push the expected_results.json file to github - # subprocess.run(["git", "add", expected_results_path]) - # subprocess.run(["git", "commit", "-m", "Update expected results with improved metrics"]) - # subprocess.run(["git", "push"]) - - # COREMARK VALIDATION - # coremark_run = {} - # with open(coremarkDir, newline='') as csvfile: - # reader = csv.DictReader(csvfile) - # for row in reader: - # arch = row["Architecture"] - # coremark_run[arch] = row - # Now you can directly index into it - # actual_CM_MHz = coremark_run["rv32im_zicsr_zba_zbb_zbs"]["CM / MHz"] - # expected_wally_CM_Mhz = expected_data['coremark']['coremark/mhz'] - # if (str(actual_CM_MHz) != str(expected_wally_CM_Mhz)): - # failure = True - # failing_value += f"coremark's actual CM/MHz of {actual_CM_MHz} does not match expected value of {expected_wally_CM_Mhz}\n" - - - # Read in the expected results from the expected_coremark_results.csv file, - # as well as the new one created by the test - actual_results = read_csv_as_sorted_list(coremarkDir) - expected_results = read_csv_as_sorted_list(coremarkDir_expected) - - # Compare the two CSV files - if actual_results != expected_results: - failing_value = "Coremark results do not match expected results.\n" - print(failing_value) - failing_value += f"Coremark results:\n{actual_results}\n" - failing_value += f"Expected results:\n{expected_results}\n" - exit(1) - - # Check if there were any failures - if (failing_value == ""): - print("Validation Tests completed with 0 errors") - else: - print(failing_value) - exit(1) - - -def read_csv_as_sorted_list(filename): - with open(filename, newline='') as f: - reader = csv.reader(f) - rows = list(reader) - rows.sort() # sort rows for consistent ordering - return rows - -def main(): - create_expected_results_json() # NOTE: need to uncomment this line to create the expected_results.json file - validate_results() - -if __name__ == "__main__": - main() From c700a9bb072a403b446b262a305fa957444b95ea Mon Sep 17 00:00:00 2001 From: SadhviNarayanan Date: Mon, 28 Apr 2025 12:08:18 -0700 Subject: [PATCH 12/43] updated the script to use external file for comparison, and condensed grep logic for embench --- .../embench}/expected_results.json | 11 ++- bin/regression-wally | 72 ++++++++++++------- 2 files changed, 49 insertions(+), 34 deletions(-) rename {bin => benchmarks/embench}/expected_results.json (61%) diff --git a/bin/expected_results.json b/benchmarks/embench/expected_results.json similarity index 61% rename from bin/expected_results.json rename to benchmarks/embench/expected_results.json index 8ffd582a8..949f88acc 100644 --- a/bin/expected_results.json +++ b/benchmarks/embench/expected_results.json @@ -1,23 +1,20 @@ { - "coremark": { - "coremark/mhz": 3.38 - }, "embench_rv32imc": { "wallySizeOpt_size": { "size geometric mean": 1.04, "size geometric standard deviation": 1.26 }, "wallySizeOpt_speed": { - "size geometric mean": 1.07, - "size geometric standard deviation": 1.51 + "speed geometric mean": 1.07, + "speed geometric standard deviation": 1.51 }, "wallySpeedOpt_size": { "size geometric mean": 1.21, "size geometric standard deviation": 1.28 }, "wallySpeedOpt_speed": { - "size geometric mean": 1.15, - "size geometric standard deviation": 1.61 + "speed geometric mean": 1.15, + "speed geometric standard deviation": 1.61 } } } \ No newline at end of file diff --git a/bin/regression-wally b/bin/regression-wally index d8af9ffaa..b76d5685c 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -14,6 +14,7 @@ # ################################## import argparse +import json import multiprocessing import os import shutil @@ -279,7 +280,7 @@ lockstepwaivers = [ # Data Types & Functions ################################## -TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr', 'grepfile', 'diffcommand', 'simlog']) +TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr', 'grepfile', 'altcommand', 'simlog']) # name: the name of this test configuration (used in printing human-readable # output and picking logfile names) # cmd: the command to run to test (should include the logfile as '{}', and @@ -288,7 +289,7 @@ TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr', 'grepfil # grep finds that string in the logfile (is used by grep, so it may # be any pattern grep accepts, see `man 1 grep` for more info). # grepfile: a string containing the location of the file to be searched for output -# diffcommand: the command to run, if enabled, to check the output of the CoreMark benchmark +# altcommand: the command to run, if enabled, to check the output of the CoreMark benchmark # against the expected output. The command should write to the # validation log file. If None, no diff command is run. # simlog: the name of the logfile to be used for this test. @@ -321,7 +322,7 @@ def addTests(testList, sim, coverStr, configs): cmd=f"{cmdPrefix} {t} > {sim_log}", grepstr=gs, grepfile = grepfile, - diffcommand=None, + altcommand=None, simlog=sim_log) configs.append(tc) @@ -359,7 +360,7 @@ def addTestsByDir(testDir, config, sim, coverStr, configs, lockstepMode=0, breke cmd=f"{cmdPrefix} {fullfile} > {sim_log}", grepstr=gs, grepfile = sim_log, - diffcommand=None, + altcommand=None, simlog=sim_log) configs.append(tc) @@ -376,7 +377,7 @@ def search_log_for_text(text, grepfile): def run_test_case(config, dryrun: bool = False): grepfile = config.grepfile cmd = config.cmd - diffcommand = config.diffcommand + altcommand = config.altcommand if dryrun: print(f"Executing {cmd}", flush=True) return 0 @@ -386,9 +387,9 @@ def run_test_case(config, dryrun: bool = False): print(f"{bcolors.FAIL}{cmd}: Failed to execute{bcolors.ENDC}", flush=True) print(f" Check {grepfile} for more details.", flush=True) return 1 - elif diffcommand: + elif altcommand: sim_log = config.simlog - check_ret_code = os.system(diffcommand) + check_ret_code = os.system(altcommand) with open(sim_log, 'a') as f: if check_ret_code == 0: # Success message @@ -451,7 +452,7 @@ def process_args(args): elif args.branch: TIMEOUT_DUR = 120*60 # seconds elif args.nightly or args.performance: - TIMEOUT_DUR = 5*3600 # seconds + TIMEOUT_DUR = 60*60 # seconds else: TIMEOUT_DUR = 10*60 # seconds @@ -467,7 +468,7 @@ def selectTests(args, sims, coverStr): cmd=f"lint-wally {'--nightly' if args.nightly else ''} | tee {regressionDir}/verilator/logs/all_lints.log", grepstr="lints run with no errors or warnings", grepfile = f"{regressionDir}/verilator/logs/all_lints.log", - diffcommand=None, + altcommand=None, simlog=f"{regressionDir}/verilator/logs/all_lints.log"), ] @@ -534,38 +535,55 @@ def selectTests(args, sims, coverStr): cmd=f"wsim --tb testbench_fp --sim {testfloatsim} {config} {test} > {sim_log}", grepstr="All Tests completed with 0 errors", grepfile = sim_log, - diffcommand=None, + altcommand=None, simlog=sim_log) configs.append(tc) if (args.performance or args.nightly): # RUNNING THE EMBENCH TEST + embench_expected_json = f"{WALLY}/benchmarks/embench/expected_results.json" + with open(embench_expected_json) as f: + embench_expected = json.load(f) + + # As of now, we are only benchmarking rv32imc for embench performance + embench_expected_values = embench_expected["embench_rv32imc"] + + # Extracting the actual values from the JSON file wallySizeOpt_size_json = f"{WALLY}/benchmarks/embench/wallySizeOpt_size.json" wallySizeOpt_speed_json = f"{WALLY}/benchmarks/embench/wallySizeOpt_speed.json" wallySpeedOpt_size_json = f"{WALLY}/benchmarks/embench/wallySpeedOpt_size.json" wallySpeedOpt_speed_json = f"{WALLY}/benchmarks/embench/wallySpeedOpt_speed.json" + # Map file names to their expected values + file_to_expectations = { + wallySizeOpt_size_json: embench_expected_values["wallySizeOpt_size"], + wallySizeOpt_speed_json: embench_expected_values["wallySizeOpt_speed"], + wallySpeedOpt_size_json: embench_expected_values["wallySpeedOpt_size"], + wallySpeedOpt_speed_json: embench_expected_values["wallySpeedOpt_speed"] + } + + # Dynamically generate the grep commands - checks for geometric (mean|std. dev.) + grep_commands = [] + for filepath, checks in file_to_expectations.items(): + for key, expected_value in checks.items(): + grep_commands.append(f"grep -q '{key}.*{expected_value}' {filepath}") + + # Join all grep commands with "&&" so that all need to pass + grep_cmds_combined = " && ".join(grep_commands) + embench_test = TestCase( name="embench", - variant="rv32gc", # is this the correct variant here? or rv32imac_zicsr + variant="rv32gc", cmd=( - f"touch $WALLY/benchmarks/embench/run.log && (" - f"cd $WALLY/benchmarks/embench && make run | tee run.log && " - f"grep -q 'size geometric mean.*1.04' {wallySizeOpt_size_json} && " - f"grep -q 'size geometric standard deviation.*1.26' {wallySizeOpt_size_json} && " - f"grep -q 'speed geometric mean.*1.07' {wallySizeOpt_speed_json} && " - f"grep -q 'speed geometric standard deviation.*1.51' {wallySizeOpt_speed_json} && " - f"grep -q 'size geometric mean.*1.21' {wallySpeedOpt_size_json} && " - f"grep -q 'size geometric standard deviation.*1.28' {wallySpeedOpt_size_json} && " - f"grep -q 'speed geometric mean.*1.15' {wallySpeedOpt_speed_json} && " - f"grep -q 'speed geometric standard deviation.*1.61' {wallySpeedOpt_speed_json}" - f") && echo 'EMBENCH_TEST_PASSED' >> $WALLY/benchmarks/embench/run.log " - f"|| (echo 'EMBENCH_TEST_FAILED: Values did not match expected metrics' >> $WALLY/benchmarks/embench/run.log && exit 1)" - ), - + f"touch $WALLY/benchmarks/embench/run.log && (" + f"cd $WALLY/benchmarks/embench && make run | tee run.log && " + f"{grep_cmds_combined}" + f") && echo 'EMBENCH_TEST_PASSED' >> $WALLY/benchmarks/embench/run.log " + f"|| (echo 'EMBENCH_TEST_FAILED: Values did not match expected metrics' >> $WALLY/benchmarks/embench/run.log && exit 1)" + ), grepstr="EMBENCH_TEST_PASSED", # make sure this matches the grep string in the command grepfile=os.path.expandvars("$WALLY/benchmarks/embench/run.log"), - diffcommand=None, + altcommand=None, simlog=os.path.expandvars("$WALLY/benchmarks/embench/run.log") ) configs.append(embench_test) @@ -588,7 +606,7 @@ def selectTests(args, sims, coverStr): cmd=(f"python3 {coremark_sweep_test_dir}"), grepstr=None, grepfile=None, - diffcommand=f"diff -q {actual_coremark_values_csv} {expected_coremark_values_csv}", + altcommand=f"diff -q {actual_coremark_values_csv} {expected_coremark_values_csv}", simlog=sim_log ) From 3f69cffdf8688ae8372f0cd96e840f96fac589ca Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 29 Apr 2025 14:54:34 -0500 Subject: [PATCH 13/43] Getting close to making this hptw ifu cache interaction test work. --- tests/coverage/ebuIcacheDTLBMiss.S | 260 +++++++++++++++++++++++++++++ 1 file changed, 260 insertions(+) create mode 100644 tests/coverage/ebuIcacheDTLBMiss.S diff --git a/tests/coverage/ebuIcacheDTLBMiss.S b/tests/coverage/ebuIcacheDTLBMiss.S new file mode 100644 index 000000000..3c7e7a352 --- /dev/null +++ b/tests/coverage/ebuIcacheDTLBMiss.S @@ -0,0 +1,260 @@ +/////////////////////////////////////////// +// ebu.S +// +// Written: David_Harris@hmc.edu 21 January 2024 +// +// Purpose: Test coverage for EBU +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate + +#include "WALLY-init-lib.h" + +# run-elf.bash find this in project description +main: + li t5, 0x1 + slli t5, t5, 62 + ori t5, t5, 0xF0 + csrs menvcfg, t5 # menvcfg.PBMTE = 1, CBZE, CBCFE, CBIE all 1 + + # Page table root address at 0x80010000; SV39 + li t5, 0x9000000000080010 + csrw satp, t5 + + # sfence.vma x0, x0 + + # switch to supervisor mode + li a0, 1 + ecall + + # + +# Tricky case to cover. I$ miss concurrent with DTLB miss. HPTW has to hit the first +# access in the cache and miss a later one. Trigger this by doing a load that touches +# a page not in the DTLB but where the top-level PTE is already there. Has to happen +# near the end of the 16-instruction I$ line. +# +# Condition Coverage for instance /core/ebu/ebu/ebufsmarb -- +# +# File ../src/ebu/ebufsmarb.sv +#----------------Focused Condition View------------------- +#Line 72 Item 1 ((HREADY & FinalBeatD) & (LSUReq ~& IFUReq)) +#Condition totals: 2 of 4 input terms covered = 50.00% +# +# Input Term Covered Reason for no coverage Hint +# ----------- -------- ----------------------- -------------- +# HREADY Y +# FinalBeatD Y +# LSUReq N '_1' not hit Hit '_1' +# IFUReq N No hits Hit '_0' and '_1' +# +# Rows: Hits FEC Target Non-masking condition(s) +# --------- --------- -------------------- ------------------------- +# Row 1: 2 HREADY_0 ((LSUReq ~& IFUReq) && FinalBeatD) +# Row 2: 14 HREADY_1 ((LSUReq ~& IFUReq) && FinalBeatD) +# Row 3: 1 FinalBeatD_0 ((LSUReq ~& IFUReq) && HREADY) +# Row 4: 14 FinalBeatD_1 ((LSUReq ~& IFUReq) && HREADY) +# Row 5: 14 LSUReq_0 ((HREADY & FinalBeatD) && IFUReq) +# Row 6: ***0*** LSUReq_1 ((HREADY & FinalBeatD) && IFUReq) +# Row 7: ***0*** IFUReq_0 ((HREADY & FinalBeatD) && LSUReq) +# Row 8: ***0*** IFUReq_1 ((HREADY & FinalBeatD) && LSUReq) + + + li a0, 0x80000000 + li a1, 0x81000000 + j label1 + +.align 6 # start on multiple of 64 bytes / 16 instruction cache line +label1: + addi t2, t3, 0x100 # occupy part of cache line + sfence.vma # flush tlb + lw t0, 0x234(a0) # load to get an entry in the DTLB accessing top-level PTE + addi t2, t3, 0x103 # occupy part of cache line + addi t2, t3, 0x104 # occupy part of cache line + addi t2, t3, 0x105 # occupy part of cache line + addi t2, t3, 0x106 # occupy part of cache line + addi t2, t3, 0x107 # occupy part of cache line + addi t2, t3, 0x108 # occupy part of cache line + addi t2, t3, 0x109 # occupy part of cache line + addi t2, t3, 0x10A # occupy part of cache line + lw t0, 0x234(a1) # trigger DTLB miss + addi t2, t3, 0x10C # occupy part of cache line + addi t2, t3, 0x10D # occupy part of cache line + addi t2, t3, 0x10E # occupy part of cache line + addi t2, t3, 0x10F # occupy part of cache line + + + # wrap up + li a0, 3 # switch back to machine mode because code at 0x80000000 may not have clean page table entry + ecall + j done + + + +.data + +.align 16 +# root Page table situated at 0x80010000 +pagetable: + .8byte 0x20004401 # 0x00000000-0x80_00000000: PTE at 0x80011000 01 valid + .8byte 0x000000000000100F # misaligned terapage at 0x80_00000000 + +# next page table at 0x80011000 +.align 12 + .8byte 0x000000000000100F # misaligned gigapage at 0x00000000 + .8byte 0x0000000020005801 # PTE for pages at 0x40000000 + .8byte 0x0000000020004801 # + + +# Next page table at 0x80012000 for gigapage at 0x80000000 +.align 12 + .8byte 0x00000000200000CF # megapage + .8byte 0x0000000020014C0F # for VA starting at 80200000 (misaligned megapage) + .8byte 0x0000000020005001 # for VA starting at 80400000 (bad PBMT pages) + .8byte 0x4000000020004C01 # for VA starting at 80600000 (bad entry: nonleaf PTE can't have PBMT != 0) + .8byte 0x0000000020005401 # for VA starting at 80800000 (testing rwx permissiosn with cbom/cboz) + .8byte 0x00000000200000CF # megapage + .8byte 0x00000000200000CF # megapage + .8byte 0x00000000200000CF # megapage + .8byte 0x00000000200000CF # megapage + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + +# Leaf page table at 0x80013000 with NAPOT pages +.align 12 + #80000000 + .8byte 0xA0000000200020CF + .8byte 0xA0000000200020CF + .8byte 0xA0000000200020CF + .8byte 0xA0000000200020CF + + .8byte 0xA0000000200020CF + .8byte 0xA0000000200020CF + .8byte 0xA0000000200020CF + .8byte 0xA0000000200020CF + + .8byte 0xA0000000200020CF + .8byte 0xA0000000200020CF + .8byte 0xA0000000200020CF + .8byte 0xA0000000200020CF + + .8byte 0xA0000000200020CF + .8byte 0xA0000000200020CF + .8byte 0xA0000000200020CF + .8byte 0xA0000000200020CF + + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + + .8byte 0x800000002000E0CF + .8byte 0x800000002000E0CF + .8byte 0x800000002000E0CF + .8byte 0x800000002000E0CF + + .8byte 0x800000002000E0CF + .8byte 0x800000002000E0CF + +# Leaf page table at 0x80014000 with PBMT pages +.align 12 + #80400000 + .8byte 0x60000000200020CF # reserved entry + +# Leaf page table at 0x80015000 with various permissions for testing CBOM and CBOZ +.align 12 + #80800000 + .8byte 0x00000000200000CF # valid rwx for VA 80800000 + .8byte 0x00000000200000CB # valid r x for VA 80801000 + .8byte 0x00000000200000C3 # valid r for VA 80802000 + .8byte 0x00000000200000C9 # valid x for VA 80803000 + .8byte 0x00000000200000CD # valid wx for VA 80804000 (illegal combination, but used to test tlbcontrol) + .8byte 0x000000002000000F # valid rwx for VA 80805000 for covering ITLB translate and UpdateDA + .8byte 0x20000000200000CF # PBMT=1 for VA 80806000 for covering ITLB BadPBMT + +# Leaf page table at 0x80016000 with NAPOT pages +.align 12 + .8byte 0xA0000000200020CF + .8byte 0xA0000000200020CF + .8byte 0xA0000000200020CF + .8byte 0xA0000000200020CF From 5437606914f7f308b8981439ce992dcc18dc034a Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 30 Apr 2025 20:01:13 -0700 Subject: [PATCH 14/43] Cleanup setup scripts and ensure they don't kill your shell --- setup.sh | 23 +++++++++++++-------- site-setup.sh | 55 ++++++++++++++++++++++++++------------------------- 2 files changed, 43 insertions(+), 35 deletions(-) diff --git a/setup.sh b/setup.sh index 873d436eb..d14f11b08 100644 --- a/setup.sh +++ b/setup.sh @@ -2,6 +2,7 @@ # setup.sh # David_Harris@hmc.edu and kekim@hmc.edu 1 December 2021 +# jcarlin@hmc.edu 2025 # Set up tools for cvw # optionally have .bashrc or .bash_profile source this file with @@ -11,6 +12,11 @@ # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# Colors for terminal output +WARNING_COLOR='\033[93m' +FAIL_COLOR='\033[91m' +ENDC='\033[0m' # Reset to default color + echo "Executing Wally setup.sh" # Path to RISC-V Tools @@ -21,14 +27,15 @@ elif [ -d ~/riscv ]; then else # set the $RISCV directory here and remove the subsequent two lines # export RISCV= - echo "\$RISCV directory not found. Checked /opt/riscv and ~/riscv. Edit setup.sh to point to your custom \$RISCV directory." - exit 1 + echo -e "${FAIL_COLOR}\$RISCV directory not found. Checked /opt/riscv and ~/riscv. Edit setup.sh to point to your custom \$RISCV directory.${ENDC}" + return 1 fi echo \$RISCV set to "${RISCV}" # Path to Wally repository WALLY=$(dirname "${BASH_SOURCE[0]:-$0}") -export WALLY=$(cd "$WALLY" && pwd) +WALLY=$(cd "$WALLY" && pwd) +export WALLY echo \$WALLY set to "${WALLY}" # utility functions in Wally repository export PATH=$WALLY/bin:$PATH @@ -37,7 +44,7 @@ export PATH=$WALLY/bin:$PATH if [ -e "${WALLY}"/addins/cvw-arch-verif/setup.sh ]; then source "${WALLY}"/addins/cvw-arch-verif/setup.sh else - echo "setup.sh not found in \$WALLY/addins/cvw-arch-verif directory. Make sure you cloned the submodules." + echo -e "${WARNING_COLOR}setup.sh not found in \$WALLY/addins/cvw-arch-verif directory. Make sure you cloned the submodules.${ENDC}" fi # Verilator needs a larger core file size to simulate CORE-V Wally @@ -47,15 +54,15 @@ ulimit -c 300000 if [ -e "${RISCV}"/site-setup.sh ]; then source "${RISCV}"/site-setup.sh else - echo "site-setup.sh not found in \$RISCV directory. Rerun wally-toolchain-install.sh to automatically download it." - exit 1 + echo -e "${ERROR_COLOR}site-setup.sh not found in \$RISCV directory. Rerun wally-toolchain-install.sh to automatically download it.${ENDC}" + return 1 fi if [ ! -e "${WALLY}/.git/hooks/pre-commit" ]; then - pushd "${WALLY}" || exit 1 + pushd "${WALLY}" || return 1 echo "Installing pre-commit hooks" pre-commit install - popd || exit + popd || return fi echo "setup done" diff --git a/site-setup.sh b/site-setup.sh index 8bcd3d96e..32c1913f7 100755 --- a/site-setup.sh +++ b/site-setup.sh @@ -2,20 +2,27 @@ # site-setup.sh # David_Harris@hmc.edu and kekim@hmc.edu 1 December 2021 +# jcarlin@hmc.edu 2025 # System Admin should install this into $RISCV/site-setup.sh -# $RISCV is typically /opt/riscv +# It is automatically placed in the $RISCV directory by wally-toolchain-install.sh +# $RISCV is typically /opt/riscv or ~/riscv # System Admin must update the licenses and paths for localization. # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# Colors for terminal output +FAIL_COLOR='\033[91m' +ENDC='\033[0m' # Reset to default color + # license servers and commercial CAD tool paths # Must edit these based on your local environment. export MGLS_LICENSE_FILE=27002@zircon.eng.hmc.edu # Change this to your Siemens license server for Questa export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server export IMPERASD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Imperas license server -export QUESTA_HOME=/cad/mentor/questa_sim-2023.4/questasim # Change this for your path to Questa, excluding bin +export BREKER_LICENSE_FILE=1819@zircon.eng.hmc.edu # Change this to your Breker license server +export QUESTA_HOME=/cad/mentor/QUESTA # Change this for your path to Questa, excluding bin export DC_HOME=/cad/synopsys/SYN # Change this for your path to Synopsys DC, excluding bin -export VCS_HOME=/cad/synopsys/vcs/U-2023.03-SP2-4 # Change this for your path to Synopsys VCS, excluding bin -export BREKER_HOME=/cad/breker/trek5-2.1.11-GCC6_el7 # Change this for your path to Breker Trek +export VCS_HOME=/cad/synopsys/VCS # Change this for your path to Synopsys VCS, excluding bin +export BREKER_HOME=/cad/breker/TREK # Change this for your path to Breker Trek # Tools # Questa and Synopsys @@ -31,10 +38,6 @@ export SYN_MW=/home/jstine/MW export SYN_memory=/home/jstine/WallyMem/rv64gc/ #export osumemory=/import/yukari1/pdk/TSMC/WallyMem/rv64gc/ -# Environmental variables for CTG (https://github.com/riscv-software-src/riscv-ctg) -export RISCVCTG=/home/harris/repos/riscv-ctg - - # GCC if [ -z "$LD_LIBRARY_PATH" ]; then export LD_LIBRARY_PATH=$RISCV/riscv64-unknown-elf/lib @@ -50,36 +53,34 @@ export PATH=$PATH:$RISCV/bin if [ -e "$RISCV"/riscv-python/bin/activate ]; then source "$RISCV"/riscv-python/bin/activate else - echo "Python virtual environment not found. Rerun wally-toolchain-install.sh to automatically create it." - exit 1 + echo -e "${FAIL_COLOR}Python virtual environment not found. Rerun wally-toolchain-install.sh to automatically create it.${ENDC}" + return 1 fi # Environment variables needed for RISCV-DV -export RISCV_GCC=$(which riscv64-unknown-elf-gcc) # Copy this as it is -export RISCV_OBJCOPY=$(which riscv64-unknown-elf-objcopy) # Copy this as it is -export SPIKE_PATH=$RISCV/bin # Copy this as it is - -# Imperas OVPsim; put this in if you are using it -#export PATH=$RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64:$PATH -#export LD_LIBRARY_PATH=$RISCV/imperas_riscv_tests/riscv-ovpsim-plus/bin/Linux64:$LD_LIBRARY_PATH +export RISCV_GCC=$(which riscv64-unknown-elf-gcc) +export RISCV_OBJCOPY=$(which riscv64-unknown-elf-objcopy) +export SPIKE_PATH=$RISCV/bin # Imperas DV setup -export IDV=$RISCV/ImperasDV-OpenHW -if [ -e "$IDV" ]; then - # echo "Imperas exists" - export IMPERAS_HOME=$IDV +export IMPERAS_HOME=$RISCV/ImperasDV-OpenHW +if [ -e "$IMPERAS_HOME" ]; then export IMPERAS_PERSONALITY=CPUMAN_DV_ASYNC - export ROOTDIR=~/ - source "${IMPERAS_HOME}"/bin/setup.sh - setupImperas "${IMPERAS_HOME}" - export PATH=$IDV/scripts/cvw:$PATH + source "${IMPERAS_HOME}"/bin/setup.sh &> /dev/null || { + echo -e "${FAIL_COLOR}ImperasDV setup failed${ENDC}" + return 1 + } + setupImperas "${IMPERAS_HOME}" &> /dev/null || { + echo -e "${FAIL_COLOR}setupImperas failed${ENDC}" + return 1 + } fi # Use newer gcc version for older distros if [ -e /opt/rh/gcc-toolset-13/enable ]; then source /opt/rh/gcc-toolset-13/enable # Red Hat Family -elif [ -e $RISCV/gcc-13 ]; then +elif [ -e "$RISCV"/gcc-13 ]; then export PATH=$RISCV/gcc-13/bin:$PATH # SUSE Family -elif [ -e $RISCV/gcc-10 ]; then +elif [ -e "$RISCV"/gcc-10 ]; then export PATH=$RISCV/gcc-10/bin:$PATH # Ubuntu 20.04 LTS fi From b7f0b706e7ce3fcd778577b01f51d528fbc35b9d Mon Sep 17 00:00:00 2001 From: SadhviNarayanan Date: Fri, 2 May 2025 03:22:56 -0700 Subject: [PATCH 15/43] updated the script with better logging --- bin/regression-wally | 52 ++++++++++++++++++++++++++++++++------------ 1 file changed, 38 insertions(+), 14 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index b76d5685c..0235c8f84 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -548,7 +548,7 @@ def selectTests(args, sims, coverStr): # As of now, we are only benchmarking rv32imc for embench performance embench_expected_values = embench_expected["embench_rv32imc"] - # Extracting the actual values from the JSON file + # Extracting the JSON file names embench stores the results in wallySizeOpt_size_json = f"{WALLY}/benchmarks/embench/wallySizeOpt_size.json" wallySizeOpt_speed_json = f"{WALLY}/benchmarks/embench/wallySizeOpt_speed.json" wallySpeedOpt_size_json = f"{WALLY}/benchmarks/embench/wallySpeedOpt_size.json" @@ -562,32 +562,56 @@ def selectTests(args, sims, coverStr): wallySpeedOpt_speed_json: embench_expected_values["wallySpeedOpt_speed"] } - # Dynamically generate the grep commands - checks for geometric (mean|std. dev.) + # Dynamically generate the grep commands + logfile_path = os.path.expandvars("$WALLY/benchmarks/embench/run.log") grep_commands = [] + grep_commands.append("mismatch_detected=0") # Initialize flag before the checks + # Iterate over the file_to_expectations to build the grep commands for filepath, checks in file_to_expectations.items(): for key, expected_value in checks.items(): - grep_commands.append(f"grep -q '{key}.*{expected_value}' {filepath}") + mismatch_message = f"MISMATCH: {key} != {expected_value} in {filepath}" + # If the mismatch is found, set mismatch_detected to 1 + grep_commands.append( + f"grep -q '{key}.*{expected_value}' {filepath} || " + f'{{ echo "{mismatch_message}" >> {logfile_path}; ' + f"mismatch_detected=1; }}" + ) - # Join all grep commands with "&&" so that all need to pass - grep_cmds_combined = " && ".join(grep_commands) + # Join all grep commands with newlines + grep_cmds_combined = "\n".join(grep_commands) + # Wrap in full shell block + full_check_block = f"{grep_cmds_combined}\n" + + # Final check: if mismatch_detected is 1, fail the test and log the failure message + final_check_block = ( + f"if [ $mismatch_detected -eq 1 ]; then\n" + f" echo 'EMBENCH_TEST_FAILED: Values did not match expected metrics' >> {logfile_path};\n" + f" exit 1;\n" + f"else\n" + f" echo 'EMBENCH_TEST_PASSED' >> {logfile_path};\n" + f"fi" + ) + + # Combine everything into the embench_test command embench_test = TestCase( name="embench", variant="rv32gc", cmd=( - f"touch $WALLY/benchmarks/embench/run.log && (" + f"touch {logfile_path} && " f"cd $WALLY/benchmarks/embench && make run | tee run.log && " - f"{grep_cmds_combined}" - f") && echo 'EMBENCH_TEST_PASSED' >> $WALLY/benchmarks/embench/run.log " - f"|| (echo 'EMBENCH_TEST_FAILED: Values did not match expected metrics' >> $WALLY/benchmarks/embench/run.log && exit 1)" + f"{full_check_block}\n" # Runs all grep checks + f"{final_check_block}" # Final check for mismatch_detected and the result ), - grepstr="EMBENCH_TEST_PASSED", # make sure this matches the grep string in the command - grepfile=os.path.expandvars("$WALLY/benchmarks/embench/run.log"), + grepstr="EMBENCH_TEST_PASSED", # Ensure this matches the success message + grepfile=logfile_path, altcommand=None, - simlog=os.path.expandvars("$WALLY/benchmarks/embench/run.log") - ) + simlog=logfile_path + ) + configs.append(embench_test) + # RUNNING THE COREMARK TEST sim_log = f"{regressionDir}/{defaultsim}/logs/validation.log" # Create the directory if it doesn't exist @@ -606,7 +630,7 @@ def selectTests(args, sims, coverStr): cmd=(f"python3 {coremark_sweep_test_dir}"), grepstr=None, grepfile=None, - altcommand=f"diff -q {actual_coremark_values_csv} {expected_coremark_values_csv}", + altcommand=f"diff -u {actual_coremark_values_csv} {expected_coremark_values_csv} >> {sim_log}", simlog=sim_log ) From 4370ee83ad230bd73e6d7478afd6b7bcf346ebd5 Mon Sep 17 00:00:00 2001 From: SadhviNarayanan Date: Sun, 4 May 2025 01:19:29 -0700 Subject: [PATCH 16/43] updated code for more modularity and simplicity --- .../expected_wallySizeOpt_size.json | 29 ++++ .../expected_wallySizeOpt_speed.json | 29 ++++ .../expected_wallySpeedOpt_size.json | 29 ++++ .../expected_wallySpeedOpt_speed.json | 29 ++++ bin/regression-wally | 135 +++++++----------- 5 files changed, 171 insertions(+), 80 deletions(-) create mode 100644 benchmarks/embench/expected_embench_results/expected_wallySizeOpt_size.json create mode 100644 benchmarks/embench/expected_embench_results/expected_wallySizeOpt_speed.json create mode 100644 benchmarks/embench/expected_embench_results/expected_wallySpeedOpt_size.json create mode 100644 benchmarks/embench/expected_embench_results/expected_wallySpeedOpt_speed.json diff --git a/benchmarks/embench/expected_embench_results/expected_wallySizeOpt_size.json b/benchmarks/embench/expected_embench_results/expected_wallySizeOpt_size.json new file mode 100644 index 000000000..4c80ab462 --- /dev/null +++ b/benchmarks/embench/expected_embench_results/expected_wallySizeOpt_size.json @@ -0,0 +1,29 @@ +{ "size results" : + { "detailed size results" : + { "aha-mont64" : 0.96, + "crc32" : 0.74, + "cubic" : 2.01, + "edn" : 1.09, + "huffbench" : 1.16, + "matmult-int" : 0.87, + "md5sum" : 1.00, + "minver" : 0.87, + "nbody" : 0.92, + "nettle-aes" : 1.26, + "nettle-sha256" : 1.62, + "nsichneu" : 1.42, + "picojpeg" : 1.14, + "primecount" : 0.73, + "qrduino" : 1.03, + "sglib-combined" : 1.01, + "slre" : 1.05, + "st" : 0.93, + "statemate" : 0.82, + "tarfind" : 0.95, + "ud" : 0.96, + "wikisort" : 0.94 + }, + "size geometric mean" : 1.04, + "size geometric standard deviation" : 1.26 + } +} diff --git a/benchmarks/embench/expected_embench_results/expected_wallySizeOpt_speed.json b/benchmarks/embench/expected_embench_results/expected_wallySizeOpt_speed.json new file mode 100644 index 000000000..f9a787973 --- /dev/null +++ b/benchmarks/embench/expected_embench_results/expected_wallySizeOpt_speed.json @@ -0,0 +1,29 @@ +{ "speed results" : + { "detailed speed results" : + { "aha-mont64" : 0.81, + "crc32" : 1.00, + "cubic" : 0.42, + "edn" : 0.88, + "huffbench" : 1.38, + "matmult-int" : 1.11, + "md5sum" : 2.00, + "minver" : 0.63, + "nbody" : 0.67, + "nettle-aes" : 0.82, + "nettle-sha256" : 0.96, + "nsichneu" : 1.14, + "picojpeg" : 0.79, + "primecount" : 1.30, + "qrduino" : 1.22, + "sglib-combined" : 1.17, + "slre" : 1.25, + "st" : 0.84, + "statemate" : 2.15, + "tarfind" : 2.42, + "ud" : 0.88, + "wikisort" : 1.71 + }, + "speed geometric mean" : 1.07, + "speed geometric standard deviation" : 1.51 + } +} diff --git a/benchmarks/embench/expected_embench_results/expected_wallySpeedOpt_size.json b/benchmarks/embench/expected_embench_results/expected_wallySpeedOpt_size.json new file mode 100644 index 000000000..00c54abd7 --- /dev/null +++ b/benchmarks/embench/expected_embench_results/expected_wallySpeedOpt_size.json @@ -0,0 +1,29 @@ +{ "size results" : + { "detailed size results" : + { "aha-mont64" : 1.50, + "crc32" : 0.70, + "cubic" : 2.04, + "edn" : 1.10, + "huffbench" : 1.27, + "matmult-int" : 1.15, + "md5sum" : 1.18, + "minver" : 1.10, + "nbody" : 1.12, + "nettle-aes" : 1.37, + "nettle-sha256" : 1.71, + "nsichneu" : 1.51, + "picojpeg" : 1.67, + "primecount" : 0.73, + "qrduino" : 1.43, + "sglib-combined" : 1.13, + "slre" : 1.28, + "st" : 1.29, + "statemate" : 0.87, + "tarfind" : 1.09, + "ud" : 1.14, + "wikisort" : 1.13 + }, + "size geometric mean" : 1.21, + "size geometric standard deviation" : 1.28 + } +} diff --git a/benchmarks/embench/expected_embench_results/expected_wallySpeedOpt_speed.json b/benchmarks/embench/expected_embench_results/expected_wallySpeedOpt_speed.json new file mode 100644 index 000000000..837d3ef2a --- /dev/null +++ b/benchmarks/embench/expected_embench_results/expected_wallySpeedOpt_speed.json @@ -0,0 +1,29 @@ +{ "speed results" : + { "detailed speed results" : + { "aha-mont64" : 0.84, + "crc32" : 1.05, + "cubic" : 0.42, + "edn" : 1.06, + "huffbench" : 1.58, + "matmult-int" : 1.11, + "md5sum" : 1.92, + "minver" : 0.65, + "nbody" : 0.67, + "nettle-aes" : 0.93, + "nettle-sha256" : 0.99, + "nsichneu" : 0.70, + "picojpeg" : 0.99, + "primecount" : 1.41, + "qrduino" : 1.32, + "sglib-combined" : 1.41, + "slre" : 1.54, + "st" : 0.86, + "statemate" : 3.13, + "tarfind" : 3.31, + "ud" : 0.94, + "wikisort" : 1.74 + }, + "speed geometric mean" : 1.15, + "speed geometric standard deviation" : 1.61 + } +} diff --git a/bin/regression-wally b/bin/regression-wally index 0235c8f84..98caa9c74 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -14,7 +14,6 @@ # ################################## import argparse -import json import multiprocessing import os import shutil @@ -280,7 +279,7 @@ lockstepwaivers = [ # Data Types & Functions ################################## -TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr', 'grepfile', 'altcommand', 'simlog']) +TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr', 'grepfile', 'simlog', 'altcommand'], defaults=[None]) # applies the None default to altcommand # name: the name of this test configuration (used in printing human-readable # output and picking logfile names) # cmd: the command to run to test (should include the logfile as '{}', and @@ -289,10 +288,9 @@ TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr', 'grepfil # grep finds that string in the logfile (is used by grep, so it may # be any pattern grep accepts, see `man 1 grep` for more info). # grepfile: a string containing the location of the file to be searched for output -# altcommand: the command to run, if enabled, to check the output of the CoreMark benchmark -# against the expected output. The command should write to the -# validation log file. If None, no diff command is run. # simlog: the name of the logfile to be used for this test. +# altcommand: the command, if enabled, performs a validation check other than grep +# on the log files. None by default, and if specified the command will be run class bcolors: HEADER = '\033[95m' OKBLUE = '\033[94m' @@ -322,7 +320,6 @@ def addTests(testList, sim, coverStr, configs): cmd=f"{cmdPrefix} {t} > {sim_log}", grepstr=gs, grepfile = grepfile, - altcommand=None, simlog=sim_log) configs.append(tc) @@ -360,7 +357,6 @@ def addTestsByDir(testDir, config, sim, coverStr, configs, lockstepMode=0, breke cmd=f"{cmdPrefix} {fullfile} > {sim_log}", grepstr=gs, grepfile = sim_log, - altcommand=None, simlog=sim_log) configs.append(tc) @@ -384,7 +380,7 @@ def run_test_case(config, dryrun: bool = False): else: ret_code = os.system(cmd) if ret_code != 0: - print(f"{bcolors.FAIL}{cmd}: Failed to execute{bcolors.ENDC}", flush=True) + print(f"{bcolors.FAIL}{cmd}: Execution failed{bcolors.ENDC}", flush=True) print(f" Check {grepfile} for more details.", flush=True) return 1 elif altcommand: @@ -394,12 +390,12 @@ def run_test_case(config, dryrun: bool = False): if check_ret_code == 0: # Success message print(f"{bcolors.OKGREEN}{cmd}: Success{bcolors.ENDC}", flush=True) - f.write("Coremark Validation Tests completed with 0 errors\n") # Write success message to the log + f.write("Validation Tests completed with 0 errors\n") # Write success message to the log return 0 else: # Failure message - print(f"{bcolors.FAIL}{cmd}: Failures detected in output: there is a difference in the coremark csv files. Check {sim_log}.{bcolors.ENDC}", flush=True) - f.write("ERROR: There is a difference in the coremark CSV files\n") # Write failure message to the log + print(f"{bcolors.FAIL}{cmd}: Failures detected in output. Check {sim_log}.{bcolors.ENDC}", flush=True) + f.write("ERROR: There is a difference detected in the output\n") # Write failure message to the log return 1 elif search_log_for_text(config.grepstr, grepfile): # Flush is needed to flush output to stdout when running in multiprocessing Pool @@ -422,7 +418,6 @@ def parse_args(): parser.add_argument("--branch", help="Run branch predictor accuracy tests", action="store_true") parser.add_argument("--breker", help="Run Breker tests", action="store_true") # Requires a license for the breker tool. See tests/breker/README.md for details parser.add_argument("--dryrun", help="Print commands invoked to console without running regression", action="store_true") - parser.add_argument("--performance", help="Check for performance changes or discrepancies in embench and coremark", action="store_true") return parser.parse_args() @@ -468,8 +463,7 @@ def selectTests(args, sims, coverStr): cmd=f"lint-wally {'--nightly' if args.nightly else ''} | tee {regressionDir}/verilator/logs/all_lints.log", grepstr="lints run with no errors or warnings", grepfile = f"{regressionDir}/verilator/logs/all_lints.log", - altcommand=None, - simlog=f"{regressionDir}/verilator/logs/all_lints.log"), + simlog=f"{regressionDir}/verilator/logs/all_lints.log") ] # run full buildroot boot simulation (slow) if buildroot flag is set. Start it early to overlap with other tests @@ -535,80 +529,65 @@ def selectTests(args, sims, coverStr): cmd=f"wsim --tb testbench_fp --sim {testfloatsim} {config} {test} > {sim_log}", grepstr="All Tests completed with 0 errors", grepfile = sim_log, - altcommand=None, simlog=sim_log) configs.append(tc) if (args.performance or args.nightly): # RUNNING THE EMBENCH TEST - embench_expected_json = f"{WALLY}/benchmarks/embench/expected_results.json" - with open(embench_expected_json) as f: - embench_expected = json.load(f) + actual_json_path_start = f"{WALLY}/benchmarks/embench/" + expected_json_path_start = f"{WALLY}/benchmarks/embench/expected_embench_results/" + file_name_order = ["wallySizeOpt_size.json", "wallySizeOpt_speed.json", "wallySpeedOpt_size.json", "wallySpeedOpt_speed.json"] + # These are the actual file paths names that embench generates + file_paths_actual = [f"{actual_json_path_start}{file_name}" for file_name in file_name_order] + # The expected file paths are the same as the actual ones, but with "expected_" in front + file_paths_expected = [f"{expected_json_path_start}expected_{file_name}" for file_name in file_name_order] - # As of now, we are only benchmarking rv32imc for embench performance - embench_expected_values = embench_expected["embench_rv32imc"] + embench_logfile_path = os.path.expandvars("$WALLY/benchmarks/embench/run.log") + diff_commands = [] + for expected, actual in zip(file_paths_expected, file_paths_actual): + diff_commands.append( + f'echo "\n==============================================" >> "{embench_logfile_path}"\n' + f'echo "Comparing {expected} and {actual}:" >> "{embench_logfile_path}"\n' + # Run diff + f'echo "\nDiff output:" >> "{embench_logfile_path}"\n' + f'diff -u "{actual}" "{expected}" >> "{embench_logfile_path}" 2>&1\n' + f'if [ $? -ne 0 ]; then\n' + f' echo "MISMATCH found for {expected} and {actual}" >> "{embench_logfile_path}"\n' + f' mismatch_detected=1;\n' + f'else\n' + f' echo "Files match." >> "{embench_logfile_path}"\n' + f'fi\n' + f'echo "==============================================" >> "{embench_logfile_path}"' + ) - # Extracting the JSON file names embench stores the results in - wallySizeOpt_size_json = f"{WALLY}/benchmarks/embench/wallySizeOpt_size.json" - wallySizeOpt_speed_json = f"{WALLY}/benchmarks/embench/wallySizeOpt_speed.json" - wallySpeedOpt_size_json = f"{WALLY}/benchmarks/embench/wallySpeedOpt_size.json" - wallySpeedOpt_speed_json = f"{WALLY}/benchmarks/embench/wallySpeedOpt_speed.json" + diff_cmds_combined = "\n".join(diff_commands) - # Map file names to their expected values - file_to_expectations = { - wallySizeOpt_size_json: embench_expected_values["wallySizeOpt_size"], - wallySizeOpt_speed_json: embench_expected_values["wallySizeOpt_speed"], - wallySpeedOpt_size_json: embench_expected_values["wallySpeedOpt_size"], - wallySpeedOpt_speed_json: embench_expected_values["wallySpeedOpt_speed"] - } - - # Dynamically generate the grep commands - logfile_path = os.path.expandvars("$WALLY/benchmarks/embench/run.log") - grep_commands = [] - grep_commands.append("mismatch_detected=0") # Initialize flag before the checks - # Iterate over the file_to_expectations to build the grep commands - for filepath, checks in file_to_expectations.items(): - for key, expected_value in checks.items(): - mismatch_message = f"MISMATCH: {key} != {expected_value} in {filepath}" - # If the mismatch is found, set mismatch_detected to 1 - grep_commands.append( - f"grep -q '{key}.*{expected_value}' {filepath} || " - f'{{ echo "{mismatch_message}" >> {logfile_path}; ' - f"mismatch_detected=1; }}" - ) - - # Join all grep commands with newlines - grep_cmds_combined = "\n".join(grep_commands) - - # Wrap in full shell block - full_check_block = f"{grep_cmds_combined}\n" - - # Final check: if mismatch_detected is 1, fail the test and log the failure message final_check_block = ( - f"if [ $mismatch_detected -eq 1 ]; then\n" - f" echo 'EMBENCH_TEST_FAILED: Values did not match expected metrics' >> {logfile_path};\n" - f" exit 1;\n" - f"else\n" - f" echo 'EMBENCH_TEST_PASSED' >> {logfile_path};\n" - f"fi" + f'if [ $mismatch_detected -eq 1 ]; then\n' + f' echo "EMBENCH_TEST_FAILED: Values did not match expected metrics" >> "{embench_logfile_path}";\n' + f' exit 1;\n' + f'else\n' + f' echo "EMBENCH_TEST_PASSED" >> "{embench_logfile_path}";\n' + f'fi' ) + full_shell_block = f"mismatch_detected=0\n{diff_cmds_combined}\n{final_check_block}" + # Combine everything into the embench_test command embench_test = TestCase( name="embench", variant="rv32gc", - cmd=( - f"touch {logfile_path} && " - f"cd $WALLY/benchmarks/embench && make run | tee run.log && " - f"{full_check_block}\n" # Runs all grep checks - f"{final_check_block}" # Final check for mismatch_detected and the result + cmd = ( + f"rm -f {embench_logfile_path} && " + f"touch {embench_logfile_path} && " + f"cd $WALLY/benchmarks/embench && " + f"make run >> {embench_logfile_path} 2>&1 && " + f"bash << 'EOF'\n{full_shell_block}\nEOF" ), - grepstr="EMBENCH_TEST_PASSED", # Ensure this matches the success message - grepfile=logfile_path, - altcommand=None, - simlog=logfile_path - ) - + grepstr="EMBENCH_TEST_PASSED", # Make sure this matches success message + grepfile=embench_logfile_path, + simlog=embench_logfile_path + ) configs.append(embench_test) @@ -617,21 +596,17 @@ def selectTests(args, sims, coverStr): # Create the directory if it doesn't exist os.makedirs(os.path.dirname(sim_log), exist_ok=True) - # Clear the file contents for a fresh start - with open(sim_log, 'w') as f: - f.write('') # clears the file - - coremark_sweep_test_dir = f"{WALLY}/benchmarks/coremark/coremark_sweep.py" + coremark_sweep_test_file = f"{WALLY}/benchmarks/coremark/coremark_sweep.py" actual_coremark_values_csv = f"{WALLY}/benchmarks/coremark/coremark_results.csv" expected_coremark_values_csv = f"{WALLY}/benchmarks/coremark/expected_coremark_results.csv" coremark_test = TestCase( name="validate_coremark_sweep", variant="coremark check", - cmd=(f"python3 {coremark_sweep_test_dir}"), + cmd=(f"python3 {coremark_sweep_test_file}"), grepstr=None, grepfile=None, - altcommand=f"diff -u {actual_coremark_values_csv} {expected_coremark_values_csv} >> {sim_log}", - simlog=sim_log + simlog=sim_log, + altcommand=f"diff -u {actual_coremark_values_csv} {expected_coremark_values_csv} >> {sim_log}" ) configs.append(coremark_test) From 60f4b909299af2565985b6771486ce31fb3decc2 Mon Sep 17 00:00:00 2001 From: SadhviNarayanan Date: Sun, 4 May 2025 01:21:35 -0700 Subject: [PATCH 17/43] updated code for more modularity and simplicity --- bin/regression-wally | 1 - 1 file changed, 1 deletion(-) diff --git a/bin/regression-wally b/bin/regression-wally index 1bbc2e9b9..4455008e2 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -607,7 +607,6 @@ def selectTests(args, sims, coverStr): simlog=sim_log, altcommand=f"diff -u {actual_coremark_values_csv} {expected_coremark_values_csv} >> {sim_log}" ) - configs.append(coremark_test) return configs From 29f86bb5cb33aff118ae977fc52975a2a8b09ea4 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Sun, 4 May 2025 12:20:18 -0500 Subject: [PATCH 18/43] Test forces the EBU to have a partially overlapping IFU and LSU request. The LSU request occurs duing an ongoing IFU request. --- tests/coverage/ebuIcacheDTLBMiss.S | 160 ++++++++++++++++++++++++++++- 1 file changed, 159 insertions(+), 1 deletion(-) diff --git a/tests/coverage/ebuIcacheDTLBMiss.S b/tests/coverage/ebuIcacheDTLBMiss.S index 3c7e7a352..2b5fc70f3 100644 --- a/tests/coverage/ebuIcacheDTLBMiss.S +++ b/tests/coverage/ebuIcacheDTLBMiss.S @@ -80,10 +80,80 @@ main: li a0, 0x80000000 li a1, 0x81000000 + la a2, pagetableL1Target + addi a2, a2, 0x40 # address of last level of the page table which needs to be removed from the data cache j label1 .align 6 # start on multiple of 64 bytes / 16 instruction cache line label1: + addi t2, t3, 0x100 # occupy part of cache line + sfence.vma # flush tlb + lw t0, 0x234(a0) # load to get an entry in the DTLB accessing top-level PTE + addi t2, t3, 0x103 # occupy part of cache line + addi t2, t3, 0x104 # occupy part of cache line + addi t2, t3, 0x105 # occupy part of cache line + addi t2, t3, 0x106 # occupy part of cache line + lw t0, 0x234(a1) # trigger DTLB miss + addi t2, t3, 0x107 # occupy part of cache line + addi t2, t3, 0x108 # occupy part of cache line + addi t2, t3, 0x109 # occupy part of cache line + addi t2, t3, 0x10A # occupy part of cache line + addi t2, t3, 0x10C # occupy part of cache line + addi t2, t3, 0x10D # occupy part of cache line + addi t2, t3, 0x10E # occupy part of cache line + cbo.inval (a2) + + addi t2, t3, 0x100 # occupy part of cache line + sfence.vma # flush tlb + lw t0, 0x234(a0) # load to get an entry in the DTLB accessing top-level PTE + addi t2, t3, 0x103 # occupy part of cache line + addi t2, t3, 0x104 # occupy part of cache line + addi t2, t3, 0x105 # occupy part of cache line + addi t2, t3, 0x106 # occupy part of cache line + addi t2, t3, 0x107 # occupy part of cache line + lw t0, 0x234(a1) # trigger DTLB miss + addi t2, t3, 0x108 # occupy part of cache line + addi t2, t3, 0x109 # occupy part of cache line + addi t2, t3, 0x10A # occupy part of cache line + addi t2, t3, 0x10C # occupy part of cache line + addi t2, t3, 0x10D # occupy part of cache line + addi t2, t3, 0x10E # occupy part of cache line + cbo.inval (a2) + + addi t2, t3, 0x100 # occupy part of cache line + sfence.vma # flush tlb + lw t0, 0x234(a0) # load to get an entry in the DTLB accessing top-level PTE + addi t2, t3, 0x103 # occupy part of cache line + addi t2, t3, 0x104 # occupy part of cache line + addi t2, t3, 0x105 # occupy part of cache line + addi t2, t3, 0x106 # occupy part of cache line + addi t2, t3, 0x107 # occupy part of cache line + addi t2, t3, 0x108 # occupy part of cache line + lw t0, 0x234(a1) # trigger DTLB miss + addi t2, t3, 0x109 # occupy part of cache line + addi t2, t3, 0x10A # occupy part of cache line + addi t2, t3, 0x10C # occupy part of cache line + addi t2, t3, 0x10D # occupy part of cache line + addi t2, t3, 0x10E # occupy part of cache line + cbo.inval (a2) + + addi t2, t3, 0x100 # occupy part of cache line + sfence.vma # flush tlb + lw t0, 0x234(a0) # load to get an entry in the DTLB accessing top-level PTE + addi t2, t3, 0x103 # occupy part of cache line + addi t2, t3, 0x104 # occupy part of cache line + addi t2, t3, 0x105 # occupy part of cache line + addi t2, t3, 0x106 # occupy part of cache line + addi t2, t3, 0x107 # occupy part of cache line + addi t2, t3, 0x108 # occupy part of cache line + addi t2, t3, 0x109 # occupy part of cache line + lw t0, 0x234(a1) # trigger DTLB miss + addi t2, t3, 0x10A # occupy part of cache line + addi t2, t3, 0x10C # occupy part of cache line + addi t2, t3, 0x10D # occupy part of cache line + addi t2, t3, 0x10E # occupy part of cache line + cbo.inval (a2) + addi t2, t3, 0x100 # occupy part of cache line sfence.vma # flush tlb lw t0, 0x234(a0) # load to get an entry in the DTLB accessing top-level PTE @@ -99,8 +169,95 @@ label1: addi t2, t3, 0x10C # occupy part of cache line addi t2, t3, 0x10D # occupy part of cache line addi t2, t3, 0x10E # occupy part of cache line - addi t2, t3, 0x10F # occupy part of cache line + cbo.inval (a2) + addi t2, t3, 0x100 # occupy part of cache line + sfence.vma # flush tlb + lw t0, 0x234(a0) # load to get an entry in the DTLB accessing top-level PTE + addi t2, t3, 0x103 # occupy part of cache line + addi t2, t3, 0x104 # occupy part of cache line + addi t2, t3, 0x105 # occupy part of cache line + addi t2, t3, 0x106 # occupy part of cache line + addi t2, t3, 0x107 # occupy part of cache line + addi t2, t3, 0x108 # occupy part of cache line + addi t2, t3, 0x109 # occupy part of cache line + addi t2, t3, 0x10A # occupy part of cache line + addi t2, t3, 0x10C # occupy part of cache line + lw t0, 0x234(a1) # trigger DTLB miss + addi t2, t3, 0x10D # occupy part of cache line + addi t2, t3, 0x10E # occupy part of cache line + cbo.inval (a2) + + addi t2, t3, 0x100 # occupy part of cache line + sfence.vma # flush tlb + lw t0, 0x234(a0) # load to get an entry in the DTLB accessing top-level PTE + addi t2, t3, 0x103 # occupy part of cache line + addi t2, t3, 0x104 # occupy part of cache line + addi t2, t3, 0x105 # occupy part of cache line + addi t2, t3, 0x106 # occupy part of cache line + addi t2, t3, 0x107 # occupy part of cache line + addi t2, t3, 0x108 # occupy part of cache line + addi t2, t3, 0x109 # occupy part of cache line + addi t2, t3, 0x10A # occupy part of cache line + addi t2, t3, 0x10C # occupy part of cache line + addi t2, t3, 0x10D # occupy part of cache line + lw t0, 0x234(a1) # trigger DTLB miss + addi t2, t3, 0x10E # occupy part of cache line + cbo.inval (a2) + + addi t2, t3, 0x100 # occupy part of cache line + sfence.vma # flush tlb + lw t0, 0x234(a0) # load to get an entry in the DTLB accessing top-level PTE + addi t2, t3, 0x103 # occupy part of cache line + addi t2, t3, 0x104 # occupy part of cache line + addi t2, t3, 0x105 # occupy part of cache line + addi t2, t3, 0x106 # occupy part of cache line + addi t2, t3, 0x107 # occupy part of cache line + addi t2, t3, 0x108 # occupy part of cache line + addi t2, t3, 0x109 # occupy part of cache line + addi t2, t3, 0x10A # occupy part of cache line + addi t2, t3, 0x10C # occupy part of cache line + addi t2, t3, 0x10D # occupy part of cache line + addi t2, t3, 0x10E # occupy part of cache line + lw t0, 0x234(a1) # trigger DTLB miss + cbo.inval (a2) + + addi t2, t3, 0x100 # occupy part of cache line + sfence.vma # flush tlb + lw t0, 0x234(a0) # load to get an entry in the DTLB accessing top-level PTE + addi t2, t3, 0x103 # occupy part of cache line + addi t2, t3, 0x104 # occupy part of cache line + addi t2, t3, 0x105 # occupy part of cache line + addi t2, t3, 0x106 # occupy part of cache line + addi t2, t3, 0x107 # occupy part of cache line + addi t2, t3, 0x108 # occupy part of cache line + addi t2, t3, 0x109 # occupy part of cache line + addi t2, t3, 0x10A # occupy part of cache line + addi t2, t3, 0x10C # occupy part of cache line + addi t2, t3, 0x10D # occupy part of cache line + addi t2, t3, 0x10E # occupy part of cache line + addi t2, t3, 0x10F # occupy part of cache line + lw t0, 0x234(a1) # trigger DTLB miss + cbo.inval (a2) + + addi t2, t3, 0x100 # occupy part of cache line + sfence.vma # flush tlb + lw t0, 0x234(a0) # load to get an entry in the DTLB accessing top-level PTE + addi t2, t3, 0x103 # occupy part of cache line + addi t2, t3, 0x104 # occupy part of cache line + addi t2, t3, 0x105 # occupy part of cache line + addi t2, t3, 0x106 # occupy part of cache line + addi t2, t3, 0x107 # occupy part of cache line + addi t2, t3, 0x108 # occupy part of cache line + addi t2, t3, 0x109 # occupy part of cache line + addi t2, t3, 0x10A # occupy part of cache line + addi t2, t3, 0x10C # occupy part of cache line + addi t2, t3, 0x10D # occupy part of cache line + addi t2, t3, 0x10E # occupy part of cache line + addi t2, t3, 0x10F # occupy part of cache line + addi t2, t3, 0x110 # occupy part of cache line + lw t0, 0x234(a1) # trigger DTLB miss + cbo.inval (a2) # wrap up li a0, 3 # switch back to machine mode because code at 0x80000000 may not have clean page table entry @@ -126,6 +283,7 @@ pagetable: # Next page table at 0x80012000 for gigapage at 0x80000000 .align 12 +pagetableL1Target: .8byte 0x00000000200000CF # megapage .8byte 0x0000000020014C0F # for VA starting at 80200000 (misaligned megapage) .8byte 0x0000000020005001 # for VA starting at 80400000 (bad PBMT pages) From bb0c6637071ae5ceb19ba95119e68e6894b4992c Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Sun, 4 May 2025 12:21:23 -0500 Subject: [PATCH 19/43] Added in David's testbench check for traps without a trap handler. Generates an error message and stops simulation. --- testbench/testbench.sv | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index ee2eb430d..1b8b74485 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -716,13 +716,15 @@ module testbench; always @(posedge clk) begin - // if (reset) PrevPCZero <= 0; - // else if (dut.core.InstrValidM) PrevPCZero <= (functionName.PCM == 0 & dut.core.ifu.InstrM == 0); TestComplete <= ((InstrM == 32'h6f) & dut.core.InstrValidM ) | ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"] & dut.core.lsu.IEUAdrM != 0) & InstrMName == "SW"); // | // (functionName.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.InstrValidM & PrevPCZero)); - // if (functionName.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.InstrValidM & PrevPCZero) - // $error("Program fetched illegal instruction 0x00000000 from address 0x00000000 twice in a row. Usually due to fault with no fault handler."); + if (reset) PrevPCZero <= 0; + else if (dut.core.InstrValidM) PrevPCZero <= (dut.core.PCM == 0 & dut.core.ifu.InstrM == 0); + if (dut.core.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.InstrValidM & PrevPCZero) begin + $error("Program fetched illegal instruction 0x00000000 from address 0x00000000 twice in a row. Usually due to fault with no fault handler."); + $fatal(1); + end end DCacheFlushFSM #(P) DCacheFlushFSM(.clk, .start(DCacheFlushStart), .done(DCacheFlushDone)); From cb3d3d9913c246aa7962824357628137b4f9ecb4 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Sun, 4 May 2025 12:24:34 -0500 Subject: [PATCH 20/43] Updated author. --- tests/coverage/ebuIcacheDTLBMiss.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/coverage/ebuIcacheDTLBMiss.S b/tests/coverage/ebuIcacheDTLBMiss.S index 2b5fc70f3..9c9288e4f 100644 --- a/tests/coverage/ebuIcacheDTLBMiss.S +++ b/tests/coverage/ebuIcacheDTLBMiss.S @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ebu.S // -// Written: David_Harris@hmc.edu 21 January 2024 +// Written: Rose Thompson rose@rosethompson.net 4/29/2025 // // Purpose: Test coverage for EBU // From d923d961c1a319b097ebc42655c3cc67acdd543d Mon Sep 17 00:00:00 2001 From: SadhviNarayanan Date: Sun, 4 May 2025 12:03:15 -0700 Subject: [PATCH 21/43] diff logic for embench - directory level --- benchmarks/embench/Makefile | 8 +- .../wallySizeOpt_size.json} | 0 .../wallySizeOpt_speed.json} | 0 .../wallySpeedOpt_size.json} | 0 .../wallySpeedOpt_speed.json} | 0 .../wallySizeOpt_size.json | 29 +++++++ .../wallySizeOpt_speed.json | 29 +++++++ .../wallySpeedOpt_size.json | 29 +++++++ .../wallySpeedOpt_speed.json | 29 +++++++ benchmarks/embench/expected_results.json | 20 ----- benchmarks/graphGen.py | 8 +- bin/regression-wally | 87 ++++++------------- 12 files changed, 150 insertions(+), 89 deletions(-) rename benchmarks/embench/{expected_embench_results/expected_wallySizeOpt_size.json => actual_embench_results/wallySizeOpt_size.json} (100%) rename benchmarks/embench/{expected_embench_results/expected_wallySizeOpt_speed.json => actual_embench_results/wallySizeOpt_speed.json} (100%) rename benchmarks/embench/{expected_embench_results/expected_wallySpeedOpt_size.json => actual_embench_results/wallySpeedOpt_size.json} (100%) rename benchmarks/embench/{expected_embench_results/expected_wallySpeedOpt_speed.json => actual_embench_results/wallySpeedOpt_speed.json} (100%) create mode 100644 benchmarks/embench/expected_embench_results/wallySizeOpt_size.json create mode 100644 benchmarks/embench/expected_embench_results/wallySizeOpt_speed.json create mode 100644 benchmarks/embench/expected_embench_results/wallySpeedOpt_size.json create mode 100644 benchmarks/embench/expected_embench_results/wallySpeedOpt_speed.json delete mode 100644 benchmarks/embench/expected_results.json diff --git a/benchmarks/embench/Makefile b/benchmarks/embench/Makefile index 0a52f79ae..00504d741 100644 --- a/benchmarks/embench/Makefile +++ b/benchmarks/embench/Makefile @@ -65,13 +65,13 @@ spike_run: # python wrapper to present results of embench size benchmark size: buildsize - $(embench_dir)/benchmark_size.py --builddir=bd_speedopt_size --json-output > wallySpeedOpt_size.json - $(embench_dir)/benchmark_size.py --builddir=bd_sizeopt_size --json-output > wallySizeOpt_size.json + $(embench_dir)/benchmark_size.py --builddir=bd_speedopt_size --json-output > actual_embench_results/wallySpeedOpt_size.json + $(embench_dir)/benchmark_size.py --builddir=bd_sizeopt_size --json-output > actual_embench_results/wallySizeOpt_size.json # python wrapper to present results of embench speed benchmark speed: - $(embench_dir)/benchmark_speed.py --builddir=bd_sizeopt_speed --target-module run_wally --cpu-mhz=1 --json-output > wallySizeOpt_speed.json - $(embench_dir)/benchmark_speed.py --builddir=bd_speedopt_speed --target-module run_wally --cpu-mhz=1 --json-output > wallySpeedOpt_speed.json + $(embench_dir)/benchmark_speed.py --builddir=bd_sizeopt_speed --target-module run_wally --cpu-mhz=1 --json-output > actual_embench_results/wallySizeOpt_speed.json + $(embench_dir)/benchmark_speed.py --builddir=bd_speedopt_speed --target-module run_wally --cpu-mhz=1 --json-output > actual_embench_results/wallySpeedOpt_speed.json # deletes all files clean: diff --git a/benchmarks/embench/expected_embench_results/expected_wallySizeOpt_size.json b/benchmarks/embench/actual_embench_results/wallySizeOpt_size.json similarity index 100% rename from benchmarks/embench/expected_embench_results/expected_wallySizeOpt_size.json rename to benchmarks/embench/actual_embench_results/wallySizeOpt_size.json diff --git a/benchmarks/embench/expected_embench_results/expected_wallySizeOpt_speed.json b/benchmarks/embench/actual_embench_results/wallySizeOpt_speed.json similarity index 100% rename from benchmarks/embench/expected_embench_results/expected_wallySizeOpt_speed.json rename to benchmarks/embench/actual_embench_results/wallySizeOpt_speed.json diff --git a/benchmarks/embench/expected_embench_results/expected_wallySpeedOpt_size.json b/benchmarks/embench/actual_embench_results/wallySpeedOpt_size.json similarity index 100% rename from benchmarks/embench/expected_embench_results/expected_wallySpeedOpt_size.json rename to benchmarks/embench/actual_embench_results/wallySpeedOpt_size.json diff --git a/benchmarks/embench/expected_embench_results/expected_wallySpeedOpt_speed.json b/benchmarks/embench/actual_embench_results/wallySpeedOpt_speed.json similarity index 100% rename from benchmarks/embench/expected_embench_results/expected_wallySpeedOpt_speed.json rename to benchmarks/embench/actual_embench_results/wallySpeedOpt_speed.json diff --git a/benchmarks/embench/expected_embench_results/wallySizeOpt_size.json b/benchmarks/embench/expected_embench_results/wallySizeOpt_size.json new file mode 100644 index 000000000..4c80ab462 --- /dev/null +++ b/benchmarks/embench/expected_embench_results/wallySizeOpt_size.json @@ -0,0 +1,29 @@ +{ "size results" : + { "detailed size results" : + { "aha-mont64" : 0.96, + "crc32" : 0.74, + "cubic" : 2.01, + "edn" : 1.09, + "huffbench" : 1.16, + "matmult-int" : 0.87, + "md5sum" : 1.00, + "minver" : 0.87, + "nbody" : 0.92, + "nettle-aes" : 1.26, + "nettle-sha256" : 1.62, + "nsichneu" : 1.42, + "picojpeg" : 1.14, + "primecount" : 0.73, + "qrduino" : 1.03, + "sglib-combined" : 1.01, + "slre" : 1.05, + "st" : 0.93, + "statemate" : 0.82, + "tarfind" : 0.95, + "ud" : 0.96, + "wikisort" : 0.94 + }, + "size geometric mean" : 1.04, + "size geometric standard deviation" : 1.26 + } +} diff --git a/benchmarks/embench/expected_embench_results/wallySizeOpt_speed.json b/benchmarks/embench/expected_embench_results/wallySizeOpt_speed.json new file mode 100644 index 000000000..f9a787973 --- /dev/null +++ b/benchmarks/embench/expected_embench_results/wallySizeOpt_speed.json @@ -0,0 +1,29 @@ +{ "speed results" : + { "detailed speed results" : + { "aha-mont64" : 0.81, + "crc32" : 1.00, + "cubic" : 0.42, + "edn" : 0.88, + "huffbench" : 1.38, + "matmult-int" : 1.11, + "md5sum" : 2.00, + "minver" : 0.63, + "nbody" : 0.67, + "nettle-aes" : 0.82, + "nettle-sha256" : 0.96, + "nsichneu" : 1.14, + "picojpeg" : 0.79, + "primecount" : 1.30, + "qrduino" : 1.22, + "sglib-combined" : 1.17, + "slre" : 1.25, + "st" : 0.84, + "statemate" : 2.15, + "tarfind" : 2.42, + "ud" : 0.88, + "wikisort" : 1.71 + }, + "speed geometric mean" : 1.07, + "speed geometric standard deviation" : 1.51 + } +} diff --git a/benchmarks/embench/expected_embench_results/wallySpeedOpt_size.json b/benchmarks/embench/expected_embench_results/wallySpeedOpt_size.json new file mode 100644 index 000000000..00c54abd7 --- /dev/null +++ b/benchmarks/embench/expected_embench_results/wallySpeedOpt_size.json @@ -0,0 +1,29 @@ +{ "size results" : + { "detailed size results" : + { "aha-mont64" : 1.50, + "crc32" : 0.70, + "cubic" : 2.04, + "edn" : 1.10, + "huffbench" : 1.27, + "matmult-int" : 1.15, + "md5sum" : 1.18, + "minver" : 1.10, + "nbody" : 1.12, + "nettle-aes" : 1.37, + "nettle-sha256" : 1.71, + "nsichneu" : 1.51, + "picojpeg" : 1.67, + "primecount" : 0.73, + "qrduino" : 1.43, + "sglib-combined" : 1.13, + "slre" : 1.28, + "st" : 1.29, + "statemate" : 0.87, + "tarfind" : 1.09, + "ud" : 1.14, + "wikisort" : 1.13 + }, + "size geometric mean" : 1.21, + "size geometric standard deviation" : 1.28 + } +} diff --git a/benchmarks/embench/expected_embench_results/wallySpeedOpt_speed.json b/benchmarks/embench/expected_embench_results/wallySpeedOpt_speed.json new file mode 100644 index 000000000..837d3ef2a --- /dev/null +++ b/benchmarks/embench/expected_embench_results/wallySpeedOpt_speed.json @@ -0,0 +1,29 @@ +{ "speed results" : + { "detailed speed results" : + { "aha-mont64" : 0.84, + "crc32" : 1.05, + "cubic" : 0.42, + "edn" : 1.06, + "huffbench" : 1.58, + "matmult-int" : 1.11, + "md5sum" : 1.92, + "minver" : 0.65, + "nbody" : 0.67, + "nettle-aes" : 0.93, + "nettle-sha256" : 0.99, + "nsichneu" : 0.70, + "picojpeg" : 0.99, + "primecount" : 1.41, + "qrduino" : 1.32, + "sglib-combined" : 1.41, + "slre" : 1.54, + "st" : 0.86, + "statemate" : 3.13, + "tarfind" : 3.31, + "ud" : 0.94, + "wikisort" : 1.74 + }, + "speed geometric mean" : 1.15, + "speed geometric standard deviation" : 1.61 + } +} diff --git a/benchmarks/embench/expected_results.json b/benchmarks/embench/expected_results.json deleted file mode 100644 index 949f88acc..000000000 --- a/benchmarks/embench/expected_results.json +++ /dev/null @@ -1,20 +0,0 @@ -{ - "embench_rv32imc": { - "wallySizeOpt_size": { - "size geometric mean": 1.04, - "size geometric standard deviation": 1.26 - }, - "wallySizeOpt_speed": { - "speed geometric mean": 1.07, - "speed geometric standard deviation": 1.51 - }, - "wallySpeedOpt_size": { - "size geometric mean": 1.21, - "size geometric standard deviation": 1.28 - }, - "wallySpeedOpt_speed": { - "speed geometric mean": 1.15, - "speed geometric standard deviation": 1.61 - } - } -} \ No newline at end of file diff --git a/benchmarks/graphGen.py b/benchmarks/graphGen.py index fd283190e..878bb8847 100755 --- a/benchmarks/graphGen.py +++ b/benchmarks/graphGen.py @@ -95,10 +95,10 @@ def main(): embenchSizeOpt_SizeData = {} embenchSpeedOpt_SizeData = {} coremarkData = loadCoremark(coremarkData) - embenchSpeedOpt_SpeedData = loadEmbench("embench/wallySpeedOpt_speed.json", embenchSpeedOpt_SpeedData) - embenchSizeOpt_SpeedData = loadEmbench("embench/wallySizeOpt_speed.json", embenchSizeOpt_SpeedData) - embenchSpeedOpt_SizeData = loadEmbench("embench/wallySpeedOpt_size.json", embenchSpeedOpt_SizeData) - embenchSizeOpt_SizeData = loadEmbench("embench/wallySizeOpt_size.json", embenchSizeOpt_SizeData) + embenchSpeedOpt_SpeedData = loadEmbench("embench/actual_embench_results/wallySpeedOpt_speed.json", embenchSpeedOpt_SpeedData) + embenchSizeOpt_SpeedData = loadEmbench("embench/actual_embench_results/wallySizeOpt_speed.json", embenchSizeOpt_SpeedData) + embenchSpeedOpt_SizeData = loadEmbench("embench/actual_embench_results/wallySpeedOpt_size.json", embenchSpeedOpt_SizeData) + embenchSizeOpt_SizeData = loadEmbench("embench/actual_embench_results/wallySizeOpt_size.json", embenchSizeOpt_SizeData) graphEmbench(embenchSpeedOpt_SpeedData, embenchSizeOpt_SpeedData, embenchSpeedOpt_SizeData, embenchSizeOpt_SizeData) diff --git a/bin/regression-wally b/bin/regression-wally index 4455008e2..f037d804b 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -279,7 +279,7 @@ lockstepwaivers = [ # Data Types & Functions ################################## -TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr', 'grepfile', 'simlog', 'altcommand'], defaults=[None]) # applies the None default to altcommand +TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr', 'grepfile', 'altcommand'], defaults=[None]) # applies the None default to altcommand # name: the name of this test configuration (used in printing human-readable # output and picking logfile names) # cmd: the command to run to test (should include the logfile as '{}', and @@ -288,7 +288,6 @@ TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr', 'grepfil # grep finds that string in the logfile (is used by grep, so it may # be any pattern grep accepts, see `man 1 grep` for more info). # grepfile: a string containing the location of the file to be searched for output -# simlog: the name of the logfile to be used for this test. # altcommand: the command, if enabled, performs a validation check other than grep # on the log files. None by default, and if specified the command will be run class bcolors: @@ -319,8 +318,7 @@ def addTests(testList, sim, coverStr, configs): variant=config, cmd=f"{cmdPrefix} {t} > {sim_log}", grepstr=gs, - grepfile = grepfile, - simlog=sim_log) + grepfile = grepfile) configs.append(tc) @@ -356,8 +354,7 @@ def addTestsByDir(testDir, config, sim, coverStr, configs, lockstepMode=0, breke variant=config, cmd=f"{cmdPrefix} {fullfile} > {sim_log}", grepstr=gs, - grepfile = sim_log, - simlog=sim_log) + grepfile = sim_log) configs.append(tc) def search_log_for_text(text, grepfile): @@ -384,7 +381,7 @@ def run_test_case(config, dryrun: bool = False): print(f" Check {grepfile} for more details.", flush=True) return 1 elif altcommand: - sim_log = config.simlog + sim_log = config.grepfile check_ret_code = os.system(altcommand) with open(sim_log, 'a') as f: if check_ret_code == 0: @@ -462,8 +459,7 @@ def selectTests(args, sims, coverStr): variant="all", cmd=f"lint-wally {'--nightly' if args.nightly else ''} | tee {regressionDir}/verilator/logs/all_lints.log", grepstr="lints run with no errors or warnings", - grepfile = f"{regressionDir}/verilator/logs/all_lints.log", - simlog=f"{regressionDir}/verilator/logs/all_lints.log") + grepfile = f"{regressionDir}/verilator/logs/all_lints.log") ] # run full buildroot boot simulation (slow) if buildroot flag is set. Start it early to overlap with other tests @@ -527,85 +523,54 @@ def selectTests(args, sims, coverStr): variant=config, cmd=f"wsim --tb testbench_fp --sim {testfloatsim} {config} {test} > {sim_log}", grepstr="All Tests completed with 0 errors", - grepfile = sim_log, - simlog=sim_log) + grepfile = sim_log) configs.append(tc) if (args.performance or args.nightly): # RUNNING THE EMBENCH TEST - actual_json_path_start = f"{WALLY}/benchmarks/embench/" - expected_json_path_start = f"{WALLY}/benchmarks/embench/expected_embench_results/" - file_name_order = ["wallySizeOpt_size.json", "wallySizeOpt_speed.json", "wallySpeedOpt_size.json", "wallySpeedOpt_speed.json"] - # These are the actual file paths names that embench generates - file_paths_actual = [f"{actual_json_path_start}{file_name}" for file_name in file_name_order] - # The expected file paths are the same as the actual ones, but with "expected_" in front - file_paths_expected = [f"{expected_json_path_start}expected_{file_name}" for file_name in file_name_order] - + actual_embench_directory = f"{WALLY}/benchmarks/embench/actual_embench_results/" + expected_embench_directory = f"{WALLY}/benchmarks/embench/expected_embench_results/" embench_logfile_path = os.path.expandvars("$WALLY/benchmarks/embench/run.log") - diff_commands = [] - for expected, actual in zip(file_paths_expected, file_paths_actual): - diff_commands.append( - f'echo "\n==============================================" >> "{embench_logfile_path}"\n' - f'echo "Comparing {expected} and {actual}:" >> "{embench_logfile_path}"\n' - # Run diff - f'echo "\nDiff output:" >> "{embench_logfile_path}"\n' - f'diff -u "{actual}" "{expected}" >> "{embench_logfile_path}" 2>&1\n' - f'if [ $? -ne 0 ]; then\n' - f' echo "MISMATCH found for {expected} and {actual}" >> "{embench_logfile_path}"\n' - f' mismatch_detected=1;\n' - f'else\n' - f' echo "Files match." >> "{embench_logfile_path}"\n' - f'fi\n' - f'echo "==============================================" >> "{embench_logfile_path}"' - ) - - diff_cmds_combined = "\n".join(diff_commands) - - final_check_block = ( - f'if [ $mismatch_detected -eq 1 ]; then\n' - f' echo "EMBENCH_TEST_FAILED: Values did not match expected metrics" >> "{embench_logfile_path}";\n' - f' exit 1;\n' - f'else\n' - f' echo "EMBENCH_TEST_PASSED" >> "{embench_logfile_path}";\n' - f'fi' - ) - - full_shell_block = f"mismatch_detected=0\n{diff_cmds_combined}\n{final_check_block}" - + # Create the file if it doesn't exist + with open(embench_logfile_path, 'w'): + pass + # Combine everything into the embench_test command + # finds any differences between the two embench directories and appends them to the log file embench_test = TestCase( name="embench", variant="rv32gc", - cmd = ( - f"rm -f {embench_logfile_path} && " - f"touch {embench_logfile_path} && " + cmd=( f"cd $WALLY/benchmarks/embench && " - f"make run >> {embench_logfile_path} 2>&1 && " - f"bash << 'EOF'\n{full_shell_block}\nEOF" + f"make run >> {embench_logfile_path} 2>&1" ), - grepstr="EMBENCH_TEST_PASSED", # Make sure this matches success message + grepstr=None, grepfile=embench_logfile_path, - simlog=embench_logfile_path + altcommand=f"diff -ru {actual_embench_directory} {expected_embench_directory} >> {embench_logfile_path}" ) configs.append(embench_test) # RUNNING THE COREMARK TEST sim_log = f"{regressionDir}/{defaultsim}/logs/validation.log" - # Create the directory if it doesn't exist - os.makedirs(os.path.dirname(sim_log), exist_ok=True) + coremark_logfile_path = os.path.expandvars(sim_log) + # Create the directory (and file) if it doesn't exist + os.makedirs(os.path.dirname(coremark_logfile_path), exist_ok=True) + with open(coremark_logfile_path, 'w'): + pass coremark_sweep_test_file = f"{WALLY}/benchmarks/coremark/coremark_sweep.py" actual_coremark_values_csv = f"{WALLY}/benchmarks/coremark/coremark_results.csv" expected_coremark_values_csv = f"{WALLY}/benchmarks/coremark/expected_coremark_results.csv" + + # calculates the difference between the coremark expected outcomes and appends them to the log file coremark_test = TestCase( name="validate_coremark_sweep", variant="coremark check", cmd=(f"python3 {coremark_sweep_test_file}"), grepstr=None, - grepfile=None, - simlog=sim_log, - altcommand=f"diff -u {actual_coremark_values_csv} {expected_coremark_values_csv} >> {sim_log}" + grepfile=coremark_logfile_path, + altcommand=f"diff -u {actual_coremark_values_csv} {expected_coremark_values_csv} >> {coremark_logfile_path}" ) configs.append(coremark_test) From 534a467ff383c44e81ead1e72a74d5ba49603ee6 Mon Sep 17 00:00:00 2001 From: SadhviNarayanan Date: Sun, 4 May 2025 15:57:02 -0700 Subject: [PATCH 22/43] gitignore added --- .gitignore | 1 + benchmarks/embench/Makefile | 10 +++++++--- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/.gitignore b/.gitignore index 8a3c7fad9..f6d9fce7d 100644 --- a/.gitignore +++ b/.gitignore @@ -82,6 +82,7 @@ synthDC/Summary.csv # Benchmarks benchmarks/embench/wally*.json +benchmarks/embench/actual_embench_results/wally*.json benchmarks/embench/run* benchmarks/coremark/coremark_results.csv diff --git a/benchmarks/embench/Makefile b/benchmarks/embench/Makefile index 00504d741..46a75ff5f 100644 --- a/benchmarks/embench/Makefile +++ b/benchmarks/embench/Makefile @@ -60,16 +60,20 @@ sim_build_memfile: objdump spike: buildspeed spike_run speed # command to run spike on all of the benchmarks -spike_run: +spike_run: find $(embench_dir)/bd_*opt_speed/ -type f -name "*.elf" | while read f; do spike --isa=rv32imac +signature=$$f.spike.output +signature-granularity=4 $$f; done +# creates the directory to store the results of the embench tests +actual_embench_results: + mkdir -p actual_embench_results + # python wrapper to present results of embench size benchmark -size: buildsize +size: actual_embench_results buildsize $(embench_dir)/benchmark_size.py --builddir=bd_speedopt_size --json-output > actual_embench_results/wallySpeedOpt_size.json $(embench_dir)/benchmark_size.py --builddir=bd_sizeopt_size --json-output > actual_embench_results/wallySizeOpt_size.json # python wrapper to present results of embench speed benchmark -speed: +speed: actual_embench_results $(embench_dir)/benchmark_speed.py --builddir=bd_sizeopt_speed --target-module run_wally --cpu-mhz=1 --json-output > actual_embench_results/wallySizeOpt_speed.json $(embench_dir)/benchmark_speed.py --builddir=bd_speedopt_speed --target-module run_wally --cpu-mhz=1 --json-output > actual_embench_results/wallySpeedOpt_speed.json From 534971f37cfb3fdd7acea22d66414647ec5a0cb9 Mon Sep 17 00:00:00 2001 From: SadhviNarayanan Date: Sun, 4 May 2025 15:58:47 -0700 Subject: [PATCH 23/43] removed actual_results for embench run --- .../wallySizeOpt_size.json | 29 ------------------- .../wallySizeOpt_speed.json | 29 ------------------- .../wallySpeedOpt_size.json | 29 ------------------- .../wallySpeedOpt_speed.json | 29 ------------------- 4 files changed, 116 deletions(-) delete mode 100644 benchmarks/embench/actual_embench_results/wallySizeOpt_size.json delete mode 100644 benchmarks/embench/actual_embench_results/wallySizeOpt_speed.json delete mode 100644 benchmarks/embench/actual_embench_results/wallySpeedOpt_size.json delete mode 100644 benchmarks/embench/actual_embench_results/wallySpeedOpt_speed.json diff --git a/benchmarks/embench/actual_embench_results/wallySizeOpt_size.json b/benchmarks/embench/actual_embench_results/wallySizeOpt_size.json deleted file mode 100644 index 4c80ab462..000000000 --- a/benchmarks/embench/actual_embench_results/wallySizeOpt_size.json +++ /dev/null @@ -1,29 +0,0 @@ -{ "size results" : - { "detailed size results" : - { "aha-mont64" : 0.96, - "crc32" : 0.74, - "cubic" : 2.01, - "edn" : 1.09, - "huffbench" : 1.16, - "matmult-int" : 0.87, - "md5sum" : 1.00, - "minver" : 0.87, - "nbody" : 0.92, - "nettle-aes" : 1.26, - "nettle-sha256" : 1.62, - "nsichneu" : 1.42, - "picojpeg" : 1.14, - "primecount" : 0.73, - "qrduino" : 1.03, - "sglib-combined" : 1.01, - "slre" : 1.05, - "st" : 0.93, - "statemate" : 0.82, - "tarfind" : 0.95, - "ud" : 0.96, - "wikisort" : 0.94 - }, - "size geometric mean" : 1.04, - "size geometric standard deviation" : 1.26 - } -} diff --git a/benchmarks/embench/actual_embench_results/wallySizeOpt_speed.json b/benchmarks/embench/actual_embench_results/wallySizeOpt_speed.json deleted file mode 100644 index f9a787973..000000000 --- a/benchmarks/embench/actual_embench_results/wallySizeOpt_speed.json +++ /dev/null @@ -1,29 +0,0 @@ -{ "speed results" : - { "detailed speed results" : - { "aha-mont64" : 0.81, - "crc32" : 1.00, - "cubic" : 0.42, - "edn" : 0.88, - "huffbench" : 1.38, - "matmult-int" : 1.11, - "md5sum" : 2.00, - "minver" : 0.63, - "nbody" : 0.67, - "nettle-aes" : 0.82, - "nettle-sha256" : 0.96, - "nsichneu" : 1.14, - "picojpeg" : 0.79, - "primecount" : 1.30, - "qrduino" : 1.22, - "sglib-combined" : 1.17, - "slre" : 1.25, - "st" : 0.84, - "statemate" : 2.15, - "tarfind" : 2.42, - "ud" : 0.88, - "wikisort" : 1.71 - }, - "speed geometric mean" : 1.07, - "speed geometric standard deviation" : 1.51 - } -} diff --git a/benchmarks/embench/actual_embench_results/wallySpeedOpt_size.json b/benchmarks/embench/actual_embench_results/wallySpeedOpt_size.json deleted file mode 100644 index 00c54abd7..000000000 --- a/benchmarks/embench/actual_embench_results/wallySpeedOpt_size.json +++ /dev/null @@ -1,29 +0,0 @@ -{ "size results" : - { "detailed size results" : - { "aha-mont64" : 1.50, - "crc32" : 0.70, - "cubic" : 2.04, - "edn" : 1.10, - "huffbench" : 1.27, - "matmult-int" : 1.15, - "md5sum" : 1.18, - "minver" : 1.10, - "nbody" : 1.12, - "nettle-aes" : 1.37, - "nettle-sha256" : 1.71, - "nsichneu" : 1.51, - "picojpeg" : 1.67, - "primecount" : 0.73, - "qrduino" : 1.43, - "sglib-combined" : 1.13, - "slre" : 1.28, - "st" : 1.29, - "statemate" : 0.87, - "tarfind" : 1.09, - "ud" : 1.14, - "wikisort" : 1.13 - }, - "size geometric mean" : 1.21, - "size geometric standard deviation" : 1.28 - } -} diff --git a/benchmarks/embench/actual_embench_results/wallySpeedOpt_speed.json b/benchmarks/embench/actual_embench_results/wallySpeedOpt_speed.json deleted file mode 100644 index 837d3ef2a..000000000 --- a/benchmarks/embench/actual_embench_results/wallySpeedOpt_speed.json +++ /dev/null @@ -1,29 +0,0 @@ -{ "speed results" : - { "detailed speed results" : - { "aha-mont64" : 0.84, - "crc32" : 1.05, - "cubic" : 0.42, - "edn" : 1.06, - "huffbench" : 1.58, - "matmult-int" : 1.11, - "md5sum" : 1.92, - "minver" : 0.65, - "nbody" : 0.67, - "nettle-aes" : 0.93, - "nettle-sha256" : 0.99, - "nsichneu" : 0.70, - "picojpeg" : 0.99, - "primecount" : 1.41, - "qrduino" : 1.32, - "sglib-combined" : 1.41, - "slre" : 1.54, - "st" : 0.86, - "statemate" : 3.13, - "tarfind" : 3.31, - "ud" : 0.94, - "wikisort" : 1.74 - }, - "speed geometric mean" : 1.15, - "speed geometric standard deviation" : 1.61 - } -} From 048fa377ca5277ebc7a3d49f733208b509008a62 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 5 May 2025 00:41:10 -0500 Subject: [PATCH 24/43] Created a new test which reproduces the same error as the zsh bug, github issue #1263. --- tests/coverage/misalignedStoreSpill.S | 215 ++++++++++++++++++++++++++ 1 file changed, 215 insertions(+) create mode 100644 tests/coverage/misalignedStoreSpill.S diff --git a/tests/coverage/misalignedStoreSpill.S b/tests/coverage/misalignedStoreSpill.S new file mode 100644 index 000000000..777cb8e68 --- /dev/null +++ b/tests/coverage/misalignedStoreSpill.S @@ -0,0 +1,215 @@ +/////////////////////////////////////////// +// misalignedStoreSpill.S +// +// Written: Rose Thompson rose@rosethompson.net 05 May 2025 +// +// Purpose: Test coverage for EBU +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate + +#include "WALLY-init-lib.h" + +# run-elf.bash find this in project description +main: + li t5, 0x1 + slli t5, t5, 62 + ori t5, t5, 0xF0 + csrs menvcfg, t5 # menvcfg.PBMTE = 1, CBZE, CBCFE, CBIE all 1 + + # Page table root address at 0x80010000; SV48 + li t5, 0x9000000000080010 + csrw satp, t5 + + # sfence.vma x0, x0 + + # switch to supervisor mode + li a0, 1 + ecall + + + + li a0, 0x80000fff + j label1 + +.align 6 # start on multiple of 64 bytes / 16 instruction cache line +label1: + li t0, 0xdeadbeef01234567 + sfence.vma # flush tlb + sd t0, 0x0(a0) # load to get an entry in the DTLB accessing top-level PTE + + + # wrap up + li a0, 3 # switch back to machine mode because code at 0x80000000 may not have clean page table entry + ecall + j done + + + +.data + +.align 16 +# root Page table situated at 0x80010000 +pagetable: + .8byte 0x20004401 # 0x00000000-0x80_00000000: PTE at 0x80011000 01 valid + .8byte 0x000000000000100F # misaligned terapage at 0x80_00000000 + +# next page table at 0x80011000 +.align 12 + .8byte 0x000000000000100F # misaligned gigapage at 0x00000000 + .8byte 0x0000000020005801 # PTE for pages at 0x40000000 + .8byte 0x0000000020004801 # gigapage at 0x80000000 pointing to 0x80120000 + + +# Next page table at 0x80012000 for gigapage at 0x80000000 +.align 12 + .8byte 0x0000000020004C01 # for VA starting at 80000000 (pointer to NAPOT 64 KiB pages) + .8byte 0x0000000020014C0F # for VA starting at 80200000 (misaligned megapage) + .8byte 0x0000000020005001 # for VA starting at 80400000 (bad PBMT pages) + .8byte 0x4000000020004C01 # for VA starting at 80600000 (bad entry: nonleaf PTE can't have PBMT != 0) + .8byte 0x0000000020005401 # for VA starting at 80800000 (testing rwx permissiosn with cbom/cboz) + .8byte 0x0000000020005801 # for VA starting at 80A00000 (pointer to NAPOT 64 KiB pages like at 80000000) + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + +# Leaf page table at 0x80013000 with NAPOT pages +.align 12 + #80000000 + .8byte 0x00000000200020CF + .8byte 0x00000000200020CF + .8byte 0x00000000200020CF + .8byte 0x00000000200020CF + + .8byte 0x00000000200020CF + .8byte 0x00000000200020CF + .8byte 0x00000000200020CF + .8byte 0x00000000200020CF + + .8byte 0x00000000200020CF + .8byte 0x00000000200020CF + .8byte 0x00000000200020CF + .8byte 0x00000000200020CF + + .8byte 0x00000000200020CF + .8byte 0x00000000200020CF + .8byte 0x00000000200020CF + .8byte 0x00000000200020CF + + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + + .8byte 0x800000002000E0CF + .8byte 0x800000002000E0CF + .8byte 0x800000002000E0CF + .8byte 0x800000002000E0CF + + .8byte 0x800000002000E0CF + .8byte 0x800000002000E0CF + +# Leaf page table at 0x80014000 with PBMT pages +.align 12 + #80400000 + .8byte 0x60000000200020CF # reserved entry + +# Leaf page table at 0x80015000 with various permissions for testing CBOM and CBOZ +.align 12 + #80800000 + .8byte 0x00000000200000CF # valid rwx for VA 80800000 + .8byte 0x00000000200000CB # valid r x for VA 80801000 + .8byte 0x00000000200000C3 # valid r for VA 80802000 + .8byte 0x00000000200000C9 # valid x for VA 80803000 + .8byte 0x00000000200000CD # valid wx for VA 80804000 (illegal combination, but used to test tlbcontrol) + .8byte 0x000000002000000F # valid rwx for VA 80805000 for covering ITLB translate and UpdateDA + .8byte 0x20000000200000CF # PBMT=1 for VA 80806000 for covering ITLB BadPBMT + +# Leaf page table at 0x80016000 with NAPOT pages +.align 12 + .8byte 0xA0000000200020CF + .8byte 0xA0000000200020CF + .8byte 0xA0000000200020CF + .8byte 0xA0000000200020CF From 396993332771c440b4d6d6ee9e5d3f70c2ed72ab Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 5 May 2025 18:53:33 -0500 Subject: [PATCH 25/43] Possible solution to the misaligned virtual page bug. --- src/lsu/align.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lsu/align.sv b/src/lsu/align.sv index b6bae2918..2f8aa64fb 100644 --- a/src/lsu/align.sv +++ b/src/lsu/align.sv @@ -148,7 +148,7 @@ module align import cvw::*; #(parameter cvw_t P) ( flopenr #(P.LLEN) SpillDataReg(clk, reset, SpillSaveM, DCacheReadDataWordM[P.LLEN-1:0], ReadDataWordFirstHalfM); // merge together - mux2 #(2*P.LLEN) postspillmux(DCacheReadDataWordM, {DCacheReadDataWordM[P.LLEN-1:0], ReadDataWordFirstHalfM}, SelSpillM, ReadDataWordSpillAllM); + mux2 #(2*P.LLEN) postspillmux(DCacheReadDataWordM, {DCacheReadDataWordM[P.LLEN-1:0], ReadDataWordFirstHalfM}, SelSpillM & ~SelHPTW, ReadDataWordSpillAllM); // shifter (4:1 mux for 32 bit, 8:1 mux for 64 bit) From 69889cb31f88064ff41d85ad92eb8ea9d5a1ac20 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 5 May 2025 19:15:45 -0500 Subject: [PATCH 26/43] Updated debug6, the large ila. --- fpga/constraints/debug6.xdc | 24 +++- fpga/constraints/marked_debug_debug6.txt | 135 +++++++++++++++++++++++ 2 files changed, 157 insertions(+), 2 deletions(-) create mode 100644 fpga/constraints/marked_debug_debug6.txt diff --git a/fpga/constraints/debug6.xdc b/fpga/constraints/debug6.xdc index 88ae08ef8..823d1cf09 100644 --- a/fpga/constraints/debug6.xdc +++ b/fpga/constraints/debug6.xdc @@ -1,5 +1,8 @@ create_debug_core u_ila_0 ila + + + set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_0] set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] @@ -14,7 +17,8 @@ set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ] set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ] set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ] endgroup -connect_debug_port u_ila_0/clk [get_nets [list xlnx_ddr4_c0/inst/u_ddr4_infrastructure/addn_ui_clkout1 ]] +connect_debug_port u_ila_0/clk [get_nets CPUCLK] + set_property port_width 64 [get_debug_ports u_ila_0/probe0] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]] @@ -366,7 +370,7 @@ connect_debug_port u_ila_0/probe69 [get_nets [list {wallypipelinedsoc/core/priv. create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe70] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe70] -connect_debug_port u_ila_0/probe70 [get_nets [list wallypipelinedsoc/core/lsu/ITLBMissF]] +connect_debug_port u_ila_0/probe70 [get_nets [list wallypipelinedsoc/core/lsu/ITLBMissOrUpdateAF]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe71] @@ -547,3 +551,19 @@ create_debug_port u_ila_0 probe set_property port_width 48 [get_debug_ports u_ila_0/probe105] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe105] connect_debug_port u_ila_0/probe105 [get_nets [list {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[0]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[1]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[2]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[3]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[4]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[5]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[6]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[7]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[8]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[9]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[10]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[11]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[12]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[13]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[14]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[15]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[16]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[17]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[18]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[19]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[20]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[21]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[22]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[23]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[24]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[25]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[26]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[27]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[28]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[29]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[30]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[31]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[32]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[33]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[34]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[35]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[36]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[37]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[38]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[39]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[40]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[41]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[42]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[43]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[60]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[61]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[62]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[63]}]] + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe106] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe106] +connect_debug_port u_ila_0/probe106 [get_nets [list {wallypipelinedsoc/core/ieu/dp/ALUResultE[0]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[1]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[2]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[3]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[4]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[5]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[6]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[7]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[8]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[9]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[10]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[11]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[12]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[13]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[14]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[15]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[16]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[17]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[18]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[19]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[20]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[21]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[22]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[23]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[24]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[25]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[26]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[27]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[28]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[29]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[30]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[31]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[32]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[33]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[34]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[35]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[36]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[37]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[38]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[39]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[40]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[41]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[42]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[43]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[44]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[45]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[46]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[47]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[48]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[49]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[50]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[51]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[52]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[53]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[54]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[55]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[56]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[57]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[58]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[59]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[60]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[61]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[62]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[63]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 56 [get_debug_ports u_ila_0/probe107] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe107] +connect_debug_port u_ila_0/probe107 [get_nets [list {wallypipelinedsoc/core/lsu/PAdrM[0]} {wallypipelinedsoc/core/lsu/PAdrM[1]} {wallypipelinedsoc/core/lsu/PAdrM[2]} {wallypipelinedsoc/core/lsu/PAdrM[3]} {wallypipelinedsoc/core/lsu/PAdrM[4]} {wallypipelinedsoc/core/lsu/PAdrM[5]} {wallypipelinedsoc/core/lsu/PAdrM[6]} {wallypipelinedsoc/core/lsu/PAdrM[7]} {wallypipelinedsoc/core/lsu/PAdrM[8]} {wallypipelinedsoc/core/lsu/PAdrM[9]} {wallypipelinedsoc/core/lsu/PAdrM[10]} {wallypipelinedsoc/core/lsu/PAdrM[11]} {wallypipelinedsoc/core/lsu/PAdrM[12]} {wallypipelinedsoc/core/lsu/PAdrM[13]} {wallypipelinedsoc/core/lsu/PAdrM[14]} {wallypipelinedsoc/core/lsu/PAdrM[15]} {wallypipelinedsoc/core/lsu/PAdrM[16]} {wallypipelinedsoc/core/lsu/PAdrM[17]} {wallypipelinedsoc/core/lsu/PAdrM[18]} {wallypipelinedsoc/core/lsu/PAdrM[19]} {wallypipelinedsoc/core/lsu/PAdrM[20]} {wallypipelinedsoc/core/lsu/PAdrM[21]} {wallypipelinedsoc/core/lsu/PAdrM[22]} {wallypipelinedsoc/core/lsu/PAdrM[23]} {wallypipelinedsoc/core/lsu/PAdrM[24]} {wallypipelinedsoc/core/lsu/PAdrM[25]} {wallypipelinedsoc/core/lsu/PAdrM[26]} {wallypipelinedsoc/core/lsu/PAdrM[27]} {wallypipelinedsoc/core/lsu/PAdrM[28]} {wallypipelinedsoc/core/lsu/PAdrM[29]} {wallypipelinedsoc/core/lsu/PAdrM[30]} {wallypipelinedsoc/core/lsu/PAdrM[31]} {wallypipelinedsoc/core/lsu/PAdrM[32]} {wallypipelinedsoc/core/lsu/PAdrM[33]} {wallypipelinedsoc/core/lsu/PAdrM[34]} {wallypipelinedsoc/core/lsu/PAdrM[35]} {wallypipelinedsoc/core/lsu/PAdrM[36]} {wallypipelinedsoc/core/lsu/PAdrM[37]} {wallypipelinedsoc/core/lsu/PAdrM[38]} {wallypipelinedsoc/core/lsu/PAdrM[39]} {wallypipelinedsoc/core/lsu/PAdrM[40]} {wallypipelinedsoc/core/lsu/PAdrM[41]} {wallypipelinedsoc/core/lsu/PAdrM[42]} {wallypipelinedsoc/core/lsu/PAdrM[43]} {wallypipelinedsoc/core/lsu/PAdrM[44]} {wallypipelinedsoc/core/lsu/PAdrM[45]} {wallypipelinedsoc/core/lsu/PAdrM[46]} {wallypipelinedsoc/core/lsu/PAdrM[47]} {wallypipelinedsoc/core/lsu/PAdrM[48]} {wallypipelinedsoc/core/lsu/PAdrM[49]} {wallypipelinedsoc/core/lsu/PAdrM[50]} {wallypipelinedsoc/core/lsu/PAdrM[51]} {wallypipelinedsoc/core/lsu/PAdrM[52]} {wallypipelinedsoc/core/lsu/PAdrM[53]} {wallypipelinedsoc/core/lsu/PAdrM[54]} {wallypipelinedsoc/core/lsu/PAdrM[55]} ]] + + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe108] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe108] +connect_debug_port u_ila_0/probe108 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[63]} ]] diff --git a/fpga/constraints/marked_debug_debug6.txt b/fpga/constraints/marked_debug_debug6.txt new file mode 100644 index 000000000..8b858d84f --- /dev/null +++ b/fpga/constraints/marked_debug_debug6.txt @@ -0,0 +1,135 @@ +lsu/lsu.sv: logic IEUAdrM +lsu/lsu.sv: logic PAdrM +lsu/lsu.sv: logic WriteDataM +lsu/lsu.sv: logic LSUHADDR +lsu/lsu.sv: logic HRDATA +lsu/lsu.sv: logic LSUHWDATA +lsu/lsu.sv: logic LSUHREADY +lsu/lsu.sv: logic LSUHWRITE +lsu/lsu.sv: logic LSUHSIZE +lsu/lsu.sv: logic LSUHBURST +lsu/lsu.sv: logic LSUHTRANS +lsu/lsu.sv: logic LSUHWSTRB +lsu/lsu.sv: logic IHAdrM +ieu/regfile.sv: logic rf +ieu/datapath.sv: logic RegWriteW +hazard/hazard.sv: logic BPPredWrongE +hazard/hazard.sv: logic LoadStallD +hazard/hazard.sv: logic FCvtIntStallD +hazard/hazard.sv: logic DivBusyE +hazard/hazard.sv: logic EcallFaultM +hazard/hazard.sv: logic WFIStallM +hazard/hazard.sv: logic StallF +hazard/hazard.sv: logic FlushD +cache/cachefsm.sv: statetype CurrState +wally/wallypipelinedcore.sv: logic TrapM +wally/wallypipelinedcore.sv: logic SrcAM +wally/wallypipelinedcore.sv: logic InstrM +wally/wallypipelinedcore.sv: logic PCM +wally/wallypipelinedcore.sv: logic MemRWM +wally/wallypipelinedcore.sv: logic InstrValidM +wally/wallypipelinedcore.sv: logic WriteDataM +wally/wallypipelinedcore.sv: logic IEUAdrM +ieu/datapath.sv: logic ALUResultE +wally/wallypipelinedcore.sv: logic HRDATA +ifu/spill.sv: statetype CurrState +ifu/ifu.sv: logic IFUStallF +ifu/ifu.sv: logic IFUHADDR +ifu/ifu.sv: logic HRDATA +ifu/ifu.sv: logic IFUHREADY +ifu/ifu.sv: logic IFUHWRITE +ifu/ifu.sv: logic IFUHSIZE +ifu/ifu.sv: logic IFUHBURST +ifu/ifu.sv: logic IFUHTRANS +ifu/ifu.sv: logic PCF +ifu/ifu.sv: logic PCNextF +ifu/ifu.sv: logic PCPF +ifu/ifu.sv: logic PostSpillInstrRawF +mmu/hptw.sv: logic ITLBMissOrUpdateAF +mmu/hptw.sv: statetype WalkerState +mmu/hptw.sv: logic ValidPTE +privileged/csrs.sv: logic CSRSReadValM +privileged/csrs.sv: logic SEPC_REGW +privileged/csrs.sv: logic MIP_REGW +privileged/csrs.sv: logic SSCRATCH_REGW +privileged/csrs.sv: logic SCAUSE_REGW +privileged/csr.sv: logic CSRReadValM +privileged/csr.sv: logic CSRSrcM +privileged/csr.sv: logic CSRWriteValM +privileged/csr.sv: logic MSTATUS_REGW +privileged/trap.sv: logic InstrMisalignedFaultM +privileged/trap.sv: logic BreakpointFaultM +privileged/trap.sv: logic LoadAccessFaultM +privileged/trap.sv: logic LoadPageFaultM +privileged/trap.sv: logic mretM +privileged/trap.sv: logic MIP_REGW +privileged/trap.sv: logic PendingIntsM +privileged/privileged.sv: logic CSRReadM +privileged/csr.sv: logic MENVCFG_REGW +privileged/privileged.sv: logic InterruptM +privileged/csrc.sv: logic HPMCOUNTER_REGW +privileged/csri.sv: logic MExtInt +privileged/csri.sv: logic MIP_REGW_writeabl +privileged/csrm.sv: logic MIP_REGW +privileged/csrm.sv: logic MEPC_REGW +privileged/csrm.sv: logic MEDELEG_REGW +privileged/csrm.sv: logic MIDELEG_REGW +privileged/csrm.sv: logic MSCRATCH_REGW +privileged/csrm.sv: logic MCAUSE_REGW +uncore/uart_apb.sv: logic SIN +uncore/uart_apb.sv: logic SOUT +uncore/uart_apb.sv: logic OUT1b +uncore/uartPC16550D.sv: logic RBR +uncore/uartPC16550D.sv: logic FCR +uncore/uartPC16550D.sv: logic IER +uncore/uartPC16550D.sv: logic MCR +uncore/uartPC16550D.sv: logic baudpulse +uncore/uartPC16550D.sv: statetype rxstate +uncore/uartPC16550D.sv: logic rxfifo +uncore/uartPC16550D.sv: logic txfifo +uncore/uartPC16550D.sv: logic rxfifohead +uncore/uartPC16550D.sv: logic rxfifoentries +uncore/uartPC16550D.sv: logic RXBR +uncore/uartPC16550D.sv: logic rxtimeoutcnt +uncore/uartPC16550D.sv: logic rxparityerr +uncore/uartPC16550D.sv: logic rxdataready +uncore/uartPC16550D.sv: logic rxfifoempty +uncore/uartPC16550D.sv: logic rxdata +uncore/uartPC16550D.sv: logic RXerrbit +uncore/uartPC16550D.sv: logic rxfullbitunwrapped +uncore/uartPC16550D.sv: logic txdata +uncore/uartPC16550D.sv: logic txnextbit +uncore/uartPC16550D.sv: logic txfifoempty +uncore/uartPC16550D.sv: logic fifoenabled +uncore/uartPC16550D.sv: logic RXerr +uncore/uartPC16550D.sv: logic THRE +uncore/uartPC16550D.sv: logic rxdataavailintr +uncore/uartPC16550D.sv: logic intrID +uncore/uncore.sv: logic HSELEXTSDCD +uncore/plic_apb.sv: logic MExtInt +uncore/plic_apb.sv: logic Din +uncore/plic_apb.sv: logic requests +uncore/plic_apb.sv: logic intPriority +uncore/plic_apb.sv: logic intInProgress +uncore/plic_apb.sv: logic intThreshold +uncore/plic_apb.sv: logic intEn +uncore/plic_apb.sv: logic intClaim +uncore/plic_apb.sv: logic irqMatrix +uncore/plic_apb.sv: logic priorities_with_irqs +uncore/plic_apb.sv: logic max_priority_with_irqs +uncore/plic_apb.sv: logic irqs_at_max_priority +uncore/plic_apb.sv: logic threshMask +uncore/clint_apb.sv: logic MTIME +uncore/clint_apb.sv: logic MTIMECMP +ebu/ebu.sv: logic HCLK +ebu/ebu.sv: logic HREADY +ebu/ebu.sv: logic HRESP +ebu/ebu.sv: logic HADDR +ebu/ebu.sv: logic HWRITE +ebu/ebu.sv: logic HSIZE +ebu/ebu.sv: logic HBURST +ebu/ebu.sv: logic HPROT +ebu/ebu.sv: logic HTRANS +ebu/ebu.sv: logic HMASTLOC +ebu/buscachefsm.sv: busstatetype CurrState +ebu/busfsm.sv: busstatetype CurrState From 52c5e515b75b85d53d400087125e507f07a80c83 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 6 May 2025 19:24:05 -0500 Subject: [PATCH 27/43] Second fix for the zsh bug. Fixes issue #1263. A misaligned load or store page fault generates two virtual memory address translations. If the second page faults, xtval should be updated with the address of the second part of the instruction not the first part. --- src/lsu/lsu.sv | 4 +++- src/privileged/csr.sv | 4 ++-- src/privileged/privileged.sv | 4 ++-- src/wally/wallypipelinedcore.sv | 4 +++- 4 files changed, 10 insertions(+), 6 deletions(-) diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index f6a215a27..2d6e14166 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -57,6 +57,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( input logic BigEndianM, // Swap byte order to big endian input logic sfencevmaM, // Virtual memory address fence, invalidate TLB entries output logic DCacheStallM, // D$ busy with multicycle operation + output logic [P.XLEN-1:0] IEUAdrSpillM, // IEUAdrM, but could be spilled onto the next cacheline or virtual page. // fpu input logic [P.FLEN-1:0] FWriteDataM, // Write data from FPU input logic FpLoadStoreM, // Selects FPU as store for write data @@ -158,7 +159,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( flopenrc #(P.XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM); if(MISALIGN_SUPPORT) begin : ziccslm_align - logic [P.XLEN-1:0] IEUAdrSpillE, IEUAdrSpillM; + logic [P.XLEN-1:0] IEUAdrSpillE; align #(P) align(.clk, .reset, .StallM, .FlushM, .IEUAdrE, .IEUAdrM, .Funct3M, .FpLoadStoreM, .MemRWM, .DCacheReadDataWordM, .CacheBusHPWTStall, .SelHPTW, @@ -175,6 +176,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( assign LSUWriteDataSpillM = LSUWriteDataM; assign MemRWSpillM = MemRWM; assign {SpillStallM} = 1'b0; + assign IEUAdrSpillM = IEUAdrM; end if(P.ZICBOZ_SUPPORTED) begin : cboz diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index ad3dab32d..f21241f0a 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -36,7 +36,7 @@ module csr import cvw::*; #(parameter cvw_t P) ( input logic [31:0] InstrM, // current instruction input logic [31:0] InstrOrigM, // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL input logic [P.XLEN-1:0] PCM, // program counter, next PC going to trap/return logic - input logic [P.XLEN-1:0] SrcAM, IEUAdrM, // SrcA and memory address from IEU + input logic [P.XLEN-1:0] SrcAM, IEUAdrSpillM, // SrcA and memory address from IEU input logic CSRReadM, CSRWriteM, // read or write CSR input logic TrapM, // trap is occurring input logic mretM, sretM, // return instruction @@ -142,7 +142,7 @@ module csr import cvw::*; #(parameter cvw_t P) ( else case (CauseM) 12, 1, 3: NextFaultMtvalM = PCM; // Instruction page/access faults, breakpoint 2: NextFaultMtvalM = {{(P.XLEN-32){1'b0}}, InstrOrigM}; // Illegal instruction fault - 0, 4, 6, 13, 15, 5, 7: NextFaultMtvalM = IEUAdrM; // Instruction misaligned, Load/Store Misaligned/page/access faults + 0, 4, 6, 13, 15, 5, 7: NextFaultMtvalM = IEUAdrSpillM; // Instruction misaligned, Load/Store Misaligned/page/access faults default: NextFaultMtvalM = '0; // Ecall, interrupts endcase diff --git a/src/privileged/privileged.sv b/src/privileged/privileged.sv index 197ab23be..ba7aeb960 100644 --- a/src/privileged/privileged.sv +++ b/src/privileged/privileged.sv @@ -37,7 +37,7 @@ module privileged import cvw::*; #(parameter cvw_t P) ( input logic [P.XLEN-1:0] SrcAM, // GPR register to write input logic [31:0] InstrM, // Instruction input logic [31:0] InstrOrigM, // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL - input logic [P.XLEN-1:0] IEUAdrM, // address from IEU + input logic [P.XLEN-1:0] IEUAdrSpillM, // address from IEU input logic [P.XLEN-1:0] PCM, // program counter // control signals input logic InstrValidM, // Current instruction is valid (not flushed) @@ -133,7 +133,7 @@ module privileged import cvw::*; #(parameter cvw_t P) ( // Control and Status Registers csr #(P) csr(.clk, .reset, .FlushM, .FlushW, .StallE, .StallM, .StallW, - .InstrM, .InstrOrigM, .PCM, .SrcAM, .IEUAdrM, + .InstrM, .InstrOrigM, .PCM, .SrcAM, .IEUAdrSpillM, .CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .InterruptM, .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .StoreStallD, diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index b5a80a24b..2c07d190c 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -130,6 +130,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( logic [P.XLEN-1:0] IEUAdrE; logic [P.XLEN-1:0] WriteDataM; logic [P.XLEN-1:0] IEUAdrM; + logic [P.XLEN-1:0] IEUAdrSpillM; logic [P.LLEN-1:0] ReadDataW; logic CommittedM; @@ -242,6 +243,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( .ENVCFG_ADUE, // from csr .sfencevmaM, // connects to privilege .DCacheStallM, // connects to privilege + .IEUAdrSpillM, // connects to privilege .LoadPageFaultM, // connects to privilege .StoreAmoPageFaultM, // connects to privilege .LoadMisalignedFaultM, // connects to privilege @@ -299,7 +301,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( .InstrMisalignedFaultM, .IllegalIEUFPUInstrD, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, .MTimerInt, .MExtInt, .SExtInt, .MSwInt, - .MTIME_CLINT, .IEUAdrM, .SetFflagsM, + .MTIME_CLINT, .IEUAdrSpillM, .SetFflagsM, .InstrAccessFaultF, .HPTWInstrAccessFaultF, .HPTWInstrPageFaultF, .LoadAccessFaultM, .StoreAmoAccessFaultM, .SelHPTW, .PrivilegeModeW, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS, From 1d80bd1abf6e2b33e5b336aa45555720fa1d82ae Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Wed, 7 May 2025 10:53:36 -0500 Subject: [PATCH 28/43] New test for spilled store page fault. ImperasDV indicates Wally does not improve the correct mtval. --- tests/coverage/misalignedStoreSpill.S | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/tests/coverage/misalignedStoreSpill.S b/tests/coverage/misalignedStoreSpill.S index 777cb8e68..8bf47c875 100644 --- a/tests/coverage/misalignedStoreSpill.S +++ b/tests/coverage/misalignedStoreSpill.S @@ -55,6 +55,10 @@ label1: li t0, 0xdeadbeef01234567 sfence.vma # flush tlb sd t0, 0x0(a0) # load to get an entry in the DTLB accessing top-level PTE + li a1, 4096 + add a0, a0, a1 + sd t0, 0(a0) # cause a store page fault to the second half of the access. mtval should be updated to the address of the second half. + # wrap up @@ -125,7 +129,7 @@ pagetable: #80000000 .8byte 0x00000000200020CF .8byte 0x00000000200020CF - .8byte 0x00000000200020CF + .8byte 0x0000000000000000 # this is in invalid so that the second half of the access causes a fault .8byte 0x00000000200020CF .8byte 0x00000000200020CF From 950cdba29895c0097a7b359d81b7e5ec4b5453c1 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Wed, 7 May 2025 14:00:07 -0500 Subject: [PATCH 29/43] Fixed align module so that spilled addresses are aligned to native word type rather than + cacheline in bytes over the effective address. This ensures xtval is set to the aligned byte for the second half of the access. --- src/lsu/align.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lsu/align.sv b/src/lsu/align.sv index 2f8aa64fb..2d635235f 100644 --- a/src/lsu/align.sv +++ b/src/lsu/align.sv @@ -80,7 +80,7 @@ module align import cvw::*; #(parameter cvw_t P) ( /* verilator lint_off WIDTHEXPAND */ - assign IEUAdrIncrementM = IEUAdrM + LLENINBYTES; + assign IEUAdrIncrementM = {IEUAdrM[P.XLEN-1:OFFSET_LEN], {{OFFSET_LEN}{1'b0}}} + LLENINBYTES; /* verilator lint_on WIDTHEXPAND */ mux2 #(P.XLEN) ieuadrspillemux(.d0(IEUAdrE), .d1(IEUAdrIncrementM), .s(SelSpillE), .y(IEUAdrSpillE)); mux2 #(P.XLEN) ieuadrspillmmux(.d0(IEUAdrM), .d1(IEUAdrIncrementM), .s(SelSpillM), .y(IEUAdrSpillM)); From 03653f0336c666822bcd80bb7c3a321e16ee89c8 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Wed, 7 May 2025 16:26:05 -0500 Subject: [PATCH 30/43] Fixed the xtval misaligned address issue. --- src/lsu/align.sv | 6 +++++- src/lsu/lsu.sv | 7 ++++--- src/privileged/csr.sv | 4 ++-- src/privileged/privileged.sv | 4 ++-- src/wally/wallypipelinedcore.sv | 6 +++--- 5 files changed, 16 insertions(+), 11 deletions(-) diff --git a/src/lsu/align.sv b/src/lsu/align.sv index 2d635235f..0c900b3d4 100644 --- a/src/lsu/align.sv +++ b/src/lsu/align.sv @@ -52,6 +52,7 @@ module align import cvw::*; #(parameter cvw_t P) ( output logic [P.XLEN-1:0] IEUAdrSpillE, // The next PCF for one of the two memory addresses of the spill output logic [P.XLEN-1:0] IEUAdrSpillM, // IEUAdrM for one of the two memory addresses of the spill + output logic [P.XLEN-1:0] IEUAdrxTvalM, // IEUAdrM or spilled and aligned to next page output logic SelSpillE, // During the transition between the two spill operations, the IFU should stall the pipeline output logic [P.LLEN-1:0] DCacheReadDataWordSpillM, // The final 32 bit instruction after merging the two spilled fetches into 1 instruction output logic SpillStallM); @@ -80,10 +81,13 @@ module align import cvw::*; #(parameter cvw_t P) ( /* verilator lint_off WIDTHEXPAND */ - assign IEUAdrIncrementM = {IEUAdrM[P.XLEN-1:OFFSET_LEN], {{OFFSET_LEN}{1'b0}}} + LLENINBYTES; + //assign IEUAdrIncrementM = {IEUAdrM[P.XLEN-1:OFFSET_LEN], {{OFFSET_LEN}{1'b0}}} + LLENINBYTES; + assign IEUAdrIncrementM = IEUAdrM + LLENINBYTES; /* verilator lint_on WIDTHEXPAND */ mux2 #(P.XLEN) ieuadrspillemux(.d0(IEUAdrE), .d1(IEUAdrIncrementM), .s(SelSpillE), .y(IEUAdrSpillE)); mux2 #(P.XLEN) ieuadrspillmmux(.d0(IEUAdrM), .d1(IEUAdrIncrementM), .s(SelSpillM), .y(IEUAdrSpillM)); + //assign IEUAdrxTvalM = {IEUAdrSpillM[P.XLEN-1:OFFSET_LEN], {{OFFSET_LEN}{1'b0}}}; + mux2 #(P.XLEN) ieuadrxtvalmmux(.d0(IEUAdrM), .d1({IEUAdrIncrementM[P.XLEN-1:OFFSET_LEN], {{OFFSET_LEN}{1'b0}}}), .s(SelSpillM), .y(IEUAdrxTvalM)); //////////////////////////////////////////////////////////////////////////////////////////////////// // Detect spill diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index 2d6e14166..b2126ae8f 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -57,7 +57,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( input logic BigEndianM, // Swap byte order to big endian input logic sfencevmaM, // Virtual memory address fence, invalidate TLB entries output logic DCacheStallM, // D$ busy with multicycle operation - output logic [P.XLEN-1:0] IEUAdrSpillM, // IEUAdrM, but could be spilled onto the next cacheline or virtual page. + output logic [P.XLEN-1:0] IEUAdrxTvalM, // IEUAdrM, but could be spilled onto the next cacheline or virtual page. // fpu input logic [P.FLEN-1:0] FWriteDataM, // Write data from FPU input logic FpLoadStoreM, // Selects FPU as store for write data @@ -160,11 +160,12 @@ module lsu import cvw::*; #(parameter cvw_t P) ( flopenrc #(P.XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM); if(MISALIGN_SUPPORT) begin : ziccslm_align logic [P.XLEN-1:0] IEUAdrSpillE; + logic [P.XLEN-1:0] IEUAdrSpillM; align #(P) align(.clk, .reset, .StallM, .FlushM, .IEUAdrE, .IEUAdrM, .Funct3M, .FpLoadStoreM, .MemRWM, .DCacheReadDataWordM, .CacheBusHPWTStall, .SelHPTW, .ByteMaskM, .ByteMaskExtendedM, .LSUWriteDataM, .ByteMaskSpillM, .LSUWriteDataSpillM, - .IEUAdrSpillE, .IEUAdrSpillM, .SelSpillE, .DCacheReadDataWordSpillM, .SpillStallM); + .IEUAdrSpillE, .IEUAdrSpillM, .IEUAdrxTvalM, .SelSpillE, .DCacheReadDataWordSpillM, .SpillStallM); assign IEUAdrExtM = {2'b00, IEUAdrSpillM}; assign IEUAdrExtE = {2'b00, IEUAdrSpillE}; end else begin : no_ziccslm_align @@ -176,7 +177,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( assign LSUWriteDataSpillM = LSUWriteDataM; assign MemRWSpillM = MemRWM; assign {SpillStallM} = 1'b0; - assign IEUAdrSpillM = IEUAdrM; + assign IEUAdrxTvalM = IEUAdrM; end if(P.ZICBOZ_SUPPORTED) begin : cboz diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index f21241f0a..3a5edf2ea 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -36,7 +36,7 @@ module csr import cvw::*; #(parameter cvw_t P) ( input logic [31:0] InstrM, // current instruction input logic [31:0] InstrOrigM, // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL input logic [P.XLEN-1:0] PCM, // program counter, next PC going to trap/return logic - input logic [P.XLEN-1:0] SrcAM, IEUAdrSpillM, // SrcA and memory address from IEU + input logic [P.XLEN-1:0] SrcAM, IEUAdrxTvalM, // SrcA and memory address from IEU input logic CSRReadM, CSRWriteM, // read or write CSR input logic TrapM, // trap is occurring input logic mretM, sretM, // return instruction @@ -142,7 +142,7 @@ module csr import cvw::*; #(parameter cvw_t P) ( else case (CauseM) 12, 1, 3: NextFaultMtvalM = PCM; // Instruction page/access faults, breakpoint 2: NextFaultMtvalM = {{(P.XLEN-32){1'b0}}, InstrOrigM}; // Illegal instruction fault - 0, 4, 6, 13, 15, 5, 7: NextFaultMtvalM = IEUAdrSpillM; // Instruction misaligned, Load/Store Misaligned/page/access faults + 0, 4, 6, 13, 15, 5, 7: NextFaultMtvalM = IEUAdrxTvalM; // Instruction misaligned, Load/Store Misaligned/page/access faults default: NextFaultMtvalM = '0; // Ecall, interrupts endcase diff --git a/src/privileged/privileged.sv b/src/privileged/privileged.sv index ba7aeb960..36cc33026 100644 --- a/src/privileged/privileged.sv +++ b/src/privileged/privileged.sv @@ -37,7 +37,7 @@ module privileged import cvw::*; #(parameter cvw_t P) ( input logic [P.XLEN-1:0] SrcAM, // GPR register to write input logic [31:0] InstrM, // Instruction input logic [31:0] InstrOrigM, // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL - input logic [P.XLEN-1:0] IEUAdrSpillM, // address from IEU + input logic [P.XLEN-1:0] IEUAdrxTvalM, // address from IEU input logic [P.XLEN-1:0] PCM, // program counter // control signals input logic InstrValidM, // Current instruction is valid (not flushed) @@ -133,7 +133,7 @@ module privileged import cvw::*; #(parameter cvw_t P) ( // Control and Status Registers csr #(P) csr(.clk, .reset, .FlushM, .FlushW, .StallE, .StallM, .StallW, - .InstrM, .InstrOrigM, .PCM, .SrcAM, .IEUAdrSpillM, + .InstrM, .InstrOrigM, .PCM, .SrcAM, .IEUAdrxTvalM, .CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .InterruptM, .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .StoreStallD, diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index 2c07d190c..4c8fd1cfe 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -130,7 +130,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( logic [P.XLEN-1:0] IEUAdrE; logic [P.XLEN-1:0] WriteDataM; logic [P.XLEN-1:0] IEUAdrM; - logic [P.XLEN-1:0] IEUAdrSpillM; + logic [P.XLEN-1:0] IEUAdrxTvalM; logic [P.LLEN-1:0] ReadDataW; logic CommittedM; @@ -243,7 +243,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( .ENVCFG_ADUE, // from csr .sfencevmaM, // connects to privilege .DCacheStallM, // connects to privilege - .IEUAdrSpillM, // connects to privilege + .IEUAdrxTvalM, // connects to privilege .LoadPageFaultM, // connects to privilege .StoreAmoPageFaultM, // connects to privilege .LoadMisalignedFaultM, // connects to privilege @@ -301,7 +301,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( .InstrMisalignedFaultM, .IllegalIEUFPUInstrD, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, .MTimerInt, .MExtInt, .SExtInt, .MSwInt, - .MTIME_CLINT, .IEUAdrSpillM, .SetFflagsM, + .MTIME_CLINT, .IEUAdrxTvalM, .SetFflagsM, .InstrAccessFaultF, .HPTWInstrAccessFaultF, .HPTWInstrPageFaultF, .LoadAccessFaultM, .StoreAmoAccessFaultM, .SelHPTW, .PrivilegeModeW, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS, From 33a10fd017cbe21eaf6cdc9fece65590162b1d12 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Wed, 7 May 2025 16:26:26 -0500 Subject: [PATCH 31/43] Creating separate test for instruction misaligned page fault. --- tests/coverage/misalignedStoreSpill.S | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/tests/coverage/misalignedStoreSpill.S b/tests/coverage/misalignedStoreSpill.S index 8bf47c875..40766d828 100644 --- a/tests/coverage/misalignedStoreSpill.S +++ b/tests/coverage/misalignedStoreSpill.S @@ -52,14 +52,15 @@ main: .align 6 # start on multiple of 64 bytes / 16 instruction cache line label1: + # test 1 li t0, 0xdeadbeef01234567 sfence.vma # flush tlb sd t0, 0x0(a0) # load to get an entry in the DTLB accessing top-level PTE + + # test 2 li a1, 4096 add a0, a0, a1 sd t0, 0(a0) # cause a store page fault to the second half of the access. mtval should be updated to the address of the second half. - - # wrap up li a0, 3 # switch back to machine mode because code at 0x80000000 may not have clean page table entry @@ -67,7 +68,6 @@ label1: j done - .data .align 16 @@ -80,7 +80,7 @@ pagetable: .align 12 .8byte 0x000000000000100F # misaligned gigapage at 0x00000000 .8byte 0x0000000020005801 # PTE for pages at 0x40000000 - .8byte 0x0000000020004801 # gigapage at 0x80000000 pointing to 0x80120000 + .8byte 0x0000000020004801 # # Next page table at 0x80012000 for gigapage at 0x80000000 @@ -152,7 +152,7 @@ pagetable: .8byte 0x80000000200060CF .8byte 0x80000000200060CF - .8byte 0x80000000200060CF + .8byte 0x80000000200060CF # A .8byte 0x80000000200060CF .8byte 0x80000000200060CF .8byte 0x80000000200060CF @@ -162,8 +162,8 @@ pagetable: .8byte 0x80000000200060CF .8byte 0x80000000200060CF - .8byte 0x80000000200060CF - .8byte 0x80000000200060CF + .8byte 0x80000000200060CF # e0 + .8byte 0x00000000200060CF # e8 .8byte 0x80000000200060CF .8byte 0x80000000200060CF From 3f3f5e83fe37c2dc984d7f20ece0504ecda724a5 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Wed, 7 May 2025 16:35:17 -0500 Subject: [PATCH 32/43] Good now I'm getting the Instruction page fault mismatch that I want to see. --- tests/coverage/misalignedInstrSpill.S | 4326 +++++++++++++++++++++++++ 1 file changed, 4326 insertions(+) create mode 100644 tests/coverage/misalignedInstrSpill.S diff --git a/tests/coverage/misalignedInstrSpill.S b/tests/coverage/misalignedInstrSpill.S new file mode 100644 index 000000000..72be421d7 --- /dev/null +++ b/tests/coverage/misalignedInstrSpill.S @@ -0,0 +1,4326 @@ +/////////////////////////////////////////// +// misalignedStoreSpill.S +// +// Written: Rose Thompson rose@rosethompson.net 07 May 2025 +// +// Purpose: Test coverage for EBU +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate + +#include "WALLY-init-lib.h" + +# run-elf.bash find this in project description +main: + li t5, 0x1 + slli t5, t5, 62 + ori t5, t5, 0xF0 + csrs menvcfg, t5 # menvcfg.PBMTE = 1, CBZE, CBCFE, CBIE all 1 + + # Page table root address at 0x80010000; SV48 + li t5, 0x9000000000080010 + csrw satp, t5 + + # sfence.vma x0, x0 + + # switch to supervisor mode + li a0, 1 + ecall + + + + li a0, 0x80000fff + j label1 + +.align 6 # start on multiple of 64 bytes / 16 instruction cache line +label1: + # test 1 + sfence.vma # flush tlb + + j instrVPNJumpPoint1 + +goback: + + # wrap up + li a0, 3 # switch back to machine mode because code at 0x80000000 may not have clean page table entry + ecall + j done + +.align 13 +labelCodeVPN1: + c.addi t1, 4 + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + 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lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb +instrVPNJumpPoint1: + sfence.vma + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + lui t1, 0xdeadb + j goback + +.data + +.align 16 +# root Page table situated at 0x80010000 +pagetable: + .8byte 0x20004401 # 0x00000000-0x80_00000000: PTE at 0x80011000 01 valid + .8byte 0x000000000000100F # misaligned terapage at 0x80_00000000 + +# next page table at 0x80011000 +.align 12 + .8byte 0x000000000000100F # misaligned gigapage at 0x00000000 + .8byte 0x0000000020005801 # PTE for pages at 0x40000000 + .8byte 0x0000000020004801 # + + +# Next page table at 0x80012000 for gigapage at 0x80000000 +.align 12 + .8byte 0x0000000020004C01 # for VA starting at 80000000 (pointer to NAPOT 64 KiB pages) + .8byte 0x0000000020014C0F # for VA starting at 80200000 (misaligned megapage) + .8byte 0x0000000020005001 # for VA starting at 80400000 (bad PBMT pages) + .8byte 0x4000000020004C01 # for VA starting at 80600000 (bad entry: nonleaf PTE can't have PBMT != 0) + .8byte 0x0000000020005401 # for VA starting at 80800000 (testing rwx permissiosn with cbom/cboz) + .8byte 0x0000000020005801 # for VA starting at 80A00000 (pointer to NAPOT 64 KiB pages like at 80000000) + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + .8byte 0x0000000020004C01 + +# Leaf page table at 0x80013000 with NAPOT pages +.align 12 + #80000000 + .8byte 0x00000000200020CF + .8byte 0x00000000200020CF + .8byte 0x0000000000000000 # this is in invalid so that the second half of the access causes a fault + .8byte 0x00000000200020CF + + .8byte 0x00000000200020CF + .8byte 0x00000000200020CF + .8byte 0x00000000200020CF + .8byte 0x00000000200020CF + + .8byte 0x00000000200020CF + .8byte 0x00000000200020CF + .8byte 0x00000000200020CF + .8byte 0x00000000200020CF + + .8byte 0x00000000200020CF + .8byte 0x00000000200020CF + .8byte 0x00000000200020CF + .8byte 0x00000000200020CF + + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + + .8byte 0x80000000200060CF # A + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + + .8byte 0x80000000200060CF # e0 + .8byte 0x00000000200060CF # e8 + #.8byte 0x0 # e8 + #.8byte 0x80000000200060CF + .8byte 0x0 + .8byte 0x80000000200060CF + + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + + .8byte 0x800000002000E0CF + .8byte 0x800000002000E0CF + .8byte 0x800000002000E0CF + .8byte 0x800000002000E0CF + + .8byte 0x800000002000E0CF + .8byte 0x800000002000E0CF + +# Leaf page table at 0x80014000 with PBMT pages +.align 12 + #80400000 + .8byte 0x60000000200020CF # reserved entry + +# Leaf page table at 0x80015000 with various permissions for testing CBOM and CBOZ +.align 12 + #80800000 + .8byte 0x00000000200000CF # valid rwx for VA 80800000 + .8byte 0x00000000200000CB # valid r x for VA 80801000 + .8byte 0x00000000200000C3 # valid r for VA 80802000 + .8byte 0x00000000200000C9 # valid x for VA 80803000 + .8byte 0x00000000200000CD # valid wx for VA 80804000 (illegal combination, but used to test tlbcontrol) + .8byte 0x000000002000000F # valid rwx for VA 80805000 for covering ITLB translate and UpdateDA + .8byte 0x20000000200000CF # PBMT=1 for VA 80806000 for covering ITLB BadPBMT + +# Leaf page table at 0x80016000 with NAPOT pages +.align 12 + .8byte 0xA0000000200020CF + .8byte 0xA0000000200020CF + .8byte 0xA0000000200020CF + .8byte 0xA0000000200020CF From d71b88bb210460c98535bc23d2ac70ecacaad09e Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 7 May 2025 22:35:12 -0700 Subject: [PATCH 33/43] Update nightly to delete cvw directories after 1 week instead of 1 day --- bin/nightly_build.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bin/nightly_build.py b/bin/nightly_build.py index 9c6250eda..82530dead 100755 --- a/bin/nightly_build.py +++ b/bin/nightly_build.py @@ -830,14 +830,14 @@ def main(): ############################################# # DELETE REPOSITORY OF PREVIOUS NIGHTLYS # ############################################# - threshold = time.time() - 86400*1 + threshold = time.time() - 86400*7 # 1 week for log_dir in os.listdir(args.path): try: cvw_dir = os.path.join(args.path,log_dir,"cvw") cvw_mtime = os.stat(cvw_dir).st_mtime if cvw_mtime < threshold: - logger.info(f"Found {cvw_dir} older than 1 day, removing") + logger.info(f"Found {cvw_dir} older than 1 week, removing") shutil.rmtree(cvw_dir) except Exception as e: if os.path.exists(cvw_dir): From 5271234591aabf4bcc05b515edfd82087956a564 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 8 May 2025 00:15:48 -0700 Subject: [PATCH 34/43] Fix lots of spelling errors --- .github/workflows/lint.yml | 2 +- .../coremark/riscv64-baremetal/core_portme.c | 4 +- .../coremark/riscv64-baremetal/core_portme.h | 2 +- benchmarks/coremark/riscv64-baremetal/link.ld | 4 +- bin/exe2memfile.pl | 4 +- bin/extractFunctionRadix.sh | 4 +- bin/iterelf | 4 +- bin/nightly_build.py | 20 ++++----- bin/parseHPMC.py | 18 ++++---- bin/wally-distro-check.sh | 2 +- bin/wally-package-install.sh | 2 +- bin/wally-tool-chain-install.sh | 6 +-- docs/docker/Makefile | 2 +- docs/docker/README.md | 6 +-- examples/C/common/test.ld | 4 +- examples/C/fir/fir.c | 2 +- examples/crypto/aes/aes.c | 2 +- .../exercises/fma16/synthDC/scripts/synth.tcl | 4 +- fpga/rvvidaemon/rvvidaemon.c | 2 +- fpga/src/fpgaTopArtyA7.sv | 4 +- fpga/zsbl/gpt.c | 2 +- fpga/zsbl/sd.c | 2 +- linux/qemuBoot.sh | 2 +- sim/questa/coverage-exclusions-rv64gc.do | 4 +- sim/questa/wally.do | 2 +- sim/verilator/Makefile | 2 +- src/cache/cachefsm.sv | 6 +-- src/cache/cacheway.sv | 2 +- src/cvw.sv | 2 +- src/ebu/ahbcacheinterface.sv | 2 +- src/ebu/ebu.sv | 2 +- src/ebu/ebufsmarb.sv | 4 +- src/fpu/fctrl.sv | 12 +++--- src/fpu/fcvt.sv | 20 ++++----- src/fpu/fdivsqrt/fdivsqrtexpcalc.sv | 2 +- src/fpu/fdivsqrt/fdivsqrtpreproc.sv | 8 ++-- src/fpu/fhazard.sv | 6 +-- src/fpu/fma/fmaadd.sv | 4 +- src/fpu/fma/fmaalign.sv | 6 +-- src/fpu/fma/fmasign.sv | 2 +- src/fpu/fpu.sv | 6 +-- src/fpu/fregfile.sv | 2 +- src/fpu/postproc/cvtshiftcalc.sv | 10 ++--- src/fpu/postproc/divshiftcalc.sv | 4 +- src/fpu/postproc/flags.sv | 16 +++---- src/fpu/postproc/fmashiftcalc.sv | 2 +- src/fpu/postproc/postprocess.sv | 16 +++---- src/fpu/postproc/resultsign.sv | 6 +-- src/fpu/postproc/round.sv | 6 +-- src/fpu/postproc/roundsign.sv | 2 +- src/fpu/postproc/shiftcorrection.sv | 14 +++---- src/fpu/postproc/specialcase.sv | 8 ++-- src/fpu/unpackinput.sv | 16 +++---- src/generic/mem/ram1p1rwbe_64x22.sv | 2 +- src/generic/priorityonehot.sv | 2 +- src/generic/prioritythermometer.sv | 2 +- src/hazard/hazard.sv | 4 +- src/ieu/aes/aes64ks1i.sv | 2 +- src/ieu/bmu/bitmanipalu.sv | 2 +- src/ieu/bmu/bmuctrl.sv | 4 +- src/ieu/controller.sv | 4 +- src/ieu/shifter.sv | 2 +- src/ifu/bpred/bpred.sv | 4 +- src/ifu/bpred/btb.sv | 2 +- src/ifu/ifu.sv | 6 +-- src/ifu/irom.sv | 4 +- src/lsu/align.sv | 4 +- src/lsu/lrsc.sv | 2 +- src/lsu/lsu.sv | 6 +-- src/mdu/div.sv | 2 +- src/mdu/mdu.sv | 2 +- src/mmu/hptw.sv | 6 +-- src/mmu/mmu.sv | 8 ++-- src/mmu/pmachecker.sv | 4 +- src/mmu/pmpadrdec.sv | 2 +- src/mmu/pmpchecker.sv | 2 +- src/mmu/tlb/tlbcamline.sv | 2 +- src/mmu/tlb/tlbcontrol.sv | 2 +- src/mmu/tlb/tlbmixer.sv | 2 +- src/privileged/csrsr.sv | 8 ++-- src/privileged/privdec.sv | 2 +- src/privileged/privileged.sv | 4 +- src/privileged/trap.sv | 2 +- src/rvvi/rvvisynth.sv | 2 +- src/uncore/clint_apb.sv | 2 +- src/uncore/plic_apb.sv | 4 +- src/uncore/ram_ahb.sv | 2 +- src/uncore/spi_apb.sv | 2 +- src/uncore/uartPC16550D.sv | 16 +++---- src/uncore/uart_apb.sv | 2 +- src/uncore/uncore.sv | 6 +-- synthDC/ppa/ppaAnalyze.py | 2 +- synthDC/scripts/synth.tcl | 4 +- synthDC/wallySynth.py | 2 +- testbench/common/functionName.sv | 6 +-- testbench/common/loggers.sv | 6 +-- testbench/common/ramxdetector.sv | 4 +- testbench/common/riscvassertions.sv | 4 +- testbench/common/rvvitbwrapper.sv | 2 +- testbench/sdc/sd_defines.h | 2 +- testbench/testbench.sv | 8 ++-- testbench/testbench_fp.sv | 26 ++++++------ testbench/tests.vh | 6 +-- testbench/trek_files/trek_user_backdoor.sv | 2 +- tests/coverage/Makefile | 2 +- tests/coverage/amoAccessFault.S | 2 +- tests/coverage/btbthrash.S | 4 +- tests/coverage/csrwrites.S | 2 +- tests/coverage/dcache1.py | 6 +-- tests/coverage/ebu.S | 4 +- tests/coverage/fpu.S | 6 +-- tests/coverage/gshare.S | 2 +- tests/coverage/hptwAccessFault.S | 2 +- tests/coverage/ieu.S | 4 +- tests/coverage/ifu.S | 2 +- tests/coverage/ifuCamlineWrite.S | 2 +- tests/coverage/lsu.S | 2 +- tests/coverage/nonleafpbmtfault.S | 2 +- tests/coverage/priv.S | 2 +- tests/coverage/tlbASID.S | 2 +- tests/coverage/tlbGLB.S | 4 +- tests/coverage/tlbGP.S | 2 +- tests/coverage/tlbMP.S | 2 +- tests/coverage/tlbMisaligned.S | 4 +- tests/coverage/tlbNAPOT.S | 2 +- tests/coverage/tlbTP.S | 2 +- tests/coverage/tlbmisc.S | 4 +- tests/coverage/vm64check.S | 2 +- tests/fp/README.md | 2 +- .../fp/combined_IF_vectors/IF_vectors/README | 2 +- tests/riscof/makefile-memfile | 2 +- tests/riscof/spike/riscof_spike.py | 4 +- .../riscv-test-suite/env/arch_test.h | 20 ++++----- .../riscv-test-suite/env/test_macros.h | 2 +- .../references/WALLY-spi-01.reference_output | 4 +- .../WALLY-status-mie-01.reference_output | 2 +- .../WALLY-status-sie-01.reference_output | 2 +- .../references/WALLY-trap-01.reference_output | 8 ++-- .../WALLY-trap-s-01.reference_output | 8 ++-- .../WALLY-trap-u-01.reference_output | 8 ++-- .../rv32i_m/privilege/src/WALLY-TEST-LIB-32.h | 42 +++++++++---------- .../privilege/src/WALLY-csr-permission-s-01.S | 2 +- .../privilege/src/WALLY-csr-permission-u-01.S | 2 +- .../privilege/src/WALLY-endianness-01.S | 2 +- .../rv32i_m/privilege/src/WALLY-misa-01.S | 2 +- .../rv32i_m/privilege/src/WALLY-mmu-sv32-01.S | 2 +- .../privilege/src/WALLY-mmu-sv32-svadu-01.S | 4 +- .../rv32i_m/privilege/src/WALLY-periph-01.S | 2 +- .../rv32i_m/privilege/src/WALLY-periph-s-01.S | 2 +- .../privilege/src/WALLY-satp-invalid-01.S | 4 +- .../rv32i_m/privilege/src/WALLY-sie-01.S | 2 +- .../rv32i_m/privilege/src/WALLY-spi-01.S | 28 ++++++------- .../privilege/src/WALLY-status-sie-01.S | 2 +- .../rv32i_m/privilege/src/WALLY-trap-s-01.S | 2 +- .../rv32i_m/privilege/src/WALLY-trap-u-01.S | 4 +- .../privilege/src/WALLY-uart-timeout-01.S | 2 +- .../references/WALLY-pma-01.reference_output | 2 +- .../references/WALLY-pmp-01.reference_output | 2 +- .../references/WALLY-spi-01.reference_output | 4 +- .../WALLY-status-mie-01.reference_output | 2 +- .../WALLY-status-sie-01.reference_output | 2 +- .../references/WALLY-trap-01.reference_output | 8 ++-- .../WALLY-trap-s-01.reference_output | 8 ++-- .../WALLY-trap-u-01.reference_output | 8 ++-- .../rv64i_m/privilege/src/WALLY-TEST-LIB-64.h | 40 +++++++++--------- .../privilege/src/WALLY-csr-permission-s-01.S | 4 +- .../privilege/src/WALLY-csr-permission-u-01.S | 2 +- .../privilege/src/WALLY-endianness-01.S | 2 +- .../rv64i_m/privilege/src/WALLY-misa-01.S | 2 +- .../rv64i_m/privilege/src/WALLY-mmu-sv39-01.S | 4 +- .../WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S | 4 +- .../rv64i_m/privilege/src/WALLY-mmu-sv48-01.S | 2 +- .../privilege/src/WALLY-mmu-sv48-svadu-01.S | 2 +- .../rv64i_m/privilege/src/WALLY-periph-01.S | 2 +- .../privilege/src/WALLY-satp-invalid-01.S | 4 +- .../rv64i_m/privilege/src/WALLY-sie-01.S | 2 +- .../rv64i_m/privilege/src/WALLY-spi-01.S | 28 ++++++------- .../privilege/src/WALLY-status-sie-01.S | 2 +- .../rv64i_m/privilege/src/WALLY-trap-s-01.S | 2 +- .../rv64i_m/privilege/src/WALLY-trap-u-01.S | 4 +- 180 files changed, 443 insertions(+), 443 deletions(-) diff --git a/.github/workflows/lint.yml b/.github/workflows/lint.yml index f4c7501d5..00517e77c 100644 --- a/.github/workflows/lint.yml +++ b/.github/workflows/lint.yml @@ -21,7 +21,7 @@ jobs: name: Lint (Python ${{matrix.version}}) strategy: matrix: - version: [39, 312] # Test on oldest and newest verions used in wally-package-install.sh + version: [39, 312] # Test on oldest and newest versions used in wally-package-install.sh runs-on: ubuntu-latest steps: diff --git a/benchmarks/coremark/riscv64-baremetal/core_portme.c b/benchmarks/coremark/riscv64-baremetal/core_portme.c index 017bef74e..50f909851 100755 --- a/benchmarks/coremark/riscv64-baremetal/core_portme.c +++ b/benchmarks/coremark/riscv64-baremetal/core_portme.c @@ -194,7 +194,7 @@ void stop_time(void) { Actual value returned may be cpu cycles, milliseconds or any other value, as long as it can be converted to seconds by . - This methodology is taken to accomodate any hardware or simulated platform. + This methodology is taken to accommodate any hardware or simulated platform. The sample implementation returns millisecs by default, and the resolution is controlled by */ @@ -213,7 +213,7 @@ CORE_TICKS get_time(void) { /* Function: time_in_secs Convert the value returned by get_time to seconds. - The type is used to accomodate systems with no support for floating point. + The type is used to accommodate systems with no support for floating point. Default implementation implemented by the EE_TICKS_PER_SEC macro above. */ secs_ret time_in_secs(CORE_TICKS ticks) { diff --git a/benchmarks/coremark/riscv64-baremetal/core_portme.h b/benchmarks/coremark/riscv64-baremetal/core_portme.h index 8db43d20a..83020bd04 100755 --- a/benchmarks/coremark/riscv64-baremetal/core_portme.h +++ b/benchmarks/coremark/riscv64-baremetal/core_portme.h @@ -99,7 +99,7 @@ typedef clock_t CORE_TICKS; #endif /* Data Types: - To avoid compiler issues, define the data types that need ot be used for 8b, 16b and 32b in . + To avoid compiler issues, define the data types that need to be used for 8b, 16b and 32b in . *Imprtant*: ee_ptr_int needs to be the data type used to hold pointers, otherwise coremark may fail!!! diff --git a/benchmarks/coremark/riscv64-baremetal/link.ld b/benchmarks/coremark/riscv64-baremetal/link.ld index 4f8892ee2..335cf326a 100644 --- a/benchmarks/coremark/riscv64-baremetal/link.ld +++ b/benchmarks/coremark/riscv64-baremetal/link.ld @@ -9,7 +9,7 @@ /* The OUTPUT_ARCH command specifies the machine architecture where the argument is one of the names used in the BFD library. More - specifically one of the entires in bfd/cpu-mips.c */ + specifically one of the entries in bfd/cpu-mips.c */ OUTPUT_ARCH( "riscv" ) ENTRY(_start) @@ -60,7 +60,7 @@ SECTIONS *(.tbss.end) } - /* End of uninitalized data segement */ + /* End of uninitialized data segment */ _end = .; } diff --git a/bin/exe2memfile.pl b/bin/exe2memfile.pl index 2d09c1fdb..bab777151 100755 --- a/bin/exe2memfile.pl +++ b/bin/exe2memfile.pl @@ -94,7 +94,7 @@ for(my $i=0; $i<=$#ARGV; $i++) { # if (/^\s*(\S\S\S\S\S\S\S\S):\s+(.*)/) { # changed to \t 30 Oct 2021 dmh to fix parsing issue in d_fmadd_b17 if (/^\s*(\S\S\S\S\S\S\S\S):\s+(.*)/) { $address = &fixadr($1); - # print "addresss $address maxaddress $maxaddress\n"; + # print "address $address maxaddress $maxaddress\n"; if ($address > $maxaddress) { $maxaddress = $address; } #print "test $address $1 $2\n"; my $lineorig = $2; @@ -157,7 +157,7 @@ for(my $i=0; $i<=$#ARGV; $i++) { print("\n"); sub emitData { - # print the data portion of the ELF into a memroy file, including 0s for empty stuff + # print the data portion of the ELF into a memory file, including 0s for empty stuff # deal with endianness my $address = shift; my $payload = shift; diff --git a/bin/extractFunctionRadix.sh b/bin/extractFunctionRadix.sh index c9446a3b5..19274075b 100755 --- a/bin/extractFunctionRadix.sh +++ b/bin/extractFunctionRadix.sh @@ -8,10 +8,10 @@ ## Created: March 1, 2021 ## Modified: March 10, 2021 ## -## Purpose: Processes all compiled object files into 2 types of files which assist in debuging applications. +## Purpose: Processes all compiled object files into 2 types of files which assist in debugging applications. ## File 1: .addr: A sorted list of function starting addresses. ## When a the PCE is greater than or equal to the function's starting address, the label will be associated with this address. -## File 2: .lab: A sorted list of funciton labels. The names of functions. Modelsim will display these names rather than the function address. +## File 2: .lab: A sorted list of function labels. The names of functions. Modelsim will display these names rather than the function address. ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/iterelf b/bin/iterelf index 64c537a92..55e6e7262 100755 --- a/bin/iterelf +++ b/bin/iterelf @@ -35,7 +35,7 @@ def search_log_for_mismatches(logfile): return os.system(grepcmd) == 0 def run_test_case(elf): - """Run the given test case, and return 0 if the test suceeds and 1 if it fails""" + """Run the given test case, and return 0 if the test succeeds and 1 if it fails""" WALLY = os.environ.get("WALLY") fields = elf.rsplit("/", 3) if fields[2] == "ref": @@ -70,7 +70,7 @@ parser.add_argument("--config", help="Configuration", default="rv64gc") parser.add_argument("--sim", "-s", help="Simulator", choices=["questa", "vcs"], default="questa") parser.add_argument("--coverage", "-c", help="Code & Functional Coverage", action="store_true") parser.add_argument("--fcov", "-f", help="Code & Functional Coverage", action="store_true") -parser.add_argument("--exclude", help="Exclude files with this sufix", default="my.elf") +parser.add_argument("--exclude", help="Exclude files with this suffix", default="my.elf") args = parser.parse_args() # find all ELF files in directory diff --git a/bin/nightly_build.py b/bin/nightly_build.py index 9c6250eda..c6f5d2c78 100755 --- a/bin/nightly_build.py +++ b/bin/nightly_build.py @@ -167,7 +167,7 @@ class FolderManager: None """ cvw = folder.joinpath("cvw") - tmp_folder = os.path.join(cvw, "tmp") # temprorary files will be stored in here + tmp_folder = os.path.join(cvw, "tmp") # temporary files will be stored in here if not cvw.exists(): os.system(f"git clone --recurse-submodules {repo_url} {cvw}") os.makedirs(tmp_folder) @@ -196,7 +196,7 @@ class TestRunner: folder: the "nightly-runs/repos/" Returns: - bool: True if the script is copied successfuly, False otherwise. + bool: True if the script is copied successfully, False otherwise. """ # Get today's date in YYYY-MM-DD format self.todays_date = datetime.now().strftime("%Y-%m-%d") @@ -346,9 +346,9 @@ class TestRunner: result = subprocess.run(command, stdout=f, stderr=subprocess.STDOUT, text=True, shell=True, executable="/bin/bash") except Exception as e: self.logger.error(f"There was an error in running the tests in the run_tests function: {e}") - # Check if the command executed successfuly + # Check if the command executed successfully if result.returncode or result.returncode == 0: - self.logger.info(f"Test ran successfuly. Test name: {test_name}, test extension: {' '.join(test_extensions)}") + self.logger.info(f"Test ran successfully. Test name: {test_name}, test extension: {' '.join(test_extensions)}") return True, output_file else: self.logger.error(f"Error making test. Test name: {test_name}, test extension: {' '.join(test_extensions)}") @@ -763,7 +763,7 @@ def main(): output_log_list = [] # a list where the output markdown file locations will be saved to total_number_failures = 0 # an integer where the total number failures from all of the tests will be collected - total_number_success = 0 # an integer where the total number of sucess will be collected + total_number_success = 0 # an integer where the total number of successes will be collected total_failures = [] total_success = [] @@ -772,21 +772,21 @@ def main(): check, output_location = test_runner.run_tests(test_type=test_type, test_name=test_name, test_extensions=test_extensions) try: - if check: # this checks if the test actually ran successfuly + if check: # this checks if the test actually ran successfully output_log_list.append(output_location) - logger.info(f"{test_name} ran successfuly. Output location: {output_location}") + logger.info(f"{test_name} ran successfully. Output location: {output_location}") # format tests to markdown try: passed, failed = test_runner.clean_format_output(input_file = output_location) logger.info(f"{test_name} has been formatted to markdown") except: - logger.error(f"Error occured with formatting {test_name}") + logger.error(f"Error occurred with formatting {test_name}") logger.info(f"The # of failures are for {test_name}: {len(failed)}") total_number_failures+= len(failed) total_failures.append(failed) - logger.info(f"The # of sucesses are for {test_name}: {len(passed)}") + logger.info(f"The # of successes are for {test_name}: {len(passed)}") total_number_success += len(passed) total_success.append(passed) test_runner.rewrite_to_markdown(test_name, passed, failed) @@ -797,7 +797,7 @@ def main(): except Exception as e: logger.error(f"There was an error in running the tests: {e}") - logger.info(f"The total sucesses for all tests ran are: {total_number_success}") + logger.info(f"The total successes for all tests ran are: {total_number_success}") logger.info(f"The total failures for all tests ran are: {total_number_failures}") # Copy actual test logs from sim/questa, sim/verilator, sim/vcs diff --git a/bin/parseHPMC.py b/bin/parseHPMC.py index f845ba68c..6dbf726a2 100755 --- a/bin/parseHPMC.py +++ b/bin/parseHPMC.py @@ -45,7 +45,7 @@ RefDataBTB = [('BTBCModel6', 'BTBCModel', 64, 128, 1.51480272475844), ('BTBCMode def ParseBranchListFile(path): '''Take the path to the list of Questa Sim log files containing the performance counters outputs. File - is formated in row columns. Each row is a trace with the file, branch predictor type, and the parameters. + is formatted in row columns. Each row is a trace with the file, branch predictor type, and the parameters. parameters can be any number and depend on the predictor type. Returns a list of lists.''' lst = [] with open(path) as BranchList: @@ -59,7 +59,7 @@ def ParseBranchListFile(path): return lst def ProcessFile(fileName): - '''Extract preformance counters from a modelsim log. Outputs a list of tuples for each test/benchmark. + '''Extract performance counters from a modelsim log. Outputs a list of tuples for each test/benchmark. The tuple contains the test name, optimization characteristics, and dictionary of performance counters.''' # 1 find lines with Read memfile and extract test name # 2 parse counters into a list of (name, value) tuples (dictionary maybe?) @@ -328,23 +328,23 @@ def ReportAsGraph(benchmarkDict, bar, FileName): markers = ['x', '.', '+', '*', '^', 'o', ',', 's'] colors = ['blue', 'black', 'gray', 'dodgerblue', 'lightsteelblue', 'turquoise', 'black', 'blue'] - # the benchmarkDict['Mean'] contains sequencies of results for multiple + # the benchmarkDict['Mean'] contains sequences of results for multiple # branch predictors with various parameterizations # group the parameterizations by the common typ. - sequencies = {} + sequences = {} for (name, typ, entries, size, value) in benchmarkDict['Mean']: - if typ not in sequencies: - sequencies[typ] = [(entries if not args.size else int(size/8), value)] + if typ not in sequences: + sequences[typ] = [(entries if not args.size else int(size/8), value)] else: - sequencies[typ].append((entries if not args.size else int(size/8) ,value)) + sequences[typ].append((entries if not args.size else int(size/8) ,value)) # then graph the common typ as a single line+scatter plot # finally repeat for all typs of branch predictors and overlay fig, axes = plt.subplots() index = 0 if(args.invert): plt.title(titlesInvert[ReportPredictorType]) else: plt.title(titles[ReportPredictorType]) - for branchPredName in sequencies: - data = sequencies[branchPredName] + for branchPredName in sequences: + data = sequences[branchPredName] (xdata, ydata) = zip(*data) if args.invert: ydata = [100 - x for x in ydata] axes.plot(xdata, ydata, color=colors[index]) diff --git a/bin/wally-distro-check.sh b/bin/wally-distro-check.sh index 2f24c3daf..0ea7fdaf3 100755 --- a/bin/wally-distro-check.sh +++ b/bin/wally-distro-check.sh @@ -6,7 +6,7 @@ ## Created: 30 June 2024 ## Modified: ## -## Purpose: Check for compatible Linux distibution and set variables accordingly +## Purpose: Check for compatible Linux distribution and set variables accordingly ## ## A component of the CORE-V-WALLY configurable RISC-V project. ## https://github.com/openhwgroup/cvw diff --git a/bin/wally-package-install.sh b/bin/wally-package-install.sh index d7ca0a718..7c7285b1c 100755 --- a/bin/wally-package-install.sh +++ b/bin/wally-package-install.sh @@ -62,7 +62,7 @@ case "$FAMILY" in SPIKE_PACKAGES+=(dtc boost-regex boost-system) VERILATOR_PACKAGES+=(gperftools mold) BUILDROOT_PACKAGES+=(ncurses ncurses-base ncurses-libs ncurses-devel gcc-gfortran) # gcc-gfortran is only needed for compiling spec benchmarks on buildroot linux - # Extra packages not availale in rhel8, nice for Verilator + # Extra packages not available in rhel8, nice for Verilator if (( RHEL_VERSION >= 9 )); then VERILATOR_PACKAGES+=(perl-doc) fi diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index c40b23592..ddbf7372b 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -236,9 +236,9 @@ pip install --upgrade pip && pip install --upgrade -r "$dir"/requirements.txt source "$RISCV"/riscv-python/bin/activate # reload python virtual environment echo -e "${SUCCESS_COLOR}Python environment successfully configured!${ENDC}" -# Extra dependecies needed for older distros that don't have new enough versions available from package manager +# Extra dependencies needed for older distros that don't have new enough versions available from package manager if (( RHEL_VERSION == 8 )) || (( UBUNTU_VERSION == 20 )); then - # Newer versin of glib required for QEMU. + # Newer version of glib required for QEMU. # Anything newer than this won't build on red hat 8 STATUS="glib" if [ ! -e "$RISCV"/include/glib-2.0 ]; then @@ -480,7 +480,7 @@ fi # Buildroot and Linux testvectors -# Buildroot is used to boot a minimal versio of Linux on Wally. +# Buildroot is used to boot a minimal version of Linux on Wally. # Testvectors are generated using QEMU. if [ ! "$no_buidroot" ]; then section_header "Installing Buildroot and Creating Linux testvectors" diff --git a/docs/docker/Makefile b/docs/docker/Makefile index 82560d8cb..88a30a0d0 100644 --- a/docs/docker/Makefile +++ b/docs/docker/Makefile @@ -1,7 +1,7 @@ QUESTA_HOME?=/cad/mentor/questa_sim-2023.4 CVW_GIT?="" -commanline: +commandline: podman run -it --rm \ -v cvw_temp:/home/cad/cvw \ -v $(QUESTA_HOME):/cad/mentor/questa_sim-xxxx.x_x \ diff --git a/docs/docker/README.md b/docs/docker/README.md index e21e53211..c2c5d1168 100644 --- a/docs/docker/README.md +++ b/docs/docker/README.md @@ -1,4 +1,4 @@ -# Consistant Build of Toolchain for Wally +# Consistent Build of Toolchain for Wally `Dockerfile.*` contains a ~~multi-stage~~ build for all the toolchains that are required for Wally's open-source features. @@ -69,7 +69,7 @@ Files at this folder can help you to build/fetch environment you need to run wal Here are some common use cases, it will **provides you an environment with RISC-V toolchains** that required by this project: ```shell -# By default, we assume that you have cloned the cvw respository and running the script at relative path `docs/docker` +# By default, we assume that you have cloned the cvw repository and running the script at relative path `docs/docker` # For HMC students, /opt/riscv is available and nothing needs to be built TOOLCHAINS_MOUNT=/opt/riscv QUESTA=/cad/mentor/questa_sim-2023.4 ./start.sh @@ -265,7 +265,7 @@ There are at least two ways to solve this problem: There are stages in the old Dockerfile: -- debian-based package installtion +- debian-based package installation - apt package - python3 package - user and its group configuration diff --git a/examples/C/common/test.ld b/examples/C/common/test.ld index 5eccb434c..587db3b91 100644 --- a/examples/C/common/test.ld +++ b/examples/C/common/test.ld @@ -9,7 +9,7 @@ /* The OUTPUT_ARCH command specifies the machine architecture where the argument is one of the names used in the BFD library. More - specifically one of the entires in bfd/cpu-mips.c */ + specifically one of the entries in bfd/cpu-mips.c */ OUTPUT_ARCH( "riscv" ) ENTRY(_start) @@ -60,7 +60,7 @@ SECTIONS _tbss_end = .; } - /* End of uninitalized data segement */ + /* End of uninitialized data segment */ _end = .; } diff --git a/examples/C/fir/fir.c b/examples/C/fir/fir.c index bbc5a1e1c..6505be229 100644 --- a/examples/C/fir/fir.c +++ b/examples/C/fir/fir.c @@ -33,7 +33,7 @@ int main(void) { int tmp = Y[i]; printf("Y[%d] = %d\n", i, tmp); } - // verifyDouble doesn't work exaclty because of rounding, so check for almost equal + // verifyDouble doesn't work exactly because of rounding, so check for almost equal for (int i=0; i<15; i++) { if (fabs(Y[i] - Yexpected[i]) > 1e-10) { return 1; diff --git a/examples/crypto/aes/aes.c b/examples/crypto/aes/aes.c index 6744169b3..30f0d7b6e 100644 --- a/examples/crypto/aes/aes.c +++ b/examples/crypto/aes/aes.c @@ -273,7 +273,7 @@ void mixColumn(unsigned char *column) { column[3] = b[3] ^ a[2] ^ a[1] ^ gfmul(a[0], 3); } -// The rounds in the specifcation of CIPHER() are composed of the following 4 byte-oriented +// The rounds in the specification of CIPHER() are composed of the following 4 byte-oriented // transformations on the state (Section 5.1 of FIPS 197) - outputs hex after each step void aes_cipher(unsigned char *state, unsigned char *roundKey) { subBytes(state); diff --git a/examples/exercises/fma16/synthDC/scripts/synth.tcl b/examples/exercises/fma16/synthDC/scripts/synth.tcl index b7bb6b7d8..573e5a8d1 100755 --- a/examples/exercises/fma16/synthDC/scripts/synth.tcl +++ b/examples/exercises/fma16/synthDC/scripts/synth.tcl @@ -230,11 +230,11 @@ set verilogout_no_tri true set verilogout_equation false # setting to generate output files -set write_v 1 ;# generates structual netlist +set write_v 1 ;# generates structural netlist set write_sdc 1 ;# generates synopsys design constraint file for p&r set write_ddc 1 ;# compiler file in ddc format set write_sdf 1 ;# sdf file for backannotated timing sim -set write_pow 1 ;# genrates estimated power report +set write_pow 1 ;# generates estimated power report set write_rep 1 ;# generates estimated area and timing report set write_cst 1 ;# generate report of constraints set write_hier 1 ;# generate hierarchy report diff --git a/fpga/rvvidaemon/rvvidaemon.c b/fpga/rvvidaemon/rvvidaemon.c index 3ac9c6f43..3a3d459d4 100644 --- a/fpga/rvvidaemon/rvvidaemon.c +++ b/fpga/rvvidaemon/rvvidaemon.c @@ -169,7 +169,7 @@ int main(int argc, char **argv){ if (ioctl(sockfd, SIOCGIFINDEX, &ifopts) < 0) perror("SIOCGIFINDEX"); - /* Allow the socket to be reused - incase connection is closed prematurely */ + /* Allow the socket to be reused - in case connection is closed prematurely */ if (setsockopt(sockfd, SOL_SOCKET, SO_REUSEADDR, &sockopt, sizeof sockopt) == -1) { perror("setsockopt"); close(sockfd); diff --git a/fpga/src/fpgaTopArtyA7.sv b/fpga/src/fpgaTopArtyA7.sv index 07c66ff95..c4f149f14 100644 --- a/fpga/src/fpgaTopArtyA7.sv +++ b/fpga/src/fpgaTopArtyA7.sv @@ -223,7 +223,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) // the ddr3 mig7 requires 2 input clocks // 1. sys clock which is 167 MHz = ddr3 clock / 4 // 2. a second clock which is 200 MHz - // Wally requires a slower clock. At this point I don't know what speed the atrix 7 will run so I'm initially targetting 25Mhz. + // Wally requires a slower clock. At this point I don't know what speed the atrix 7 will run so I'm initially targeting 25Mhz. // the mig will output a clock at 1/4 the sys clock or 41Mhz which might work with wally so we may be able to simplify the logic a lot. mmcm mmcm(.clk_out1(clk167), .clk_out2(clk200), @@ -486,7 +486,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) localparam [31:0] RVVI_INIT_TIME_OUT = 32'd100000000; localparam [31:0] RVVI_PACKET_DELAY = 32'd400; - // pipeline controlls + // pipeline controls logic StallE, StallM, StallW, FlushE, FlushM, FlushW; // required logic [P.XLEN-1:0] PCM; diff --git a/fpga/zsbl/gpt.c b/fpga/zsbl/gpt.c index e21176f05..241a9772f 100644 --- a/fpga/zsbl/gpt.c +++ b/fpga/zsbl/gpt.c @@ -51,7 +51,7 @@ int gpt_load_partitions() { BYTE lba2_buf[512]; ret = disk_read(lba2_buf, (LBA_t)lba1->partition_entries_lba, 1); - // Load parition entries for the relevant boot partitions. + // Load partition entries for the relevant boot partitions. partition_entries_t *fdt = (partition_entries_t *)(lba2_buf); partition_entries_t *opensbi = (partition_entries_t *)(lba2_buf + 128); partition_entries_t *kernel = (partition_entries_t *)(lba2_buf + 256); diff --git a/fpga/zsbl/sd.c b/fpga/zsbl/sd.c index 1f95d8477..a84a4d6f6 100644 --- a/fpga/zsbl/sd.c +++ b/fpga/zsbl/sd.c @@ -93,7 +93,7 @@ uint64_t sd_cmd(uint8_t cmd, uint32_t arg, uint8_t crc) { } // Make interrupt pending after response fifo receives the correct - // response length. Probably unecessary so let's wait and see what + // response length. Probably unnecessary so let's wait and see what // happens. // write_reg(SPI_RXMARK, response_len); diff --git a/linux/qemuBoot.sh b/linux/qemuBoot.sh index 9cef11bc5..9f4fbb36c 100755 --- a/linux/qemuBoot.sh +++ b/linux/qemuBoot.sh @@ -38,5 +38,5 @@ qemu-system-riscv64 \ -kernel "$IMAGES"/Image \ -initrd "$IMAGES"/rootfs.cpio \ -dtb "$IMAGES"/wally-virt.dtb \ - -cpu rva22s64,zicond=true,zfa=true,zfh=true,zcb=true,zbc=true,zkn=true,sstc=true,svadu=true,svnapot=true \ + -cpu rva22s64,zicond=true,zfa=true,zfh=true,zcb=true,zbc=true,zkn=true,sstc=true,svadu=true,svnapot=true,pmp=on,debug=off \ $GDB_FLAG diff --git a/sim/questa/coverage-exclusions-rv64gc.do b/sim/questa/coverage-exclusions-rv64gc.do index 159353660..25e12758a 100644 --- a/sim/questa/coverage-exclusions-rv64gc.do +++ b/sim/questa/coverage-exclusions-rv64gc.do @@ -197,7 +197,7 @@ coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$lin set line [GetLineNum ${SRC}/mmu/pmachecker.sv "exclusion-tag: unused-tim"] coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4 coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4 -set line [GetLineNum ${SRC}/mmu/pmachecker.sv "exclusion-tag: unused-cachable"] +set line [GetLineNum ${SRC}/mmu/pmachecker.sv "exclusion-tag: unused-cacheable"] coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2 coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2 set line [GetLineNum ${SRC}/mmu/pmachecker.sv "exclusion-tag: unused-idempotent"] @@ -440,7 +440,7 @@ coverage exclude -scope /dut/core/hzu -linerange [GetLineNum ${SRC}/hazard/hazar # Privileged #################### -# Instruction Misaligned never asserted because compresssed instructions are accepted +# Instruction Misaligned never asserted because compressed instructions are accepted coverage exclude -scope /dut/core/priv/priv/trap -linerange [GetLineNum ${SRC}/privileged/trap.sv "assign ExceptionM"] -item e 1 -fecexprrow 2 # Attempting to access fflags, frm, fcsr with mstatus.FS = 0 traps, so checking for (STATUS_FS != 2'b00) diff --git a/sim/questa/wally.do b/sim/questa/wally.do index 153cf6d22..53be9de3d 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -75,7 +75,7 @@ set SVLib "" set GUI 0 set accFlag "" -# Need to be able to pass arguments to vopt. Unforunately argv does not work because +# Need to be able to pass arguments to vopt. Unfortunately argv does not work because # it takes on different values if vsim and the do file are called from the command line or # if the do file is called from questa sim directly. This chunk of code uses the $n variables # and compacts them into a single list for passing to vopt. Shift is used to move the arguments diff --git a/sim/verilator/Makefile b/sim/verilator/Makefile index ecb6b5f42..72cfd937c 100644 --- a/sim/verilator/Makefile +++ b/sim/verilator/Makefile @@ -22,7 +22,7 @@ TESTBENCH?=testbench # constants # assume WALLY variable is correctly configured in the shell environment -# INCLUDE_PATH are pathes that Verilator should search for files it needs +# INCLUDE_PATH are paths that Verilator should search for files it needs INCLUDE_PATH="-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" "-I${WALLY}/config/deriv/$(WALLYCONF)" # SOURCES are source files SOURCES=${WALLY}/src/cvw.sv ${WALLY}/testbench/${TESTBENCH}.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index 91aa5c97b..504c6e2ab 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -62,7 +62,7 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) ( output logic ClearDirty, // Clear the dirty bit in the selected way and set output logic SelWriteback, // Overrides cached tag check to select a specific way and set for writeback output logic LRUWriteEn, // Update the LRU state - output logic SelVictim, // Overides HitWay Tag matching. Selects selects the victim tag/data regardless of hit + output logic SelVictim, // Overrides HitWay Tag matching. Selects selects the victim tag/data regardless of hit output logic FlushAdrCntEn, // Enable the counter for Flush Adr output logic FlushWayCntEn, // Enable the way counter during a flush output logic FlushCntRst, // Reset both flush counters @@ -83,7 +83,7 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) ( STATE_FETCH, STATE_WRITEBACK, STATE_WRITE_LINE, - STATE_ADDRESS_SETUP, // required for back to back reads. structural hazard on writting SRAM + STATE_ADDRESS_SETUP, // required for back to back reads. structural hazard on writing SRAM // flush cache STATE_FLUSH, STATE_FLUSH_WRITEBACK @@ -165,7 +165,7 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) ( (CurrState == STATE_WRITE_LINE & (CacheRW[0])) | (CurrState == STATE_WRITEBACK & (CMOpM[3] & CacheBusAck)); assign ClearDirty = (CurrState == STATE_WRITE_LINE & ~(CacheRW[0])) | // exclusion-tag: icache ClearDirty - (CurrState == STATE_FLUSH & LineDirty) | // This is wrong in a multicore snoop cache protocal. Dirty must be cleared concurrently and atomically with writeback. For single core cannot clear after writeback on bus ack and change flushadr. Clears the wrong set. + (CurrState == STATE_FLUSH & LineDirty) | // This is wrong in a multicore snoop cache protocol. Dirty must be cleared concurrently and atomically with writeback. For single core cannot clear after writeback on bus ack and change flushadr. Clears the wrong set. // Flush and eviction controls CurrState == STATE_WRITEBACK & (CMOpM[1] | CMOpM[2]) & CacheBusAck; assign SelVictim = (CurrState == STATE_WRITEBACK & ((~CacheBusAck & ~(CMOpM[1] | CMOpM[2])) | (CacheBusAck & CMOpM[3]))) | diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index e2db5a46c..76e5c67e0 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -42,7 +42,7 @@ module cacheway import cvw::*; #(parameter cvw_t P, input logic SetValid, // Set the valid bit in the selected way and set input logic ClearValid, // Clear the valid bit in the selected way and set input logic SetDirty, // Set the dirty bit in the selected way and set - input logic SelVictim, // Overides HitWay Tag matching. Selects selects the victim tag/data regardless of hit + input logic SelVictim, // Overrides HitWay Tag matching. Selects selects the victim tag/data regardless of hit input logic ClearDirty, // Clear the dirty bit in the selected way and set input logic FlushCache, // [0] Use SelAdr, [1] SRAM reads/writes from FlushAdr input logic VictimWay, // LRU selected this way as victim to evict diff --git a/src/cvw.sv b/src/cvw.sv index ed0493484..4c637ecf2 100644 --- a/src/cvw.sv +++ b/src/cvw.sv @@ -23,7 +23,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -// Usiing global `define statements isn't ideal in a large SystemVerilog system because +// Using global `define statements isn't ideal in a large SystemVerilog system because // of the risk of `define name conflicts across different subsystems. // Instead, CORE-V-Wally loads the appropriate configuration one time and places it in a package // that is referenced by all Wally modules but not by other subsystems. diff --git a/src/ebu/ahbcacheinterface.sv b/src/ebu/ahbcacheinterface.sv index f3fc676b0..2408322eb 100644 --- a/src/ebu/ahbcacheinterface.sv +++ b/src/ebu/ahbcacheinterface.sv @@ -53,7 +53,7 @@ module ahbcacheinterface import cvw::*; #( input logic [P.PA_BITS-1:0] CacheBusAdr, // Address of cache line input logic [P.LLEN-1:0] CacheReadDataWordM, // One word of cache line during a writeback input logic CacheableOrFlushCacheM, // Memory operation is cacheable or flushing D$ - input logic Cacheable, // Memory operation is cachable + input logic Cacheable, // Memory operation is cacheable input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch output logic CacheBusAck, // Handshake to $ indicating bus transaction completed output logic [LINELEN-1:0] FetchBuffer, // Register to hold beats of cache line as the arrive from bus diff --git a/src/ebu/ebu.sv b/src/ebu/ebu.sv index 642eb6de4..cb1127493 100644 --- a/src/ebu/ebu.sv +++ b/src/ebu/ebu.sv @@ -91,7 +91,7 @@ module ebu import cvw::*; #(parameter cvw_t P) ( assign HRESETn = ~reset; // if two requests come in at once pick one to select and save the others Address phase - // inputs. Abritration scheme is LSU always goes first. + // inputs. Arbitration scheme is LSU always goes first. //////////////////////////////////////////////////////////////////////////////////////////////////// // input stages and muxing for IFU and LSU diff --git a/src/ebu/ebufsmarb.sv b/src/ebu/ebufsmarb.sv index 853acd09b..66f85af81 100644 --- a/src/ebu/ebufsmarb.sv +++ b/src/ebu/ebufsmarb.sv @@ -59,7 +59,7 @@ module ebufsmarb ( logic [3:0] Threshold; // Number of beats derived from HBURST //////////////////////////////////////////////////////////////////////////////////////////////////// - // Aribtration scheme + // Arbitration scheme // FSM decides if arbitration needed. Arbitration is held until the last beat of // a burst is completed. //////////////////////////////////////////////////////////////////////////////////////////////////// @@ -87,7 +87,7 @@ module ebufsmarb ( // Once the LSU request is done the fsm returns to IDLE. To prevent the LSU from regaining // priority and re-issuing the same memory operation, the delayed IFUReqDelay squashes the LSU request. // This is necessary because the pipeline is stalled for the entire duration of both transactions, - // and the LSU memory request will stil be active. + // and the LSU memory request will still be active. flopr #(1) ifureqreg(HCLK, ~HRESETn, IFUReq, IFUReqDelay); assign LSUDisable = (CurrState == ARBITRATE) ? 1'b0 : (IFUReqDelay & ~(HREADY & FinalBeatD)); assign LSUSelect = (NextState == ARBITRATE) ? 1'b1: LSUReq; diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index 805d56857..8e34b3099 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -60,8 +60,8 @@ module fctrl import cvw::*; #(parameter cvw_t P) ( // register control signals output logic FRegWriteE, FRegWriteM, FRegWriteW, // FP register write enable output logic FWriteIntE, FWriteIntM, // Write to integer register - output logic [4:0] Adr1D, Adr2D, Adr3D, // adresses of each input - output logic [4:0] Adr1E, Adr2E, Adr3E, // adresses of each input + output logic [4:0] Adr1D, Adr2D, Adr3D, // addresses of each input + output logic [4:0] Adr1E, Adr2E, Adr3E, // addresses of each input // other control signals output logic IllegalFPUInstrD, // Is the instruction an illegal fpu instruction output logic FDivStartE, IDivStartE // Start division or squareroot @@ -355,12 +355,12 @@ module fctrl import cvw::*; #(parameter cvw_t P) ( // 01 - negate sign // 10 - xor sign - // rename input adresses for readability + // rename input addresses for readability assign Adr1D = InstrD[19:15]; assign Adr2D = InstrD[24:20]; assign Adr3D = InstrD[31:27]; - // D/E pipleine register + // D/E pipeline register flopenrc #(`FCTRLW+2+P.FMTBITS) DECtrlReg3(clk, reset, FlushE, ~StallE, {FRegWriteD, PostProcSelD, FResSelD, FrmD, FmtD, OpCtrlD, FWriteIntD, FCvtIntD, ZfaD, ZfaFRoundNXD, ~IllegalFPUInstrD}, {FRegWriteE, PostProcSelE, FResSelE, FrmE, FmtE, OpCtrlE, FWriteIntE, FCvtIntE, ZfaE, ZfaFRoundNXE, FPUActiveE}); @@ -372,7 +372,7 @@ module fctrl import cvw::*; #(parameter cvw_t P) ( if (P.M_SUPPORTED & P.IDIV_ON_FPU) assign IDivStartE = IntDivE; else assign IDivStartE = 1'b0; - // E/M pipleine register + // E/M pipeline register flopenrc #(14+int'(P.FMTBITS)) EMCtrlReg (clk, reset, FlushM, ~StallM, {FRegWriteE, FResSelE, PostProcSelE, FrmE, FmtE, OpCtrlE, FWriteIntE, FCvtIntE, ZfaE}, {FRegWriteM, FResSelM, PostProcSelM, FrmM, FmtM, OpCtrlM, FWriteIntM, FCvtIntM, ZfaM}); @@ -380,7 +380,7 @@ module fctrl import cvw::*; #(parameter cvw_t P) ( // renameing for readability assign FpLoadStoreM = FResSelM[1]; - // M/W pipleine register + // M/W pipeline register flopenrc #(4) MWCtrlReg(clk, reset, FlushW, ~StallW, {FRegWriteM, FResSelM, FCvtIntM}, {FRegWriteW, FResSelW, FCvtIntW}); diff --git a/src/fpu/fcvt.sv b/src/fpu/fcvt.sv index 90e8d7a23..e37675533 100644 --- a/src/fpu/fcvt.sv +++ b/src/fpu/fcvt.sv @@ -32,10 +32,10 @@ module fcvt import cvw::*; #(parameter cvw_t P) ( input logic [P.NF:0] Xm, // input's fraction input logic [P.XLEN-1:0] Int, // integer input - from IEU input logic [2:0] OpCtrl, // choose which operation (look below for values) - input logic ToInt, // is fp->int (since it's writting to the integer register) + input logic ToInt, // is fp->int (since it's writing to the integer register) input logic XZero, // is the input zero input logic [P.FMTBITS-1:0] Fmt, // the input's precision (11=quad 01=double 00=single 10=half) - output logic [P.NE:0] Ce, // the calculated expoent + output logic [P.NE:0] Ce, // the calculated exponent output logic [P.LOGCVTLEN-1:0] ShiftAmt, // how much to shift by output logic ResSubnormUf, // does the result underflow or is subnormal output logic Cs, // the result's sign @@ -64,7 +64,7 @@ module fcvt import cvw::*; #(parameter cvw_t P) ( logic [P.CVTLEN:0] LzcInFull; // input to the Leading Zero Counter (priority encoder) logic [P.LOGCVTLEN-1:0] LeadingZeros; // output from the LZC - // seperate OpCtrl for code readability + // separate OpCtrl for code readability assign Signed = OpCtrl[0]; assign Int64 = OpCtrl[1]; assign IntToFp = OpCtrl[2]; @@ -80,7 +80,7 @@ module fcvt import cvw::*; #(parameter cvw_t P) ( /////////////////////////////////////////////////////////////////////////// // negation /////////////////////////////////////////////////////////////////////////// - // 1) negate the input if the input is a negative singed integer + // 1) negate the input if the input is a negative signed integer // 2) trim the input to the proper size (kill the 32 most significant zeroes if needed) assign PosInt = Cs ? -Int : Int; @@ -150,20 +150,20 @@ module fcvt import cvw::*; #(parameter cvw_t P) ( // - XExp - Largest bias + new bias - (LeadingZeros+1) // only do ^ if the input was subnormal // - convert the expoenent to the final preciaion (Exp - oldBias + newBias) - // - correct the expoent when there is a normalization shift ( + LeadingZeros+1) + // - correct the exponent when there is a normalization shift ( + LeadingZeros+1) // - the plus 1 is built into the leading zeros by counting the leading zeroes in the mantissa rather than the fraction // fp -> int : XExp - Largest Bias + 1 - (LeadingZeros+1) - // | P.XLEN zeros | Mantissa | 0's if nessisary | << CalcExp + // | P.XLEN zeros | Mantissa | 0's if necessary | << CalcExp // process: // - start - // | P.XLEN zeros | Mantissa | 0's if nessisary | + // | P.XLEN zeros | Mantissa | 0's if necessary | // // - shift left 1 (1) - // | P.XLEN-1 zeros |bit| frac | 0's if nessisary | + // | P.XLEN-1 zeros |bit| frac | 0's if necessary | // . <- binary point // // - shift left till unbiased exponent is 0 (XExp - Largest Bias) - // | 0's | Mantissa | 0's if nessisary | + // | 0's | Mantissa | 0's if necessary | // | keep | // // - if the input is subnormal then we dont shift... so the "- LeadingZeros" is just leftovers from other options @@ -199,7 +199,7 @@ module fcvt import cvw::*; #(parameter cvw_t P) ( // - shift left by NF-1+CalcExp - to shift till the biased expoenent is 0 // ??? -> fp: // - shift left by LeadingZeros - to shift till the result is normalized - // - only shift fp -> fp if the intital value is subnormal + // - only shift fp -> fp if the initial value is subnormal // - this is a problem because the input to the lzc was the fraction rather than the mantissa // - rather have a few and-gates than an extra bit in the priority encoder??? always_comb diff --git a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv index 058a3d17b..6aa208434 100644 --- a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv @@ -4,7 +4,7 @@ // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu // Modified:13 January 2022 // -// Purpose: Exponent caclulation for divide and square root +// Purpose: Exponent calculation for divide and square root // // Documentation: RISC-V System on Chip Design // diff --git a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index a399e4a4f..078ea01d1 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -88,7 +88,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( assign AsE = AE[P.XLEN-1] & SignedDivE; assign BsE = BE[P.XLEN-1] & SignedDivE; - // Force integer inputs to be postiive + // Force integer inputs to be positive mux2 #(P.XLEN) posamux(AE, -AE, AsE, PosA); mux2 #(P.XLEN) posbmux(BE, -BE, BsE, PosB); @@ -165,7 +165,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( // Then multiply by R is left shift by r (1 or 2 for radix 2 or 4) // This is optimized in hardware by first right shifting by 0 or 1 bit (instead of 1 or 2), then left shifting by (r-1), then subtracting 2 or 4 // Subtracting 2 is equivalent to adding 1110. Subtracting 4 is equivalent to adding 1100. Prepend leading 1s to do a free subtraction. - // This also means only one extra fractional bit is needed becaue we never shift right by more than 1. + // This also means only one extra fractional bit is needed because we never shift right by more than 1. // Radix Exponent odd Exponent Even // 2 x-2 = 2(x/2 - 1) x/2 - 2 = 2(x/4 - 1) // 4 2(x)-4 = 4(x/2 - 1)) 2(x/2)-4 = 4(x/4 - 1) @@ -194,7 +194,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( mux2 #(P.DIVb+4) prexmux(DivX, SqrtX, SqrtE, PreShiftX); ////////////////////////////////////////////////////// - // Selet integer or floating-point operands + // Select integer or floating-point operands ////////////////////////////////////////////////////// if (P.IDIV_ON_FPU) begin @@ -203,7 +203,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( assign X = PreShiftX; end - // Divisior register + // Divisor register flopen #(P.DIVb+4) dreg(clk, IFDivStartE, {3'b000, Dnorm}, D); // Floating-point exponent diff --git a/src/fpu/fhazard.sv b/src/fpu/fhazard.sv index c31324ad1..4260427e9 100644 --- a/src/fpu/fhazard.sv +++ b/src/fpu/fhazard.sv @@ -28,10 +28,10 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module fhazard( - input logic [4:0] Adr1D, Adr2D, Adr3D, // read data adresses - input logic [4:0] Adr1E, Adr2E, Adr3E, // read data adresses + input logic [4:0] Adr1D, Adr2D, Adr3D, // read data addresses + input logic [4:0] Adr1E, Adr2E, Adr3E, // read data addresses input logic FRegWriteE, FRegWriteM, FRegWriteW, // is the fp register being written to - input logic [4:0] RdE, RdM, RdW, // the adress being written to + input logic [4:0] RdE, RdM, RdW, // the address being written to input logic [1:0] FResSelM, // the result being selected input logic XEnD, YEnD, ZEnD, // are the inputs needed output logic FPUStallD, // stall the decode stage diff --git a/src/fpu/fma/fmaadd.sv b/src/fpu/fma/fmaadd.sv index 4942f9d9f..ce19f7d30 100644 --- a/src/fpu/fma/fmaadd.sv +++ b/src/fpu/fma/fmaadd.sv @@ -31,11 +31,11 @@ module fmaadd import cvw::*; #(parameter cvw_t P) ( input logic [3*P.NF+5:0] Am, // aligned addend's mantissa for addition in U(NF+5.2NF+1) input logic [P.NE-1:0] Ze, // exponent of Z input logic Ps, // the product sign and the alligend addeded's sign (Modified Z sign for other operations) - input logic [P.NE+1:0] Pe, // product's exponet + input logic [P.NE+1:0] Pe, // product's exponent input logic [2*P.NF+1:0] Pm, // the product's mantissa input logic InvA, // invert the aligned addend input logic KillProd, // should the product be set to 0 - input logic ASticky, // Alighed addend's sticky bit + input logic ASticky, // Aligned addend's sticky bit output logic [3*P.NF+5:0] AmInv, // aligned addend possibly inverted output logic [2*P.NF+1:0] PmKilled, // the product's mantissa possibly killed output logic Ss, // sum's sign diff --git a/src/fpu/fma/fmaalign.sv b/src/fpu/fma/fmaalign.sv index 292472f7f..6e4cfc1f6 100644 --- a/src/fpu/fma/fmaalign.sv +++ b/src/fpu/fma/fmaalign.sv @@ -4,7 +4,7 @@ // Written: 6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu // Modified: // -// Purpose: FMA alginment shift +// Purpose: FMA alignment shift // // Documentation: RISC-V System on Chip Design // @@ -32,7 +32,7 @@ module fmaalign import cvw::*; #(parameter cvw_t P) ( input logic [P.NF:0] Zm, // significand in U(0.NF) format] input logic XZero, YZero, ZZero, // is the input zero output logic [P.FMALEN-1:0] Am, // addend aligned for addition in U(NF+5.2NF+1) - output logic ASticky, // Sticky bit calculated from the aliged addend + output logic ASticky, // Sticky bit calculated from the aligned addend output logic KillProd // should the product be set to zero ); @@ -51,7 +51,7 @@ module fmaalign import cvw::*; #(parameter cvw_t P) ( // This could have been done using Pe, but ACnt is on the critical path so we replicate logic for speed assign ACnt = {2'b0, Xe} + {2'b0, Ye} - {2'b0, (P.NE)'(P.BIAS)} + (P.NE+2)'(P.NF+3) - {2'b0, Ze}; - // Default Addition with only inital left shift + // Default Addition with only initial left shift // extra bit at end and beginning so the correct guard bit is calculated when subtracting // | 54'b0 | 106'b(product) | 2'b0 | // | addnend | diff --git a/src/fpu/fma/fmasign.sv b/src/fpu/fma/fmasign.sv index 8220f0aad..cce5d3e27 100644 --- a/src/fpu/fma/fmasign.sv +++ b/src/fpu/fma/fmasign.sv @@ -28,7 +28,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module fmasign( - input logic [2:0] OpCtrl, // operation contol + input logic [2:0] OpCtrl, // operation control input logic Xs, Ys, Zs, // sign of the inputs output logic Ps, // the product's sign - takes operation into account output logic As, // aligned addend sign used in fma - takes operation into account diff --git a/src/fpu/fpu.sv b/src/fpu/fpu.sv index 7619b92af..4731c369e 100755 --- a/src/fpu/fpu.sv +++ b/src/fpu/fpu.sv @@ -78,8 +78,8 @@ module fpu import cvw::*; #(parameter cvw_t P) ( logic [2:0] OpCtrlE, OpCtrlM; // Select which operation to do in each component logic [1:0] FResSelE, FResSelM, FResSelW; // Select one of the results that finish in the memory stage logic [1:0] PostProcSelE, PostProcSelM; // select result in the post processing unit - logic [4:0] Adr1D, Adr2D, Adr3D; // register adresses of each input - logic [4:0] Adr1E, Adr2E, Adr3E; // register adresses of each input + logic [4:0] Adr1D, Adr2D, Adr3D; // register addresses of each input + logic [4:0] Adr1E, Adr2E, Adr3E; // register addresses of each input logic XEnD, YEnD, ZEnD; // X, Y, Z inputs used for current operation logic XEnE, YEnE, ZEnE; // X, Y, Z inputs used for current operation logic FRegWriteE; // Write floating-point register @@ -129,7 +129,7 @@ module fpu import cvw::*; #(parameter cvw_t P) ( logic [$clog2(P.FMALEN+1)-1:0] SCntE, SCntM; // LZA sum leading zero count // Cvt Signals - logic [P.NE:0] CeE, CeM; // convert intermediate expoent + logic [P.NE:0] CeE, CeM; // convert intermediate exponent logic [P.LOGCVTLEN-1:0] CvtShiftAmtE, CvtShiftAmtM; // how much to shift by logic CvtResSubnormUfE, CvtResSubnormUfM; // does the result underflow or is subnormal logic CsE, CsM; // convert result sign diff --git a/src/fpu/fregfile.sv b/src/fpu/fregfile.sv index 40933de17..2614336a9 100644 --- a/src/fpu/fregfile.sv +++ b/src/fpu/fregfile.sv @@ -30,7 +30,7 @@ module fregfile #(parameter FLEN) ( input logic clk, reset, input logic we4, // write enable - input logic [4:0] a1, a2, a3, a4, // adresses + input logic [4:0] a1, a2, a3, a4, // addresses input logic [FLEN-1:0] wd4, // write data output logic [FLEN-1:0] rd1, rd2, rd3 // read data ); diff --git a/src/fpu/postproc/cvtshiftcalc.sv b/src/fpu/postproc/cvtshiftcalc.sv index 84f5120a0..7d6568dbc 100644 --- a/src/fpu/postproc/cvtshiftcalc.sv +++ b/src/fpu/postproc/cvtshiftcalc.sv @@ -30,12 +30,12 @@ module cvtshiftcalc import cvw::*; #(parameter cvw_t P) ( input logic XZero, // is the input zero? input logic ToInt, // to integer conversion? - input logic IntToFp, // interger to floating point conversion? + input logic IntToFp, // integer to floating point conversion? input logic [P.FMTBITS-1:0] OutFmt, // output format - input logic [P.NE:0] CvtCe, // the calculated expoent + input logic [P.NE:0] CvtCe, // the calculated exponent input logic [P.NF:0] Xm, // input mantissas input logic [P.CVTLEN-1:0] CvtLzcIn, // input to the Leading Zero Counter (without msb) - input logic CvtResSubnormUf, // is the conversion result subnormal or underlows + input logic CvtResSubnormUf, // is the conversion result subnormal or underflows output logic CvtResUf, // does the cvt result unerflow output logic [P.CVTLEN+P.NF:0] CvtShiftIn // number to be shifted ); @@ -51,12 +51,12 @@ module cvtshiftcalc import cvw::*; #(parameter cvw_t P) ( // | P.XLEN zeros | mantissa | 0's if necessary | // . // Other problems: - // - if shifting to the right (neg CalcExp) then don't a 1 in the round bit (to prevent an incorrect plus 1 later durring rounding) + // - if shifting to the right (neg CalcExp) then don't a 1 in the round bit (to prevent an incorrect plus 1 later during rounding) // - we do however want to keep the one in the sticky bit so set one of bits in the sticky bit area to 1 // - ex: for the case 0010000.... (double) // ??? -> fp: // - if result is subnormal or underflowed then we want to shift right i.e. shift right then shift left: - // | P.NF-1 zeros | mantissa | 0's if nessisary | + // | P.NF-1 zeros | mantissa | 0's if necessary | // . // - otherwise: // | LzcInM | 0's if necessary | diff --git a/src/fpu/postproc/divshiftcalc.sv b/src/fpu/postproc/divshiftcalc.sv index d46b58f35..a3e6146f2 100644 --- a/src/fpu/postproc/divshiftcalc.sv +++ b/src/fpu/postproc/divshiftcalc.sv @@ -57,8 +57,8 @@ module divshiftcalc import cvw::*; #(parameter cvw_t P) ( // 00000000.xxxxxxx... << NF Exp = DivUe+1 // 00000000x.xxxxxx... << NF Exp = DivUe (extra shift done afterwards) // 00000000xx.xxxxx... << 1? Exp = DivUe-1 (determined after) - // inital Left shift amount = NF - // shift one more if the it's a minimally redundent radix 4 - one entire cycle needed for integer bit + // initial Left shift amount = NF + // shift one more if the it's a minimally redundant radix 4 - one entire cycle needed for integer bit assign NormShift = (P.LOGNORMSHIFTSZ)'(P.NF); // if the shift amount is negative then don't shift (keep sticky bit) diff --git a/src/fpu/postproc/flags.sv b/src/fpu/postproc/flags.sv index be28a490c..fe5ca1880 100644 --- a/src/fpu/postproc/flags.sv +++ b/src/fpu/postproc/flags.sv @@ -47,7 +47,7 @@ module flags import cvw::*; #(parameter cvw_t P) ( input logic IntToFp, // convert integer to floating point input logic Int64, // convert to 64 bit integer input logic Signed, // convert to a signed integer - input logic [P.NE:0] CvtCe, // the calculated expoent - Cvt + input logic [P.NE:0] CvtCe, // the calculated exponent - Cvt input logic [1:0] CvtNegResMsbs, // the negative integer result's most significant bits // divsqrt input logic DivOp, // conversion operation? @@ -70,7 +70,7 @@ module flags import cvw::*; #(parameter cvw_t P) ( logic FmaInvalid; // integer invalid flag logic DivInvalid; // integer invalid flag logic Underflow; // Underflow flag - logic ResExpGteMax; // is the result greater than or equal to the maximum floating point expoent + logic ResExpGteMax; // is the result greater than or equal to the maximum floating point exponent logic ShiftGtIntSz; // is the shift greater than the the integer size (use Re to account for possible rounding "shift") /////////////////////////////////////////////////////////////////////////////// @@ -81,7 +81,7 @@ module flags import cvw::*; #(parameter cvw_t P) ( // the shift amount is greater than the integers size (for cvt to int) // ShiftGtIntSz calculation: // a left shift of intlen+1 is still in range but any more than that is an overflow - // inital: | 64 0's | XLEN | + // initial: | 64 0's | XLEN | // | 64 0's | XLEN | << 64 // | XLEN | 00000... | // 65 = ...0 0 0 0 0 1 0 0 0 0 0 1 @@ -89,8 +89,8 @@ module flags import cvw::*; #(parameter cvw_t P) ( // 33 = ...0 0 0 0 0 0 1 0 0 0 0 1 // | or | | or | // larger or equal if: - // - any of the bits after the most significan 1 is one - // - the most signifcant in 65 or 33 is still a one in the number and + // - any of the bits after the most significant 1 is one + // - the most significant in 65 or 33 is still a one in the number and // one of the later bits is one if (P.FPSIZES == 1) begin assign ResExpGteMax = &FullRe[P.NE-1:0] | FullRe[P.NE]; @@ -121,7 +121,7 @@ module flags import cvw::*; #(parameter cvw_t P) ( assign ShiftGtIntSz = (|FullRe[P.Q_NE:7]|(FullRe[6]&~Int64)) | ((|FullRe[4:0]|(FullRe[5]&Int64))&((FullRe[5]&~Int64) | FullRe[6]&Int64)); end - // calulate overflow flag: + // calculate overflow flag: // if the result is greater than or equal to the max exponent(not taking into account sign) // | and the exponent isn't negative // | | if the input isnt infinity or NaN @@ -146,8 +146,8 @@ module flags import cvw::*; #(parameter cvw_t P) ( // Inexact /////////////////////////////////////////////////////////////////////////////// - // Set Inexact flag if the result is diffrent from what would be outputed given infinite precision - // - Don't set the underflow flag if an underflowed res isn't outputed + // Set Inexact flag if the result is different from what would be outputted given infinite precision + // - Don't set the underflow flag if an underflowed res isn't outputted assign FpInexact = (Sticky|Guard|Overflow|Round)&~(InfIn|NaNIn|DivByZero|Invalid); // if the res is too small to be represented and not 0 diff --git a/src/fpu/postproc/fmashiftcalc.sv b/src/fpu/postproc/fmashiftcalc.sv index 22c354e30..f1660aebd 100644 --- a/src/fpu/postproc/fmashiftcalc.sv +++ b/src/fpu/postproc/fmashiftcalc.sv @@ -34,7 +34,7 @@ module fmashiftcalc import cvw::*; #(parameter cvw_t P) ( input logic [$clog2(P.FMALEN+1)-1:0] FmaSCnt, // normalization shift count output logic [P.NE+1:0] NormSumExp, // exponent of the normalized sum not taking into account Subnormal or zero results output logic FmaSZero, // is the sum zero - output logic FmaPreResultSubnorm, // is the result subnormal - calculated before LZA corection + output logic FmaPreResultSubnorm, // is the result subnormal - calculated before LZA correction output logic [$clog2(P.FMALEN+1)-1:0] FmaShiftAmt // normalization shift count ); logic [P.NE+1:0] PreNormSumExp; // the exponent of the normalized sum with the P.FLEN bias diff --git a/src/fpu/postproc/postprocess.sv b/src/fpu/postproc/postprocess.sv index 3674303eb..8e931da1c 100644 --- a/src/fpu/postproc/postprocess.sv +++ b/src/fpu/postproc/postprocess.sv @@ -56,7 +56,7 @@ module postprocess import cvw::*; #(parameter cvw_t P) ( input logic [P.NE:0] CvtCe, // the calculated exponent input logic CvtResSubnormUf, // the convert result is subnormal or underflows input logic [P.LOGCVTLEN-1:0] CvtShiftAmt, // how much to shift by - input logic ToInt, // is fp->int (since it's writting to the integer register) + input logic ToInt, // is fp->int (since it's writing to the integer register) input logic Zfa, // Zfa operation (fcvtmod.w.d) input logic [P.CVTLEN-1:0] CvtLzcIn, // input to the Leading Zero Counter (without msb) input logic IntZero, // is the integer input zero @@ -77,7 +77,7 @@ module postprocess import cvw::*; #(parameter cvw_t P) ( logic UfPlus1; // do you add one (for determining underflow flag) logic [P.LOGNORMSHIFTSZ-1:0] ShiftAmt; // normalization shift amount logic [P.NORMSHIFTSZ-1:0] ShiftIn; // input to normalization shift - logic [P.NORMSHIFTSZ-1:0] Shifted; // the ouput of the normalized shifter (before shift correction) + logic [P.NORMSHIFTSZ-1:0] Shifted; // the output of the normalized shifter (before shift correction) logic Plus1; // add one to the final result? logic Overflow; // overflow flag used to select results logic Invalid; // invalid flag used to select results @@ -87,14 +87,14 @@ module postprocess import cvw::*; #(parameter cvw_t P) ( logic [P.NE+1:0] FmaMe; // exponent of the normalized sum logic FmaSZero; // is the sum zero logic [P.NE+1:0] NormSumExp; // exponent of the normalized sum not taking into account Subnormal or zero results - logic FmaPreResultSubnorm; // is the result subnormal - calculated before LZA corection + logic FmaPreResultSubnorm; // is the result subnormal - calculated before LZA correction logic [$clog2(P.FMALEN+1)-1:0] FmaShiftAmt; // normalization shift amount for fma // division signals - logic [P.LOGNORMSHIFTSZ-1:0] DivShiftAmt; // divsqrt shif amount - logic [P.NE+1:0] Ue; // divsqrt corrected exponent after corretion shift + logic [P.LOGNORMSHIFTSZ-1:0] DivShiftAmt; // divsqrt shift amount + logic [P.NE+1:0] Ue; // divsqrt corrected exponent after correction shift logic DivByZero; // divide by zero flag logic DivResSubnorm; // is the divsqrt result subnormal - logic DivSubnormShiftPos; // is the divsqrt subnorm shift amout positive (not underflowed) + logic DivSubnormShiftPos; // is the divsqrt subnorm shift amount positive (not underflowed) // conversion signals logic [P.CVTLEN+P.NF:0] CvtShiftIn; // number to be shifted for converter logic [1:0] CvtNegResMsbs; // most significant bits of possibly negated int result @@ -107,7 +107,7 @@ module postprocess import cvw::*; #(parameter cvw_t P) ( logic Int64; // is the integer 64 bits? logic Signed; // is the operation with a signed integer? logic IntToFp; // is the operation an int->fp conversion? - logic CvtOp; // convertion operation + logic CvtOp; // conversion operation logic FmaOp; // fma operation logic DivOp; // divider operation logic InfIn; // are any of the inputs infinity @@ -187,7 +187,7 @@ module postprocess import cvw::*; #(parameter cvw_t P) ( // round to infinity // round to nearest max magnitude - // calulate result sign used in rounding unit + // calculate result sign used in rounding unit roundsign roundsign(.FmaOp, .DivOp, .CvtOp, .Sqrt, .FmaSs, .Xs, .Ys, .CvtCs, .Ms); round #(P) round(.OutFmt, .Frm, .FmaASticky, .Plus1, .PostProcSel, .CvtCe, .Ue, diff --git a/src/fpu/postproc/resultsign.sv b/src/fpu/postproc/resultsign.sv index 9425ec7ee..499bc0e21 100644 --- a/src/fpu/postproc/resultsign.sv +++ b/src/fpu/postproc/resultsign.sv @@ -30,7 +30,7 @@ module resultsign( input logic [2:0] Frm, // rounding mode input logic FmaOp, // is the operation an Fma - input logic Mult, // is the fma operation multipy + input logic Mult, // is the fma operation multiply input logic ZInf, // is Z infinity input logic InfIn, // are any of the inputs infinity input logic FmaSZero, // is the fma sum zero @@ -48,12 +48,12 @@ module resultsign( // determine the sign for a result of 0 // The IEEE754-2019 standard specifies: - // - the sign of an exact zero sum (with operands of diffrent signs) should be positive unless rounding toward negative infinity + // - the sign of an exact zero sum (with operands of different signs) should be positive unless rounding toward negative infinity // - when the exact result of an FMA operation is non-zero, but is zero due to rounding, use the sign of the exact result // - if x = +0 or -0 then x+x=x and x-(-x)=x // - the sign of a product is the exclisive or or the opperand's signs // Zero sign will only be selected if: - // - P=Z and a cancelation occurs - exact zero + // - P=Z and a cancellation occurs - exact zero // - Z is zero and P is zero - exact zero // - P is killed and Z is zero - Psgn // - Z is killed and P is zero - impossible diff --git a/src/fpu/postproc/round.sv b/src/fpu/postproc/round.sv index 4c6d251fb..a02ce5536 100644 --- a/src/fpu/postproc/round.sv +++ b/src/fpu/postproc/round.sv @@ -40,13 +40,13 @@ module round import cvw::*; #(parameter cvw_t P) ( // divsqrt input logic DivOp, // is a division operation being done input logic DivSticky, // divsqrt sticky bit - input logic [P.NE+1:0] Ue, // the divsqrt calculated expoent + input logic [P.NE+1:0] Ue, // the divsqrt calculated exponent // cvt input logic CvtOp, // is a convert operation being done input logic ToInt, // is the cvt op a cvt to integer input logic CvtResSubnormUf, // is the cvt result subnormal or underflow input logic CvtResUf, // does the cvt result underflow - input logic [P.NE:0] CvtCe, // the cvt calculated expoent + input logic [P.NE:0] CvtCe, // the cvt calculated exponent // outputs output logic [P.NE+1:0] Me, // normalied fraction output logic UfPlus1, // do you add one to the result if given an unbounded exponent @@ -172,7 +172,7 @@ module round import cvw::*; #(parameter cvw_t P) ( (|Mf[P.NORMSHIFTSZ-P.XLEN-2:P.NORMSHIFTSZ-P.Q_NF-1]&(~(OutFmt==P.Q_FMT)|IntRes)) | (|Mf[P.NORMSHIFTSZ-P.Q_NF-2:0]); // 3: NF > NF1 > XLEN - // The extra XLEN bit will be ored later when caculating the final sticky bit - the ufplus1 not needed for integer + // The extra XLEN bit will be ored later when calculating the final sticky bit - the ufplus1 not needed for integer if (XLENPOS == 3) assign NormSticky = (|Mf[P.NORMSHIFTSZ-P.H_NF-2:P.NORMSHIFTSZ-P.S_NF-1]&FpRes&(OutFmt==P.H_FMT)) | (|Mf[P.NORMSHIFTSZ-P.S_NF-2:P.NORMSHIFTSZ-P.XLEN-1]&FpRes&((OutFmt==P.S_FMT)|(OutFmt==P.H_FMT))) | (|Mf[P.NORMSHIFTSZ-P.XLEN-2:P.NORMSHIFTSZ-P.D_NF-1]&((OutFmt==P.S_FMT)|(OutFmt==P.H_FMT)|IntRes)) | diff --git a/src/fpu/postproc/roundsign.sv b/src/fpu/postproc/roundsign.sv index fe422b98c..203e090e1 100644 --- a/src/fpu/postproc/roundsign.sv +++ b/src/fpu/postproc/roundsign.sv @@ -44,7 +44,7 @@ module roundsign( // calculate divsqrt sign assign Qs = Xs^(Ys&~Sqrt); - // Select sign for rounding calulation + // Select sign for rounding calculation assign Ms = (FmaSs&FmaOp) | (CvtCs&CvtOp) | (Qs&DivOp); endmodule diff --git a/src/fpu/postproc/shiftcorrection.sv b/src/fpu/postproc/shiftcorrection.sv index 0524ca364..1f32963db 100644 --- a/src/fpu/postproc/shiftcorrection.sv +++ b/src/fpu/postproc/shiftcorrection.sv @@ -37,7 +37,7 @@ module shiftcorrection import cvw::*; #(parameter cvw_t P) ( //fma input logic FmaOp, // is it an fma operation input logic [P.NE+1:0] NormSumExp, // exponent of the normalized sum not taking into account Subnormal or zero results - input logic FmaPreResultSubnorm, // is the result subnormal - calculated before LZA corection + input logic FmaPreResultSubnorm, // is the result subnormal - calculated before LZA correction input logic FmaSZero, // output output logic [P.NE+1:0] FmaMe, // exponent of the normalized sum @@ -61,10 +61,10 @@ module shiftcorrection import cvw::*; #(parameter cvw_t P) ( assign LZAPlus1 = Shifted[P.NORMSHIFTSZ-1]; // correct the shifting of the divsqrt caused by producing a result in (0.5, 2) range - // condition: if the msb is 1 or the exponent was one, but the shifted quotent was < 1 (Subnorm) + // condition: if the msb is 1 or the exponent was one, but the shifted quotient was < 1 (Subnorm) assign LeftShiftQm = (LZAPlus1|(DivUe==1&~LZAPlus1)); - // Determine the shif for either FMA or divsqrt + // Determine the shift for either FMA or divsqrt assign RightShift = FmaOp ? LZAPlus1 : LeftShiftQm; // possible one bit right shift for FMA or division @@ -79,8 +79,8 @@ module shiftcorrection import cvw::*; #(parameter cvw_t P) ( // main exponent issues: // - LZA was one too large // - LZA was two too large - // - if the result was calulated to be subnorm but it's norm and the LZA was off by 1 - // - if the result was calulated to be subnorm but it's norm and the LZA was off by 2 + // - if the result was calculated to be subnorm but it's norm and the LZA was off by 1 + // - if the result was calculated to be subnorm but it's norm and the LZA was off by 2 // if plus1 If plus2 kill if the result Zero or actually subnormal // | | | assign FmaMe = (NormSumExp+{{P.NE+1{1'b0}}, LZAPlus1} +{{P.NE+1{1'b0}}, FmaPreResultSubnorm}) & {P.NE+2{~(FmaSZero|ResSubnorm)}}; @@ -88,8 +88,8 @@ module shiftcorrection import cvw::*; #(parameter cvw_t P) ( // recalculate if the result is subnormal after LZA correction assign ResSubnorm = FmaPreResultSubnorm&~Shifted[P.NORMSHIFTSZ-2]&~Shifted[P.NORMSHIFTSZ-1]; - // the quotent is in the range (.5,2) if there is no early termination - // if the quotent < 1 and not Subnormal then subtract 1 to account for the normalization shift + // the quotient is in the range (.5,2) if there is no early termination + // if the quotient < 1 and not Subnormal then subtract 1 to account for the normalization shift assign Ue = (DivResSubnorm & DivSubnormShiftPos) ? 0 : DivUe - {(P.NE+1)'(0), ~LZAPlus1}; endmodule diff --git a/src/fpu/postproc/specialcase.sv b/src/fpu/postproc/specialcase.sv index bb655942d..a5b0b2409 100644 --- a/src/fpu/postproc/specialcase.sv +++ b/src/fpu/postproc/specialcase.sv @@ -55,7 +55,7 @@ module specialcase import cvw::*; #(parameter cvw_t P) ( input logic Int64, // is the integer 64 bits input logic Signed, // is the integer signed input logic Zfa, // Zfa conversion operation: fcvtmod.w.d - input logic [P.NE:0] CvtCe, // the calculated expoent for cvt + input logic [P.NE:0] CvtCe, // the calculated exponent for cvt input logic IntInvalid, // integer invalid flag to choose the result input logic CvtResUf, // does the convert result underflow input logic [P.XLEN+1:0] CvtNegRes, // the possibly negated of the integer result @@ -240,7 +240,7 @@ module specialcase import cvw::*; #(parameter cvw_t P) ( endcase end - // determine if you shoould kill the res - Cvt + // determine if you should kill the res - Cvt // - do so if the res underflows, is zero (the exp doesnt calculate correctly). or the integer input is 0 // - dont set to zero if fp input is zero but not using the fp input // - dont set to zero if int input is zero but not using the int input @@ -334,7 +334,7 @@ module specialcase import cvw::*; #(parameter cvw_t P) ( end // fcvtmod.w.d logic - // fcvtmod.w.d is like fcvt.w.d excep thtat it takes bits [31:0] and sign extends the rest, + // fcvtmod.w.d is like fcvt.w.d excep that it takes bits [31:0] and sign extends the rest, // and converts +/-inf and NaN to zero. if (P.ZFA_SUPPORTED & P.D_SUPPORTED) // fcvtmod.w.d support @@ -358,7 +358,7 @@ module specialcase import cvw::*; #(parameter cvw_t P) ( // - if the input underflows // - if rounding and signed operation and negative input, output -1 // - otherwise output a rounded 0 - // - otherwise output the normal res (trmined and sign extended if nessisary) + // - otherwise output the normal res (trmined and sign extended if necessary) always_comb if(SelCvtOfRes) FCvtIntRes = OfIntRes2; else if(CvtCe[P.NE]) diff --git a/src/fpu/unpackinput.sv b/src/fpu/unpackinput.sv index c90ede41d..f703740b6 100644 --- a/src/fpu/unpackinput.sv +++ b/src/fpu/unpackinput.sv @@ -88,10 +88,10 @@ module unpackinput import cvw::*; #(parameter cvw_t P) ( end else PostBox = In; - // choose sign bit depending on format - 1=larger precsion 0=smaller precision + // choose sign bit depending on format - 1=larger precision 0=smaller precision assign Sgn = Fmt ? In[P.FLEN-1] : (BadNaNBox ? 0 : In[P.LEN1-1]); // improperly boxed NaNs are treated as positive - // extract the fraction, add trailing zeroes to the mantissa if nessisary + // extract the fraction, add trailing zeroes to the mantissa if necessary assign Frac = Fmt ? In[P.NF-1:0] : {In[P.NF1-1:0], (P.NF-P.NF1)'(0)}; // is the exponent non-zero @@ -105,14 +105,14 @@ module unpackinput import cvw::*; #(parameter cvw_t P) ( // dexp = 0bdd dbbb bbbb // also need to take into account possible zero/Subnorm/inf/NaN values - // extract the exponent, converting the smaller exponent into the larger precision if nessisary + // extract the exponent, converting the smaller exponent into the larger precision if necessary // - if the original precision had a Subnormal number convert the exponent value 1 assign Exp = Fmt ? {In[P.FLEN-2:P.NF+1], In[P.NF]|~ExpNonZero} : {In[P.LEN1-2], {P.NE-P.NE1{~In[P.LEN1-2]}}, In[P.LEN1-3:P.NF1+1], In[P.NF1]|~ExpNonZero}; // is the exponent all 1's assign ExpMax = Fmt ? &In[P.FLEN-2:P.NF] : &In[P.LEN1-2:P.NF1]; - end else if (P.FPSIZES == 3) begin // three floating point precsions supported + end else if (P.FPSIZES == 3) begin // three floating point precisions supported // largest format | larger format | smallest format //--------------------------------------------------- @@ -171,8 +171,8 @@ module unpackinput import cvw::*; #(parameter cvw_t P) ( always_comb case (Fmt) P.FMT: ExpNonZero = |In[P.FLEN-2:P.NF]; // if input is largest precision (P.FLEN - ie quad or double) - P.FMT1: ExpNonZero = |In[P.LEN1-2:P.NF1]; // if input is larger precsion (P.LEN1 - double or single) - P.FMT2: ExpNonZero = |In[P.LEN2-2:P.NF2]; // if input is smallest precsion (P.LEN2 - single or half) + P.FMT1: ExpNonZero = |In[P.LEN1-2:P.NF1]; // if input is larger precision (P.LEN1 - double or single) + P.FMT2: ExpNonZero = |In[P.LEN2-2:P.NF2]; // if input is smallest precision (P.LEN2 - single or half) default: ExpNonZero = 1'bx; endcase @@ -269,7 +269,7 @@ module unpackinput import cvw::*; #(parameter cvw_t P) ( // dexp = 0bdd dbbb bbbb // also need to take into account possible zero/Subnorm/inf/NaN values - // convert the double precsion exponent into quad precsion + // convert the double precision exponent into quad precision // 1 is added to the exponent if the input is zero or subnormal always_comb case (Fmt) @@ -294,7 +294,7 @@ module unpackinput import cvw::*; #(parameter cvw_t P) ( assign FracZero = ~|Frac & ~BadNaNBox; // is the fraction zero? assign Man = {ExpNonZero, Frac}; // add the assumed one (or zero if Subnormal or zero) to create the significand assign NaN = ((ExpMax & ~FracZero)|BadNaNBox)&En; // is the input a NaN? - assign SNaN = NaN&~Frac[P.NF-1]&~BadNaNBox; // is the input a singnaling NaN? + assign SNaN = NaN&~Frac[P.NF-1]&~BadNaNBox; // is the input a signaling NaN? assign Inf = ExpMax & FracZero & En; // is the input infinity? assign Zero = ~ExpNonZero & FracZero; // is the input zero? assign Subnorm = ~ExpNonZero & ~FracZero & ~BadNaNBox; // is the input subnormal diff --git a/src/generic/mem/ram1p1rwbe_64x22.sv b/src/generic/mem/ram1p1rwbe_64x22.sv index 1b5e1bdb7..018e91c39 100755 --- a/src/generic/mem/ram1p1rwbe_64x22.sv +++ b/src/generic/mem/ram1p1rwbe_64x22.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ram1p1rwbe_64x22.sv // -// Written: james.stine@okstate.edu 2 Feburary 2023 +// Written: james.stine@okstate.edu 2 February 2023 // Modified: // // Purpose: RAM wrapper for instantiating RAM IP diff --git a/src/generic/priorityonehot.sv b/src/generic/priorityonehot.sv index 65882dd75..d14eb72f2 100644 --- a/src/generic/priorityonehot.sv +++ b/src/generic/priorityonehot.sv @@ -3,7 +3,7 @@ // // Written: tfleming@hmc.edu & jtorrey@hmc.edu 7 April 2021 // Modified: Teo Ene 15 Apr 2021: -// Temporarily removed paramterized priority encoder for non-parameterized one +// Temporarily removed parameterized priority encoder for non-parameterized one // To get synthesis working quickly // Kmacsaigoren@hmc.edu 28 May 2021: // Added working version of parameterized priority encoder. diff --git a/src/generic/prioritythermometer.sv b/src/generic/prioritythermometer.sv index ecf37e80e..db4366fcf 100644 --- a/src/generic/prioritythermometer.sv +++ b/src/generic/prioritythermometer.sv @@ -5,7 +5,7 @@ // David_Harris@Hmc.edu switched to one-hot output // // Purpose: Priority circuit producing a thermometer code output. -// with 1's in all the least signficant bits of the output +// with 1's in all the least significant bits of the output // until the column where the least significant 1 occurs in the input. // // Example: msb lsb diff --git a/src/hazard/hazard.sv b/src/hazard/hazard.sv index c15ff208f..ede9366f5 100644 --- a/src/hazard/hazard.sv +++ b/src/hazard/hazard.sv @@ -67,7 +67,7 @@ module hazard ( // Trap returns (RetM) also flush the entire pipeline after the RetM (all stages except W) because all the subsequent instructions must be discarded. // Similarly, CSR writes and fences flush all subsequent instructions and refetch them in light of the new operating modes and cache/TLB contents // Branch misprediction is found in the Execute stage and must flush the next two instructions. - // However, an active division operation resides in the Execute stage, and when the BP incorrectly mispredicts the divide as a taken branch, the divde must still complete + // However, an active division operation resides in the Execute stage, and when the BP incorrectly mispredicts the divide as a taken branch, the divide must still complete // When a WFI is interrupted and causes a trap, it flushes the rest of the pipeline but not the W stage, because the WFI needs to commit assign FlushDCause = TrapM | RetM | CSRWriteFenceM | BPWrongE; assign FlushECause = TrapM | RetM | CSRWriteFenceM |(BPWrongE & ~(DivBusyE | FDivBusyE)); @@ -75,7 +75,7 @@ module hazard ( assign FlushWCause = TrapM & ~WFIInterruptedM; // Stall causes - // Most data depenency stalls are identified in the decode stage + // Most data dependency stalls are identified in the decode stage // Division stalls in the execute stage // Flushing any stage has priority over the corresponding stage stall. // Even if the register gave clear priority over enable, various FSMs still need to disable the stall, so it's best to gate the stall here with flush diff --git a/src/ieu/aes/aes64ks1i.sv b/src/ieu/aes/aes64ks1i.sv index cb2d71018..7a541d6de 100644 --- a/src/ieu/aes/aes64ks1i.sv +++ b/src/ieu/aes/aes64ks1i.sv @@ -37,7 +37,7 @@ module aes64ks1i( logic [31:0] rcon, rs1Rotate; rconlut32 rc(round, rcon); // Get rcon value from lookup table - assign rs1Rotate = {rs1[39:32], rs1[63:40]}; // Get rotated value fo ruse in tmp2 + assign rs1Rotate = {rs1[39:32], rs1[63:40]}; // Get rotated value for use in tmp2 assign finalround = (round == 4'b1010); // round 10 is the last one assign SboxKIn = finalround ? rs1[63:32] : rs1Rotate; // Don't rotate on the last round diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv index 9bb0905ad..8ba1b9ca7 100644 --- a/src/ieu/bmu/bitmanipalu.sv +++ b/src/ieu/bmu/bitmanipalu.sv @@ -55,7 +55,7 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) ( logic [P.XLEN-1:0] MaskB; // BitMask of B logic [P.XLEN-1:0] RevA; // Bit-reversed A logic Mask; // Indicates if it is ZBS instruction - logic PreShift; // Inidicates if it is sh1add, sh2add, sh3add instruction + logic PreShift; // Indicates if it is sh1add, sh2add, sh3add instruction logic [1:0] PreShiftAmt; // Amount to Pre-Shift A logic [P.XLEN-1:0] CondZextA; // A Conditional Extend Intermediary Signal logic [P.XLEN-1:0] ABMU, BBMU; // Gated data inputs to reduce BMU activity diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index fe781e78b..6f49c5825 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -35,8 +35,8 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) ( input logic ALUOpD, // Regular ALU Operation output logic BRegWriteD, // Indicates if it is a R type B instruction in Decode Stage output logic BALUSrcBD, // Indicates if it is an I/IW (non auipc) type B instruction in Decode Stage - output logic BW64D, // Indiciates if it is a W type B instruction in Decode Stage - output logic BUW64D, // Indiciates if it is a .uw type B instruction in Decode Stage + output logic BW64D, // Indicates if it is a W type B instruction in Decode Stage + output logic BUW64D, // Indicates if it is a .uw type B instruction in Decode Stage output logic BSubArithD, // TRUE if ext, clr, andn, orn, xnor instruction in Decode Stage output logic IllegalBitmanipInstrD, // Indicates if it is unrecognized B instruction in Decode Stage // Execute stage control signals diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index eafbe4530..03cea93c9 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -158,7 +158,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( logic MatchDE; // Match between a source register in Decode stage and destination register in Execute stage logic FCvtIntStallD, MDUStallD, CSRRdStallD; // Stall due to conversion, load, multiply/divide, CSR read logic FunctCZeroD; // Funct7 and Funct3 indicate czero.* (not including Op check) - logic BUW64D; // Indiciates if it is a .uw type B instruction in Decode Stage + logic BUW64D; // Indicates if it is a .uw type B instruction in Decode Stage // Extract fields assign OpD = InstrD[6:0]; @@ -401,7 +401,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( IFUPrefetchD = 1'b0; LSUPrefetchD = 1'b0; ImmSrcD = PreImmSrcD; - if (P.ZICBOP_SUPPORTED & (InstrD[14:0] == 15'b110_00000_0010011)) begin // ori with destiation x0 is hint for Prefetch + if (P.ZICBOP_SUPPORTED & (InstrD[14:0] == 15'b110_00000_0010011)) begin // ori with destination x0 is hint for Prefetch /* verilator lint_off CASEINCOMPLETE */ case (Rs2D) // which type of prefectch? Note: prefetch.r and .w are handled the same in Wally 5'b00000: IFUPrefetchD = 1'b1; // prefetch.i diff --git a/src/ieu/shifter.sv b/src/ieu/shifter.sv index 8d4da28d9..f99a87562 100644 --- a/src/ieu/shifter.sv +++ b/src/ieu/shifter.sv @@ -60,7 +60,7 @@ module shifter import cvw::*; #(parameter cvw_t P) ( if (P.ZBB_SUPPORTED | P.ZBKB_SUPPORTED) begin: rotfunnel64 // rv64 shifter with rotates // shifter rotate source select mux logic [P.XLEN-1:0] RotA; // rotate source - mux2 #(P.XLEN) rotmux(A, {A[31:0], A[31:0]}, W64, RotA); // W64 rotatons + mux2 #(P.XLEN) rotmux(A, {A[31:0], A[31:0]}, W64, RotA); // W64 rotations always_comb // funnel mux case ({Right, Rotate}) 2'b00: Z = {A64[63:0],{63'b0}}; diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index 8b8793f27..3160ea29d 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -55,7 +55,7 @@ module bpred import cvw::*; #(parameter cvw_t P) ( input logic InstrValidD, InstrValidE, input logic BranchD, BranchE, input logic JumpD, JumpE, - input logic PCSrcE, // Executation stage branch is taken + input logic PCSrcE, // Execution stage branch is taken input logic [P.XLEN-1:0] IEUAdrE, // The branch/jump target address input logic [P.XLEN-1:0] IEUAdrM, // The branch/jump target address input logic [P.XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address) @@ -188,7 +188,7 @@ module bpred import cvw::*; #(parameter cvw_t P) ( mux2 #(P.XLEN) pccorrectemux(PCLinkE, IEUAdrE, PCSrcE, PCCorrectE); // If the fence/csrw was predicted as a taken branch then we select PCF, rather than PCE. - // Effectively this is PCM+4 or the non-existant PCLinkM + // Effectively this is PCM+4 or the non-existent PCLinkM if(`INSTR_CLASS_PRED) mux2 #(P.XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPWrongM, NextValidPCE); else assign NextValidPCE = PCE; diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv index 6c6ace763..19aca3bc6 100644 --- a/src/ifu/bpred/btb.sv +++ b/src/ifu/bpred/btb.sv @@ -6,7 +6,7 @@ // Modified: 24 January 2023 // // Purpose: Branch Target Buffer (BTB). The BTB predicts the target address of all control flow instructions. -// It also guesses the type of instrution; jalr(r), return, jump (jr), or branch. +// It also guesses the type of instruction; jalr(r), return, jump (jr), or branch. // // Documentation: RISC-V System on Chip Design // diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index cc4576fd2..1621addd9 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -49,7 +49,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( output logic [P.XLEN-1:0] PCSpillF, // PCF with possible + 2 to handle spill to HPTW // Execute output logic [P.XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address) - input logic PCSrcE, // Executation stage branch is taken + input logic PCSrcE, // Execution stage branch is taken input logic [P.XLEN-1:0] IEUAdrE, // The branch/jump target address input logic [P.XLEN-1:0] IEUAdrM, // The branch/jump target address output logic [P.XLEN-1:0] PCE, // Execution stage instruction address @@ -78,7 +78,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( output logic IllegalIEUFPUInstrD, // Illegal instruction including compressed & FP output logic InstrMisalignedFaultM, // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed) // mmu management - input logic [1:0] PrivilegeModeW, // Priviledge mode in Writeback stage + input logic [1:0] PrivilegeModeW, // Privilege mode in Writeback stage input logic [P.XLEN-1:0] PTE, // Hardware page table walker (HPTW) writes Page table entry (PTE) to ITLB input logic [1:0] PageType, // Hardware page table walker (HPTW) writes PageType to ITLB input logic ITLBWriteF, // Writes PTE and PageType to ITLB @@ -208,7 +208,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( //////////////////////////////////////////////////////////////////////////////////////////////// // CommittedM tells the CPU's privileged unit the current instruction - // in the memory stage is a memory operaton and that memory operation is either completed + // in the memory stage is a memory operation and that memory operation is either completed // or is partially executed. Partially completed memory operations need to prevent an interrupts. // There is not a clean way to restore back to a partial executed instruction. CommiteedM will // delay the interrupt until the LSU is in a clean state. diff --git a/src/ifu/irom.sv b/src/ifu/irom.sv index f85b60a5d..550eeff42 100644 --- a/src/ifu/irom.sv +++ b/src/ifu/irom.sv @@ -40,7 +40,7 @@ module irom import cvw::*; #(parameter cvw_t P) ( logic [31:0] RawIROMInstrF; logic [2:1] AdrD; - // preload IROM with the FPGA bootloader by default so that it syntehsizes to something, avoiding having the IEU optimized away because instructions are all 0 + // preload IROM with the FPGA bootloader by default so that it synthesizes to something, avoiding having the IEU optimized away because instructions are all 0 // the testbench replaces these dummy contents with the actual program of interest during simulation rom1p1r #(ADDR_WDITH, P.XLEN, 1) rom(.clk, .ce, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(IROMInstrFFull)); if (P.XLEN == 32) assign RawIROMInstrF = IROMInstrFFull; @@ -50,7 +50,7 @@ module irom import cvw::*; #(parameter cvw_t P) ( flopen #(1) AdrReg2(clk, ce, Adr[2], AdrD[2]); assign RawIROMInstrF = AdrD[2] ? IROMInstrFFull[63:32] : IROMInstrFFull[31:0]; end - // If the memory addres is aligned to 2 bytes return the upper 2 bytes in the lower 2 bytes. + // If the memory address is aligned to 2 bytes return the upper 2 bytes in the lower 2 bytes. // The spill logic will handle merging the two together. if (P.ZCA_SUPPORTED) begin flopen #(1) AdrReg1(clk, ce, Adr[1], AdrD[1]); diff --git a/src/lsu/align.sv b/src/lsu/align.sv index b6bae2918..10e8e0764 100644 --- a/src/lsu/align.sv +++ b/src/lsu/align.sv @@ -6,7 +6,7 @@ // Modified: 26 October 2023 // // Purpose: This module implements native alignment support for the Zicclsm extension -// It is simlar to the IFU's spill module and probably could be merged together with +// It is similar to the IFU's spill module and probably could be merged together with // some effort. // // Documentation: RISC-V System on Chip Design @@ -94,7 +94,7 @@ module align import cvw::*; #(parameter cvw_t P) ( // 2) offset // 3) access location within the cacheline - // compute misalignement + // compute misalignment always_comb begin case (Funct3M & {FpLoadStoreM, 2'b11}) 3'b000: AccessByteOffsetM = '0; // byte access diff --git a/src/lsu/lrsc.sv b/src/lsu/lrsc.sv index 20d3cb8f6..39487f78a 100644 --- a/src/lsu/lrsc.sv +++ b/src/lsu/lrsc.sv @@ -36,7 +36,7 @@ module lrsc import cvw::*; #(parameter cvw_t P) ( input logic MemReadM, // Memory read input logic [1:0] PreLSURWM, // Memory operation from the HPTW or IEU [1]: read, [0]: write output logic [1:0] LSURWM, // Memory operation after potential squash of SC - input logic [1:0] LSUAtomicM, // Atomic memory operaiton + input logic [1:0] LSUAtomicM, // Atomic memory operation input logic [P.PA_BITS-1:0] PAdrM, // Physical memory address output logic SquashSCW // Squash the store conditional by not allowing rf write ); diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index f6a215a27..3e75c1b02 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -141,7 +141,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( logic DTLBMissM; // DTLB miss causes HPTW walk logic DTLBWriteM; // Writes PTE and PageType to DTLB - logic LSULoadAccessFaultM; // Load acces fault + logic LSULoadAccessFaultM; // Load access fault logic LSUStoreAmoAccessFaultM; // Store access fault logic HPTWFlushW; // HPTW needs to flush operation logic LSUFlushW; // HPTW or hazard unit flushes operation @@ -300,7 +300,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( logic [P.PA_BITS-1:0] DCacheBusAdr; // Cacheline address to fetch or writeback. logic [AHBWLOGBWPL-1:0] BeatCount; // Position within a cacheline. ahbcacheinterface to cache logic DCacheBusAck; // ahbcacheinterface completed fetch or writeback - logic SelBusBeat; // ahbcacheinterface selects postion in cacheline with BeatCount + logic SelBusBeat; // ahbcacheinterface selects position in cacheline with BeatCount logic [1:0] CacheBusRW; // Cache sends request to ahbcacheinterface logic [1:0] BusRW; // Uncached bus memory access logic CacheableOrFlushCacheM; // Memory address is cacheable or operation is a cache flush @@ -350,7 +350,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( mux3 #(P.LLEN) UnCachedDataMux(.d0(DCacheReadDataWordSpillM), .d1({LLENPOVERAHBW{FetchBuffer[P.XLEN-1:0]}}), .d2({{P.LLEN-P.XLEN{1'b0}}, DTIMReadDataWordM[P.XLEN-1:0]}), .s({SelDTIM, ~(CacheableOrFlushCacheM)}), .y(ReadDataWordMuxM)); - end else begin : passthrough // No Cache, use simple ahbinterface instad of ahbcacheinterface + end else begin : passthrough // No Cache, use simple ahbinterface instead of ahbcacheinterface logic [1:0] BusRW; // Non-DTIM memory access, ignore cacheableM logic [P.XLEN-1:0] FetchBuffer; assign BusRW = ~SelDTIM ? LSURWM : 0; diff --git a/src/mdu/div.sv b/src/mdu/div.sv index 66fe5d9d4..5dd4f620c 100644 --- a/src/mdu/div.sv +++ b/src/mdu/div.sv @@ -78,7 +78,7 @@ module div import cvw::*; #(parameter cvw_t P) ( assign DinE = ForwardedSrcBE; end - // Extract sign bits and check fo division by zero + // Extract sign bits and check for division by zero assign SignDE = DivSignedE & DinE[P.XLEN-1]; assign SignXE = DivSignedE & XinE[P.XLEN-1]; assign NegQE = SignDE ^ SignXE; diff --git a/src/mdu/mdu.sv b/src/mdu/mdu.sv index b2f0f7514..6620a7f4f 100644 --- a/src/mdu/mdu.sv +++ b/src/mdu/mdu.sv @@ -33,7 +33,7 @@ module mdu import cvw::*; #(parameter cvw_t P) ( input logic FlushE, FlushM, FlushW, input logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // inputs A and B from IEU forwarding mux output input logic [2:0] Funct3E, Funct3M, // type of MDU operation - input logic IntDivE, W64E, // Integer division/remainder, and W-type instrutions + input logic IntDivE, W64E, // Integer division/remainder, and W-type instructions input logic MDUActiveE, // Mul/Div instruction being executed output logic [P.XLEN-1:0] MDUResultW, // multiply/divide result output logic DivBusyE // busy signal to stall pipeline in Execute stage diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index 6b7df68fb..40ad3ff23 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -200,8 +200,8 @@ module hptw import cvw::*; #(parameter cvw_t P) ( assign InvalidOp = DTLBWalk ? (InvalidRead | InvalidWrite) : ~Executable; assign OtherPageFault = ImproperPrivilege | InvalidOp | UpperBitsUnequalD | Misaligned | ~Valid; - // hptw needs to know if there is a Dirty or Access fault occuring on this - // memory access. If there is the PTE needs to be updated seting Access + // hptw needs to know if there is a Dirty or Access fault occurring on this + // memory access. If there is the PTE needs to be updated setting Access // and possibly also Dirty. Dirty is set if the operation is a store/amo. // However any other fault should not cause the update, and updates are in software when ENVCFG_ADUE = 0 assign HPTWUpdateDA = ValidLeafPTE & (~Accessed | SetDirty) & ENVCFG_ADUE & ~OtherPageFault; @@ -316,7 +316,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( // HTPW address/data/control muxing // Once the walk is done and it is time to update the TLB we need to switch back - // to the orignal data virtual address. + // to the original data virtual address. assign SelHPTWAdr = SelHPTW & ~(DTLBWriteM | ITLBWriteF); // multiplex the outputs to LSU diff --git a/src/mmu/mmu.sv b/src/mmu/mmu.sv index a1022de51..f1aee2218 100644 --- a/src/mmu/mmu.sv +++ b/src/mmu/mmu.sv @@ -47,7 +47,7 @@ module mmu import cvw::*; #(parameter cvw_t P, input logic TLBFlush, // Invalidate all TLB entries output logic [P.PA_BITS-1:0] PhysicalAddress, // PAdr when no translation, or translated VAdr (TLBPAdr) when there is translation output logic TLBMiss, // Miss TLB - output logic Cacheable, // PMA indicates memory address is cachable + output logic Cacheable, // PMA indicates memory address is cacheable output logic Idempotent, // PMA indicates memory address is idempotent output logic SelTIM, // Select a tightly integrated memory // Faults @@ -105,8 +105,8 @@ module mmu import cvw::*; #(parameter cvw_t P, assign TLBPAdr = '0; end - // If translation is occuring, select translated physical address from TLB - // the lower 12 bits are the page offset. These are never changed from the orginal + // If translation is occurring, select translated physical address from TLB + // the lower 12 bits are the page offset. These are never changed from the original // non translated address. mux2 #(P.PA_BITS-12) addressmux(VAdr[P.PA_BITS-1:12], TLBPAdr[P.PA_BITS-1:12], Translate, PhysicalAddress[P.PA_BITS-1:12]); assign PhysicalAddress[11:0] = VAdr[11:0]; @@ -141,7 +141,7 @@ module mmu import cvw::*; #(parameter cvw_t P, 2'b10: DataMisalignedM = VAdr[1] | VAdr[0]; // lw, sw, flw, fsw, lwu 2'b11: DataMisalignedM = |VAdr[2:0]; // ld, sd, fld, fsd endcase - // When ZiCCLSM_SUPPORTED, misalgined cachable loads and stores are handled in hardware so they do not throw a misaligned fault + // When ZiCCLSM_SUPPORTED, misalgined cacheable loads and stores are handled in hardware so they do not throw a misaligned fault assign LoadMisalignedFaultM = DataMisalignedM & ReadNoAmoAccessM & ~(P.ZICCLSM_SUPPORTED & Cacheable) & ~TLBMiss; assign StoreAmoMisalignedFaultM = DataMisalignedM & WriteAccessM & ~(P.ZICCLSM_SUPPORTED & Cacheable) & ~TLBMiss; // Store and AMO both assert WriteAccess diff --git a/src/mmu/pmachecker.sv b/src/mmu/pmachecker.sv index 021f448b2..3490205c0 100644 --- a/src/mmu/pmachecker.sv +++ b/src/mmu/pmachecker.sv @@ -58,8 +58,8 @@ module pmachecker import cvw::*; #(parameter cvw_t P) ( // Determine which region of physical memory (if any) is being accessed adrdecs #(P) adrdecs(PhysicalAddress, AccessRW, AccessRX, AccessRWXC, Size, SelRegions); - // Only non-core RAM/ROM memory regions are cacheable. PBMT can override cachable; NC and IO are uncachable - assign CacheableRegion = SelRegions[3] | SelRegions[4] | SelRegions[5]; // exclusion-tag: unused-cachable + // Only non-core RAM/ROM memory regions are cacheable. PBMT can override cacheable; NC and IO are uncachable + assign CacheableRegion = SelRegions[3] | SelRegions[4] | SelRegions[5]; // exclusion-tag: unused-cacheable assign Cacheable = (PBMemoryType == 2'b00) ? CacheableRegion : 1'b0; // Nonidemdempotent means access could have side effect and must not be done speculatively or redundantly diff --git a/src/mmu/pmpadrdec.sv b/src/mmu/pmpadrdec.sv index 6ba4b85da..234650417 100644 --- a/src/mmu/pmpadrdec.sv +++ b/src/mmu/pmpadrdec.sv @@ -76,7 +76,7 @@ module pmpadrdec import cvw::*; #(parameter cvw_t P) ( // form a mask where the bottom k bits are 1, corresponding to a size of 2^k bytes for this memory region. // This assumes we're using at least an NA4 region, but works for any size NAPOT region. assign NABase = {(PMPAdr & ~NAMask[P.PA_BITS-1:2]), 2'b00}; // base physical address of the pmp region - assign NAMatch = &((NABase ~^ PhysicalAddress) | NAMask); // check if upper bits of base address match, ignore lower bits correspoonding to inside the memory range + assign NAMatch = &((NABase ~^ PhysicalAddress) | NAMask); // check if upper bits of base address match, ignore lower bits corresponding to inside the memory range // finally pick the appropriate match for the access type assign Match = (AdrMode == TOR) ? TORMatch : diff --git a/src/mmu/pmpchecker.sv b/src/mmu/pmpchecker.sv index 3877089b6..de12d7eee 100644 --- a/src/mmu/pmpchecker.sv +++ b/src/mmu/pmpchecker.sv @@ -75,7 +75,7 @@ module pmpchecker import cvw::*; #(parameter cvw_t P) ( .Match, .PMPTop, .L, .X, .W, .R); end - priorityonehot #(P.PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // combine the match signal from all the adress decoders to find the first one that matches. + priorityonehot #(P.PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // combine the match signal from all the address decoders to find the first one that matches. // Distributed AND-OR mux to select the first matching results // If the access does not match all bytes of the PMP region, it is too big and the matches are disabled diff --git a/src/mmu/tlb/tlbcamline.sv b/src/mmu/tlb/tlbcamline.sv index e66c22da2..8068e8fd7 100644 --- a/src/mmu/tlb/tlbcamline.sv +++ b/src/mmu/tlb/tlbcamline.sv @@ -71,7 +71,7 @@ module tlbcamline import cvw::*; #(parameter cvw_t P, // Calculate the actual match value based on the input vpn and the page type. // For example, a megapage in SV32 only cares about VPN[1], so VPN[0] // should automatically match. - assign Match0 = (Query0 == Key0) | (PageType[0]); // least signifcant section + assign Match0 = (Query0 == Key0) | (PageType[0]); // least significant section assign Match1 = (Query1 == Key1); assign Match = Match0 & Match1 & MatchASID & Valid; diff --git a/src/mmu/tlb/tlbcontrol.sv b/src/mmu/tlb/tlbcontrol.sv index 96184b011..9e3de45a0 100644 --- a/src/mmu/tlb/tlbcontrol.sv +++ b/src/mmu/tlb/tlbcontrol.sv @@ -115,7 +115,7 @@ module tlbcontrol import cvw::*; #(parameter cvw_t P, ITLB = 0) ( assign PreUpdateDA = ~PTE_A | WriteAccess & ~PTE_D; end - // Determine wheter to update DA bits. With SVADU, it is done in hardware + // Determine whether to update DA bits. With SVADU, it is done in hardware assign UpdateDA = P.SVADU_SUPPORTED & PreUpdateDA & Translate & TLBHit & ~TLBPageFault & ENVCFG_ADUE; // Determine whether page fault occurs diff --git a/src/mmu/tlb/tlbmixer.sv b/src/mmu/tlb/tlbmixer.sv index 502d3ef83..33b37707a 100644 --- a/src/mmu/tlb/tlbmixer.sv +++ b/src/mmu/tlb/tlbmixer.sv @@ -63,7 +63,7 @@ module tlbmixer import cvw::*; #(parameter cvw_t P) ( // In Svnapot, when N=1, use bottom bits of VPN for contiugous translations if (P.SVNAPOT_SUPPORTED) begin - // 64 KiB contiguous NAPOT translations suported + // 64 KiB contiguous NAPOT translations supported logic [3:0] PPNMixedBot; mux2 #(4) napotmux(PPNMixed[3:0], VPN[3:0], PTE_N, PPNMixedBot); assign PPNMixed2 = {PPNMixed[P.PPN_BITS-1:4], PPNMixedBot}; diff --git a/src/privileged/csrsr.sv b/src/privileged/csrsr.sv index 08c6e4c19..6d5e0c2d2 100644 --- a/src/privileged/csrsr.sv +++ b/src/privileged/csrsr.sv @@ -90,14 +90,14 @@ module csrsr import cvw::*; #(parameter cvw_t P) ( end // hardwired STATUS bits - assign STATUS_TSR = P.S_SUPPORTED & STATUS_TSR_INT; // override reigster with 0 if supervisor mode not supported + assign STATUS_TSR = P.S_SUPPORTED & STATUS_TSR_INT; // override register with 0 if supervisor mode not supported assign STATUS_TW = P.U_SUPPORTED & STATUS_TW_INT; // override register with 0 if only machine mode supported - assign STATUS_TVM = P.S_SUPPORTED & STATUS_TVM_INT; // override reigster with 0 if supervisor mode not supported - assign STATUS_MXR = P.S_SUPPORTED & STATUS_MXR_INT; // override reigster with 0 if supervisor mode not supported + assign STATUS_TVM = P.S_SUPPORTED & STATUS_TVM_INT; // override register with 0 if supervisor mode not supported + assign STATUS_MXR = P.S_SUPPORTED & STATUS_MXR_INT; // override register with 0 if supervisor mode not supported // SXL and UXL bits only matter for RV64. Set to 10 for RV64 if mode is supported, or 0 if not assign STATUS_SXL = P.S_SUPPORTED ? 2'b10 : 2'b00; // 10 if supervisor mode supported assign STATUS_UXL = P.U_SUPPORTED ? 2'b10 : 2'b00; // 10 if user mode supported - assign STATUS_SUM = P.S_SUPPORTED & P.VIRTMEM_SUPPORTED & STATUS_SUM_INT; // override reigster with 0 if supervisor mode not supported + assign STATUS_SUM = P.S_SUPPORTED & P.VIRTMEM_SUPPORTED & STATUS_SUM_INT; // override register with 0 if supervisor mode not supported assign STATUS_MPRV = P.U_SUPPORTED & STATUS_MPRV_INT; // override with 0 if user mode not supported assign STATUS_FS = P.F_SUPPORTED ? STATUS_FS_INT : 2'b00; // off if no FP assign STATUS_SD = (STATUS_FS == 2'b11) | (STATUS_XS == 2'b11); // dirty state logic diff --git a/src/privileged/privdec.sv b/src/privileged/privdec.sv index 6b4ba92f1..0689cef10 100644 --- a/src/privileged/privdec.sv +++ b/src/privileged/privdec.sv @@ -83,7 +83,7 @@ module privdec import cvw::*; #(parameter cvw_t P) ( assign WFICountPlus1 = wfiM ? WFICount + 1 : '0; // restart counting on WFI flopr #(P.WFI_TIMEOUT_BIT+1) wficountreg(clk, reset, WFICountPlus1, WFICount); // count while in WFI // coverage off -item e 1 -fecexprrow 1 - // WFI Timout trap will not occur when STATUS_TW is low while in supervisor mode, so the system gets stuck waiting for an interrupt and triggers a watchdog timeout. + // WFI Timeout trap will not occur when STATUS_TW is low while in supervisor mode, so the system gets stuck waiting for an interrupt and triggers a watchdog timeout. assign WFITimeoutM = ((STATUS_TW & PrivilegeModeW != P.M_MODE) | (P.S_SUPPORTED & PrivilegeModeW == P.U_MODE)) & WFICount[P.WFI_TIMEOUT_BIT]; // coverage on end else assign WFITimeoutM = 1'b0; diff --git a/src/privileged/privileged.sv b/src/privileged/privileged.sv index 197ab23be..8b6c59251 100644 --- a/src/privileged/privileged.sv +++ b/src/privileged/privileged.sv @@ -51,7 +51,7 @@ module privileged import cvw::*; #(parameter cvw_t P) ( input logic DCacheStallM, // D cache stalled input logic BPDirWrongM, // branch predictor guessed wrong direction input logic BTAWrongM, // branch predictor guessed wrong target - input logic RASPredPCWrongM, // return adddress stack guessed wrong target + input logic RASPredPCWrongM, // return address stack guessed wrong target input logic IClassWrongM, // branch predictor guessed wrong instruction class input logic BPWrongM, // branch predictor is wrong input logic [3:0] IClassM, // actual instruction class @@ -113,7 +113,7 @@ module privileged import cvw::*; #(parameter cvw_t P) ( logic [11:0] MIP_REGW, MIE_REGW; // interrupt pending and enable bits logic [1:0] NextPrivilegeModeM; // next privilege mode based on trap or return logic DelegateM; // trap should be delegated - logic InterruptM; // interrupt occuring + logic InterruptM; // interrupt occurring logic ExceptionM; // Memory stage instruction caused a fault logic HPTWInstrAccessFaultM; // Hardware page table access fault while fetching instruction PTE logic HPTWInstrPageFaultM; // Hardware page table page fault while fetching instruction PTE diff --git a/src/privileged/trap.sv b/src/privileged/trap.sv index 95ae26e1a..12b0c8441 100644 --- a/src/privileged/trap.sv +++ b/src/privileged/trap.sv @@ -48,7 +48,7 @@ module trap import cvw::*; #(parameter cvw_t P) ( output logic [3:0] CauseM // trap cause ); - logic MIntGlobalEnM, SIntGlobalEnM; // Global interupt enables + logic MIntGlobalEnM, SIntGlobalEnM; // Global interrupt enables logic Committed; // LSU or IFU has committed to a bus operation that can't be interrupted logic BothInstrAccessFaultM, BothInstrPageFaultM; // instruction or HPTW ITLB fill caused an Instruction Access Fault logic [11:0] PendingIntsM, ValidIntsM, EnabledIntsM; // interrupts are pending, valid, or enabled diff --git a/src/rvvi/rvvisynth.sv b/src/rvvi/rvvisynth.sv index 3e8170c93..0dcb752dd 100644 --- a/src/rvvi/rvvisynth.sv +++ b/src/rvvi/rvvisynth.sv @@ -48,7 +48,7 @@ module rvvisynth import cvw::*; #(parameter cvw_t P, output logic [72+(5*P.XLEN) + MAX_CSRS*(P.XLEN+16)-1:0] rvvi ); - // pipeline controlls + // pipeline controls // required logic [P.XLEN-1:0] PCW; diff --git a/src/uncore/clint_apb.sv b/src/uncore/clint_apb.sv index e03745194..7219940d6 100644 --- a/src/uncore/clint_apb.sv +++ b/src/uncore/clint_apb.sv @@ -215,7 +215,7 @@ module timereg import cvw::*; #(parameter cvw_t P) ( done <= ack_stored & ~ack; end - // synchronize the reset and reqest into the TIMECLK domain + // synchronize the reset and request into the TIMECLK domain sync resetsync(TIMECLK, PRESETn, resetn_sync); sync rsync(TIMECLK, req, req_sync); // synchronize the acknowledge back to the PCLK domain to indicate the request was handled and can be lowered diff --git a/src/uncore/plic_apb.sv b/src/uncore/plic_apb.sv index 607994906..9e7b1d2c3 100644 --- a/src/uncore/plic_apb.sv +++ b/src/uncore/plic_apb.sv @@ -37,7 +37,7 @@ // up to 63 sources supported; in the future, allow up to 1023 sources `define C 2 -// number of conexts +// number of contexts // hardcoded to 2 contexts for now; later upgrade to arbitrary (up to 15872) contexts module plic_apb import cvw::*; #(parameter cvw_t P) ( @@ -195,7 +195,7 @@ module plic_apb import cvw::*; #(parameter cvw_t P) ( end end - // which prority levels have one or more active requests? + // which priority levels have one or more active requests? assign priorities_with_irqs[ctx][7:1] = { |irqMatrix[ctx][7], |irqMatrix[ctx][6], diff --git a/src/uncore/ram_ahb.sv b/src/uncore/ram_ahb.sv index 60c870138..08b0a940f 100644 --- a/src/uncore/ram_ahb.sv +++ b/src/uncore/ram_ahb.sv @@ -60,7 +60,7 @@ module ram_ahb import cvw::*; #(parameter cvw_t P, flopenr #(1) memwritereg(HCLK, ~HRESETn, HREADY, memwrite, memwriteD); flopenr #(P.PA_BITS) haddrreg(HCLK, ~HRESETn, HREADY, HADDR, HADDRD); - // Stall on a read after a write because the RAM can't take both adddresses on the same cycle + // Stall on a read after a write because the RAM can't take both addresses on the same cycle assign nextHREADYRam = (~(memwriteD & memread)) & ~DelayReady; flopr #(1) readyreg(HCLK, ~HRESETn, nextHREADYRam, HREADYRam); diff --git a/src/uncore/spi_apb.sv b/src/uncore/spi_apb.sv index 4f4fcbc40..71cf77d33 100644 --- a/src/uncore/spi_apb.sv +++ b/src/uncore/spi_apb.sv @@ -7,7 +7,7 @@ // // Purpose: SPI peripheral // -// SPI module is written to the specifications described in FU540-C000-v1.0. At the top level, it is consists of synchronous 8 byte transmit and recieve FIFOs connected to shift registers. +// SPI module is written to the specifications described in FU540-C000-v1.0. At the top level, it is consists of synchronous 8 byte transmit and receive FIFOs connected to shift registers. // The FIFOs are connected to WALLY by an apb control register interface, which includes various control registers for modifying the SPI transmission along with registers for writing // to the transmit FIFO and reading from the receive FIFO. The transmissions themselves are then controlled by a finite state machine. The SPI module uses 4 tristate pins for SPI input/output, // along with a 4 bit Chip Select signal, a clock signal, and an interrupt signal to WALLY. diff --git a/src/uncore/uartPC16550D.sv b/src/uncore/uartPC16550D.sv index 3639fe8d5..d8042647a 100644 --- a/src/uncore/uartPC16550D.sv +++ b/src/uncore/uartPC16550D.sv @@ -4,13 +4,13 @@ // Written: David_Harris@hmc.edu 21 January 2021 // Modified: // -// Purpose: Universial Asynchronous Receiver/ Transmitter with FIFOs +// Purpose: Universal Asynchronous Receiver/ Transmitter with FIFOs // Emulates interface of Texas Instruments PC16550D // https://media.digikey.com/pdf/Data%20Sheets/Texas%20Instruments%20PDFs/PC16550D.pdf // Compatible with UART in Imperas Virtio model // // Compatible with most of PC16550D with the following known exceptions: -// Generates 2 rather than 1.5 stop bits when 5-bit word length is slected and LCR[2] = 1 +// Generates 2 rather than 1.5 stop bits when 5-bit word length is selected and LCR[2] = 1 // Timeout not yet implemented // // Documentation: RISC-V System on Chip Design @@ -71,7 +71,7 @@ module uartPC16550D #(parameter UART_PRESCALE) ( logic [3:0] IER, MSR; logic [4:0] MCR; - // Syncrhonized and delayed UART signals + // Synchronized and delayed UART signals logic SINd, DSRbd, DCDbd, CTSbd, RIbd; logic SINsync, DSRbsync, DCDbsync, CTSbsync, RIbsync; logic DSRb2, DCDb2, CTSb2, RIb2; @@ -88,7 +88,7 @@ module uartPC16550D #(parameter UART_PRESCALE) ( logic [3:0] rxbitsreceived, txbitssent; statetype rxstate, txstate; - // shift registrs and FIFOs + // shift registers and FIFOs logic [9:0] rxshiftreg; logic [10:0] rxfifo[15:0]; logic [7:0] txfifo[15:0]; @@ -137,7 +137,7 @@ module uartPC16550D #(parameter UART_PRESCALE) ( always_ff @(posedge PCLK) begin {SINd, DSRbd, DCDbd, CTSbd, RIbd} <= {SIN, DSRb, DCDb, CTSb, RIb}; {SINsync, DSRbsync, DCDbsync, CTSbsync, RIbsync} <= loop ? {SOUTbit, ~MCR[0], ~MCR[3], ~MCR[1], ~MCR[2]} : - {SINd, DSRbd, DCDbd, CTSbd, RIbd}; // syncrhonized signals, handle loopback testing + {SINd, DSRbd, DCDbd, CTSbd, RIbd}; // synchronized signals, handle loopback testing {DSRb2, DCDb2, CTSb2, RIb2} <= {DSRbsync, DCDbsync, CTSbsync, RIbsync}; // for detecting state changes end @@ -171,7 +171,7 @@ module uartPC16550D #(parameter UART_PRESCALE) ( end // Line Status Register (8.6.3) - // Ben 6/9/21 I don't like how this is a register. A lot of the individual bits have clocked components, so this just adds unecessary delay. + // Ben 6/9/21 I don't like how this is a register. A lot of the individual bits have clocked components, so this just adds unnecessary delay. if (~MEMWb & (A == UART_LSR)) LSR[6:1] <= Din[6:1]; // recommended only for test, see 8.6.3 else begin @@ -203,7 +203,7 @@ module uartPC16550D #(parameter UART_PRESCALE) ( case (A) UART_DLL_RBR: if (DLAB) Dout = DLL; else Dout = RBR[7:0]; UART_DLM_IER: if (DLAB) Dout = DLM; else Dout = {4'b0, IER[3:0]}; - UART_IIR: Dout = {{2{fifoenabled}}, 2'b00, intrID[2:0], ~intrpending}; // Read only Interupt Ident Register + UART_IIR: Dout = {{2{fifoenabled}}, 2'b00, intrID[2:0], ~intrpending}; // Read only Interrupt Ident Register UART_LCR: Dout = LCR; UART_MCR: Dout = {3'b000, MCR}; UART_LSR: Dout = LSR; @@ -472,7 +472,7 @@ module uartPC16550D #(parameter UART_PRESCALE) ( // pointer indicates where the next write goes and not the location of the // current head, the head and tail pointer being equal imply two different // things. First it could mean the fifo is empty and second it could mean - // the fifo is full. To differenciate we need to know which pointer moved + // the fifo is full. To differentiate we need to know which pointer moved // to cause them to be equal. If the head pointer moved then it is full. // If the tail pointer moved then it is empty. it resets to empty so // if reset with the tail pointer indicating the last update. diff --git a/src/uncore/uart_apb.sv b/src/uncore/uart_apb.sv index f7dcf2a60..982cbe4b5 100644 --- a/src/uncore/uart_apb.sv +++ b/src/uncore/uart_apb.sv @@ -4,7 +4,7 @@ // Written: David_Harris@hmc.edu 21 January 2021 // Modified: // -// Purpose: APB Interface to Universial Asynchronous Receiver/ Transmitter with FIFOs +// Purpose: APB Interface to Universal Asynchronous Receiver/ Transmitter with FIFOs // Emulates interface of Texas Instruments PC165550D // Compatible with UART in Imperas Virtio model // diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv index f17fc67fe..0a4712ff6 100644 --- a/src/uncore/uncore.sv +++ b/src/uncore/uncore.sv @@ -195,9 +195,9 @@ module uncore import cvw::*; #(parameter cvw_t P)( // Address Decoder Delay (figure 4-2 in spec) // The select for HREADY needs to be based on the address phase address. If the device - // takes more than 1 cycle to repsond it needs to hold on to the old select until the - // device is ready. Hense this register must be selectively enabled by HREADY. - // However on reset None must be seleted. + // takes more than 1 cycle to respond it needs to hold on to the old select until the + // device is ready. Hence this register must be selectively enabled by HREADY. + // However on reset None must be selected. flopenl #(12) hseldelayreg(HCLK, ~HRESETn, HREADY, HSELRegions, 12'b1, {HSELSPID, HSELSDCD, HSELPLICD, HSELUARTD, HSELGPIOD, HSELCLINTD, HSELRamD, HSELBootRomD, HSELEXTD, HSELIROMD, HSELDTIMD, HSELNoneD}); diff --git a/synthDC/ppa/ppaAnalyze.py b/synthDC/ppa/ppaAnalyze.py index 296abf20d..aa9b0296d 100755 --- a/synthDC/ppa/ppaAnalyze.py +++ b/synthDC/ppa/ppaAnalyze.py @@ -16,7 +16,7 @@ import matplotlib.lines as lines import matplotlib.pyplot as plt import numpy as np import scipy.optimize as opt -import sklearn.metrics as skm # depricated, will need to replace with scikit-learn +import sklearn.metrics as skm # deprecated, will need to replace with scikit-learn from matplotlib.cbook import flatten diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index 53f1645f4..f5e296688 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -250,11 +250,11 @@ set verilogout_no_tri true set verilogout_equation false # setting to generate output files -set write_v 1 ;# generates structual netlist +set write_v 1 ;# generates structural netlist set write_sdc 1 ;# generates synopsys design constraint file for p&r set write_ddc 1 ;# compiler file in ddc format set write_sdf 1 ;# sdf file for backannotated timing sim -set write_pow 1 ;# genrates estimated power report +set write_pow 1 ;# generates estimated power report set write_rep 1 ;# generates estimated area and timing report set write_cst 1 ;# generate report of constraints set write_hier 1 ;# generate hierarchy report diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py index 1e8e1a66e..241fa1417 100755 --- a/synthDC/wallySynth.py +++ b/synthDC/wallySynth.py @@ -33,7 +33,7 @@ if __name__ == '__main__': parser.add_argument("-f", "--featuresweep", action='store_true', help = "Synthesize wally with features turned off progressively to visualize critical path") parser.add_argument("-v", "--version", choices=allConfigs, help = "Configuration of wally") - parser.add_argument("-t", "--targetfreq", type=int, help = "Target frequncy") + parser.add_argument("-t", "--targetfreq", type=int, help = "Target frequency") parser.add_argument("-e", "--tech", choices=techs, help = "Technology") parser.add_argument("-o", "--maxopt", action='store_true', help = "Turn on MAXOPT") parser.add_argument("-r", "--usesram", action='store_true', help = "Use SRAM modules") diff --git a/testbench/common/functionName.sv b/testbench/common/functionName.sv index 141dcd88f..203d7fc55 100644 --- a/testbench/common/functionName.sv +++ b/testbench/common/functionName.sv @@ -93,9 +93,9 @@ module functionName import cvw::*; #(parameter cvw_t P) ( end end // while (left <= right) // if the element pc is now found, right and left will be equal at this point. - // we need to check if pc is less than the array at left or greather. + // we need to check if pc is less than the array at left or greater. // if it is less than pc, then we select left as the index. - // if it is greather we want 1 less than left. + // if it is greater we want 1 less than left. if (array[left] < pc) begin minval = array[left]; mid = left; @@ -120,7 +120,7 @@ module functionName import cvw::*; #(parameter cvw_t P) ( // initial begin always @ (negedge reset) begin - // cannot readmemh directoy to a dynmaic array. Sad times :( + // cannot readmemh directly to a dynamic array. Sad times :( // Let's initialize a static array with FFFF_FFFF for all addresses. // Then we can readmemh and finally copy to the dynamic array. diff --git a/testbench/common/loggers.sv b/testbench/common/loggers.sv index 5ed07b6d6..dfb92a3f9 100644 --- a/testbench/common/loggers.sv +++ b/testbench/common/loggers.sv @@ -126,8 +126,8 @@ module loggers import cvw::*; #(parameter cvw_t P, assign EndSample = EndSampleFirst & ~ EndSampleDelayed; end else begin - // default start condiction is reset - // default end condiction is end of test (DCacheFlushDone) + // default start condition is reset + // default end condition is end of test (DCacheFlushDone) //assign StartSampleFirst = reset; //flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed); //assign StartSample = StartSampleFirst & ~ StartSampleDelayed; @@ -221,7 +221,7 @@ module loggers import cvw::*; #(parameter cvw_t P, dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b1000 ? "Z" : // cbo.zero dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0001 ? "V" : // cbo.inval should just clear the valid and dirty bits dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0010 ? "C" : // cbo.clean should act like a read in terms of the lru, but clears the dirty bit - dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0100 ? "L" : // cbo.flush should just clear and the valid and drity bits + dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0100 ? "L" : // cbo.flush should just clear and the valid and dirty bits "NULL"; end diff --git a/testbench/common/ramxdetector.sv b/testbench/common/ramxdetector.sv index fac34fb43..db5616169 100644 --- a/testbench/common/ramxdetector.sv +++ b/testbench/common/ramxdetector.sv @@ -4,7 +4,7 @@ // Written: David_Harris@hmc.edu // Modified: 2 July 2023 // -// Purpose: Detects if the processor is attempting to read unitialized RAM +// Purpose: Detects if the processor is attempting to read uninitialized RAM // // A component of the Wally configurable RISC-V project. // @@ -39,7 +39,7 @@ module ramxdetector #(parameter XLEN, LLEN) ( /* verilator lint_off WIDTHXZEXPAND */ if (MemReadM & ~LSULoadAccessFaultM & (ReadDataM === 'bx)) begin /* verilator lint_on WIDTHXZEXPAND */ - $display("WARNING: Attempting to read from unitialized RAM. Processor may go haywire if it uses x value. But this is normal in WALLY-mmu and ExceptionInstr tests."); + $display("WARNING: Attempting to read from uninitialized RAM. Processor may go haywire if it uses x value. But this is normal in WALLY-mmu and ExceptionInstr tests."); $display(" PCM = %x InstrM = %x (%s), IEUAdrM = %x", PCM, InstrM, InstrMName, IEUAdrM); //$stop; end diff --git a/testbench/common/riscvassertions.sv b/testbench/common/riscvassertions.sv index 4481d3f96..da38b7d3e 100644 --- a/testbench/common/riscvassertions.sv +++ b/testbench/common/riscvassertions.sv @@ -29,10 +29,10 @@ module riscvassertions import cvw::*; #(parameter cvw_t P); assert (P.F_SUPPORTED | ~P.ZFH_SUPPORTED) else $fatal(1, "Can't support half-precision fp (ZFH) without supporting float (F)"); assert (P.DCACHE_SUPPORTED | ~P.F_SUPPORTED | P.FLEN <= P.XLEN) else $fatal(1, "Data cache required to support FLEN > XLEN because AHB/DTIM bus width is XLEN"); assert (P.I_SUPPORTED ^ P.E_SUPPORTED) else $fatal(1, "Exactly one of I and E must be supported"); - assert (P.DCACHE_WAYSIZEINBYTES <= 4096 | (!P.DCACHE_SUPPORTED) | P.VIRTMEM_SUPPORTED == 0) else $fatal(1, "DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); + assert (P.DCACHE_WAYSIZEINBYTES <= 4096 | (!P.DCACHE_SUPPORTED) | P.VIRTMEM_SUPPORTED == 0) else $fatal(1, "DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and virtual memory is enabled (to prevent aliasing)"); assert (P.DCACHE_LINELENINBITS >= 128 | (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); assert (P.DCACHE_LINELENINBITS < P.DCACHE_WAYSIZEINBYTES*8) else $fatal(1, "DCACHE_LINELENINBITS must be smaller than way size"); - assert (P.ICACHE_WAYSIZEINBYTES <= 4096 | (!P.ICACHE_SUPPORTED) | P.VIRTMEM_SUPPORTED == 0) else $fatal(1, "ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); + assert (P.ICACHE_WAYSIZEINBYTES <= 4096 | (!P.ICACHE_SUPPORTED) | P.VIRTMEM_SUPPORTED == 0) else $fatal(1, "ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and virtual memory is enabled (to prevent aliasing)"); assert (P.ICACHE_LINELENINBITS >= 32 | (!P.ICACHE_SUPPORTED)) else $fatal(1, "ICACHE_LINELENINBITS must be at least 32 when caches are enabled"); assert (P.ICACHE_LINELENINBITS < P.ICACHE_WAYSIZEINBYTES*8) else $fatal(1, "ICACHE_LINELENINBITS must be smaller than way size"); assert (2**$clog2(P.DCACHE_LINELENINBITS) == P.DCACHE_LINELENINBITS | (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_LINELENINBITS must be a power of 2"); diff --git a/testbench/common/rvvitbwrapper.sv b/testbench/common/rvvitbwrapper.sv index f9c1f316c..689825468 100644 --- a/testbench/common/rvvitbwrapper.sv +++ b/testbench/common/rvvitbwrapper.sv @@ -45,7 +45,7 @@ module rvvitbwrapper import cvw::*; #(parameter cvw_t P, localparam TOTAL_CSRS = 36; - // pipeline controlls + // pipeline controls logic StallE, StallM, StallW, FlushE, FlushM, FlushW; // required logic [P.XLEN-1:0] PCM; diff --git a/testbench/sdc/sd_defines.h b/testbench/sdc/sd_defines.h index 9421fa5c0..118c3553d 100644 --- a/testbench/sdc/sd_defines.h +++ b/testbench/sdc/sd_defines.h @@ -49,7 +49,7 @@ `endif //SD-Clock Defines --------- -//Use bus clock or a seperate clock +//Use bus clock or a separate clock `define SDC_CLK_BUS_CLK //`define SDC_CLK_SEP diff --git a/testbench/testbench.sv b/testbench/testbench.sv index ee2eb430d..1f77dd967 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -264,7 +264,7 @@ module testbench; // Do this in parts so it easier to verify // part 1: build a version which echos the same behavior as the below code, but does not drive anything // part 2: drive some of the controls - // part 3: drive all logic and remove old inital and always @ negedge clk block + // part 3: drive all logic and remove old initial and always @ negedge clk block typedef enum logic [3:0]{STATE_TESTBENCH_RESET, STATE_INIT_TEST, @@ -407,7 +407,7 @@ module testbench; end // declare memory labels that interest us, the updateProgramAddrLabelArray task will find // the addr of each label and fill the array. To expand, add more elements to this array - // and initialize them to zero (also initilaize them to zero at the start of the next test) + // and initialize them to zero (also initialize them to zero at the start of the next test) updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, memfilename, WALLY_DIR, ProgramAddrLabelArray); end if(Validate) begin @@ -682,7 +682,7 @@ module testbench; InstrM, InstrW, InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); - // watch for problems such as lockup, reading unitialized memory, bad configs + // watch for problems such as lockup, reading uninitialized memory, bad configs watchdog #(P.XLEN, 1000000) watchdog(.clk, .reset, .TEST); // check if PCW is stuck ramxdetector #(P.XLEN, P.LLEN) ramxdetector(clk, dut.core.lsu.MemRWM[1], dut.core.lsu.LSULoadAccessFaultM, dut.core.lsu.ReadDataM, dut.core.ifu.PCM, InstrM, dut.core.lsu.IEUAdrM, InstrMName); @@ -766,7 +766,7 @@ end string filename; initial begin - // imperasDV requires the elffile be defined at the begining of the simulation. + // imperasDV requires the elffile be defined at the beginning of the simulation. int iter; longint x64; int x32[2]; diff --git a/testbench/testbench_fp.sv b/testbench/testbench_fp.sv index 48d4a293d..c163941ab 100644 --- a/testbench/testbench_fp.sv +++ b/testbench/testbench_fp.sv @@ -54,7 +54,7 @@ module testbench_fp; logic [P.Q_LEN*4+7:0] TestVectors[MAXVECTORS-1:0]; // list of test vectors logic [1:0] FmtVal; // value of the current Fmt - logic [2:0] UnitVal, OpCtrlVal, FrmVal; // value of the currnet Unit/OpCtrl/FrmVal + logic [2:0] UnitVal, OpCtrlVal, FrmVal; // value of the current Unit/OpCtrl/FrmVal logic WriteIntVal; // value of the current WriteInt logic [P.Q_LEN-1:0] X, Y, Z; // inputs read from TestFloat logic [P.FLEN-1:0] XPostBox; // inputs read from TestFloat @@ -67,7 +67,7 @@ module testbench_fp; logic [P.FLEN-1:0] FpRes, FpCmpRes; // Results from each unit logic [P.XLEN-1:0] IntRes, CmpRes; // Results from each unit logic [P.Q_LEN-1:0] FpResExtended; // FpRes extended to same length as Ans/Res - logic [4:0] FmaFlg, CvtFlg, DivFlg, CmpFlg; // Outputed flags + logic [4:0] FmaFlg, CvtFlg, DivFlg, CmpFlg; // Outputted flags logic AnsNaN, ResNaN, NaNGood; logic Xs, Ys, Zs; // sign of the inputs logic [P.NE-1:0] Xe, Ye, Ze; // exponent of the inputs @@ -141,10 +141,10 @@ module testbench_fp; /////////////////////////////////////////////////////////////////////////////////////////////// - // select tests relevent to the specified configuration + // select tests relevant to the specified configuration // cvtint - test integer conversion unit (fcvtint) // cvtfp - test floating-point conversion unit (fcvtfp) - // cmp - test comparison unit's LT, LE, EQ opperations (fcmp) + // cmp - test comparison unit's LT, LE, EQ operations (fcmp) // add - test addition // sub - test subtraction // div - test division @@ -157,7 +157,7 @@ module testbench_fp; // $display("This simulation for TEST is %s", TEST); // $display("This simulation for TEST is of the operand size of %s", TEST_SIZE); - if (P.Q_SUPPORTED & (TEST_SIZE == "QP" | TEST_SIZE == "all")) begin // if Quad percision is supported + if (P.Q_SUPPORTED & (TEST_SIZE == "QP" | TEST_SIZE == "all")) begin // if Quad precision is supported if (TEST === "cvtint" | TEST === "all") begin // if testing integer conversion // add the 128-bit cvtint tests to the to-be-tested list Tests = {Tests, f128rv32cvtint}; @@ -359,7 +359,7 @@ module testbench_fp; end end end - if (TEST === "cmp" | TEST === "all") begin // if comparisions are being tested + if (TEST === "cmp" | TEST === "all") begin // if comparisons are being tested // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f64cmp}; OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL}; @@ -470,7 +470,7 @@ module testbench_fp; end end end - if (TEST === "cmp" | TEST === "all") begin // if comparision is being tested + if (TEST === "cmp" | TEST === "all") begin // if comparison is being tested // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f32cmp}; OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL}; @@ -563,7 +563,7 @@ module testbench_fp; end end end - if (TEST === "cmp" | TEST === "all") begin // if comparisions are being tested + if (TEST === "cmp" | TEST === "all") begin // if comparisons are being tested // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f16cmp}; OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL}; @@ -904,8 +904,8 @@ module testbench_fp; // check results on falling edge of clk always @(negedge clk) begin // check if the NaN value is good. IEEE754-2019 sections 6.3 and 6.2.3 specify: - // - the sign of the NaN does not matter for the opperations being tested - // - when 2 or more NaNs are inputed the NaN that is propigated doesn't matter + // - the sign of the NaN does not matter for the operations being tested + // - when 2 or more NaNs are inputted the NaN that is propagated doesn't matter if (UnitVal !== `CVTFPUNIT & UnitVal !== `CVTINTUNIT) case (FmtVal) 2'b11: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res === {1'b0, {P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) | @@ -1275,7 +1275,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( `CVTINTUNIT: case (Fmt) 2'b11: begin // quad - // {is the integer a long, is the opperation to an integer} + // {is the integer a long, is the operation to an integer} casez ({OpCtrl[2:1]}) 2'b11: begin // long -> quad X = {P.Q_LEN{1'bx}}; @@ -1327,7 +1327,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( endcase end 2'b00: if (P.F_SUPPORTED) begin // single - // {is the integer a long, is the opperation to an integer} + // {is the integer a long, is the operation to an integer} casez ({OpCtrl[2:1]}) 2'b11: begin // long -> single X = {P.Q_LEN{1'bx}}; @@ -1353,7 +1353,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( endcase end 2'b10: begin // half - // {is the integer a long, is the opperation to an integer} + // {is the integer a long, is the operation to an integer} casez ({OpCtrl[2:1]}) 2'b11: begin // long -> half X = {P.Q_LEN{1'bx}}; diff --git a/testbench/tests.vh b/testbench/tests.vh index 46911dca5..45605b5dc 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -94,7 +94,7 @@ string embench[] = '{ "bd_speedopt_speed/src/edn/edn", "bd_speedopt_speed/src/huffbench/huffbench", "bd_speedopt_speed/src/matmult-int/matmult-int", - "bd_speedopt_speed/src/md5sum/md5sum", //commenting out tests from embench 2.0. When embench 2.0 launches stabilty, add these tests back + "bd_speedopt_speed/src/md5sum/md5sum", //commenting out tests from embench 2.0. When embench 2.0 launches stably, add these tests back "bd_speedopt_speed/src/minver/minver", "bd_speedopt_speed/src/nettle-aes/nettle-aes", "bd_speedopt_speed/src/nettle-sha256/nettle-sha256", @@ -1867,12 +1867,12 @@ string arch64d[] = '{ "rv64i_m/D/src/fssub.d_b8-01.S" }; -string arch64zicboz[] = '{ // as of 12/17/23 presently cbo.zero is the only CMO insturction with riscv-arch-test support +string arch64zicboz[] = '{ // as of 12/17/23 presently cbo.zero is the only CMO instruction with riscv-arch-test support `RISCVARCHTEST, "rv64i_m/CMO/src/cbo.zero-01.S" }; -string arch32zicboz[] = '{ // as of 12/17/23 presently cbo.zero is the only CMO insturction with riscv-arch-test support +string arch32zicboz[] = '{ // as of 12/17/23 presently cbo.zero is the only CMO instruction with riscv-arch-test support `RISCVARCHTEST, "rv32i_m/CMO/src/cbo.zero-01.S" }; diff --git a/testbench/trek_files/trek_user_backdoor.sv b/testbench/trek_files/trek_user_backdoor.sv index 342ade7b9..c93ea1783 100644 --- a/testbench/trek_files/trek_user_backdoor.sv +++ b/testbench/trek_files/trek_user_backdoor.sv @@ -84,7 +84,7 @@ bit trek_is_event_addr; // (`RAM_PATH.n_we == 1'b0)); //end -// Design specifc: one stage delayed so write has a time to settle +// Design specific: one stage delayed so write has a time to settle //always @(posedge trek_c2t_mbox_event) begin: read_all_mailboxes always @(posedge testbench.clk) begin: read_all_mailboxes trek_poll_mbox(); diff --git a/tests/coverage/Makefile b/tests/coverage/Makefile index 7e68c28c0..d1c529251 100644 --- a/tests/coverage/Makefile +++ b/tests/coverage/Makefile @@ -12,7 +12,7 @@ MEMFILES := $(addsuffix .memfile, $(ELFS)) all: $(OBJDUMPS) $(MEMFILES) -# Create dissassembly +# Create disassembly %.elf.objdump: %.elf riscv64-unknown-elf-objdump -S -D $< > $@ extractFunctionRadix.sh $@ diff --git a/tests/coverage/amoAccessFault.S b/tests/coverage/amoAccessFault.S index b69c545a4..f44d5be17 100644 --- a/tests/coverage/amoAccessFault.S +++ b/tests/coverage/amoAccessFault.S @@ -24,7 +24,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -// load code to initalize stack, handle interrupts, terminate +// load code to initialize stack, handle interrupts, terminate #include "WALLY-init-lib.h" diff --git a/tests/coverage/btbthrash.S b/tests/coverage/btbthrash.S index 8fedf372a..47bf5af5e 100644 --- a/tests/coverage/btbthrash.S +++ b/tests/coverage/btbthrash.S @@ -24,7 +24,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -// load code to initalize stack, handle interrupts, terminate +// load code to initialize stack, handle interrupts, terminate #include "WALLY-init-lib.h" main: @@ -140,6 +140,6 @@ jump23: addi x31, x31, -1 bne x31, x0, jump1 -finsihed: +finished: j done diff --git a/tests/coverage/csrwrites.S b/tests/coverage/csrwrites.S index ef0c283ec..d197526bc 100644 --- a/tests/coverage/csrwrites.S +++ b/tests/coverage/csrwrites.S @@ -24,7 +24,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -// load code to initalize stack, handle interrupts, terminate +// load code to initialize stack, handle interrupts, terminate #include "WALLY-init-lib.h" main: diff --git a/tests/coverage/dcache1.py b/tests/coverage/dcache1.py index 728d58ae9..17e6fca17 100644 --- a/tests/coverage/dcache1.py +++ b/tests/coverage/dcache1.py @@ -57,7 +57,7 @@ def write_repro_instrs(): if i == 12: wl('sd zero, 0(t0)') # D$ write to set PCM = PCF + 8 for proper alignment (stallD will happen). elif i == 13: - # the store in question happens here, at adresses 0x34, 0x74 + # the store in question happens here, at addresses 0x34, 0x74 wl('sd zero, 0(t0)') # it should hit this time else: # can't be a NOP or anything else that is encoded as compressed. @@ -73,7 +73,7 @@ if __name__ == "__main__": wl('#include "WALLY-init-lib.h"') wl('main:') - # excercise all 4 D$ ways. If they're not all full, it uses the first empty. + # exercise all 4 D$ ways. If they're not all full, it uses the first empty. # So we are sure all 4 ways are exercised. for i in range(dcache_num_ways): wl(comment=f"start way test #{i+1}") @@ -81,6 +81,6 @@ if __name__ == "__main__": wl('.align 6') # start at i$ set boundary. 6 lsb bits are zero. wl(comment=f"i$ boundary, way test #{i+1}") write_repro_instrs() - mem_addr += dcache_way_size_in_bytes # so that we excercise a new D$ way. + mem_addr += dcache_way_size_in_bytes # so that we exercise a new D$ way. wl("j done") diff --git a/tests/coverage/ebu.S b/tests/coverage/ebu.S index 4537686a1..268b624a5 100644 --- a/tests/coverage/ebu.S +++ b/tests/coverage/ebu.S @@ -24,7 +24,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -// load code to initalize stack, handle interrupts, terminate +// load code to initialize stack, handle interrupts, terminate #include "WALLY-init-lib.h" @@ -183,7 +183,7 @@ pagetable: .8byte 0x0000000020014C0F # for VA starting at 80200000 (misaligned megapage) .8byte 0x0000000020005001 # for VA starting at 80400000 (bad PBMT pages) .8byte 0x4000000020004C01 # for VA starting at 80600000 (bad entry: nonleaf PTE can't have PBMT != 0) - .8byte 0x0000000020005401 # for VA starting at 80800000 (testing rwx permissiosn with cbom/cboz) + .8byte 0x0000000020005401 # for VA starting at 80800000 (testing rwx permissions with cbom/cboz) .8byte 0x0000000020005801 # for VA starting at 80A00000 (pointer to NAPOT 64 KiB pages like at 80000000) .8byte 0x0000000020004C01 .8byte 0x0000000020004C01 diff --git a/tests/coverage/fpu.S b/tests/coverage/fpu.S index 760898306..bef7dd4a8 100644 --- a/tests/coverage/fpu.S +++ b/tests/coverage/fpu.S @@ -24,7 +24,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -// load code to initalize stack, handle interrupts, terminate +// load code to initialize stack, handle interrupts, terminate #include "WALLY-init-lib.h" main: @@ -120,9 +120,9 @@ main: fcvt.s.l ft0, t0 fcvt.s.lu ft0, t0 - // Tests verfying that half and quad floating point convertion instructions are not supported by rv64gc + // Tests verifying that half and quad floating point conversion instructions are not supported by rv64gc # fcvt.h.d ft3, ft0 // Somehow this instruction is taking the route on line 124 - // idea: enable the Q extension for this to work properly? A: Q and halfs not supported in rv64gc + // idea: enable the Q extension for this to work properly? A: Q and halves not supported in rv64gc # fcvt.h.w ft3, a0 # fcvt.w.h a0, ft0 # fcvt.q.w ft3, a0 diff --git a/tests/coverage/gshare.S b/tests/coverage/gshare.S index ef0fcab77..e591770d5 100644 --- a/tests/coverage/gshare.S +++ b/tests/coverage/gshare.S @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -// load code to initalize stack, handle interrupts, terminate +// load code to initialize stack, handle interrupts, terminate #include "WALLY-init-lib.h" diff --git a/tests/coverage/hptwAccessFault.S b/tests/coverage/hptwAccessFault.S index cb918a6e3..9692c6263 100644 --- a/tests/coverage/hptwAccessFault.S +++ b/tests/coverage/hptwAccessFault.S @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -// load code to initalize stack, handle interrupts, terminate +// load code to initialize stack, handle interrupts, terminate #include "WALLY-init-lib.h" diff --git a/tests/coverage/ieu.S b/tests/coverage/ieu.S index 285a170cb..fac8121e1 100644 --- a/tests/coverage/ieu.S +++ b/tests/coverage/ieu.S @@ -24,7 +24,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -// load code to initalize stack, handle interrupts, terminate +// load code to initialize stack, handle interrupts, terminate #include "WALLY-init-lib.h" main: @@ -97,7 +97,7 @@ main: csrw menvcfg, x1 csrw senvcfg, x1 li a0, 0 - ecall # swtich to user mode + ecall # switch to user mode cbo.inval (x2) cbo.clean (x3) cbo.flush (x1) diff --git a/tests/coverage/ifu.S b/tests/coverage/ifu.S index 054f4f336..9e0bcc941 100644 --- a/tests/coverage/ifu.S +++ b/tests/coverage/ifu.S @@ -24,7 +24,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -// load code to initalize stack, handle interrupts, terminate +// load code to initialize stack, handle interrupts, terminate #include "WALLY-init-lib.h" main: diff --git a/tests/coverage/ifuCamlineWrite.S b/tests/coverage/ifuCamlineWrite.S index 31dcc5d05..4f24fa11e 100644 --- a/tests/coverage/ifuCamlineWrite.S +++ b/tests/coverage/ifuCamlineWrite.S @@ -27,7 +27,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -// load code to initalize stack, handle interrupts, terminate +// load code to initialize stack, handle interrupts, terminate #include "WALLY-init-lib.h" diff --git a/tests/coverage/lsu.S b/tests/coverage/lsu.S index 1c1d7fea6..2f986c450 100644 --- a/tests/coverage/lsu.S +++ b/tests/coverage/lsu.S @@ -24,7 +24,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -// load code to initalize stack, handle interrupts, terminate +// load code to initialize stack, handle interrupts, terminate #include "WALLY-init-lib.h" main: diff --git a/tests/coverage/nonleafpbmtfault.S b/tests/coverage/nonleafpbmtfault.S index 29ca490d6..0f5efd2c9 100644 --- a/tests/coverage/nonleafpbmtfault.S +++ b/tests/coverage/nonleafpbmtfault.S @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -// load code to initalize stack, handle interrupts, terminate +// load code to initialize stack, handle interrupts, terminate #include "WALLY-init-lib.h" diff --git a/tests/coverage/priv.S b/tests/coverage/priv.S index 211e7d13a..41db80970 100644 --- a/tests/coverage/priv.S +++ b/tests/coverage/priv.S @@ -24,7 +24,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -// load code to initalize stack, handle interrupts, terminate +// load code to initialize stack, handle interrupts, terminate #include "WALLY-init-lib.h" main: diff --git a/tests/coverage/tlbASID.S b/tests/coverage/tlbASID.S index 29078f0da..f4077d04f 100644 --- a/tests/coverage/tlbASID.S +++ b/tests/coverage/tlbASID.S @@ -28,7 +28,7 @@ -// load code to initalize stack, handle interrupts, terminate +// load code to initialize stack, handle interrupts, terminate #include "WALLY-init-lib.h" diff --git a/tests/coverage/tlbGLB.S b/tests/coverage/tlbGLB.S index b8fdee742..01554f07b 100644 --- a/tests/coverage/tlbGLB.S +++ b/tests/coverage/tlbGLB.S @@ -27,7 +27,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// -// load code to initalize stack, handle interrupts, terminate +// load code to initialize stack, handle interrupts, terminate #include "WALLY-init-lib.h" @@ -43,7 +43,7 @@ main: li t5, 0 # j = 0, run nASID only once li t3, 32 //Max amount of Loops = 32 - li t4, 0x1000 //offset between addressses. + li t4, 0x1000 //offset between addresses. li t1, 0x00008067 //load in jalr x0 x1 0 instruction to be stored setup: diff --git a/tests/coverage/tlbGP.S b/tests/coverage/tlbGP.S index 25fb2af94..5864858ec 100644 --- a/tests/coverage/tlbGP.S +++ b/tests/coverage/tlbGP.S @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -// load code to initalize stack, handle interrupts, terminate +// load code to initialize stack, handle interrupts, terminate #include "WALLY-init-lib.h" diff --git a/tests/coverage/tlbMP.S b/tests/coverage/tlbMP.S index 7c7a76bbd..2939fca97 100644 --- a/tests/coverage/tlbMP.S +++ b/tests/coverage/tlbMP.S @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -// load code to initalize stack, handle interrupts, terminate +// load code to initialize stack, handle interrupts, terminate #include "WALLY-init-lib.h" diff --git a/tests/coverage/tlbMisaligned.S b/tests/coverage/tlbMisaligned.S index d72643c08..a4cf4b400 100644 --- a/tests/coverage/tlbMisaligned.S +++ b/tests/coverage/tlbMisaligned.S @@ -24,7 +24,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -// load code to initalize stack, handle interrupts, terminate +// load code to initialize stack, handle interrupts, terminate #include "WALLY-init-lib.h" @@ -57,7 +57,7 @@ main: add t0, t0, t2 # go to the next page lw t1, 1(t0) # load a misaligned aligned uncached address should fault add t0, t0, t2 # go to the next page - sw t1, 1(t0) # store to another misaligned uncached address should falt. + sw t1, 1(t0) # store to another misaligned uncached address should fault. fence.I diff --git a/tests/coverage/tlbNAPOT.S b/tests/coverage/tlbNAPOT.S index 859476d23..216570cf2 100644 --- a/tests/coverage/tlbNAPOT.S +++ b/tests/coverage/tlbNAPOT.S @@ -26,7 +26,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -// load code to initalize stack, handle interrupts, terminate +// load code to initialize stack, handle interrupts, terminate #include "WALLY-init-lib.h" diff --git a/tests/coverage/tlbTP.S b/tests/coverage/tlbTP.S index 89b5d1ec7..e189cbdd5 100644 --- a/tests/coverage/tlbTP.S +++ b/tests/coverage/tlbTP.S @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -// load code to initalize stack, handle interrupts, terminate +// load code to initialize stack, handle interrupts, terminate #include "WALLY-init-lib.h" diff --git a/tests/coverage/tlbmisc.S b/tests/coverage/tlbmisc.S index b16cca8cd..22a7314b3 100644 --- a/tests/coverage/tlbmisc.S +++ b/tests/coverage/tlbmisc.S @@ -24,7 +24,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -// load code to initalize stack, handle interrupts, terminate +// load code to initialize stack, handle interrupts, terminate #include "WALLY-init-lib.h" @@ -365,7 +365,7 @@ SpecialPage: .8byte 0x0000000020014CCF # for VA starting at 80200000 (misaligned megapage) .8byte 0x0000000020005001 # for VA starting at 80400000 (bad PBMT pages page table at 0x80014000) .8byte 0x4000000020004C01 # for VA starting at 80600000 (bad entry: nonleaf PTE can't have PBMT != 0) - .8byte 0x0000000020005401 # for VA starting at 80800000 (testing rwx permissiosn with cbom/cboz . page table at 0x80015000) + .8byte 0x0000000020005401 # for VA starting at 80800000 (testing rwx permissions with cbom/cboz . page table at 0x80015000) .8byte 0x0000000020004C01 # for VA starting at 80A00000 (pointer to NAPOT 64 KiB pages like at 80000000. page table at 0x80013000) .8byte 0x0F00000020004CCF # for VA starting at 80C00000 (bad reserved field in bits 60:54) .8byte 0x000000002000000F # for VA starting at 80E00000 (megapage not dirty or accessed) diff --git a/tests/coverage/vm64check.S b/tests/coverage/vm64check.S index 0cc16ef8d..b732098c7 100644 --- a/tests/coverage/vm64check.S +++ b/tests/coverage/vm64check.S @@ -25,7 +25,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// // Cover IMMU vm64check block by jumping to illegal virtual addresses -// Need a nonstandard trap handler to deal with returns from theses jumps +// Need a nonstandard trap handler to deal with returns from these jumps // assign eq_46_38 = &(VAdr[46:38]) | ~|(VAdr[46:38]); // assign eq_63_47 = &(VAdr[63:47]) | ~|(VAdr[63:47]); // assign UpperBitsUnequal = SV39Mode ? ~(eq_63_47 & eq_46_38) : ~eq_63_47; diff --git a/tests/fp/README.md b/tests/fp/README.md index c4cd2b97b..f642cbef7 100644 --- a/tests/fp/README.md +++ b/tests/fp/README.md @@ -42,7 +42,7 @@ The choices for `` are as follows: cvtint - test integer conversion unit (fcvtint) cvtfp - test floating-point conversion unit (fcvtfp) - cmp - test comparison unit's LT, LE, EQ opperations (fcmp) + cmp - test comparison unit's LT, LE, EQ operations (fcmp) add - test addition fma - test fma mul - test mult with fma diff --git a/tests/fp/combined_IF_vectors/IF_vectors/README b/tests/fp/combined_IF_vectors/IF_vectors/README index bfbf368dd..64bda21c0 100644 --- a/tests/fp/combined_IF_vectors/IF_vectors/README +++ b/tests/fp/combined_IF_vectors/IF_vectors/README @@ -1,4 +1,4 @@ -This folder holds the archtest and testfloat vectors necessary fo evaluating performance +This folder holds the archtest and testfloat vectors necessary for evaluating performance of standalone intdiv vs combined IFdivsqrt to generate vectors, uncomment line 8 in create_all_vectors.sh \ No newline at end of file diff --git a/tests/riscof/makefile-memfile b/tests/riscof/makefile-memfile index 6ccdca37c..309f36116 100644 --- a/tests/riscof/makefile-memfile +++ b/tests/riscof/makefile-memfile @@ -15,7 +15,7 @@ wally-sim-files: $(MEMFILES) $(ADDRFILES) # in the recipe. # because elf2hex requires a bit width we use findstring to figure out if the compiled directory # is XLEN=64 or 32. This is hacky and will likely break in the future. -# the .addr is a separate target so make can split into more jobs and more parallism. +# the .addr is a separate target so make can split into more jobs and more parallelism. %.elf.memfile: BITWIDTH ?= $(if $(findstring rv64,$*),64,32) %.elf.memfile: %.elf riscv64-unknown-elf-elf2hex --bit-width $(BITWIDTH) --input $< --output $@ diff --git a/tests/riscof/spike/riscof_spike.py b/tests/riscof/spike/riscof_spike.py index ece688241..43d1339a1 100644 --- a/tests/riscof/spike/riscof_spike.py +++ b/tests/riscof/spike/riscof_spike.py @@ -38,7 +38,7 @@ class spike(pluginTemplate): # Path to the directory where this python file is located. Collect it from the config.ini self.pluginpath=os.path.abspath(config['pluginpath']) - # Collect the paths to the riscv-config absed ISA and platform yaml files. One can choose + # Collect the paths to the riscv-config based ISA and platform yaml files. One can choose # to hardcode these here itself instead of picking it from the config.ini file. self.isa_spec = os.path.abspath(config['ispec']) self.platform_spec = os.path.abspath(config['pspec']) @@ -154,7 +154,7 @@ class spike(pluginTemplate): # function earlier make.makeCommand = 'make -j' + self.num_jobs - # we will iterate over each entry in the testList. Each entry node will be refered to by the + # we will iterate over each entry in the testList. Each entry node will be referred to by the # variable testname. for testname in testList: diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/env/arch_test.h b/tests/wally-riscv-arch-test/riscv-test-suite/env/arch_test.h index fee1e748b..e545fde6e 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/env/arch_test.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/env/arch_test.h @@ -271,7 +271,7 @@ #define MPP_SMODE (1<>IMMSGN)==0))/* fits 12b after shift? */ ;\ li reg, imm12sh /* <= 12bit, will be simple li */ ;\ slli reg, reg, edge1 /* add trailing zeros */ ;\ - .elseif ((immx==imme)&&(((absimmsh>>WDSGN)+crysh)==0)) /* fits 32 <>WDSGN)+crysh)==0)) /* fits 32 <>IMMSZ)+crysh)&LIMMMSK /* <=32b, use lui/addi */ ;\ .if ((imm12sh&IMMMSK)!=0) /* but skip this if low bits ==0 */ ;\ addi reg, reg, imm12sh ;\ @@ -1082,9 +1082,9 @@ rvtest_\__MODE__\()prolog_done: /**********************************************************************/ /**** This is the entry point for all x-modetraps, vectored or not.****/ /**** xtvec should either point here, or trampoline code does and ****/ - /**** trampoline code was copied to whereever xtvec pointed to. ****/ + /**** trampoline code was copied to wherever xtvec pointed to. ****/ /**** At entry, xscratch will contain a pointer to a scratch area. ****/ - /**** This is an array of branches at 4B intevals that spreads out ****/ + /**** This is an array of branches at 4B intervals that spreads out ****/ /**** to an array of 12B xhandler stubs for specd int causes, and ****/ /**** to a return for anything above that (which causes a mismatch)****/ /**********************************************************************/ @@ -1171,7 +1171,7 @@ spcl_\__MODE__\()2mmode_test: slli T3, T5, 1 // remove MSB, cause<<1 addi T3, T3, -(IRQ_M_TIMER)<<1 // is cause (w/o MSB) an extint or larger? ( (cause<<1) > (8<<1) )? bgez T3, \__MODE__\()trap_sig_sv // yes, keep std length - li T2, 3*REGWIDTH // no, its a timer or swint, overrride preinc to 3*regsz + li T2, 3*REGWIDTH // no, its a timer or swint, override preinc to 3*regsz j \__MODE__\()trap_sig_sv /**********************************************************************/ @@ -1635,7 +1635,7 @@ excpt_\__MODE__\()hndlr_tbl: // handler code should only touch T2..T6 \__MODE__\()clr_Mext_int: // inT11 default to just return after saving IntID in T3 RVMODEL_CLR_MEXT_INT - SREG T3, 3*REGWIDTH(T1) // save 4rd sig value, (intID) + SREG T3, 3*REGWIDTH(T1) // save 4th sig value, (intID) j resto_\__MODE__\()rtn //------------- SMode---------------- @@ -1649,7 +1649,7 @@ excpt_\__MODE__\()hndlr_tbl: // handler code should only touch T2..T6 \__MODE__\()clr_Sext_int: // int 9 default to just return after saving IntID in T3 RVMODEL_CLR_SEXT_INT - SREG T3, 3*REGWIDTH(T1) // save 4rd sig value, (intID) + SREG T3, 3*REGWIDTH(T1) // save 4th sig value, (intID) j resto_\__MODE__\()rtn //------------- VSmode---------------- @@ -1663,7 +1663,7 @@ excpt_\__MODE__\()hndlr_tbl: // handler code should only touch T2..T6 \__MODE__\()clr_Vext_int: // int 8 default to just return after saving IntID in T3 RVMODEL_CLR_VEXT_INT - SREG T3, 3*REGWIDTH(T1) // save 4rd sig value, (intID) + SREG T3, 3*REGWIDTH(T1) // save 4th sig value, (intID) j resto_\__MODE__\()rtn .ifc \__MODE__ , M @@ -1791,7 +1791,7 @@ rvtest_\__MODE__\()end: /*******************************************************************************/ /**** This macro defines per/mode save areas for mmode for each mode ****/ /**** note that it is the code area, not the data area, and ****/ -/**** must be mulitple of 8B, so multiple instantiations stay aligned ****/ +/**** must be multiple of 8B, so multiple instantiations stay aligned ****/ /**** This is preceded by the current signature pointer, (@Mtrpreg_sv -64? ****/ /*******************************************************************************/ .macro RVTEST_TRAP_SAVEAREA __MODE__ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/env/test_macros.h b/tests/wally-riscv-arch-test/riscv-test-suite/env/test_macros.h index be19bf88e..3101193ae 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/env/test_macros.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/env/test_macros.h @@ -7,7 +7,7 @@ Arguments: _PAR: Register containing Physical Address _PR: Register containing Permissions for Leaf PTE. - (Note: No-leaf PTE (if-any) has only valid permssion (pte.v) set) + (Note: No-leaf PTE (if-any) has only valid permission (pte.v) set) _TR0, _TR1, _TR2: Temporary registers used and modified by function VA: Virtual address level: Level at which PTE would be setup diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-spi-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-spi-01.reference_output index e19f75391..d2c5c1c8e 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-spi-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-spi-01.reference_output @@ -270,9 +270,9 @@ 00000022 #clear 1 frame from rx fifo -00000000 # read recieve ip +00000000 # read receive ip -00000002 #read recieve ip +00000002 #read receive ip 00000000 #read mip diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-mie-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-mie-01.reference_output index ef904a667..6798a887f 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-mie-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-mie-01.reference_output @@ -2,7 +2,7 @@ 0007ec03 # value to indicate successful vectoring on m soft interrupt 80000003 # mcause value from m time interrupt 00000000 # mtval for mtime interrupt (0x0) -00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 # Note here that we atempt to cause an interrupt after zeroing status.mie, but it shouldn't fire. +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 # Note here that we attempt to cause an interrupt after zeroing status.mie, but it shouldn't fire. 0000000b # mcause for ecall from terminating tests in M mode 00000000 # mtval of ecall (*** defined to be zero for now) 00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-sie-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-sie-01.reference_output index c621e5747..437e70ca6 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-sie-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-sie-01.reference_output @@ -6,7 +6,7 @@ 0007ec01 # value to indicate successful vectoring on s soft interrupt 80000001 # scause value from s soft interrupt 00000000 # stval for ssoft interrupt (0x0) -00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 # Note here that we atempt to cause an interrupt after zeroing status.mie, but it shouldn't fire. +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 # Note here that we attempt to cause an interrupt after zeroing status.mie, but it shouldn't fire. 00000009 # mcause for ecall from terminating tests in S mode 00000000 # mtval of ecall (*** defined to be zero for now) 00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output index e00557a76..6c3c64a34 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output @@ -8,13 +8,13 @@ FFFFFFFF # stimecmp readback FFFFFFFF # mtval of faulting instruction (0x11111111) 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000003 # mcause from Breakpoint -80000168 # mtval of breakpoint instruction adress +80000168 # mtval of breakpoint instruction address 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000004 # mcause from load address misaligned 80000171 # mtval of misaligned address 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000005 # mcause from load access -00000000 # mtval of accessed adress (0x0) +00000000 # mtval of accessed address (0x0) 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000006 # mcause from store misaligned 80000189 # mtval of address with misaligned store instr @@ -64,13 +64,13 @@ FFFFFFFF # mtval of faulting instruction (0x11111111) FFFFFFFF # stval of faulting instruction (0xFFFFFFFF) 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000003 # mcause from Breakpoint -80000168 # mtval of breakpoint instruction adress +80000168 # mtval of breakpoint instruction address 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000004 # mcause from load address misaligned 80000171 # mtval of misaligned address 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000005 # mcause from load access -00000000 # mtval of accessed adress (0x0) +00000000 # mtval of accessed address (0x0) 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000006 # mcause from store misaligned 80000189 # mtval of address with misaligned store instr diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output index bb64ad870..b098b1f84 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output @@ -9,13 +9,13 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF) 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000003 # scause from Breakpoint -80000168 # stval of breakpoint instruction adress +80000168 # stval of breakpoint instruction address 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000004 # scause from load address misaligned 80000171 # stval of misaligned address 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000005 # scause from load access -00000000 # stval of accessed adress (0x0) +00000000 # stval of accessed address (0x0) 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000006 # scause from store misaligned 80000189 # stval of address with misaligned store instr @@ -60,13 +60,13 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF) FFFFFFFF # stval of faulting instruction (0xFFFFFFFF) 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000003 # scause from Breakpoint -80000168 # stval of breakpoint instruction adress +80000168 # stval of breakpoint instruction address 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000004 # scause from load address misaligned 80000171 # stval of misaligned address 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000005 # scause from load access -00000000 # stval of accessed adress (0x0) +00000000 # stval of accessed address (0x0) 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000006 # scause from store misaligned 80000189 # stval of address with misaligned store instr diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output index 56ec350cc..817ca5167 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output @@ -9,13 +9,13 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF) 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000003 # scause from Breakpoint -80000168 # stval of breakpoint instruction adress +80000168 # stval of breakpoint instruction address 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000004 # scause from load address misaligned 80000171 # stval of misaligned address 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000005 # scause from load access -00000000 # stval of accessed adress (0x0) +00000000 # stval of accessed address (0x0) 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000006 # scause from store misaligned 80000189 # stval of address with misaligned store instr @@ -57,13 +57,13 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF) FFFFFFFF # stval of faulting instruction (0xFFFFFFFF) 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000003 # scause from Breakpoint -80000168 # stval of breakpoint instruction adress +80000168 # stval of breakpoint instruction address 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000004 # scause from load address misaligned 80000171 # stval of misaligned address 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000005 # scause from load access -00000000 # stval of accessed adress (0x0) +00000000 # stval of accessed address (0x0) 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000006 # scause from store misaligned 80000189 # stval of address with misaligned store instr diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h index 047417488..d23299a7e 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h @@ -63,7 +63,7 @@ RVTEST_CODE_BEGIN .endm -// Code to trigger traps goes here so we have consistent mtvals for instruction adresses +// Code to trigger traps goes here so we have consistent mtvals for instruction addresses // Even if more tests are added. .macro CAUSE_TRAP_TRIGGERS j end_trap_triggers @@ -81,10 +81,10 @@ cause_instr_addr_misaligned: ret cause_instr_access: - sw ra, -4(sp) // push the return adress ontot the stack + sw ra, -4(sp) // push the return address ontot the stack addi sp, sp, -4 jalr zero // cause instruction access trap (address zero is an address with no memory) - lw ra, 0(sp) // pop return adress back from the stack + lw ra, 0(sp) // pop return address back from the stack addi sp, sp, 4 ret @@ -270,7 +270,7 @@ end_trap_triggers: .if (\MODE\() == m) csrrw tp, \MODE\()tvec, ra // tp reserved for "default" trap handler address that needs to be restored before halting this test. .else - csrw \MODE\()tvec, ra // we only neet save the machine trap handler and this if statement ensures it isn't overwritten + csrw \MODE\()tvec, ra // we only need save the machine trap handler and this if statement ensures it isn't overwritten .endif li a0, 0 @@ -307,8 +307,8 @@ end_trap_triggers: // 0x0 : defaults to next instruction on the same page the trap was called on. // // a2 (x12): - // Pagetype of the current address VPN before changing privilge mode - // Used so that we can know how many bits of the adress are the offset. + // Pagetype of the current address VPN before changing privilege mode + // Used so that we can know how many bits of the address are the offset. // Ignored if a1 == 0x0 // 0: Kilopage // 1: Megapage @@ -318,7 +318,7 @@ end_trap_triggers: .align 6 trap_handler_\MODE\(): - j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler + j trap_unvectored_\MODE\() // for the unvectored implementation: jump past this table of addresses into the actual handler // ASSUMES that a cause value of 0 for an interrupt is unimplemented // otherwise, a vectored interrupt handler should jump to trap_handler_\MODE\() + 4 * Interrupt cause code // No matter the value of VECTORED, exceptions (not interrupts) are handled in an unvecotred way @@ -336,10 +336,10 @@ trap_handler_\MODE\(): // 12 through >=16 are reserved or designated for platform use trap_unvectored_\MODE\(): - csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself. + csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap handler without messing up sp's value or the stack itself. // NOTE: this means that nested traps will be screwed up but they shouldn't happen in any of these tests -trap_stack_saved_\MODE\(): // jump here after handling vectored interupt since we already switch sp and scratch there +trap_stack_saved_\MODE\(): // jump here after handling vectored interrupt since we already switch sp and scratch there // save registers on stack before using sw ra, -4(sp) sw t0, -8(sp) @@ -505,37 +505,37 @@ breakpt_\MODE\(): // note: does not mess up any registers, saves and restores them to the stack instead. s_soft_vector_\MODE\(): - csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself. + csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap handler without messing up sp's value or the stack itself. sw t0, -4(sp) // put t0 on the scratch stack before messing with it li t0, 0x7EC01 // write 0x7ec01 (for "VEC"tored and 01 for the interrupt code) j vectored_int_end_\MODE\() m_soft_vector_\MODE\(): - csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself. + csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap handler without messing up sp's value or the stack itself. sw t0, -4(sp) // put t0 on the scratch stack before messing with it li t0, 0x7EC03 // write 0x7ec03 (for "VEC"tored and 03 for the interrupt code) j vectored_int_end_\MODE\() s_time_vector_\MODE\(): - csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself. + csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap handler without messing up sp's value or the stack itself. sw t0, -4(sp) // put t0 on the scratch stack before messing with it li t0, 0x7EC05 // write 0x7ec05 (for "VEC"tored and 05 for the interrupt code) j vectored_int_end_\MODE\() m_time_vector_\MODE\(): - csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself. + csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap handler without messing up sp's value or the stack itself. sw t0, -4(sp) // put t0 on the scratch stack before messing with it li t0, 0x7EC07 // write 0x7ec07 (for "VEC"tored and 07 for the interrupt code) j vectored_int_end_\MODE\() s_ext_vector_\MODE\(): - csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself. + csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap handler without messing up sp's value or the stack itself. sw t0, -4(sp) // put t0 on the scratch stack before messing with it li t0, 0x7EC09 // write 0x7ec09 (for "VEC"tored and 08 for the interrupt code) j vectored_int_end_\MODE\() m_ext_vector_\MODE\(): - csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself. + csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap handler without messing up sp's value or the stack itself. sw t0, -4(sp) // put t0 on the scratch stack before messing with it li t0, 0x7EC0B // write 0x7ec0B (for "VEC"tored and 0B for the interrupt code) j vectored_int_end_\MODE\() @@ -668,11 +668,11 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a // read32_test : Read 32 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex // read16_test : Read 16 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex // read08_test : Read 8 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex -// executable_test : test executable on virtual page : 0x0, 0x1, or 0xc, then 0xbad : value of t2 modified by exectuion code (usually 0x111) +// executable_test : test executable on virtual page : 0x0, 0x1, or 0xc, then 0xbad : value of t2 modified by execution code (usually 0x111) // terminate_test : terminate tests : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 // goto_baremetal : satp.MODE = bare metal : None : None // goto_sv32 : satp.MODE = sv32 : None : None -// goto_m_mode : go to mahcine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 +// goto_m_mode : go to machine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 // goto_s_mode : go to supervisor mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 // goto_u_mode : go to user mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 // write_read_csr : write to specified CSR : old CSR value, 0x2, depending on perms : value written to CSR @@ -823,7 +823,7 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a // 0x2, then // 0x11 *** consider changing to something more meaningful // Fault outputs: - // 0xBAD *** consider changing this one as well. in general, do we need the branching if it hould cause an illegal instruction fault? + // 0xBAD *** consider changing this one as well. in general, do we need the branching if it should cause an illegal instruction fault? csrr t4, \CSR csrwi \CSR\(), 0xA // Attempt to write a 'random' value to the CSR csrr t5, \CSR @@ -840,7 +840,7 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a .macro EXECUTE_AT_ADDRESS ADDR // Execute the code already written to ADDR, returning the value in t2. - // *** Note: this test itself doesn't write the code to ADDR because it might be callled at a point where we dont have write access to ADDR + // *** Note: this test itself doesn't write the code to ADDR because it might be called at a point where we dont have write access to ADDR // Assumes the code modifies t2, usually to become 0x111. // Sample code: 0x11100393 (li t2, 0x111), 0x00008067 (ret) // Success outputs: @@ -939,13 +939,13 @@ test_loop: // read32_test : Read 32 bits from address : 0xd, 0xbad : readvalue in hex // read16_test : Read 16 bits from address : 0xd, 0xbad : readvalue in hex // read08_test : Read 8 bits from address : 0xd, 0xbad : readvalue in hex -// executable_test : test executable on virtual page : 0xc, 0xbad : value of t2 modified by exectuion code (usually 0x111) +// executable_test : test executable on virtual page : 0xc, 0xbad : value of t2 modified by execution code (usually 0x111) // terminate_test : terminate tests : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 // goto_baremetal : satp.MODE = bare metal : None : None // goto_sv39 : satp.MODE = sv39 : None : None // goto_sv48 : satp.MODE = sv48 : None : None // write_mxr_sum : write sstatus.[19:18] = MXR, SUM bits : None : None -// goto_m_mode : go to mahcine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 +// goto_m_mode : go to machine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 // goto_s_mode : go to supervisor mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 // goto_u_mode : go to user mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 // write_pmpcfg_x : Write one of the pmpcfg csr's : mstatuses?, 0xD : readback of pmpcfg value diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S index a222a37a5..5b225d812 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S @@ -30,7 +30,7 @@ INIT_TESTS TRAP_HANDLER m -# Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in S mode. +# Test 5.2.3.6: Test that all the machine mode CSR's are inaccessible for reads and writes in S mode. GOTO_S_MODE 0x0, 0x0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-u-01.S index 0835c8c1b..e7d82e967 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-u-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-u-01.S @@ -30,7 +30,7 @@ INIT_TESTS TRAP_HANDLER m -# Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in R mode. +# Test 5.2.3.6: Test that all the machine mode CSR's are inaccessible for reads and writes in R mode. GOTO_U_MODE 0x0, 0x0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-endianness-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-endianness-01.S index 01097e03f..38e6a62b5 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-endianness-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-endianness-01.S @@ -30,7 +30,7 @@ INIT_TESTS TRAP_HANDLER m -// Test 5.3.2.4: testing that accesses to sub-word memory acceses not on a word boundary go +// Test 5.3.2.4: testing that accesses to sub-word memory accesses not on a word boundary go // correctly with the relevant status bit indicating endianness for each mode. // do this by going to each mode with and testing loads with the big endian bit on and off work correctly diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-misa-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-misa-01.S index b5d8f271a..c8f3e6bf0 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-misa-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-misa-01.S @@ -31,7 +31,7 @@ INIT_TESTS TRAP_HANDLER m // Test 5.3.2.2: Machine ISA register test -// Misa is a specific case *** so I don't want to add a whole test case for reading nonzero but unkown value CSRs. +// Misa is a specific case *** so I don't want to add a whole test case for reading nonzero but unknown value CSRs. csrr x30, misa // should not cause a fault in machine mode. *** not writing to output because MISA is different for different configs. li x7, 0x111 // success value for read of nonzero misa bnez x30, misa_nonzero diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-01.S index d18fbd76e..c1d87c26e 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-01.S @@ -54,7 +54,7 @@ test_cases: # =========== test 11.3.1.1 Page Table Translation =========== -# test 11.3.1.1.1 write page tables / entries to phyiscal memory +# test 11.3.1.1.1 write page tables / entries to physical memory # sv32 Page table (See Figure 12.12***): # Level 1 page table, situated at 0x8000D000 .4byte 0x8000D000, 0x20004C01, write32_test # points to level 0 page table A diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S index f4c30a8e6..f391abfd4 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S @@ -54,7 +54,7 @@ test_cases: # =========== test 11.3.1.1 Page Table Translation =========== -# test 11.3.1.1.1 write page tables / entries to phyiscal memory +# test 11.3.1.1.1 write page tables / entries to physical memory # sv32 Page table (See Figure 12.12***): # Level 1 page table, situated at 0x8000D000 .4byte 0x8000D000, 0x20004C01, write32_test # points to level 0 page table A @@ -180,7 +180,7 @@ test_cases: .4byte 0x3020, 0xBEEF0770, read32_test # Read success when A=0 and SVADU is enabled # test 11.3.1.3.7(b) Dirty flag == 0 -.4byte 0x4658, 0xBEEF0AA0, write32_test # write successs when D=0 and SVADU is enabled +.4byte 0x4658, 0xBEEF0AA0, write32_test # write success when D=0 and SVADU is enabled .4byte 0x4658, 0xBEEF0AA0, read32_test # read success when D=0 # =========== test 11.3.1.4 SATP Register =========== diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-01.S index 856b41b23..56b5192c4 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-01.S @@ -693,7 +693,7 @@ Intr03BEEF13: li t1, 0b00010000 1: bne t1,a0,1b li a0, 0 - # ========== Received Data Available Intrrupt (ERBFI) & Loop Mode ========== + # ========== Received Data Available Interrupt (ERBFI) & Loop Mode ========== # Clear SCR sb x0, 7(t0) Intr03BEEF14: diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-s-01.S index d87c1a5f4..59f423b8a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-s-01.S @@ -696,7 +696,7 @@ Intr03BEEF13: li t1, 0b00010000 1: bne t1,a0,1b li a0, 0 - # ========== Received Data Available Intrrupt (ERBFI) & Loop Mode ========== + # ========== Received Data Available Interrupt (ERBFI) & Loop Mode ========== # Clear SCR sb x0, 7(t0) Intr03BEEF14: diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-satp-invalid-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-satp-invalid-01.S index 246d6e96d..bde884317 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-satp-invalid-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-satp-invalid-01.S @@ -34,8 +34,8 @@ csrw mtvec, t4 // set the new trap handler to do the pre behavior first. GOTO_S_MODE // go to S mode to attempt to turn on virtual memory -la ra, post_satp // load the address after the failing adress into ra so it doesn't get confused -GOTO_SV32 0x0, 0x0 // attempt to turn on virtual memory with satp pointing to an invlaid address. Should cause invalid instruction exception +la ra, post_satp // load the address after the failing address into ra so it doesn't get confused +GOTO_SV32 0x0, 0x0 // attempt to turn on virtual memory with satp pointing to an invalid address. Should cause invalid instruction exception post_satp: j test_end diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sie-01.S index d4d6c4f35..6f63f061a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sie-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sie-01.S @@ -44,7 +44,7 @@ WRITE_READ_CSR sie, 0x0 // force zeroing out mie CSR. // note that none of these interrupts should be caught or handled. jal cause_s_time_interrupt // write this from M mode to attempt to make s time interrupt pending -GOTO_S_MODE // this would cause S mode interrupt to fire, but it shouldn't since SIE is zeored out. +GOTO_S_MODE // this would cause S mode interrupt to fire, but it shouldn't since SIE is zeroed out. jal cause_s_soft_interrupt # li a3, 0x40 // these interrupts involve a time loop waiting for the interrupt to go off. // since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-spi-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-spi-01.S index 19b70829c..bb2c47dac 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-spi-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-spi-01.S @@ -258,7 +258,7 @@ test_cases: # Test cs-sck delay of 0 with sck phase = 0 (implicit half cycle delay) -.4byte cs_mode, 0x00000000, write32_test # reset cs_mode to auto, all cs and sck mode settings should be defualt +.4byte cs_mode, 0x00000000, write32_test # reset cs_mode to auto, all cs and sck mode settings should be default .4byte delay0, 0x00010000, write32_test # set cs-sck delay to 0 .4byte tx_data, 0x00000020, write32_test # place 8'h11 into tx_data .4byte 0x0, 0x00000000, spi_data_wait # wait for transmission to end @@ -635,23 +635,23 @@ SETUP_PLIC .4byte tx_mark, 0x00000001, write32_test # set transmit watermark to 1 (any entry turns mark off) .4byte sck_div, 0x00000100, write32_test # lower SPI clock rate so read32_tests trigger at correct times #.4byte ie, 0x00000000, write32_test # enable transmit interrupt -.4byte ip, 0x00000001, read32_test # tx watermark interupt should be pending +.4byte ip, 0x00000001, read32_test # tx watermark interrupt should be pending .4byte 0x0, 0x00000000, readmip_test .4byte tx_data, 0x55443322, spi_burst_send # place 4 entries in transmit fifo -.4byte ip, 0x00000000, read32_test # tx watermark interupt should be off 125 +.4byte ip, 0x00000000, read32_test # tx watermark interrupt should be off 125 .4byte 0x0, 0x00000003, spi_data_wait # wait for transmission to end -# test recieve watermark interrupt (triggers when entries in rx FIFO > rx watermark) +# test receive watermark interrupt (triggers when entries in rx FIFO > rx watermark) .4byte tx_mark, 0x00000000, write32_test # set tx_mark to 0 .4byte rx_data, 0x00000022, read32_test # clear one entry from rx FIFO -.4byte rx_mark, 0x00000003, write32_test # set recieve watermark to 3 +.4byte rx_mark, 0x00000003, write32_test # set receive watermark to 3 #.4byte ie, 0x0000002, write32_test # enable receive interrupts .4byte ip, 0x00000000, read32_test # rx interrupts should be low (rx FIFO has 3 entries) -.4byte rx_mark, 0x00000002, write32_test # set recieve watermark to 2 -.4byte ip, 0x00000002, read32_test # recieve interrupt should be high +.4byte rx_mark, 0x00000002, write32_test # set receive watermark to 2 +.4byte ip, 0x00000002, read32_test # receive interrupt should be high .4byte 0x0, 0x00000000, readmip_test -.4byte rx_data, 0x00000033, read32_test # clear one more entry from recieve FIFO (2 entries) +.4byte rx_data, 0x00000033, read32_test # clear one more entry from receive FIFO (2 entries) .4byte ip, 0x00000000, read32_test # receive interrupt should be low .4byte rx_data, 0x00000044, read32_test .4byte rx_data, 0x00000055, read32_test # clear rx fifo @@ -659,25 +659,25 @@ SETUP_PLIC .4byte tx_mark, 0x00000001, write32_test # set transmit watermark to 0 .4byte ie, 0x00000001, write32_test # enable transmit interrupt -.4byte ip, 0x00000001, read32_test # tx watermark interupt should be pending +.4byte ip, 0x00000001, read32_test # tx watermark interrupt should be pending .4byte 0x0, 0x00000800, readmip_test .4byte ie, 0x00000000, write32_test # disable tx intr .4byte tx_data, 0x55443322, spi_burst_send # place 4 entries in transmit fifo .4byte 0x0, 0x00000003, spi_data_wait # wait for transmission to end -# test recieve watermark interrupt (triggers when entries in rx FIFO > rx watermark) +# test receive watermark interrupt (triggers when entries in rx FIFO > rx watermark) .4byte tx_mark, 0x00000000, write32_test .4byte 0x0, 0x00000000, claim_m_plic_interrupts .4byte rx_data, 0x00000022, read32_test # clear one entry from rx FIFO -.4byte rx_mark, 0x00000003, write32_test # set recieve watermark to 3 +.4byte rx_mark, 0x00000003, write32_test # set receive watermark to 3 .4byte ie, 0x0000002, write32_test # enable receive interrupts .4byte ip, 0x00000000, read32_test # rx interrupts should be low (rx FIFO has 3 entries) .4byte 0x0, 0x00000000, readmip_test -.4byte rx_mark, 0x00000002, write32_test # set recieve watermark to 2 -.4byte ip, 0x00000002, read32_test # recieve interrupt should be high +.4byte rx_mark, 0x00000002, write32_test # set receive watermark to 2 +.4byte ip, 0x00000002, read32_test # receive interrupt should be high .4byte 0x0, 0x00000800, readmip_test -.4byte rx_data, 0x00000033, read32_test # clear one more entry from recieve FIFO (2 entries) +.4byte rx_data, 0x00000033, read32_test # clear one more entry from receive FIFO (2 entries) .4byte 0x0, 0x00000000, claim_m_plic_interrupts .4byte ip, 0x00000000, read32_test # receive interrupt should be low .4byte 0x0, 0x00000000, readmip_test diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-sie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-sie-01.S index 60e9c5c8b..ba7e21c96 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-sie-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-sie-01.S @@ -31,7 +31,7 @@ INIT_TESTS CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses TRAP_HANDLER m, EXT_SIGNATURE=1 // necessary so we can go to S mode -TRAP_HANDLER s, EXT_SIGNATURE=1 // neccessary to handle s mode interrupts. +TRAP_HANDLER s, EXT_SIGNATURE=1 // necessary to handle s mode interrupts. li x28, 0x2 csrs sstatus, x28 // set sstatus.SIE bit to 1 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S index d779f74fa..db0180350 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S @@ -68,7 +68,7 @@ li a3, 0x40 jal cause_m_ext_interrupt // Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler -// We can tell which one becuase the different trap handler modes write different bits of the status register +// We can tell which one because the different trap handler modes write different bits of the status register // to the output when EXT_SIGNATURE is on. GOTO_M_MODE // so we can write the delegate registers diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S index 98da8180e..aebd44c5b 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S @@ -55,7 +55,7 @@ jal cause_store_addr_misaligned jal cause_store_acc jal cause_ecall -// some interrupts excluded becaus writing SIP/MIP is illegal from U mode +// some interrupts excluded because writing SIP/MIP is illegal from U mode jal cause_m_soft_interrupt jal cause_m_time_interrupt li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off. @@ -65,7 +65,7 @@ li a3, 0x40 jal cause_m_ext_interrupt // Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler -// We can tell which one becuase the different trap handler modes write different bits of the status register +// We can tell which one because the different trap handler modes write different bits of the status register // to the output when EXT_SIGNATURE is on. GOTO_M_MODE // so we can write the delegate registers diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-timeout-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-timeout-01.S index 2ed238e23..3ef2e35fd 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-timeout-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-timeout-01.S @@ -87,7 +87,7 @@ TEST_STACK_AND_DATA // in your isa // first claim the plic's uart interrupt by reading the claim register corresponding to 10 on context 0. - // then you'll read all entires in the fifo. + // then you'll read all entries in the fifo. // then you'll write the completed plic register to 10 on context 0. // claim and completed have the same address. // then you'll return by mret. diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pma-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pma-01.reference_output index b4f0eb957..702650dac 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pma-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pma-01.reference_output @@ -16,7 +16,7 @@ ffffffff 00000000 00000bad 00000000 -00000002 # read 32 bits success in PLIC (confriming 32 bit write) +00000002 # read 32 bits success in PLIC (confirming 32 bit write) 00000000 00000007 # write 16 bits with access fault in PLIC 00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pmp-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pmp-01.reference_output index dd9c15aaa..a8f371666 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pmp-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pmp-01.reference_output @@ -50,7 +50,7 @@ 00000000 00000bad 00000000 -00000111 # execute sucess when X=1 +00000111 # execute success when X=1 00000000 00000009 # ecall from terminating tests in S mode 00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-spi-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-spi-01.reference_output index bc17f4beb..ecadb674f 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-spi-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-spi-01.reference_output @@ -270,9 +270,9 @@ 00000000 00000022 #clear 1 frame from rx fifo 00000000 -00000000 # read recieve ip +00000000 # read receive ip 00000000 -00000002 #read recieve ip +00000002 #read receive ip 00000000 00000000 #read mip 00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-mie-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-mie-01.reference_output index 6137356a4..00b6ac726 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-mie-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-mie-01.reference_output @@ -7,7 +7,7 @@ 00000000 # mtval for mtime interrupt (0x0) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 -00000000 # Note here that we atempt to cause an interrupt after zeroing status.mie, but it shouldn't fire. +00000000 # Note here that we attempt to cause an interrupt after zeroing status.mie, but it shouldn't fire. 0000000b # mcause for ecall from terminating tests in M mode 00000000 00000000 # mtval of ecall (*** defined to be zero for now) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-sie-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-sie-01.reference_output index fe70c5c8a..d0bf7c8e7 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-sie-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-sie-01.reference_output @@ -15,7 +15,7 @@ 00000000 # stval for ssoft interrupt (0x0) 00000000 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 -00000000 # Note here that we atempt to cause an interrupt after zeroing status.mie, but it shouldn't fire. +00000000 # Note here that we attempt to cause an interrupt after zeroing status.mie, but it shouldn't fire. 00000009 # mcause for ecall from terminating tests in S mode 00000000 00000000 # mtval of ecall (*** defined to be zero for now) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output index 0d4d58764..1b79faa57 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output @@ -19,7 +19,7 @@ FFFFFFFF # mtval of faulting instruction (0xFFFFFFFF) 00000000 00000003 # mcause from Breakpoint 00000000 -80000458 # mtval of breakpoint instruction adress (0x80000458) +80000458 # mtval of breakpoint instruction address (0x80000458) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 @@ -31,7 +31,7 @@ FFFFFFFF # mtval of faulting instruction (0xFFFFFFFF) 00000000 00000005 # mcause from load access 00000000 -00000000 # mtval of accessed adress (0x0) +00000000 # mtval of accessed address (0x0) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 @@ -131,7 +131,7 @@ FFFFFFFF # mtval of faulting instruction (0xFFFFFFFF) 00000000 00000003 # mcause from Breakpoint 00000000 -80000458 # mtval of breakpoint instruction adress (0x80000458) +80000458 # mtval of breakpoint instruction address (0x80000458) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 @@ -143,7 +143,7 @@ FFFFFFFF # mtval of faulting instruction (0xFFFFFFFF) 00000000 00000005 # mcause from load access 00000000 -00000000 # mtval of accessed adress (0x0) +00000000 # mtval of accessed address (0x0) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output index 6ee0e975f..1235ea058 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output @@ -20,7 +20,7 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF) 00000000 00000003 # scause from Breakpoint 00000000 -80000458 # stval of breakpoint instruction adress (0x80000400) +80000458 # stval of breakpoint instruction address (0x80000400) 00000000 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 @@ -32,7 +32,7 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF) 00000000 00000005 # scause from load access 00000000 -00000000 # stval of accessed adress (0x0) +00000000 # stval of accessed address (0x0) 00000000 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 @@ -122,7 +122,7 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF) 00000000 00000003 # scause from Breakpoint 00000000 -80000458 # stval of breakpoint instruction adress (0x80000400) +80000458 # stval of breakpoint instruction address (0x80000400) 00000000 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000000 @@ -134,7 +134,7 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF) 00000000 00000005 # scause from load access 00000000 -00000000 # stval of accessed adress (0x0) +00000000 # stval of accessed address (0x0) 00000000 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output index 240fe10f0..36fc6c99f 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output @@ -20,7 +20,7 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF) 00000000 00000003 # scause from Breakpoint 00000000 -80000458 # stval of breakpoint instruction adress (0x80000400) +80000458 # stval of breakpoint instruction address (0x80000400) 00000000 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 @@ -32,7 +32,7 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF) 00000000 00000005 # scause from load access 00000000 -00000000 # stval of accessed adress (0x0) +00000000 # stval of accessed address (0x0) 00000000 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 @@ -116,7 +116,7 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF) 00000000 00000003 # scause from Breakpoint 00000000 -80000458 # stval of breakpoint instruction adress (0x80000400) +80000458 # stval of breakpoint instruction address (0x80000400) 00000000 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000000 @@ -128,7 +128,7 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF) 00000000 00000005 # scause from load access 00000000 -00000000 # stval of accessed adress (0x0) +00000000 # stval of accessed address (0x0) 00000000 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h index 0d2a2c257..07a4ddda2 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h @@ -64,7 +64,7 @@ RVTEST_CODE_BEGIN .endm -// Code to trigger traps goes here so we have consistent mtvals for instruction adresses +// Code to trigger traps goes here so we have consistent mtvals for instruction addresses // Even if more tests are added. .macro CAUSE_TRAP_TRIGGERS j end_trap_triggers @@ -82,10 +82,10 @@ cause_instr_addr_misaligned: ret cause_instr_access: - sd ra, -8(sp) // push the return adress onto the stack + sd ra, -8(sp) // push the return address onto the stack addi sp, sp, -8 jalr zero // cause instruction access trap (address zero is an address with no memory) - ld ra, 0(sp) // pop return adress back from the stack + ld ra, 0(sp) // pop return address back from the stack addi sp, sp, 8 ret @@ -266,7 +266,7 @@ end_trap_triggers: .if (\MODE\() == m) csrrw tp, \MODE\()tvec, ra // tp reserved for "default" trap handler address that needs to be restored before halting this test. .else - csrw \MODE\()tvec, ra // we only neet save the machine trap handler and this if statement ensures it isn't overwritten + csrw \MODE\()tvec, ra // we only need save the machine trap handler and this if statement ensures it isn't overwritten .endif li a0, 0 @@ -303,8 +303,8 @@ end_trap_triggers: // 0x0 : defaults to next instruction on the same page the trap was called on. // // a2 (x12): - // Pagetype of the current address VPN before changing privilge mode - // Used so that we can know how many bits of the adress are the offset. + // Pagetype of the current address VPN before changing privilege mode + // Used so that we can know how many bits of the address are the offset. // Ignored if a1 == 0x0 // 0: Kilopage // 1: Megapage @@ -315,7 +315,7 @@ end_trap_triggers: .align 6 trap_handler_\MODE\(): - j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler + j trap_unvectored_\MODE\() // for the unvectored implementation: jump past this table of addresses into the actual handler // *** ASSUMES that a cause value of 0 for an interrupt is unimplemented // otherwise, a vectored interrupt handler should jump to trap_handler_\MODE\() + 4 * Interrupt cause code // No matter the value of VECTORED, exceptions (not interrupts) are handled in an unvecotred way @@ -333,10 +333,10 @@ trap_handler_\MODE\(): // 12 through >=16 are reserved or designated for platform use trap_unvectored_\MODE\(): - csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself. + csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap handler without messing up sp's value or the stack itself. // *** NOTE: this means that nested traps will be screwed up but they shouldn't happen in any of these tests -trap_stack_saved_\MODE\(): // jump here after handling vectored interupt since we already switch sp and scratch there +trap_stack_saved_\MODE\(): // jump here after handling vectored interrupt since we already switch sp and scratch there // save registers on stack before using sd ra, -8(sp) sd t0, -16(sp) @@ -502,37 +502,37 @@ breakpt_\MODE\(): // note: does not mess up any registers, saves and restores them to the stack instead. s_soft_vector_\MODE\(): - csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself. + csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap handler without messing up sp's value or the stack itself. sd t0, -8(sp) // put t0 on the scratch stack before messing with it li t0, 0x7EC01 // write 0x7ec01 (for "VEC"tored and 01 for the interrupt code) j vectored_int_end_\MODE\() m_soft_vector_\MODE\(): - csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself. + csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap handler without messing up sp's value or the stack itself. sd t0, -8(sp) // put t0 on the scratch stack before messing with it li t0, 0x7EC03 // write 0x7ec03 (for "VEC"tored and 03 for the interrupt code) j vectored_int_end_\MODE\() s_time_vector_\MODE\(): - csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself. + csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap handler without messing up sp's value or the stack itself. sd t0, -8(sp) // put t0 on the scratch stack before messing with it li t0, 0x7EC05 // write 0x7ec05 (for "VEC"tored and 05 for the interrupt code) j vectored_int_end_\MODE\() m_time_vector_\MODE\(): - csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself. + csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap handler without messing up sp's value or the stack itself. sd t0, -8(sp) // put t0 on the scratch stack before messing with it li t0, 0x7EC07 // write 0x7ec07 (for "VEC"tored and 07 for the interrupt code) j vectored_int_end_\MODE\() s_ext_vector_\MODE\(): - csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself. + csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap handler without messing up sp's value or the stack itself. sd t0, -8(sp) // put t0 on the scratch stack before messing with it li t0, 0x7EC09 // write 0x7ec09 (for "VEC"tored and 08 for the interrupt code) j vectored_int_end_\MODE\() m_ext_vector_\MODE\(): - csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself. + csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap handler without messing up sp's value or the stack itself. sd t0, -8(sp) // put t0 on the scratch stack before messing with it li t0, 0x7EC0B // write 0x7ec0B (for "VEC"tored and 0B for the interrupt code) j vectored_int_end_\MODE\() @@ -665,12 +665,12 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a // read32_test : Read 32 bits from address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex // read16_test : Read 16 bits from address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex // read08_test : Read 8 bits from address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex -// executable_test : test executable on virtual page : 0x0, 0x1, or 0xc, then 0xbad : value of t2 modified by exectuion code (usually 0x111) +// executable_test : test executable on virtual page : 0x0, 0x1, or 0xc, then 0xbad : value of t2 modified by execution code (usually 0x111) // terminate_test : terminate tests : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 // goto_baremetal : satp.MODE = bare metal : None : None // goto_sv39 : satp.MODE = sv39 : None : None // goto_sv48 : satp.MODE = sv48 : None : None -// goto_m_mode : go to mahcine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 +// goto_m_mode : go to machine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 // goto_s_mode : go to supervisor mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 // goto_u_mode : go to user mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 // write_read_csr : write to specified CSR : old CSR value, 0x2, depending on perms : value written to CSR @@ -864,7 +864,7 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a .macro EXECUTE_AT_ADDRESS ADDR // Execute the code already written to ADDR, returning the value in t2. - // Note: this test itself doesn't write the code to ADDR because it might be callled at a point where we dont have write access to ADDR + // Note: this test itself doesn't write the code to ADDR because it might be called at a point where we dont have write access to ADDR // Assumes the code modifies t2, usually to become 0x111. // Sample code: 0x11100393 (li t2, 0x111), 0x00008067 (ret) // Success outputs: @@ -965,13 +965,13 @@ test_loop: // read32_test : Read 32 bitsfrom address : 0xd, 0xbad : readvalue in hex // read16_test : Read 16 bitsfrom address : 0xd, 0xbad : readvalue in hex // read08_test : Read 8 bitsfrom address : 0xd, 0xbad : readvalue in hex -// executable_test : test executable on virtual page : 0xc, 0xbad : value of t2 modified by exectuion code (usually 0x111) +// executable_test : test executable on virtual page : 0xc, 0xbad : value of t2 modified by execution code (usually 0x111) // terminate_test : terminate tests : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 // goto_baremetal : satp.MODE = bare metal : None : None // goto_sv39 : satp.MODE = sv39 : None : None // goto_sv48 : satp.MODE = sv48 : None : None // write_mxr_sum : write sstatus.[19:18] = MXR, SUM bits : None : None -// goto_m_mode : go to mahcine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 +// goto_m_mode : go to machine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 // goto_s_mode : go to supervisor mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 // goto_u_mode : go to user mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 // write_pmpcfg_x : Write one of the pmpcfg csr's : mstatuses?, 0xD : readback of pmpcfg value diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-s-01.S index 410dd78ea..5cd8f7f56 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-s-01.S @@ -30,10 +30,10 @@ INIT_TESTS TRAP_HANDLER m -# Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in S mode. +# Test 5.2.3.6: Test that all the machine mode CSR's are inaccessible for reads and writes in S mode. # *** several of these appear not to be implemented in the assembler? -# I get "assembler messages: error: unkown CSR" with many of them. +# I get "assembler messages: error: unknown CSR" with many of them. GOTO_S_MODE 0x0, 0x0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-u-01.S index b03d44a92..a4c928c33 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-u-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-u-01.S @@ -30,7 +30,7 @@ INIT_TESTS TRAP_HANDLER m -# Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in R mode. +# Test 5.2.3.6: Test that all the machine mode CSR's are inaccessible for reads and writes in R mode. GOTO_U_MODE 0x0, 0x0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-endianness-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-endianness-01.S index b5505e1b1..ee917b2d0 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-endianness-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-endianness-01.S @@ -30,7 +30,7 @@ INIT_TESTS TRAP_HANDLER m -// Test 5.3.2.4: testing that accesses to sub-word memory acceses not on a word boundary go +// Test 5.3.2.4: testing that accesses to sub-word memory accesses not on a word boundary go // correctly with the relevant status bit indicating endianness for each mode. // do this by going to each mode with and testing loads with the big endian bit on and off work correctly diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S index fbbc4d18e..8070a0cbe 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S @@ -31,7 +31,7 @@ TRAP_HANDLER m // Test 5.3.2.2: Machine ISA register test -// Misa is a specific case so I don't want to add a whole test case for reading nonzero but unkown value CSRs. +// Misa is a specific case so I don't want to add a whole test case for reading nonzero but unknown value CSRs. csrr x30, misa // should not cause a fault in machine mode. not writing to output because MISA is different for different configs. li x7, 0x111 // success value for read of nonzero misa bnez x30, misa_nonzero diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-01.S index 0690b1282..0126cea3a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-01.S @@ -54,7 +54,7 @@ test_cases: # =========== test 11.3.1.1 Page Table Translation =========== -# test 11.3.1.1.1 write page tables / entries to phyiscal memory +# test 11.3.1.1.1 write page tables / entries to physical memory # sv39 page table (See Figure 12.12***): # Level 2 page table, situated at 0x8000D000 .8byte 0x000000008000D000, 0x0000000020004C01, write64_test# points to level 1 page table A @@ -92,7 +92,7 @@ test_cases: # test 11.3.1.1.2 write values to Paddrs in each page # each of these values is used for 11.3.1.1.3 and some other tests, specified in the comments. -# when a test is supposed to fault, nothing is written into where it'll be reading/executing since it shuold fault before getting there. +# when a test is supposed to fault, nothing is written into where it'll be reading/executing since it should fault before getting there. .8byte 0x80200AB0, 0x0000DEADBEEF0000, write64_test# 11.3.1.1.4 and 11.3.1.4.1 .8byte 0x800FFAB8, 0x0880DEADBEEF0055, write64_test# 11.3.1.1.4 .8byte 0x80200AC0, 0x0990DEADBEEF0033, write64_test# 11.3.1.3.2 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S index c086c934f..3d5fb5a9f 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S @@ -54,7 +54,7 @@ test_cases: # =========== test 11.3.1.1 Page Table Translation =========== -# test 11.3.1.1.1 write page tables / entries to phyiscal memory +# test 11.3.1.1.1 write page tables / entries to physical memory # sv39 page table (See Figure 12.12***): # Level 2 page table, situated at 0x8000D000 .8byte 0x000000008000D000, 0x0000000020004C01, write64_test# points to level 1 page table A @@ -113,7 +113,7 @@ test_cases: # test 11.3.1.1.2 write values to Paddrs in each page # each of these values is used for 11.3.1.1.3 and some other tests, specified in the comments. -# when a test is supposed to fault, nothing is written into where it'll be reading/executing since it shuold fault before getting there. +# when a test is supposed to fault, nothing is written into where it'll be reading/executing since it should fault before getting there. .8byte 0x80200AB0, 0x0000DEADBEEF0000, write64_test # 11.3.1.1.4 and 11.3.1.4.1 .8byte 0x800FFAB8, 0x0880DEADBEEF0055, write64_test # 11.3.1.1.4 .8byte 0x80200AC0, 0x0990DEADBEEF0033, write64_test # 11.3.1.3.2 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-01.S index f84e68109..3ef704b0b 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-01.S @@ -56,7 +56,7 @@ test_cases: # =========== test 11.3.1.1 Page Table Translation =========== -# test 11.3.1.1.1 write page tables / entries to phyiscal memory +# test 11.3.1.1.1 write page tables / entries to physical memory # sv48 page table (See Figure 12.12***): # Level 3 page table, situated at 0x8000D000 .8byte 0x000000008000D000, 0x0000000020004C01, write64_test # points to level 2 page table A diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S index dcea1ff33..ccb10b452 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S @@ -56,7 +56,7 @@ test_cases: # =========== test 11.3.1.1 Page Table Translation =========== -# test 11.3.1.1.1 write page tables / entries to phyiscal memory +# test 11.3.1.1.1 write page tables / entries to physical memory # sv48 page table (See Figure 12.12***): # Level 3 page table, situated at 0x8000D000 .8byte 0x000000008000D000, 0x0000000020004C01, write64_test # points to level 2 page table A diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-periph-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-periph-01.S index 93c9d1b92..c1bea7259 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-periph-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-periph-01.S @@ -693,7 +693,7 @@ Intr03BEEF13: li t1, 0b00010000 1: bne t1,a0,1b li a0, 0 - # ========== Received Data Available Intrrupt (ERBFI) & Loop Mode ========== + # ========== Received Data Available Interrupt (ERBFI) & Loop Mode ========== # Clear SCR sb x0, 7(t0) Intr03BEEF14: diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-satp-invalid-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-satp-invalid-01.S index 01b3736bc..c98cfcd83 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-satp-invalid-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-satp-invalid-01.S @@ -34,8 +34,8 @@ csrw mtvec, t4 // set the new trap handler to do the pre behavior first. GOTO_S_MODE // go to S mode to attempt to turn on virtual memory -la ra, post_satp // load the address after the failing adress into ra so it doesn't get confused -GOTO_SV39 0x0, 0x0 // attempt to turn on virtual memory with satp pointing to an invlaid address. Should cause invalid instruction exception +la ra, post_satp // load the address after the failing address into ra so it doesn't get confused +GOTO_SV39 0x0, 0x0 // attempt to turn on virtual memory with satp pointing to an invalid address. Should cause invalid instruction exception post_satp: j test_end diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-sie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-sie-01.S index fa2bd599c..f963e8bc3 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-sie-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-sie-01.S @@ -43,7 +43,7 @@ WRITE_READ_CSR sie, 0x0 // force zeroing out mie CSR. // note that none of these interrupts should be caught or handled. jal cause_s_time_interrupt // write this from M mode to attempt to make s time interrupt pending -GOTO_S_MODE // this would cause S mode interrupt to fire, but it shouldn't since SIE is zeored out. +GOTO_S_MODE // this would cause S mode interrupt to fire, but it shouldn't since SIE is zeroed out. jal cause_s_soft_interrupt li a3, 0x40 // these interrupts involve a time loop waiting for the interrupt to go off. // since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-spi-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-spi-01.S index a31069470..9344aae88 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-spi-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-spi-01.S @@ -262,7 +262,7 @@ test_cases: # Test cs-sck delay of 0 with sck phase = 0 (implicit half cycle delay) -.8byte cs_mode, 0x00000000, write32_test # reset cs_mode to auto, all cs and sck mode settings should be defualt +.8byte cs_mode, 0x00000000, write32_test # reset cs_mode to auto, all cs and sck mode settings should be default .8byte delay0, 0x00010000, write32_test # set cs-sck delay to 0 .8byte tx_data, 0x00000020, write32_test # place 8'h11 into tx_data .8byte 0x0, 0x00000000, spi_data_wait # wait for transmission to end @@ -646,23 +646,23 @@ SETUP_PLIC .8byte sck_div, 0x00000100, write32_test # lower SPI clock rate so reads are done at correct time when ICACHE not supported .8byte tx_mark, 0x00000001, write32_test # set transmit watermark to 1 (any entry turns mark off) #.8byte ie, 0x00000000, write32_test # enable transmit interrupt -.8byte ip, 0x00000001, read32_test # tx watermark interupt should be pending +.8byte ip, 0x00000001, read32_test # tx watermark interrupt should be pending .8byte 0x0, 0x00000000, readmip_test .8byte tx_data, 0x55443322, spi_burst_send # place 4 entries in transmit fifo -.8byte ip, 0x00000000, read32_test # tx watermark interupt should be off 125 +.8byte ip, 0x00000000, read32_test # tx watermark interrupt should be off 125 .8byte 0x0, 0x00000003, spi_data_wait # wait for transmission to end -# test recieve watermark interrupt (triggers when entries in rx FIFO > rx watermark) +# test receive watermark interrupt (triggers when entries in rx FIFO > rx watermark) .8byte tx_mark, 0x00000000, write32_test # set tx_mark to 0 .8byte rx_data, 0x00000022, read32_test # clear one entry from rx FIFO -.8byte rx_mark, 0x00000003, write32_test # set recieve watermark to 3 +.8byte rx_mark, 0x00000003, write32_test # set receive watermark to 3 #.8byte ie, 0x0000002, write32_test # enable receive interrupts .8byte ip, 0x00000000, read32_test # rx interrupts should be low (rx FIFO has 3 entries) -.8byte rx_mark, 0x00000002, write32_test # set recieve watermark to 2 -.8byte ip, 0x00000002, read32_test # recieve interrupt should be high +.8byte rx_mark, 0x00000002, write32_test # set receive watermark to 2 +.8byte ip, 0x00000002, read32_test # receive interrupt should be high .8byte 0x0, 0x00000000, readmip_test -.8byte rx_data, 0x00000033, read32_test # clear one more entry from recieve FIFO (2 entries) +.8byte rx_data, 0x00000033, read32_test # clear one more entry from receive FIFO (2 entries) .8byte ip, 0x00000000, read32_test # receive interrupt should be low .8byte rx_data, 0x00000044, read32_test .8byte rx_data, 0x00000055, read32_test # clear rx fifo @@ -670,25 +670,25 @@ SETUP_PLIC .8byte tx_mark, 0x00000001, write32_test # set transmit watermark to 0 .8byte ie, 0x00000001, write32_test # enable transmit interrupt -.8byte ip, 0x00000001, read32_test # tx watermark interupt should be pending +.8byte ip, 0x00000001, read32_test # tx watermark interrupt should be pending .8byte 0x0, 0x00000800, readmip_test .8byte ie, 0x00000000, write32_test # disable tx intr .8byte tx_data, 0x55443322, spi_burst_send # place 4 entries in transmit fifo .8byte 0x0, 0x00000003, spi_data_wait # wait for transmission to end -# test recieve watermark interrupt (triggers when entries in rx FIFO > rx watermark) +# test receive watermark interrupt (triggers when entries in rx FIFO > rx watermark) .8byte tx_mark, 0x00000000, write32_test .8byte 0x0, 0x00000000, claim_m_plic_interrupts .8byte rx_data, 0x00000022, read32_test # clear one entry from rx FIFO -.8byte rx_mark, 0x00000003, write32_test # set recieve watermark to 3 +.8byte rx_mark, 0x00000003, write32_test # set receive watermark to 3 .8byte ie, 0x0000002, write32_test # enable receive interrupts .8byte ip, 0x00000000, read32_test # rx interrupts should be low (rx FIFO has 3 entries) .8byte 0x0, 0x00000000, readmip_test -.8byte rx_mark, 0x00000002, write32_test # set recieve watermark to 2 -.8byte ip, 0x00000002, read32_test # recieve interrupt should be high +.8byte rx_mark, 0x00000002, write32_test # set receive watermark to 2 +.8byte ip, 0x00000002, read32_test # receive interrupt should be high .8byte 0x0, 0x00000800, readmip_test -.8byte rx_data, 0x00000033, read32_test # clear one more entry from recieve FIFO (2 entries) +.8byte rx_data, 0x00000033, read32_test # clear one more entry from receive FIFO (2 entries) .8byte 0x0, 0x00000000, claim_m_plic_interrupts .8byte ip, 0x00000000, read32_test # receive interrupt should be low .8byte 0x0, 0x00000000, readmip_test diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-sie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-sie-01.S index c52f23c3d..464a3b452 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-sie-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-sie-01.S @@ -30,7 +30,7 @@ INIT_TESTS CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses TRAP_HANDLER m, EXT_SIGNATURE=1 // necessary so we can go to S mode -TRAP_HANDLER s, EXT_SIGNATURE=1 // neccessary to handle s mode interrupts. +TRAP_HANDLER s, EXT_SIGNATURE=1 // necessary to handle s mode interrupts. li x28, 0x2 csrs sstatus, x28 // set sstatus.SIE bit to 1 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S index 4ed0941ae..3c252a0e9 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S @@ -67,7 +67,7 @@ li a3, 0x40 jal cause_m_ext_interrupt // Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler -// We can tell which one becuase the different trap handler modes write different bits of the status register +// We can tell which one because the different trap handler modes write different bits of the status register // to the output when EXT_SIGNATURE is on. GOTO_M_MODE // so we can write the delegate registers diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S index af0d9f32d..9a63b4248 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S @@ -54,7 +54,7 @@ jal cause_store_addr_misaligned jal cause_store_acc jal cause_ecall -// some interrupts excluded becaus writing SIP/MIP is illegal from U mode +// some interrupts excluded because writing SIP/MIP is illegal from U mode jal cause_m_soft_interrupt jal cause_m_time_interrupt li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off. @@ -64,7 +64,7 @@ li a3, 0x40 jal cause_m_ext_interrupt // Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler -// We can tell which one becuase the different trap handler modes write different bits of the status register +// We can tell which one because the different trap handler modes write different bits of the status register // to the output when EXT_SIGNATURE is on. GOTO_M_MODE // so we can write the delegate registers From 769172334d7b828fda03284991d896e78d21f8f0 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 8 May 2025 00:58:19 -0700 Subject: [PATCH 35/43] Add riscv-arch-test fork for cvw-arch-verif merge dev --- .gitmodules | 3 +++ addins/cvw-riscv-arch-test | 1 + 2 files changed, 4 insertions(+) create mode 160000 addins/cvw-riscv-arch-test diff --git a/.gitmodules b/.gitmodules index 672ec445f..5a35f04a3 100644 --- a/.gitmodules +++ b/.gitmodules @@ -33,3 +33,6 @@ path = addins/berkeley-testfloat-3 url = https://github.com/ucb-bar/berkeley-testfloat-3 ignore = untracked +[submodule "addins/cvw-riscv-arch-test"] + path = addins/cvw-riscv-arch-test + url = https://github.com/jordancarlin/riscv-arch-test diff --git a/addins/cvw-riscv-arch-test b/addins/cvw-riscv-arch-test new file mode 160000 index 000000000..a2b7ffd90 --- /dev/null +++ b/addins/cvw-riscv-arch-test @@ -0,0 +1 @@ +Subproject commit a2b7ffd90c183e2c64f8da9ae8438c396250d9e9 From d1958b05e0e470092cb78f59d974c75d67606de2 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 8 May 2025 01:01:08 -0700 Subject: [PATCH 36/43] Remove old quad64 makefile target --- tests/riscof/Makefile | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/tests/riscof/Makefile b/tests/riscof/Makefile index 131d724c4..c854ee7d5 100644 --- a/tests/riscof/Makefile +++ b/tests/riscof/Makefile @@ -13,7 +13,7 @@ wally_workdir := $(work)/wally-riscv-arch-test current_dir := $(shell pwd) # General make rules -.PHONY: all riscv-arch-test wally-riscv-arch-test quad64 clean +.PHONY: all riscv-arch-test wally-riscv-arch-test clean all: riscv-arch-test wally-riscv-arch-test riscv-arch-test: arch32e arch32 arch64 wally-riscv-arch-test: wally32 wally64 @@ -34,10 +34,6 @@ wally%: config$$*.ini | $(work_dir) $(wally_workdir) $(MAKE) -f makefile-memfile WORKDIR=$(work_dir)/$@ rsync -a $(work_dir)/$@/rv*/* $(wally_workdir)/rv$(patsubst %64,%64i,$(patsubst %32,%32i,$*))_m || echo "error suppressed" -quad64: config64.ini $(wally_dir)/riscv-test-suite/rv64i_m/Q/riscv-ctg/tests | $(work_dir) - riscof run --work-dir=$(work_dir)/$@ --config=$< --suite=$(wally_dir)/riscv-test-suite/rv64i_m/Q/riscv-ctg/tests/ --env=$(wally_dir)/riscv-test-suite/env - $(MAKE) -f makefile-memfile WORKDIR=$(work_dir)/$@ - clean: rm -f config??*.ini rm -rf $(work_dir) From 8a9d15cd603eb0fb9f21e4ac42b9e0ff12f738d1 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 8 May 2025 01:25:09 -0700 Subject: [PATCH 37/43] Update riscof Makefile for better scalability with multiple suites --- tests/riscof/Makefile | 34 ++++++++++++++++++++-------------- 1 file changed, 20 insertions(+), 14 deletions(-) diff --git a/tests/riscof/Makefile b/tests/riscof/Makefile index c854ee7d5..cf6834b43 100644 --- a/tests/riscof/Makefile +++ b/tests/riscof/Makefile @@ -15,31 +15,37 @@ current_dir := $(shell pwd) # General make rules .PHONY: all riscv-arch-test wally-riscv-arch-test clean all: riscv-arch-test wally-riscv-arch-test + +# Standard riscv-arch-test tests riscv-arch-test: arch32e arch32 arch64 +arch%: test_dir=$(arch_dir) +arch%: work_result=$(arch_workdir) +arch32e: riscof32e +arch32: riscof32 +arch64: riscof64 + +# wally-riscv-arch-test tests wally-riscv-arch-test: wally32 wally64 +wally%: test_dir=$(wally_dir) +wally%: work_result=$(wally_workdir) +wally32: riscof32 +wally64: riscof64 # Generate config.ini files config%.ini: config.ini sed 's,{0},$(current_dir),g;s,{1},$(patsubst %64,%64gc,$(patsubst %32,%32gc,$*)),g;s,{2},$(nproc),g' config.ini > $@ -# Generate riscv-arch-test targets -arch%: config$$*.ini | $(work_dir) $(arch_workdir) - riscof run --work-dir=$(work_dir)/$@ --config=$< --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser +# Compile tests with riscof +riscof%: config$$*.ini | $(work_dir) + riscof run --work-dir=$(work_dir)/$@ --config=$< --suite=$(test_dir)/riscv-test-suite/ --env=$(test_dir)/riscv-test-suite/env --no-browser $(MAKE) -f makefile-memfile WORKDIR=$(work_dir)/$@ BITWIDTH=$(patsubst %32e,%32,$*) - rsync -a $(work_dir)/$@/rv*/* $(arch_workdir)/rv$(patsubst %64,%64i,$(patsubst %32,%32i,$*))_m || echo "error suppressed" - -# Generate wally-riscv-arch-test targets -wally%: config$$*.ini | $(work_dir) $(wally_workdir) - riscof run --work-dir=$(work_dir)/$@ --config=$< --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run - $(MAKE) -f makefile-memfile WORKDIR=$(work_dir)/$@ - rsync -a $(work_dir)/$@/rv*/* $(wally_workdir)/rv$(patsubst %64,%64i,$(patsubst %32,%32i,$*))_m || echo "error suppressed" + mkdir -p $(work_result) + rsync -a $(work_dir)/$@/rv*/* $(work_result)/rv$(patsubst %64,%64i,$(patsubst %32,%32i,$*))_m || echo "error suppressed" clean: rm -f config??*.ini rm -rf $(work_dir) - rm -rf $(wally_workdir) - rm -rf $(arch_workdir) - rm -rf $(submodule_wor_dir) + rm -rf $(work) -$(work_dir) $(arch_workdir) $(wally_workdir): +$(work_dir): mkdir -p $@ From 7c4455e7cce7db04034fa6279b240e38439445ae Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 8 May 2025 02:39:38 -0700 Subject: [PATCH 38/43] Continued makefile work --- tests/riscof/Makefile | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/tests/riscof/Makefile b/tests/riscof/Makefile index cf6834b43..4494a5ca7 100644 --- a/tests/riscof/Makefile +++ b/tests/riscof/Makefile @@ -5,10 +5,12 @@ nproc := $(shell nproc --ignore=1) # Directories arch_dir := $(WALLY)/addins/riscv-arch-test +cvw_arch_dir := $(WALLY)/addins/cvw-riscv-arch-test wally_dir := $(WALLY)/tests/wally-riscv-arch-test work_dir := ./riscof_work work := ./work arch_workdir := $(work)/riscv-arch-test +cvw_arch_workdir := $(work)/cvw-riscv-arch-test wally_workdir := $(work)/wally-riscv-arch-test current_dir := $(shell pwd) @@ -16,27 +18,36 @@ current_dir := $(shell pwd) .PHONY: all riscv-arch-test wally-riscv-arch-test clean all: riscv-arch-test wally-riscv-arch-test +$(wally_workdir)/wally%.stamp: $(shell find $(wally_dir) -type f) config.ini + $(MAKE) wally$* + touch $@ + +$(arch_workdir)/arch%.stamp: $(shell find $(arch_dir) -type f) config.ini + $(MAKE) arch$* + touch $@ + # Standard riscv-arch-test tests +# .PHONY: arch32e arch32 arch64 riscv-arch-test: arch32e arch32 arch64 arch%: test_dir=$(arch_dir) arch%: work_result=$(arch_workdir) -arch32e: riscof32e -arch32: riscof32 -arch64: riscof64 + +# cvw-arch-verif based riscv-arch-test tests +# cvw-riscv-arch-test: cvw_arch32 cvw_arch64 +# cvw_arch%: test_dir=$(cvw_arch_dir) +# cvw_arch%: work_result=$(cvw_arch_workdir) # wally-riscv-arch-test tests wally-riscv-arch-test: wally32 wally64 wally%: test_dir=$(wally_dir) wally%: work_result=$(wally_workdir) -wally32: riscof32 -wally64: riscof64 # Generate config.ini files config%.ini: config.ini sed 's,{0},$(current_dir),g;s,{1},$(patsubst %64,%64gc,$(patsubst %32,%32gc,$*)),g;s,{2},$(nproc),g' config.ini > $@ # Compile tests with riscof -riscof%: config$$*.ini | $(work_dir) +arch% wally%: config$$*.ini | $(work_dir) riscof run --work-dir=$(work_dir)/$@ --config=$< --suite=$(test_dir)/riscv-test-suite/ --env=$(test_dir)/riscv-test-suite/env --no-browser $(MAKE) -f makefile-memfile WORKDIR=$(work_dir)/$@ BITWIDTH=$(patsubst %32e,%32,$*) mkdir -p $(work_result) From 3d368d50d7ecbcdfa4736909b332f6e6e52b9310 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 8 May 2025 02:56:28 -0700 Subject: [PATCH 39/43] Revert makefile changes --- tests/riscof/Makefile | 45 ++++++++++++++----------------------------- 1 file changed, 14 insertions(+), 31 deletions(-) diff --git a/tests/riscof/Makefile b/tests/riscof/Makefile index 4494a5ca7..c854ee7d5 100644 --- a/tests/riscof/Makefile +++ b/tests/riscof/Makefile @@ -5,58 +5,41 @@ nproc := $(shell nproc --ignore=1) # Directories arch_dir := $(WALLY)/addins/riscv-arch-test -cvw_arch_dir := $(WALLY)/addins/cvw-riscv-arch-test wally_dir := $(WALLY)/tests/wally-riscv-arch-test work_dir := ./riscof_work work := ./work arch_workdir := $(work)/riscv-arch-test -cvw_arch_workdir := $(work)/cvw-riscv-arch-test wally_workdir := $(work)/wally-riscv-arch-test current_dir := $(shell pwd) # General make rules .PHONY: all riscv-arch-test wally-riscv-arch-test clean all: riscv-arch-test wally-riscv-arch-test - -$(wally_workdir)/wally%.stamp: $(shell find $(wally_dir) -type f) config.ini - $(MAKE) wally$* - touch $@ - -$(arch_workdir)/arch%.stamp: $(shell find $(arch_dir) -type f) config.ini - $(MAKE) arch$* - touch $@ - -# Standard riscv-arch-test tests -# .PHONY: arch32e arch32 arch64 riscv-arch-test: arch32e arch32 arch64 -arch%: test_dir=$(arch_dir) -arch%: work_result=$(arch_workdir) - -# cvw-arch-verif based riscv-arch-test tests -# cvw-riscv-arch-test: cvw_arch32 cvw_arch64 -# cvw_arch%: test_dir=$(cvw_arch_dir) -# cvw_arch%: work_result=$(cvw_arch_workdir) - -# wally-riscv-arch-test tests wally-riscv-arch-test: wally32 wally64 -wally%: test_dir=$(wally_dir) -wally%: work_result=$(wally_workdir) # Generate config.ini files config%.ini: config.ini sed 's,{0},$(current_dir),g;s,{1},$(patsubst %64,%64gc,$(patsubst %32,%32gc,$*)),g;s,{2},$(nproc),g' config.ini > $@ -# Compile tests with riscof -arch% wally%: config$$*.ini | $(work_dir) - riscof run --work-dir=$(work_dir)/$@ --config=$< --suite=$(test_dir)/riscv-test-suite/ --env=$(test_dir)/riscv-test-suite/env --no-browser +# Generate riscv-arch-test targets +arch%: config$$*.ini | $(work_dir) $(arch_workdir) + riscof run --work-dir=$(work_dir)/$@ --config=$< --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser $(MAKE) -f makefile-memfile WORKDIR=$(work_dir)/$@ BITWIDTH=$(patsubst %32e,%32,$*) - mkdir -p $(work_result) - rsync -a $(work_dir)/$@/rv*/* $(work_result)/rv$(patsubst %64,%64i,$(patsubst %32,%32i,$*))_m || echo "error suppressed" + rsync -a $(work_dir)/$@/rv*/* $(arch_workdir)/rv$(patsubst %64,%64i,$(patsubst %32,%32i,$*))_m || echo "error suppressed" + +# Generate wally-riscv-arch-test targets +wally%: config$$*.ini | $(work_dir) $(wally_workdir) + riscof run --work-dir=$(work_dir)/$@ --config=$< --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run + $(MAKE) -f makefile-memfile WORKDIR=$(work_dir)/$@ + rsync -a $(work_dir)/$@/rv*/* $(wally_workdir)/rv$(patsubst %64,%64i,$(patsubst %32,%32i,$*))_m || echo "error suppressed" clean: rm -f config??*.ini rm -rf $(work_dir) - rm -rf $(work) + rm -rf $(wally_workdir) + rm -rf $(arch_workdir) + rm -rf $(submodule_wor_dir) -$(work_dir): +$(work_dir) $(arch_workdir) $(wally_workdir): mkdir -p $@ From 1002f3badb7242f933e61b2ac3b2a75066b6edbb Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 8 May 2025 03:12:01 -0700 Subject: [PATCH 40/43] Add support for cvw-riscv-arch-test --- tests/riscof/Makefile | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/tests/riscof/Makefile b/tests/riscof/Makefile index c854ee7d5..c50de30eb 100644 --- a/tests/riscof/Makefile +++ b/tests/riscof/Makefile @@ -5,10 +5,12 @@ nproc := $(shell nproc --ignore=1) # Directories arch_dir := $(WALLY)/addins/riscv-arch-test +cvw_arch_dir := $(WALLY)/addins/cvw-riscv-arch-test wally_dir := $(WALLY)/tests/wally-riscv-arch-test work_dir := ./riscof_work work := ./work arch_workdir := $(work)/riscv-arch-test +cvw_arch_workdir := $(work)/cvw-riscv-arch-test wally_workdir := $(work)/wally-riscv-arch-test current_dir := $(shell pwd) @@ -16,6 +18,7 @@ current_dir := $(shell pwd) .PHONY: all riscv-arch-test wally-riscv-arch-test clean all: riscv-arch-test wally-riscv-arch-test riscv-arch-test: arch32e arch32 arch64 +cvw-riscv-arch-test: cvw-arch32e cvw-arch32 cvw-arch64 wally-riscv-arch-test: wally32 wally64 # Generate config.ini files @@ -26,7 +29,14 @@ config%.ini: config.ini arch%: config$$*.ini | $(work_dir) $(arch_workdir) riscof run --work-dir=$(work_dir)/$@ --config=$< --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser $(MAKE) -f makefile-memfile WORKDIR=$(work_dir)/$@ BITWIDTH=$(patsubst %32e,%32,$*) - rsync -a $(work_dir)/$@/rv*/* $(arch_workdir)/rv$(patsubst %64,%64i,$(patsubst %32,%32i,$*))_m || echo "error suppressed" + rsync -a $(work_dir)/$@/rv*/* $(arch_workdir)/rv$(patsubst %64,%64i,$(patsubst %32,%32i,$*)) || echo "error suppressed" + +# Generate cvw-riscv-arch-test targets +# Generate riscv-arch-test targets +cvw-arch%: config$$*.ini | $(work_dir) $(cvw_arch_workdir) + riscof run --work-dir=$(work_dir)/$@ --config=$< --suite=$(cvw_arch_dir)/riscv-test-suite/ --env=$(cvw_arch_dir)/riscv-test-suite/env --no-browser + $(MAKE) -f makefile-memfile WORKDIR=$(work_dir)/$@ BITWIDTH=$(patsubst %32e,%32,$*) + rsync -a $(work_dir)/$@/rv*/* $(cvw_arch_workdir)/rv$(patsubst %64,%64i,$(patsubst %32,%32i,$*))_m || echo "error suppressed" # Generate wally-riscv-arch-test targets wally%: config$$*.ini | $(work_dir) $(wally_workdir) @@ -39,7 +49,7 @@ clean: rm -rf $(work_dir) rm -rf $(wally_workdir) rm -rf $(arch_workdir) - rm -rf $(submodule_wor_dir) + rm -rf $(cvw_arch_workdir) -$(work_dir) $(arch_workdir) $(wally_workdir): +$(work_dir) $(arch_workdir) $(wally_workdir) $(cvw_arch_workdir): mkdir -p $@ From 53db7995b3cddb63d992491db366fe9194b45eec Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 8 May 2025 03:12:18 -0700 Subject: [PATCH 41/43] Update regression-wally --fcov-act --- bin/regression-wally | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index f037d804b..8bb0cd5fb 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -484,10 +484,10 @@ def selectTests(args, sims, coverStr): addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/vm_sv32", "rv32gc", coveragesim, coverStr, configs, lockstepMode=1) # addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/pmp32", "rv32gc", coveragesim, coverStr, configs, lockstepMode=1) TODO: Add when working in lockstep # addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/pmp", "rv64gc", coveragesim, coverStr, configs, lockstepMode=1) TODO: Add when working in lockstep - # run riscv-arch-test tests in functional coverage mode + # run cvw-riscv-arch-test tests in functional coverage mode if args.fcov_act: - addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m", "rv32gc", coveragesim, coverStr, configs, lockstepMode=1) - addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m", "rv64gc", coveragesim, coverStr, configs, lockstepMode=1) + addTestsByDir(f"{WALLY}/tests/riscof/work/cvw-riscv-arch-test/rv32i", "rv32gc", coveragesim, coverStr, configs, lockstepMode=1) + addTestsByDir(f"{WALLY}/tests/riscof/work/cvw-riscv-arch-test/rv64i", "rv64gc", coveragesim, coverStr, configs, lockstepMode=1) # run branch predictor tests if args.branch: addTests(bpredtests, defaultsim, coverStr, configs) From c12d5a34846eabbfb03cf0b7e339c88b385cb620 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 8 May 2025 03:16:49 -0700 Subject: [PATCH 42/43] Bump cvw-riscv-test-suite --- addins/cvw-riscv-arch-test | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/addins/cvw-riscv-arch-test b/addins/cvw-riscv-arch-test index a2b7ffd90..44832a9d3 160000 --- a/addins/cvw-riscv-arch-test +++ b/addins/cvw-riscv-arch-test @@ -1 +1 @@ -Subproject commit a2b7ffd90c183e2c64f8da9ae8438c396250d9e9 +Subproject commit 44832a9d3bea991b099c6beb4c962e5b7c1ad3a3 From 385e8f6c241ebd336ea6204eb534d8ab1db6846f Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 8 May 2025 03:43:48 -0700 Subject: [PATCH 43/43] Fix type --- tests/riscof/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/riscof/Makefile b/tests/riscof/Makefile index c50de30eb..59ec8ca84 100644 --- a/tests/riscof/Makefile +++ b/tests/riscof/Makefile @@ -29,14 +29,14 @@ config%.ini: config.ini arch%: config$$*.ini | $(work_dir) $(arch_workdir) riscof run --work-dir=$(work_dir)/$@ --config=$< --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser $(MAKE) -f makefile-memfile WORKDIR=$(work_dir)/$@ BITWIDTH=$(patsubst %32e,%32,$*) - rsync -a $(work_dir)/$@/rv*/* $(arch_workdir)/rv$(patsubst %64,%64i,$(patsubst %32,%32i,$*)) || echo "error suppressed" + rsync -a $(work_dir)/$@/rv*/* $(arch_workdir)/rv$(patsubst %64,%64i,$(patsubst %32,%32i,$*))_m || echo "error suppressed" # Generate cvw-riscv-arch-test targets # Generate riscv-arch-test targets cvw-arch%: config$$*.ini | $(work_dir) $(cvw_arch_workdir) riscof run --work-dir=$(work_dir)/$@ --config=$< --suite=$(cvw_arch_dir)/riscv-test-suite/ --env=$(cvw_arch_dir)/riscv-test-suite/env --no-browser $(MAKE) -f makefile-memfile WORKDIR=$(work_dir)/$@ BITWIDTH=$(patsubst %32e,%32,$*) - rsync -a $(work_dir)/$@/rv*/* $(cvw_arch_workdir)/rv$(patsubst %64,%64i,$(patsubst %32,%32i,$*))_m || echo "error suppressed" + rsync -a $(work_dir)/$@/rv*/* $(cvw_arch_workdir)/rv$(patsubst %64,%64i,$(patsubst %32,%32i,$*)) || echo "error suppressed" # Generate wally-riscv-arch-test targets wally%: config$$*.ini | $(work_dir) $(wally_workdir)