diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-endianness-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-endianness-01.reference_output
index 34c79cda8..b9bbf6a4f 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-endianness-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-endianness-01.reference_output
@@ -1,5 +1,5 @@
-aabbccdd # Test 5.3.2.4: M mode little endian load/store word of 0xAABBCCDD # NOTE: the memory was already filled with's so subword overwrite some, but not all of them. this is why the values are filled with deadbeefs, rather than 00's or ff's
-deadccdd # M mode little endian load/store halfword of 0xAABBCCDD # NOTE: since we're doing a store that matches the width of the load, we cut out all the sign extension
+aabbccdd # Test 5.3.2.4: M mode little endian load/store word of 0xAABBCCDD NOTE: the memory was already filled with's so subword overwrite some, but not all of them. this is why the values are filled with deadbeefs, rather than 00's or ff's
+deadccdd # M mode little endian load/store halfword of 0xAABBCCDD NOTE: since we're doing a store that matches the width of the load, we cut out all the sign extension
 deadbedd # M mode little endian load/store byte of 0xAABBCCDD
 ddccbbaa # M mode big endian load/store word of 0xDDCCBBAA
 deadbbaa # M mode big endian load/store halfword of 0xDDCCBBAA
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-endianness-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-endianness-01.S
index 19433cda5..e51a6b65b 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-endianness-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-endianness-01.S
@@ -24,7 +24,7 @@
 #include "WALLY-TEST-LIB-32.h" 
 
 RVTEST_ISA("RV32I")
-RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True; def NO_SAIL=True;",endianness)
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",endianness)
 
 INIT_TESTS
 
@@ -36,7 +36,7 @@ TRAP_HANDLER m
 
 // *** It appears Sail has the MBE, SBE, and UBE bits of mstatus hardwired to zero
 
-// M Mode little Endianness tests:
+// M Mode little endianness tests:
 
 li x28, 0xAABBCCDD
 li x29, 0x8000F000
@@ -57,10 +57,10 @@ sb x30, 0(t1) // test store byte, should save 0xDD
 addi t1, t1, 4
 addi a6, a6, 4
 
-li x28, 0x2000000000
-csrs mstatus, x28 // turn on big endianness for M mode
+li x28, 0x20
+csrs mstatush, x28 // turn on big endianness for M mode
 
-// M mode Big Endianness tests
+// M mode Big endianness tests
 // In big endian modes, all values are sign extended to the right, rather than left
 
 li x28, 0xAABBCCDD
@@ -82,8 +82,8 @@ sb x30, 0(t1) // test store byte, should save 0xAA
 addi t1, t1, 4
 addi a6, a6, 4
 
-li x28, 0x2000000000
-csrc mstatus, x28 // Turn off big endianness for M mode before going into the trap handler
+li x28, 0x20
+csrc mstatush, x28 // Turn off big endianness for M mode before going into the trap handler
 
 GOTO_S_MODE
 
@@ -110,8 +110,8 @@ addi a6, a6, 4
 
 GOTO_M_MODE // Go back to M mode to be able to toggle SBE bit of mstatus
 
-li x28, 0x1000000000
-csrs mstatus, x28 // turn on big endianness for S mode
+li x28, 0x10
+csrs mstatush, x28 // turn on big endianness for S mode
 
 GOTO_S_MODE 
 
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-xlen-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-xlen-01.reference_output
index f9469d56a..4737d89b9 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-xlen-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-xlen-01.reference_output
@@ -1,4 +1,4 @@
 00000000 # Test *** Number : Read out SXL, UXL of mstatus as 2 and 2 for 64 bit systems
 0000000a
-00000000 # read of read-only uxl, sxl bits after attmepted write
-0000000a
+0000000b # ecall from ending tests in M mode
+00000000
\ No newline at end of file
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-xlen-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-xlen-01.S
index aaeaef110..ad3a3e6f7 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-xlen-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-xlen-01.S
@@ -24,7 +24,7 @@
 #include "WALLY-TEST-LIB-64.h" 
 
 RVTEST_ISA("RV64I")
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",endianness)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",xlen)
 
 INIT_TESTS
 
@@ -39,13 +39,6 @@ sd x28, 0(t1) // should store 0xA00000000 to memory
 addi t1, t1, 8
 addi a6, a6, 8
 
-csrs mstatus, x29 // attempt to write to uxl and sxl, should not work
-csrr x28, mstatus
-and x28, x28, x29
-sd x28, 0(t1) // should store 0xA00000000 to memory
-addi t1, t1, 8
-addi a6, a6, 8
-
 END_TESTS
 
 TEST_STACK_AND_DATA