diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index 8a0cdceca..8a52b016d 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit 8a0cdceca9f0b91b81905eb8497f6586bf8d1c6b +Subproject commit 8a52b016dbe1e2733cc168b9d6e5c93e39059d4d diff --git a/benchmarks/coremark/coremark_sweep.py b/benchmarks/coremark/coremark_sweep.py index e1b6c6573..82a596604 100755 --- a/benchmarks/coremark/coremark_sweep.py +++ b/benchmarks/coremark/coremark_sweep.py @@ -5,7 +5,7 @@ ## Written: Shreesh Kulkarni, kshreesh5@gmail.com ## Created: 20 March 2024 ## Modified: 22 March 2024 -## Purpose: Wally Coremark sweep Script for both 32 and 64 bit configs. +## Purpose: Wally Coremark sweep Script for both 32 and 64 bit configs with csv file extraction. ## Documentation: @@ -30,6 +30,8 @@ import os +import re +import csv # list of architectures to run. arch32_list = [ "rv32gc_zba_zbb_zbc", @@ -39,32 +41,67 @@ arch32_list = [ "rv32im_zicsr", "rv32i_zicsr" ] -arch64_list = [ - "rv64gc_zba_zbb_zbc", - "rv64im_zicsr_zba_zbb_zbc", - "rv64gc", - "rv64imc_zicsr", - "rv64im_zicsr", - "rv64i_zicsr" -] -xlen_values = ['32','64'] -for xlen_value in xlen_values: - if(xlen_value=='32'): - for arch in arch32_list: - os.system("make clean") - make_all = f"make all XLEN={xlen_value} ARCH={arch}" - os.system(make_all) - make_run = f"make run XLEN={xlen_value} ARCH={arch}" - os.system(make_run) - else: - for arch in arch64_list: - os.system("make clean") - make_all = f"make all XLEN={xlen_value} ARCH={arch}" - os.system(make_all) - make_run = f"make run XLEN={xlen_value} ARCH={arch}" - os.system(make_run) +#uncomment this array for 64bit configurations +#arch64_list = [ +# "rv64gc_zba_zbb_zbc", +# "rv64im_zicsr_zba_zbb_zbc", +# "rv64gc", +# "rv64imc_zicsr", +# "rv64im_zicsr", +# "rv64i_zicsr" +#] +xlen_value = '32' +#xlen_value = '64' #uncomment this for 64 bit. +# Define regular expressions to match the desired fields +mt_regex = r"Elapsed MTIME: (\d+).*?Elapsed MINSTRET: (\d+).*?COREMARK/MHz Score: [\d,]+ / [\d,]+ = (\d+\.\d+).*?CPI: \d+ / \d+ = (\d+\.\d+).*?Load Stalls (\d+).*?Store Stalls (\d+).*?D-Cache Accesses (\d+).*?D-Cache Misses (\d+).*?I-Cache Accesses (\d+).*?I-Cache Misses (\d+).*?Branches (\d+).*?Branches Miss Predictions (\d+).*?BTB Misses (\d+).*?Jump and JR (\d+).*?RAS Wrong (\d+).*?Returns (\d+).*?BP Class Wrong (\d+)" +#cpi_regex = r"CPI: \d+ / \d+ = (\d+\.\d+)" +#cmhz_regex = r"COREMARK/MHz Score: [\d,]+ / [\d,]+ = (\d+\.\d+)" +# Open a CSV file to write the results +with open('coremark_results.csv', mode='w', newline='') as csvfile: + fieldnames = ['Architecture', 'MTIME','MINSTRET','CM / MHz','CPI','Load Stalls','Store Stalls','D$ Accesses', + 'D$ Misses','I$ Accesses','I$ Misses','Branches','Branch Mispredicts','BTB Misses', + 'Jump/JR','RAS Wrong','Returns','BP Class Pred Wrong'] + writer = csv.DictWriter(csvfile, fieldnames=fieldnames) + writer.writeheader() + # Loop through each architecture and run the make commands + for arch in arch32_list: + os.system("make clean") + make_all = f"make all XLEN={xlen_value} ARCH={arch}" + os.system(make_all) + make_run = f"make run XLEN={xlen_value} ARCH={arch}" + output = os.popen(make_run).read() # Capture the output of the command + # Extract the Coremark values using regular expressions + mt_match = re.search(mt_regex, output,re.DOTALL) + #cpi_match = re.search(cpi_regex,output,re.DOTALL) + #cmhz_match = re.search(cmhz_regex,output,re.DOTALL) + #minstret_match = re.search(minstret_regex,output) + + # Write the architecture and extracted values to the CSV file + + mtime = mt_match.group(1) + minstret= mt_match.group(2) + cmhz= mt_match.group(3) + cpi= mt_match.group(4) + lstalls= mt_match.group(5) + swtalls= mt_match.group(6) + dacc= mt_match.group(7) + dmiss= mt_match.group(8) + iacc= mt_match.group(9) + imiss= mt_match.group(10) + br= mt_match.group(11) + brm= mt_match.group(12) + btb= mt_match.group(13) + jmp= mt_match.group(14) + ras= mt_match.group(15) + ret= mt_match.group(16) + bpc= mt_match.group(17) + #minstret = mt_instret_match.group(2) + writer.writerow({'Architecture': arch, 'MTIME': mtime,'MINSTRET':minstret,'CM / MHz':cmhz,'CPI':cpi, + 'Load Stalls':lstalls, + 'Store Stalls':swtalls,'D$ Accesses':dacc,'D$ Misses':dmiss,'I$ Accesses':iacc,'I$ Misses':imiss, + 'Branches':br,'Branch Mispredicts':brm,'BTB Misses':btb,'Jump/JR':jmp,'RAS Wrong':ras,'Returns':ret,'BP Class Pred Wrong':bpc}) diff --git a/linux/Makefile b/linux/Makefile index 46a193090..6f7b6c7fb 100644 --- a/linux/Makefile +++ b/linux/Makefile @@ -1,4 +1,3 @@ -RISCV := /opt/riscv #BUILDROOT := ${RISCV}/buildroot-test BUILDROOT := buildroot IMAGES := ${BUILDROOT}/output/images @@ -32,6 +31,8 @@ OBJDUMPS := $(foreach name, $(OBJDUMPS), $(DIS)/$(name).objdump) all: clean download Image disassemble install +all_nosudo: clean download Image disassemble install_nosudo + Image: bash -c "unset LD_LIBRARY_PATH; make -C $(BUILDROOT) --jobs;" $(MAKE) generate @@ -40,6 +41,18 @@ install: sudo rm -rf $(RISCV)/$(BUILDROOT) sudo mv $(BUILDROOT) $(RISCV)/$(BUILDROOT) +install_nosudo: + rm -rf $(RISCV)/$(BUILDROOT) + mv $(BUILDROOT) $(RISCV)/$(BUILDROOT) + +dumptvs: + sudo mkdir -p $(RISCV)/linux-testvectors + cd testvector-generation; sudo ./genInitMem.sh + +dumptvs_nosudo: + mkdir -p $(RISCV)/linux-testvectors + cd testvector-generation; ./genInitMem.sh + # Temp rule for debugging test: echo $(shell find $(BUILDROOT)/output/build -maxdepth 2 -type d -regex ".*/linux-[0-9]+\.[0-9]+\.[0-9]+$$") diff --git a/sim/run-imperas-linux.sh b/sim/run-imperas-linux.sh index 86e6d1f64..65e4826fb 100755 --- a/sim/run-imperas-linux.sh +++ b/sim/run-imperas-linux.sh @@ -7,4 +7,4 @@ export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=100" #export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=10500000" #export OTHERFLAGS="" -vsim -do "do wally-linux-imperas.do buildroot buildroot $::env(RISCV) 0 0 0" +vsim -c -do "do wally-linux-imperas.do buildroot buildroot $::env(RISCV) 0 0 0" diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 8587e227a..62f45691b 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -246,7 +246,7 @@ module testbench; logic ResetCntRst; logic CopyRAM; - string signame, memfilename, bootmemfilename, pathname; + string signame, memfilename, bootmemfilename, uartoutfilename, pathname; integer begin_signature_addr, end_signature_addr, signature_size; assign ResetThreshold = 3'd5; @@ -338,6 +338,8 @@ module testbench; else if(TEST == "buildroot") begin memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"}; bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"}; + uartoutfilename = {"logs/",TEST,"_uart.out"}; + $system("rm ",uartoutfilename); // Delete existing UARToutfile end else memfilename = {pathname, tests[test], ".elf.memfile"}; if (riscofTest) begin @@ -578,6 +580,16 @@ module testbench; .clk(clk), .ProgramAddrMapFile(ProgramAddrMapFile), .ProgramLabelMapFile(ProgramLabelMapFile)); end + // Append UART output to file for tests + always @(posedge clk) begin + if (TEST == "buildroot") begin + if (~dut.uncore.uncore.uart.uart.MEMWb & dut.uncore.uncore.uart.uart.u.A == 3'b000 & ~dut.uncore.uncore.uart.uart.u.DLAB) begin + memFile = $fopen(uartoutfilename, "ab"); + $fwrite(memFile, "%c", dut.uncore.uncore.uart.uart.u.Din); + $fclose(memFile); + end + end + end // Termination condition // terminate on a specific ECALL after li x3,1 for old Imperas tests, *** remove this when old imperas tests are removed