diff --git a/fpga/src/fpgaTopArtyA7.sv b/fpga/src/fpgaTopArtyA7.sv
index fa2aa59a9..9133baa25 100644
--- a/fpga/src/fpgaTopArtyA7.sv
+++ b/fpga/src/fpgaTopArtyA7.sv
@@ -28,7 +28,7 @@
 
 import cvw::*;
 
-module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 1)
+module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0)
   (input           default_100mhz_clk,
 (* mark_debug = "true" *)   input           resetn,
    input           south_reset,