From da4eca48544607a55c7b1824173c5da04d34785a Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 15 Jan 2024 13:24:57 -0800 Subject: [PATCH 1/9] Tested Zfh support using unreleased version of risch-arch-test Zfh tests. Fixed two bugs in fmv to/from int. --- config/buildroot/config.vh | 1 + config/rv32e/config.vh | 1 + config/rv32gc/config.vh | 1 + config/rv32i/config.vh | 1 + config/rv32imc/config.vh | 1 + config/rv64fpquad/config.vh | 3 +- config/rv64gc/config.vh | 1 + config/rv64i/config.vh | 1 + config/shared/parameter-defs.vh | 1 + src/cvw.sv | 1 + src/fpu/fpu.sv | 20 +- testbench/common/instrNameDecTB.sv | 131 ++++-------- testbench/testbench.sv | 4 + testbench/tests.vh | 327 ++++++++++++++++++++++++++++- 14 files changed, 395 insertions(+), 99 deletions(-) diff --git a/config/buildroot/config.vh b/config/buildroot/config.vh index e183d9cbd..d36fcf6e3 100644 --- a/config/buildroot/config.vh +++ b/config/buildroot/config.vh @@ -41,6 +41,7 @@ localparam ZICNTR_SUPPORTED = 1; localparam ZIHPM_SUPPORTED = 1; localparam COUNTERS = 12'd32; localparam ZFH_SUPPORTED = 0; +localparam ZFA_SUPPORTED = 0; localparam SSTC_SUPPORTED = 1; localparam ZICBOM_SUPPORTED = 1; localparam ZICBOZ_SUPPORTED = 1; diff --git a/config/rv32e/config.vh b/config/rv32e/config.vh index 8906bb571..70d455b4e 100644 --- a/config/rv32e/config.vh +++ b/config/rv32e/config.vh @@ -41,6 +41,7 @@ localparam COUNTERS = 12'd0; localparam ZICNTR_SUPPORTED = 0; localparam ZIHPM_SUPPORTED = 0; localparam ZFH_SUPPORTED = 0; +localparam ZFA_SUPPORTED = 0; localparam SSTC_SUPPORTED = 0; localparam ZICBOM_SUPPORTED = 0; localparam ZICBOZ_SUPPORTED = 0; diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh index 67855c817..a59bb1ab3 100644 --- a/config/rv32gc/config.vh +++ b/config/rv32gc/config.vh @@ -42,6 +42,7 @@ localparam COUNTERS = 12'd32; localparam ZICNTR_SUPPORTED = 1; localparam ZIHPM_SUPPORTED = 1; localparam ZFH_SUPPORTED = 0; +localparam ZFA_SUPPORTED = 0; localparam SSTC_SUPPORTED = 1; localparam ZICBOM_SUPPORTED = 1; localparam ZICBOZ_SUPPORTED = 1; diff --git a/config/rv32i/config.vh b/config/rv32i/config.vh index 2f90656f2..6e5d08803 100644 --- a/config/rv32i/config.vh +++ b/config/rv32i/config.vh @@ -41,6 +41,7 @@ localparam COUNTERS = 0; localparam ZICNTR_SUPPORTED = 0; localparam ZIHPM_SUPPORTED = 0; localparam ZFH_SUPPORTED = 0; +localparam ZFA_SUPPORTED = 0; localparam SSTC_SUPPORTED = 0; localparam ZICBOM_SUPPORTED = 0; localparam ZICBOZ_SUPPORTED = 0; diff --git a/config/rv32imc/config.vh b/config/rv32imc/config.vh index ecb7b8f78..a32dc3bd6 100644 --- a/config/rv32imc/config.vh +++ b/config/rv32imc/config.vh @@ -40,6 +40,7 @@ localparam COUNTERS = 12'd32; localparam ZICNTR_SUPPORTED = 1; localparam ZIHPM_SUPPORTED = 1; localparam ZFH_SUPPORTED = 0; +localparam ZFA_SUPPORTED = 0; localparam SSTC_SUPPORTED = 0; localparam ZICBOM_SUPPORTED = 0; localparam ZICBOZ_SUPPORTED = 0; diff --git a/config/rv64fpquad/config.vh b/config/rv64fpquad/config.vh index 11feba734..09885808f 100644 --- a/config/rv64fpquad/config.vh +++ b/config/rv64fpquad/config.vh @@ -31,7 +31,7 @@ localparam XLEN = 32'd64; // IEEE 754 compliance -localparam IEEE754 = 0; +localparam IEEE754 = 1; // MISA RISC-V configuration per specification localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 ); @@ -41,6 +41,7 @@ localparam COUNTERS = 12'd32; localparam ZICNTR_SUPPORTED = 1; localparam ZIHPM_SUPPORTED = 1; localparam ZFH_SUPPORTED = 1; +localparam ZFA_SUPPORTED = 0; localparam SSTC_SUPPORTED = 0; localparam ZICBOM_SUPPORTED = 0; localparam ZICBOZ_SUPPORTED = 0; diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh index af6e4aebd..af828589d 100644 --- a/config/rv64gc/config.vh +++ b/config/rv64gc/config.vh @@ -41,6 +41,7 @@ localparam COUNTERS = 12'd32; localparam ZICNTR_SUPPORTED = 1; localparam ZIHPM_SUPPORTED = 1; localparam ZFH_SUPPORTED = 0; +localparam ZFA_SUPPORTED = 0; localparam SSTC_SUPPORTED = 1; localparam ZICBOM_SUPPORTED = 1; localparam ZICBOZ_SUPPORTED = 1; diff --git a/config/rv64i/config.vh b/config/rv64i/config.vh index 1908f900f..609a50f97 100644 --- a/config/rv64i/config.vh +++ b/config/rv64i/config.vh @@ -41,6 +41,7 @@ localparam COUNTERS = 0; localparam ZICNTR_SUPPORTED = 0; localparam ZIHPM_SUPPORTED = 0; localparam ZFH_SUPPORTED = 0; +localparam ZFA_SUPPORTED = 0; localparam SSTC_SUPPORTED = 0; localparam ZICBOM_SUPPORTED = 0; localparam ZICBOZ_SUPPORTED = 0; diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh index ec6fc7ec5..7dc0a0bcf 100644 --- a/config/shared/parameter-defs.vh +++ b/config/shared/parameter-defs.vh @@ -14,6 +14,7 @@ localparam cvw_t P = '{ ZICNTR_SUPPORTED : ZICNTR_SUPPORTED, ZIHPM_SUPPORTED : ZIHPM_SUPPORTED, ZFH_SUPPORTED : ZFH_SUPPORTED, + ZFA_SUPPORTED : ZFA_SUPPORTED, SSTC_SUPPORTED : SSTC_SUPPORTED, VIRTMEM_SUPPORTED : VIRTMEM_SUPPORTED, VECTORED_INTERRUPTS_SUPPORTED : VECTORED_INTERRUPTS_SUPPORTED, diff --git a/src/cvw.sv b/src/cvw.sv index 53cbb5a70..a9ee9d093 100644 --- a/src/cvw.sv +++ b/src/cvw.sv @@ -49,6 +49,7 @@ typedef struct packed { logic ZICNTR_SUPPORTED; logic ZIHPM_SUPPORTED; logic ZFH_SUPPORTED; + logic ZFA_SUPPORTED; logic SSTC_SUPPORTED; logic VIRTMEM_SUPPORTED; logic VECTORED_INTERRUPTS_SUPPORTED; diff --git a/src/fpu/fpu.sv b/src/fpu/fpu.sv index 7d7574a45..14fc4259b 100755 --- a/src/fpu/fpu.sv +++ b/src/fpu/fpu.sv @@ -263,15 +263,17 @@ module fpu import cvw::*; #(parameter cvw_t P) ( .ToInt(FWriteIntE), .XZero(XZeroE), .Fmt(FmtE), .Ce(CeE), .ShiftAmt(CvtShiftAmtE), .ResSubnormUf(CvtResSubnormUfE), .Cs(CsE), .IntZero(IntZeroE), .LzcIn(CvtLzcInE)); - // NaN Box SrcA to convert integer to requested FP size + // NaN Box SrcA to convert integer to requested FP size for fmv int->fp if(P.FPSIZES == 1) assign AlignedSrcAE = {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE}; else if(P.FPSIZES == 2) mux2 #(P.FLEN) SrcAMux ({{P.FLEN-P.LEN1{1'b1}}, ForwardedSrcAE[P.LEN1-1:0]}, {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE}, FmtE, AlignedSrcAE); - else if(P.FPSIZES == 3 | P.FPSIZES == 4) + else if(P.FPSIZES == 3 | P.FPSIZES == 4) begin + localparam XD_LEN = P.D_LEN < P.XLEN ? P.D_LEN : P.XLEN; // shorter of D_LEN and XLEN mux4 #(P.FLEN) SrcAMux ({{P.FLEN-P.S_LEN{1'b1}}, ForwardedSrcAE[P.S_LEN-1:0]}, - {{P.FLEN-P.D_LEN{1'b1}}, ForwardedSrcAE[P.D_LEN-1:0]}, + {{P.FLEN-XD_LEN{1'b1}}, ForwardedSrcAE[XD_LEN-1:0]}, {{P.FLEN-P.H_LEN{1'b1}}, ForwardedSrcAE[P.H_LEN-1:0]}, {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE}, FmtE, AlignedSrcAE); // NaN boxing zeroes + end // select a result that may be written to the FP register mux3 #(P.FLEN) FResMux(SgnResE, AlignedSrcAE, CmpFpResE, {OpCtrlE[2], &OpCtrlE[1:0]}, PreFpResE); @@ -282,20 +284,20 @@ module fpu import cvw::*; #(parameter cvw_t P) ( assign mvsgn = XE[P.FLEN-1]; assign SgnExtXE = XE; end else if(P.FPSIZES == 2) begin - mux2 #(1) sgnmux (XE[P.LEN1-1], XE[P.FLEN-1],FmtE, mvsgn); + mux2 #(1) sgnmux (XE[P.LEN1-1], XE[P.FLEN-1],FmtE, mvsgn); mux2 #(P.FLEN) sgnextmux ({{P.FLEN-P.LEN1{mvsgn}}, XE[P.LEN1-1:0]}, XE, FmtE, SgnExtXE); end else if(P.FPSIZES == 3 | P.FPSIZES == 4) begin - mux4 #(1) sgnmux (XE[P.H_LEN-1], XE[P.S_LEN-1], XE[P.D_LEN-1], XE[P.LLEN-1], FmtE, mvsgn); - mux4 #(P.FLEN) fmulzeromux ({{P.FLEN-P.H_LEN{mvsgn}}, XE[P.H_LEN-1:0]}, - {{P.FLEN-P.S_LEN{mvsgn}}, XE[P.S_LEN-1:0]}, - {{P.FLEN-P.D_LEN{mvsgn}}, XE[P.D_LEN-1:0]}, + mux4 #(1) sgnmux (XE[P.S_LEN-1], XE[P.D_LEN-1], XE[P.H_LEN-1], XE[P.LLEN-1], FmtE, mvsgn); + mux4 #(P.FLEN) sgnextmux ({{P.FLEN-P.S_LEN{mvsgn}}, XE[P.S_LEN-1:0]}, + {{P.FLEN-P.D_LEN{mvsgn}}, XE[P.D_LEN-1:0]}, + {{P.FLEN-P.H_LEN{mvsgn}}, XE[P.H_LEN-1:0]}, XE, FmtE, SgnExtXE); end if (P.FLEN>P.XLEN) assign IntSrcXE = SgnExtXE[P.XLEN-1:0]; else - assign IntSrcXE = {{P.XLEN-P.FLEN{mvsgn}}, SgnExtXE}; + assign IntSrcXE = {{P.XLEN-P.FLEN{mvsgn}}, SgnExtXE}; mux3 #(P.XLEN) IntResMux (ClassResE, IntSrcXE, CmpIntResE, {~FResSelE[1], FResSelE[0]}, FIntResE); // E/M pipe registers diff --git a/testbench/common/instrNameDecTB.sv b/testbench/common/instrNameDecTB.sv index 96ef6d67f..a3b5ef58e 100644 --- a/testbench/common/instrNameDecTB.sv +++ b/testbench/common/instrNameDecTB.sv @@ -232,95 +232,7 @@ module instrNameDecTB( 10'b1000111_???: name = "FMSUB"; 10'b1001011_???: name = "FNMSUB"; 10'b1001111_???: name = "FNMADD"; - 10'b1010011_000: if (funct7[6:2] == 5'b00000) name = "FADD"; - else if (funct7[6:2] == 5'b00001) name = "FSUB"; - else if (funct7[6:2] == 5'b00010) name = "FMUL"; - else if (funct7[6:2] == 5'b00011) name = "FDIV"; - else if (funct7[6:2] == 5'b01011) name = "FSQRT"; - else if (funct7 == 7'b1100000 & rs2 == 5'b00000) name = "FCVT.W.S"; - else if (funct7 == 7'b1100000 & rs2 == 5'b00001) name = "FCVT.WU.S"; - else if (funct7 == 7'b1100000 & rs2 == 5'b00010) name = "FCVT.L.S"; - else if (funct7 == 7'b1100000 & rs2 == 5'b00011) name = "FCVT.LU.S"; - else if (funct7 == 7'b1101000 & rs2 == 5'b00000) name = "FCVT.S.W"; - else if (funct7 == 7'b1101000 & rs2 == 5'b00001) name = "FCVT.S.WU"; - else if (funct7 == 7'b1101000 & rs2 == 5'b00010) name = "FCVT.S.L"; - else if (funct7 == 7'b1101000 & rs2 == 5'b00011) name = "FCVT.S.LU"; - else if (funct7 == 7'b1100001 & rs2 == 5'b00000) name = "FCVT.W.D"; - else if (funct7 == 7'b1100001 & rs2 == 5'b00001) name = "FCVT.WU.D"; - else if (funct7 == 7'b1100001 & rs2 == 5'b00010) name = "FCVT.L.D"; - else if (funct7 == 7'b1100001 & rs2 == 5'b00011) name = "FCVT.LU.D"; - else if (funct7 == 7'b1101001 & rs2 == 5'b00000) name = "FCVT.D.W"; - else if (funct7 == 7'b1101001 & rs2 == 5'b00001) name = "FCVT.D.WU"; - else if (funct7 == 7'b1101001 & rs2 == 5'b00010) name = "FCVT.D.L"; - else if (funct7 == 7'b1101001 & rs2 == 5'b00011) name = "FCVT.D.LU"; - else if (funct7 == 7'b0100000 & rs2 == 5'b00001) name = "FCVT.S.D"; - else if (funct7 == 7'b0100001 & rs2 == 5'b00000) name = "FCVT.D.S"; - else if (funct7 == 7'b1110000 & rs2 == 5'b00000) name = "FMV.X.W"; - else if (funct7 == 7'b1111000 & rs2 == 5'b00000) name = "FMV.W.X"; - else if (funct7 == 7'b1110001 & rs2 == 5'b00000) name = "FMV.X.D"; // DOUBLE - else if (funct7 == 7'b1111001 & rs2 == 5'b00000) name = "FMV.D.X"; // DOUBLE - else if (funct7[6:2] == 5'b00100) name = "FSGNJ"; - else if (funct7[6:2] == 5'b00101) name = "FMIN"; - else if (funct7[6:2] == 5'b10100) name = "FLE"; - else name = "ILLEGAL"; - 10'b1010011_001: if (funct7[6:2] == 5'b00000) name = "FADD"; - else if (funct7[6:2] == 5'b00001) name = "FSUB"; - else if (funct7[6:2] == 5'b00010) name = "FMUL"; - else if (funct7[6:2] == 5'b00011) name = "FDIV"; - else if (funct7[6:2] == 5'b01011) name = "FSQRT"; - else if (funct7 == 7'b1100000 & rs2 == 5'b00000) name = "FCVT.W.S"; - else if (funct7 == 7'b1100000 & rs2 == 5'b00001) name = "FCVT.WU.S"; - else if (funct7 == 7'b1100000 & rs2 == 5'b00010) name = "FCVT.L.S"; - else if (funct7 == 7'b1100000 & rs2 == 5'b00011) name = "FCVT.LU.S"; - else if (funct7 == 7'b1101000 & rs2 == 5'b00000) name = "FCVT.S.W"; - else if (funct7 == 7'b1101000 & rs2 == 5'b00001) name = "FCVT.S.WU"; - else if (funct7 == 7'b1101000 & rs2 == 5'b00010) name = "FCVT.S.L"; - else if (funct7 == 7'b1101000 & rs2 == 5'b00011) name = "FCVT.S.LU"; - else if (funct7 == 7'b1100001 & rs2 == 5'b00000) name = "FCVT.W.D"; - else if (funct7 == 7'b1100001 & rs2 == 5'b00001) name = "FCVT.WU.D"; - else if (funct7 == 7'b1100001 & rs2 == 5'b00010) name = "FCVT.L.D"; - else if (funct7 == 7'b1100001 & rs2 == 5'b00011) name = "FCVT.LU.D"; - else if (funct7 == 7'b1101001 & rs2 == 5'b00000) name = "FCVT.D.W"; - else if (funct7 == 7'b1101001 & rs2 == 5'b00001) name = "FCVT.D.WU"; - else if (funct7 == 7'b1101001 & rs2 == 5'b00010) name = "FCVT.D.L"; - else if (funct7 == 7'b1101001 & rs2 == 5'b00011) name = "FCVT.D.LU"; - else if (funct7 == 7'b0100000 & rs2 == 5'b00001) name = "FCVT.S.D"; - else if (funct7 == 7'b0100001 & rs2 == 5'b00000) name = "FCVT.D.S"; - else if (funct7[6:2] == 5'b00100) name = "FSGNJN"; - else if (funct7[6:2] == 5'b00101) name = "FMAX"; - else if (funct7[6:2] == 5'b10100) name = "FLT"; - else if (funct7[6:2] == 5'b11100) name = "FCLASS"; - else name = "ILLEGAL"; - 10'b1010011_010: if (funct7[6:2] == 5'b00000) name = "FADD"; - else if (funct7[6:2] == 5'b00001) name = "FSUB"; - else if (funct7[6:2] == 5'b00010) name = "FMUL"; - else if (funct7[6:2] == 5'b00011) name = "FDIV"; - else if (funct7[6:2] == 5'b01011) name = "FSQRT"; - else if (funct7 == 7'b1100000 & rs2 == 5'b00000) name = "FCVT.W.S"; - else if (funct7 == 7'b1100000 & rs2 == 5'b00001) name = "FCVT.WU.S"; - else if (funct7 == 7'b1100000 & rs2 == 5'b00010) name = "FCVT.L.S"; - else if (funct7 == 7'b1100000 & rs2 == 5'b00011) name = "FCVT.LU.S"; - else if (funct7 == 7'b1101000 & rs2 == 5'b00000) name = "FCVT.S.W"; - else if (funct7 == 7'b1101000 & rs2 == 5'b00001) name = "FCVT.S.WU"; - else if (funct7 == 7'b1101000 & rs2 == 5'b00010) name = "FCVT.S.L"; - else if (funct7 == 7'b1101000 & rs2 == 5'b00011) name = "FCVT.S.LU"; - else if (funct7 == 7'b1100001 & rs2 == 5'b00000) name = "FCVT.W.D"; - else if (funct7 == 7'b1100001 & rs2 == 5'b00001) name = "FCVT.WU.D"; - else if (funct7 == 7'b1100001 & rs2 == 5'b00010) name = "FCVT.L.D"; - else if (funct7 == 7'b1100001 & rs2 == 5'b00011) name = "FCVT.LU.D"; - else if (funct7 == 7'b1101001 & rs2 == 5'b00000) name = "FCVT.D.W"; - else if (funct7 == 7'b1101001 & rs2 == 5'b00001) name = "FCVT.D.WU"; - else if (funct7 == 7'b1101001 & rs2 == 5'b00010) name = "FCVT.D.L"; - else if (funct7 == 7'b1101001 & rs2 == 5'b00011) name = "FCVT.D.LU"; - else if (funct7 == 7'b0100000 & rs2 == 5'b00001) name = "FCVT.S.D"; - else if (funct7 == 7'b0100001 & rs2 == 5'b00000) name = "FCVT.D.S"; - else if (funct7[6:2] == 5'b00100) name = "FSGNJX"; - else if (funct7[6:2] == 5'b10100) name = "FEQ"; - else name = "ILLEGAL"; - /* verilator lint_off CASEOVERLAP */ - // *** RT: definitely take a look at this. This overlaps with 10'b1010011_000 10'b1010011_???: if (funct7[6:2] == 5'b00000) name = "FADD"; - /* verilator lint_on CASEOVERLAP */ else if (funct7[6:2] == 5'b00001) name = "FSUB"; else if (funct7[6:2] == 5'b00010) name = "FMUL"; else if (funct7[6:2] == 5'b00011) name = "FDIV"; @@ -343,6 +255,49 @@ module instrNameDecTB( else if (funct7 == 7'b1101001 & rs2 == 5'b00011) name = "FCVT.D.LU"; else if (funct7 == 7'b0100000 & rs2 == 5'b00001) name = "FCVT.S.D"; else if (funct7 == 7'b0100001 & rs2 == 5'b00000) name = "FCVT.D.S"; + else if (funct7 == 7'b1100010 & rs2 == 5'b00000) name = "FCVT.W.H"; + else if (funct7 == 7'b1100010 & rs2 == 5'b00001) name = "FCVT.WU.H"; + else if (funct7 == 7'b1100010 & rs2 == 5'b00010) name = "FCVT.L.H"; + else if (funct7 == 7'b1100010 & rs2 == 5'b00011) name = "FCVT.LU.H"; + else if (funct7 == 7'b1101010 & rs2 == 5'b00000) name = "FCVT.H.W"; + else if (funct7 == 7'b1101010 & rs2 == 5'b00001) name = "FCVT.H.WU"; + else if (funct7 == 7'b1101010 & rs2 == 5'b00010) name = "FCVT.H.L"; + else if (funct7 == 7'b1101010 & rs2 == 5'b00011) name = "FCVT.H.LU"; + else if (funct7 == 7'b1100011 & rs2 == 5'b00000) name = "FCVT.W.Q"; + else if (funct7 == 7'b1100011 & rs2 == 5'b00001) name = "FCVT.WU.Q"; + else if (funct7 == 7'b1100011 & rs2 == 5'b00010) name = "FCVT.L.Q"; + else if (funct7 == 7'b1100011 & rs2 == 5'b00011) name = "FCVT.LU.Q"; + else if (funct7 == 7'b1101011 & rs2 == 5'b00000) name = "FCVT.Q.W"; + else if (funct7 == 7'b1101011 & rs2 == 5'b00001) name = "FCVT.Q.WU"; + else if (funct7 == 7'b1101011 & rs2 == 5'b00010) name = "FCVT.Q.L"; + else if (funct7 == 7'b1101011 & rs2 == 5'b00011) name = "FCVT.Q.LU"; + else if (funct7 == 7'b0100000 & rs2 == 5'b00001) name = "FCVT.S.D"; + else if (funct7 == 7'b0100000 & rs2 == 5'b00010) name = "FCVT.S.H"; + else if (funct7 == 7'b0100000 & rs2 == 5'b00011) name = "FCVT.S.Q"; + else if (funct7 == 7'b0100001 & rs2 == 5'b00000) name = "FCVT.D.S"; + else if (funct7 == 7'b0100001 & rs2 == 5'b00010) name = "FCVT.D.H"; + else if (funct7 == 7'b0100001 & rs2 == 5'b00011) name = "FCVT.D.Q"; + else if (funct7 == 7'b0100010 & rs2 == 5'b00000) name = "FCVT.H.S"; + else if (funct7 == 7'b0100010 & rs2 == 5'b00001) name = "FCVT.H.D"; + else if (funct7 == 7'b0100010 & rs2 == 5'b00011) name = "FCVT.H.Q"; + else if (funct7 == 7'b0100011 & rs2 == 5'b00000) name = "FCVT.Q.S"; + else if (funct7 == 7'b0100011 & rs2 == 5'b00001) name = "FCVT.Q.D"; + else if (funct7 == 7'b0100011 & rs2 == 5'b00010) name = "FCVT.Q.H"; + else if (funct7 == 7'b1110000 & rs2 == 5'b00000 & funct3 == 3'b000) name = "FMV.X.W"; + else if (funct7 == 7'b1111000 & rs2 == 5'b00000 & funct3 == 3'b000) name = "FMV.W.X"; + else if (funct7 == 7'b1110001 & rs2 == 5'b00000 & funct3 == 3'b000) name = "FMV.X.D"; + else if (funct7 == 7'b1111001 & rs2 == 5'b00000 & funct3 == 3'b000) name = "FMV.D.X"; + else if (funct7 == 7'b1110010 & rs2 == 5'b00000 & funct3 == 3'b000) name = "FMV.X.H"; + else if (funct7 == 7'b1111010 & rs2 == 5'b00000 & funct3 == 3'b000) name = "FMV.H.X"; + else if (funct7[6:2] == 5'b00100 & funct3 == 3'b000) name = "FSGNJ"; + else if (funct7[6:2] == 5'b00101 & funct3 == 3'b000) name = "FMIN"; + else if (funct7[6:2] == 5'b10100 & funct3 == 3'b000) name = "FLE"; + else if (funct7[6:2] == 5'b00100 & funct3 == 3'b001) name = "FSGNJN"; + else if (funct7[6:2] == 5'b00101 & funct3 == 3'b001) name = "FMAX"; + else if (funct7[6:2] == 5'b10100 & funct3 == 3'b001) name = "FLT"; + else if (funct7[6:2] == 5'b11100 & funct3 == 3'b001) name = "FCLASS"; + else if (funct7[6:2] == 5'b00100 & funct3 == 3'b010) name = "FSGNJX"; + else if (funct7[6:2] == 5'b10100 & funct3 == 3'b010) name = "FEQ"; else name = "ILLEGAL"; 10'b0000111_010: name = "FLW"; 10'b0100111_010: name = "FSW"; diff --git a/testbench/testbench.sv b/testbench/testbench.sv index e68b01b48..efd4ea637 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -127,6 +127,8 @@ module testbench; "arch64zbs": if (P.ZBS_SUPPORTED) tests = arch64zbs; "arch64zicboz": if (P.ZICBOZ_SUPPORTED) tests = arch64zicboz; "arch64zcb": if (P.ZCB_SUPPORTED) tests = arch64zcb; + "arch64zfh": if (P.ZFH_SUPPORTED) tests = arch64zfh; +// "arch64zfa": if (P.ZFA_SUPPORTED) tests = arch64zfa; endcase end else begin // RV32 case (TEST) @@ -161,6 +163,8 @@ module testbench; "arch32zbs": if (P.ZBS_SUPPORTED) tests = arch32zbs; "arch32zicboz": if (P.ZICBOZ_SUPPORTED) tests = arch32zicboz; "arch32zcb": if (P.ZCB_SUPPORTED) tests = arch32zcb; + "arch32zfh": if (P.ZFH_SUPPORTED) tests = arch32zfh; + "arch32zfaf": if (P.ZFA_SUPPORTED) tests = arch32zfaf; endcase end if (tests.size() == 0) begin diff --git a/testbench/tests.vh b/testbench/tests.vh index 39b4ecc41..2eef6fc04 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -1291,6 +1291,172 @@ string imperas32f[] = '{ "rv64i_m/F/src/fsw-align-01.S" }; + string arch64zfh[] = '{ + `RISCVARCHTEST, + "rv64i_m/Zfh/src/fmv.x.h_b1-01.S", + "rv64i_m/Zfh/src/fadd_b10-01.S", + "rv64i_m/Zfh/src/fadd_b1-01.S", + "rv64i_m/Zfh/src/fadd_b11-01.S", + "rv64i_m/Zfh/src/fadd_b12-01.S", + "rv64i_m/Zfh/src/fadd_b13-01.S", + "rv64i_m/Zfh/src/fadd_b2-01.S", + "rv64i_m/Zfh/src/fadd_b3-01.S", + "rv64i_m/Zfh/src/fadd_b4-01.S", + "rv64i_m/Zfh/src/fadd_b5-01.S", + "rv64i_m/Zfh/src/fadd_b7-01.S", + "rv64i_m/Zfh/src/fadd_b8-01.S", + "rv64i_m/Zfh/src/fclass_b1-01.S", + "rv64i_m/Zfh/src/fcvt.h.w_b25-01.S", + "rv64i_m/Zfh/src/fcvt.h.w_b26-01.S", + "rv64i_m/Zfh/src/fcvt.h.wu_b25-01.S", + "rv64i_m/Zfh/src/fcvt.h.wu_b26-01.S", + "rv64i_m/Zfh/src/fcvt.w.h_b1-01.S", + "rv64i_m/Zfh/src/fcvt.w.h_b22-01.S", + "rv64i_m/Zfh/src/fcvt.w.h_b23-01.S", + "rv64i_m/Zfh/src/fcvt.w.h_b24-01.S", + "rv64i_m/Zfh/src/fcvt.w.h_b27-01.S", + "rv64i_m/Zfh/src/fcvt.w.h_b28-01.S", + "rv64i_m/Zfh/src/fcvt.w.h_b29-01.S", + "rv64i_m/Zfh/src/fcvt.wu.h_b1-01.S", + "rv64i_m/Zfh/src/fcvt.wu.h_b22-01.S", + "rv64i_m/Zfh/src/fcvt.wu.h_b23-01.S", + "rv64i_m/Zfh/src/fcvt.wu.h_b24-01.S", + "rv64i_m/Zfh/src/fcvt.wu.h_b27-01.S", + "rv64i_m/Zfh/src/fcvt.wu.h_b28-01.S", + "rv64i_m/Zfh/src/fcvt.wu.h_b29-01.S", + "rv64i_m/Zfh/src/fcvt.h.l_b25-01.S", + "rv64i_m/Zfh/src/fcvt.h.l_b26-01.S", + "rv64i_m/Zfh/src/fcvt.h.lu_b25-01.S", + "rv64i_m/Zfh/src/fcvt.h.lu_b26-01.S", + "rv64i_m/Zfh/src/fcvt.l.h_b1-01.S", + "rv64i_m/Zfh/src/fcvt.l.h_b22-01.S", + "rv64i_m/Zfh/src/fcvt.l.h_b23-01.S", + "rv64i_m/Zfh/src/fcvt.l.h_b24-01.S", + "rv64i_m/Zfh/src/fcvt.l.h_b27-01.S", + "rv64i_m/Zfh/src/fcvt.l.h_b28-01.S", + "rv64i_m/Zfh/src/fcvt.l.h_b29-01.S", + "rv64i_m/Zfh/src/fcvt.lu.h_b1-01.S", + "rv64i_m/Zfh/src/fcvt.lu.h_b22-01.S", + "rv64i_m/Zfh/src/fcvt.lu.h_b23-01.S", + "rv64i_m/Zfh/src/fcvt.lu.h_b24-01.S", + "rv64i_m/Zfh/src/fcvt.lu.h_b27-01.S", + "rv64i_m/Zfh/src/fcvt.lu.h_b28-01.S", + "rv64i_m/Zfh/src/fcvt.lu.h_b29-01.S", + "rv64i_m/Zfh/src/fdiv_b20-01.S", + "rv64i_m/Zfh/src/fdiv_b1-01.S", + "rv64i_m/Zfh/src/fdiv_b2-01.S", + "rv64i_m/Zfh/src/fdiv_b21-01.S", + "rv64i_m/Zfh/src/fdiv_b3-01.S", + "rv64i_m/Zfh/src/fdiv_b4-01.S", + "rv64i_m/Zfh/src/fdiv_b5-01.S", + "rv64i_m/Zfh/src/fdiv_b6-01.S", + "rv64i_m/Zfh/src/fdiv_b7-01.S", + "rv64i_m/Zfh/src/fdiv_b8-01.S", + "rv64i_m/Zfh/src/fdiv_b9-01.S", + "rv64i_m/Zfh/src/feq_b1-01.S", + "rv64i_m/Zfh/src/feq_b19-01.S", + "rv64i_m/Zfh/src/fle_b1-01.S", + "rv64i_m/Zfh/src/fle_b19-01.S", + "rv64i_m/Zfh/src/flt_b1-01.S", + "rv64i_m/Zfh/src/flt_b19-01.S", + "rv64i_m/Zfh/src/flh-align-01.S", +/* "rv64i_m/Zfh/src/fmadd_b1-01.S", + "rv64i_m/Zfh/src/fmadd_b14-01.S", + "rv64i_m/Zfh/src/fmadd_b16-01.S", + "rv64i_m/Zfh/src/fmadd_b17-01.S", + "rv64i_m/Zfh/src/fmadd_b18-01.S", + "rv64i_m/Zfh/src/fmadd_b2-01.S", + "rv64i_m/Zfh/src/fmadd_b3-01.S", + "rv64i_m/Zfh/src/fmadd_b4-01.S", + "rv64i_m/Zfh/src/fmadd_b5-01.S", + "rv64i_m/Zfh/src/fmadd_b6-01.S", + "rv64i_m/Zfh/src/fmadd_b7-01.S", + "rv64i_m/Zfh/src/fmadd_b8-01.S", */ + "rv64i_m/Zfh/src/fmax_b1-01.S", + "rv64i_m/Zfh/src/fmax_b19-01.S", + "rv64i_m/Zfh/src/fmin_b1-01.S", + "rv64i_m/Zfh/src/fmin_b19-01.S", +/* "rv64i_m/Zfh/src/fmsub_b1-01.S", + "rv64i_m/Zfh/src/fmsub_b14-01.S", + "rv64i_m/Zfh/src/fmsub_b16-01.S", + "rv64i_m/Zfh/src/fmsub_b17-01.S", + "rv64i_m/Zfh/src/fmsub_b18-01.S", + "rv64i_m/Zfh/src/fmsub_b2-01.S", + "rv64i_m/Zfh/src/fmsub_b3-01.S", + "rv64i_m/Zfh/src/fmsub_b4-01.S", + "rv64i_m/Zfh/src/fmsub_b5-01.S", + "rv64i_m/Zfh/src/fmsub_b6-01.S", + "rv64i_m/Zfh/src/fmsub_b7-01.S", + "rv64i_m/Zfh/src/fmsub_b8-01.S", */ + "rv64i_m/Zfh/src/fmul_b1-01.S", + "rv64i_m/Zfh/src/fmul_b2-01.S", + "rv64i_m/Zfh/src/fmul_b3-01.S", + "rv64i_m/Zfh/src/fmul_b4-01.S", + "rv64i_m/Zfh/src/fmul_b5-01.S", + "rv64i_m/Zfh/src/fmul_b6-01.S", + "rv64i_m/Zfh/src/fmul_b7-01.S", + "rv64i_m/Zfh/src/fmul_b8-01.S", + "rv64i_m/Zfh/src/fmul_b9-01.S", + "rv64i_m/Zfh/src/fmv.h.x_b25-01.S", + "rv64i_m/Zfh/src/fmv.h.x_b26-01.S", + "rv64i_m/Zfh/src/fmv.x.h_b1-01.S", + "rv64i_m/Zfh/src/fmv.x.h_b22-01.S", + "rv64i_m/Zfh/src/fmv.x.h_b23-01.S", + "rv64i_m/Zfh/src/fmv.x.h_b24-01.S", + "rv64i_m/Zfh/src/fmv.x.h_b27-01.S", + "rv64i_m/Zfh/src/fmv.x.h_b28-01.S", + "rv64i_m/Zfh/src/fmv.x.h_b29-01.S", +/* "rv64i_m/Zfh/src/fnmadd_b1-01.S", + "rv64i_m/Zfh/src/fnmadd_b14-01.S", + "rv64i_m/Zfh/src/fnmadd_b16-01.S", + "rv64i_m/Zfh/src/fnmadd_b17-01.S", + "rv64i_m/Zfh/src/fnmadd_b18-01.S", + "rv64i_m/Zfh/src/fnmadd_b2-01.S", + "rv64i_m/Zfh/src/fnmadd_b3-01.S", + "rv64i_m/Zfh/src/fnmadd_b4-01.S", + "rv64i_m/Zfh/src/fnmadd_b5-01.S", + "rv64i_m/Zfh/src/fnmadd_b6-01.S", + "rv64i_m/Zfh/src/fnmadd_b7-01.S", + "rv64i_m/Zfh/src/fnmadd_b8-01.S", + "rv64i_m/Zfh/src/fnmsub_b1-01.S", + "rv64i_m/Zfh/src/fnmsub_b14-01.S", + "rv64i_m/Zfh/src/fnmsub_b16-01.S", + "rv64i_m/Zfh/src/fnmsub_b17-01.S", + "rv64i_m/Zfh/src/fnmsub_b18-01.S", + "rv64i_m/Zfh/src/fnmsub_b2-01.S", + "rv64i_m/Zfh/src/fnmsub_b3-01.S", + "rv64i_m/Zfh/src/fnmsub_b4-01.S", + "rv64i_m/Zfh/src/fnmsub_b5-01.S", + "rv64i_m/Zfh/src/fnmsub_b6-01.S", + "rv64i_m/Zfh/src/fnmsub_b7-01.S", + "rv64i_m/Zfh/src/fnmsub_b8-01.S", */ + "rv64i_m/Zfh/src/fsgnj_b1-01.S", + "rv64i_m/Zfh/src/fsgnjn_b1-01.S", + "rv64i_m/Zfh/src/fsgnjx_b1-01.S", + "rv64i_m/Zfh/src/fsqrt_b1-01.S", + "rv64i_m/Zfh/src/fsqrt_b20-01.S", + "rv64i_m/Zfh/src/fsqrt_b2-01.S", + "rv64i_m/Zfh/src/fsqrt_b3-01.S", + "rv64i_m/Zfh/src/fsqrt_b4-01.S", + "rv64i_m/Zfh/src/fsqrt_b5-01.S", + "rv64i_m/Zfh/src/fsqrt_b7-01.S", + "rv64i_m/Zfh/src/fsqrt_b8-01.S", + "rv64i_m/Zfh/src/fsqrt_b9-01.S", + "rv64i_m/Zfh/src/fsub_b10-01.S", + "rv64i_m/Zfh/src/fsub_b1-01.S", + "rv64i_m/Zfh/src/fsub_b11-01.S", + "rv64i_m/Zfh/src/fsub_b12-01.S", + "rv64i_m/Zfh/src/fsub_b13-01.S", + "rv64i_m/Zfh/src/fsub_b2-01.S", + "rv64i_m/Zfh/src/fsub_b3-01.S", + "rv64i_m/Zfh/src/fsub_b4-01.S", + "rv64i_m/Zfh/src/fsub_b5-01.S", + "rv64i_m/Zfh/src/fsub_b7-01.S", + "rv64i_m/Zfh/src/fsub_b8-01.S", + "rv64i_m/Zfh/src/fsh-align-01.S" + }; + + string arch64d_fma[] = '{ `RISCVARCHTEST, //"rv64i_m/D/src/fmadd.d_b15-01.S", @@ -1638,7 +1804,6 @@ string arch64zbs[] = '{ string arch32f[] = '{ `RISCVARCHTEST, - "rv32i_m/F/src/fdiv_b20-01.S", "rv32i_m/F/src/fadd_b10-01.S", "rv32i_m/F/src/fadd_b1-01.S", "rv32i_m/F/src/fadd_b11-01.S", @@ -1783,6 +1948,166 @@ string arch64zbs[] = '{ "rv32i_m/F/src/fsw-align-01.S" }; + string arch32zfh[] = '{ + `RISCVARCHTEST, + "rv32i_m/Zfh/src/fadd_b10-01.S", + "rv32i_m/Zfh/src/fadd_b1-01.S", + "rv32i_m/Zfh/src/fadd_b11-01.S", + "rv32i_m/Zfh/src/fadd_b12-01.S", + "rv32i_m/Zfh/src/fadd_b13-01.S", + "rv32i_m/Zfh/src/fadd_b2-01.S", + "rv32i_m/Zfh/src/fadd_b3-01.S", + "rv32i_m/Zfh/src/fadd_b4-01.S", + "rv32i_m/Zfh/src/fadd_b5-01.S", + "rv32i_m/Zfh/src/fadd_b7-01.S", + "rv32i_m/Zfh/src/fadd_b8-01.S", + "rv32i_m/Zfh/src/fclass_b1-01.S", + "rv32i_m/Zfh/src/fcvt.h.w_b25-01.S", + "rv32i_m/Zfh/src/fcvt.h.w_b26-01.S", + "rv32i_m/Zfh/src/fcvt.h.wu_b25-01.S", + "rv32i_m/Zfh/src/fcvt.h.wu_b26-01.S", + "rv32i_m/Zfh/src/fcvt.w.h_b1-01.S", + "rv32i_m/Zfh/src/fcvt.w.h_b22-01.S", + "rv32i_m/Zfh/src/fcvt.w.h_b23-01.S", + "rv32i_m/Zfh/src/fcvt.w.h_b24-01.S", + "rv32i_m/Zfh/src/fcvt.w.h_b27-01.S", + "rv32i_m/Zfh/src/fcvt.w.h_b28-01.S", + "rv32i_m/Zfh/src/fcvt.w.h_b29-01.S", + "rv32i_m/Zfh/src/fcvt.wu.h_b1-01.S", + "rv32i_m/Zfh/src/fcvt.wu.h_b22-01.S", + "rv32i_m/Zfh/src/fcvt.wu.h_b23-01.S", + "rv32i_m/Zfh/src/fcvt.wu.h_b24-01.S", + "rv32i_m/Zfh/src/fcvt.wu.h_b27-01.S", + "rv32i_m/Zfh/src/fcvt.wu.h_b28-01.S", + "rv32i_m/Zfh/src/fcvt.wu.h_b29-01.S", + "rv32i_m/Zfh/src/fdiv_b20-01.S", + "rv32i_m/Zfh/src/fdiv_b1-01.S", + "rv32i_m/Zfh/src/fdiv_b2-01.S", + "rv32i_m/Zfh/src/fdiv_b21-01.S", + "rv32i_m/Zfh/src/fdiv_b3-01.S", + "rv32i_m/Zfh/src/fdiv_b4-01.S", + "rv32i_m/Zfh/src/fdiv_b5-01.S", + "rv32i_m/Zfh/src/fdiv_b6-01.S", + "rv32i_m/Zfh/src/fdiv_b7-01.S", + "rv32i_m/Zfh/src/fdiv_b8-01.S", + "rv32i_m/Zfh/src/fdiv_b9-01.S", + "rv32i_m/Zfh/src/feq_b1-01.S", + "rv32i_m/Zfh/src/feq_b19-01.S", + "rv32i_m/Zfh/src/fle_b1-01.S", + "rv32i_m/Zfh/src/fle_b19-01.S", + "rv32i_m/Zfh/src/flt_b1-01.S", + "rv32i_m/Zfh/src/flt_b19-01.S", + "rv32i_m/Zfh/src/flh-align-01.S", +/* "rv32i_m/Zfh/src/fmadd_b1-01.S", + "rv32i_m/Zfh/src/fmadd_b14-01.S", + "rv32i_m/Zfh/src/fmadd_b16-01.S", + "rv32i_m/Zfh/src/fmadd_b17-01.S", + "rv32i_m/Zfh/src/fmadd_b18-01.S", + "rv32i_m/Zfh/src/fmadd_b2-01.S", + "rv32i_m/Zfh/src/fmadd_b3-01.S", + "rv32i_m/Zfh/src/fmadd_b4-01.S", + "rv32i_m/Zfh/src/fmadd_b5-01.S", + "rv32i_m/Zfh/src/fmadd_b6-01.S", + "rv32i_m/Zfh/src/fmadd_b7-01.S", + "rv32i_m/Zfh/src/fmadd_b8-01.S", */ + "rv32i_m/Zfh/src/fmax_b1-01.S", + "rv32i_m/Zfh/src/fmax_b19-01.S", + "rv32i_m/Zfh/src/fmin_b1-01.S", + "rv32i_m/Zfh/src/fmin_b19-01.S", +/* "rv32i_m/Zfh/src/fmsub_b1-01.S", + "rv32i_m/Zfh/src/fmsub_b14-01.S", + "rv32i_m/Zfh/src/fmsub_b16-01.S", + "rv32i_m/Zfh/src/fmsub_b17-01.S", + "rv32i_m/Zfh/src/fmsub_b18-01.S", + "rv32i_m/Zfh/src/fmsub_b2-01.S", + "rv32i_m/Zfh/src/fmsub_b3-01.S", + "rv32i_m/Zfh/src/fmsub_b4-01.S", + "rv32i_m/Zfh/src/fmsub_b5-01.S", + "rv32i_m/Zfh/src/fmsub_b6-01.S", + "rv32i_m/Zfh/src/fmsub_b7-01.S", + "rv32i_m/Zfh/src/fmsub_b8-01.S", */ + "rv32i_m/Zfh/src/fmul_b1-01.S", + "rv32i_m/Zfh/src/fmul_b2-01.S", + "rv32i_m/Zfh/src/fmul_b3-01.S", + "rv32i_m/Zfh/src/fmul_b4-01.S", + "rv32i_m/Zfh/src/fmul_b5-01.S", + "rv32i_m/Zfh/src/fmul_b6-01.S", + "rv32i_m/Zfh/src/fmul_b7-01.S", + "rv32i_m/Zfh/src/fmul_b8-01.S", + "rv32i_m/Zfh/src/fmul_b9-01.S", + "rv32i_m/Zfh/src/fmv.h.x_b25-01.S", + "rv32i_m/Zfh/src/fmv.h.x_b26-01.S", + "rv32i_m/Zfh/src/fmv.x.h_b1-01.S", + "rv32i_m/Zfh/src/fmv.x.h_b22-01.S", + "rv32i_m/Zfh/src/fmv.x.h_b23-01.S", + "rv32i_m/Zfh/src/fmv.x.h_b24-01.S", + "rv32i_m/Zfh/src/fmv.x.h_b27-01.S", + "rv32i_m/Zfh/src/fmv.x.h_b28-01.S", + "rv32i_m/Zfh/src/fmv.x.h_b29-01.S", +/* "rv32i_m/Zfh/src/fnmadd_b1-01.S", + "rv32i_m/Zfh/src/fnmadd_b14-01.S", + "rv32i_m/Zfh/src/fnmadd_b16-01.S", + "rv32i_m/Zfh/src/fnmadd_b17-01.S", + "rv32i_m/Zfh/src/fnmadd_b18-01.S", + "rv32i_m/Zfh/src/fnmadd_b2-01.S", + "rv32i_m/Zfh/src/fnmadd_b3-01.S", + "rv32i_m/Zfh/src/fnmadd_b4-01.S", + "rv32i_m/Zfh/src/fnmadd_b5-01.S", + "rv32i_m/Zfh/src/fnmadd_b6-01.S", + "rv32i_m/Zfh/src/fnmadd_b7-01.S", + "rv32i_m/Zfh/src/fnmadd_b8-01.S", + "rv32i_m/Zfh/src/fnmsub_b1-01.S", + "rv32i_m/Zfh/src/fnmsub_b14-01.S", + "rv32i_m/Zfh/src/fnmsub_b16-01.S", + "rv32i_m/Zfh/src/fnmsub_b17-01.S", + "rv32i_m/Zfh/src/fnmsub_b18-01.S", + "rv32i_m/Zfh/src/fnmsub_b2-01.S", + "rv32i_m/Zfh/src/fnmsub_b3-01.S", + "rv32i_m/Zfh/src/fnmsub_b4-01.S", + "rv32i_m/Zfh/src/fnmsub_b5-01.S", + "rv32i_m/Zfh/src/fnmsub_b6-01.S", + "rv32i_m/Zfh/src/fnmsub_b7-01.S", + "rv32i_m/Zfh/src/fnmsub_b8-01.S", */ + "rv32i_m/Zfh/src/fsgnj_b1-01.S", + "rv32i_m/Zfh/src/fsgnjn_b1-01.S", + "rv32i_m/Zfh/src/fsgnjx_b1-01.S", + "rv32i_m/Zfh/src/fsqrt_b1-01.S", + "rv32i_m/Zfh/src/fsqrt_b20-01.S", + "rv32i_m/Zfh/src/fsqrt_b2-01.S", + "rv32i_m/Zfh/src/fsqrt_b3-01.S", + "rv32i_m/Zfh/src/fsqrt_b4-01.S", + "rv32i_m/Zfh/src/fsqrt_b5-01.S", + "rv32i_m/Zfh/src/fsqrt_b7-01.S", + "rv32i_m/Zfh/src/fsqrt_b8-01.S", + "rv32i_m/Zfh/src/fsqrt_b9-01.S", + "rv32i_m/Zfh/src/fsub_b10-01.S", + "rv32i_m/Zfh/src/fsub_b1-01.S", + "rv32i_m/Zfh/src/fsub_b11-01.S", + "rv32i_m/Zfh/src/fsub_b12-01.S", + "rv32i_m/Zfh/src/fsub_b13-01.S", + "rv32i_m/Zfh/src/fsub_b2-01.S", + "rv32i_m/Zfh/src/fsub_b3-01.S", + "rv32i_m/Zfh/src/fsub_b4-01.S", + "rv32i_m/Zfh/src/fsub_b5-01.S", + "rv32i_m/Zfh/src/fsub_b7-01.S", + "rv32i_m/Zfh/src/fsub_b8-01.S", + "rv32i_m/Zfh/src/fsh-align-01.S" + }; + + string arch32zfaf[] = '{ + `RISCVARCHTEST, + "rv32i_m/F_Zfa/src/fle_b1-01.S", + "rv32i_m/F_Zfa/src/fle_b19-01.S", + "rv32i_m/F_Zfa/src/fli_b1-01.S", + "rv32i_m/F_Zfa/src/fltq_b1-01.S", + "rv32i_m/F_Zfa/src/fltq_b19-01.S", + "rv32i_m/F_Zfa/src/fmin_b1-01.S", + "rv32i_m/F_Zfa/src/fmin_b19-01.S", + "rv32i_m/F_Zfa/src/fmax_b1-01.S", + "rv32i_m/F_Zfa/src/fmax_b19-01.S", + "rv32i_m/F_Zfa/src/fround_b1-01.S" + }; + string arch32d_fma[] = '{ `RISCVARCHTEST, //"rv32i_m/D/src/fmadd.d_b15-01.S", From 0d56a281b9c2993c5d816f8259670828dac5bb4e Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 15 Jan 2024 13:25:46 -0800 Subject: [PATCH 2/9] Cleaned up indentation in testbench-fp --- testbench/testbench-fp.sv | 114 +++++++++++++++++++------------------- 1 file changed, 56 insertions(+), 58 deletions(-) diff --git a/testbench/testbench-fp.sv b/testbench/testbench-fp.sv index ce10c2be2..b19542d62 100644 --- a/testbench/testbench-fp.sv +++ b/testbench/testbench-fp.sv @@ -882,7 +882,7 @@ module testbenchfp; // - the sign of the NaN does not matter for the opperations being tested // - when 2 or more NaNs are inputed the NaN that is propigated doesn't matter if (UnitVal !== `CVTFPUNIT & UnitVal !== `CVTINTUNIT) - case (FmtVal) + case (FmtVal) 2'b11: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res === {1'b0, {P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) | (AnsFlg[4]&(Res[P.Q_LEN-2:0] === {{P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) | (XNaN&(Res[P.Q_LEN-2:0] === {X[P.Q_LEN-2:P.Q_NF],1'b1,X[P.Q_NF-2:0]})) | @@ -903,9 +903,9 @@ module testbenchfp; (XNaN&(Res[P.H_LEN-2:0] === {X[P.H_LEN-2:P.H_NF],1'b1,X[P.H_NF-2:0]})) | (YNaN&(Res[P.H_LEN-2:0] === {Y[P.H_LEN-2:P.H_NF],1'b1,Y[P.H_NF-2:0]})) | (ZNaN&(Res[P.H_LEN-2:0] === {Z[P.H_LEN-2:P.H_NF],1'b1,Z[P.H_NF-2:0]}))); - endcase - else if (UnitVal === `CVTFPUNIT) // if converting from floating point to floating point OpCtrl contains the final FP format - case (OpCtrlVal[1:0]) + endcase + else if (UnitVal === `CVTFPUNIT) // if converting from floating point to floating point OpCtrl contains the final FP format + case (OpCtrlVal[1:0]) 2'b11: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res === {1'b0, {P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) | (AnsFlg[4]&(Res[P.Q_LEN-2:0] === {{P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) | (AnsNaN&(Res[P.Q_LEN-2:0] === Ans[P.Q_LEN-2:0])) | @@ -926,72 +926,70 @@ module testbenchfp; (AnsNaN&(Res[P.H_LEN-2:0] === Ans[P.H_LEN-2:0])) | (XNaN&(Res[P.H_LEN-2:0] === {X[P.H_LEN-2:P.H_NF],1'b1,X[P.H_NF-2:0]})) | (YNaN&(Res[P.H_LEN-2:0] === {Y[P.H_LEN-2:P.H_NF],1'b1,Y[P.H_NF-2:0]}))); - endcase - else NaNGood = 1'b0; // integers can't be NaNs + endcase + else NaNGood = 1'b0; // integers can't be NaNs - /////////////////////////////////////////////////////////////////////////////////////////////// + /////////////////////////////////////////////////////////////////////////////////////////////// - // ||||||| ||| ||| ||||||| ||||||| ||| ||| - // ||| ||| ||| ||| ||| ||| ||| - // ||| |||||||||| ||||||| ||| |||||| - // ||| ||| ||| ||| ||| ||| ||| - // ||||||| ||| ||| ||||||| ||||||| ||| ||| + // ||||||| ||| ||| ||||||| ||||||| ||| ||| + // ||| ||| ||| ||| ||| ||| ||| + // ||| |||||||||| ||||||| ||| |||||| + // ||| ||| ||| ||| ||| ||| ||| + // ||||||| ||| ||| ||||||| ||||||| ||| ||| - /////////////////////////////////////////////////////////////////////////////////////////////// + /////////////////////////////////////////////////////////////////////////////////////////////// - // check if result is correct - // wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage) - assign ResMatch = ((Res === Ans) | NaNGood | (NaNGood === 1'bx)); - assign FlagMatch = ((ResFlg === AnsFlg) | (AnsFlg === 5'bx)); - assign divsqrtop = (OpCtrlVal == `SQRT_OPCTRL) | (OpCtrlVal == `DIV_OPCTRL); - assign FMAop = (OpCtrlVal == `FMAUNIT); - assign DivDone = OldFDivBusyE & ~FDivBusyE; + // check if result is correct + // wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage) + assign ResMatch = ((Res === Ans) | NaNGood | (NaNGood === 1'bx)); + assign FlagMatch = ((ResFlg === AnsFlg) | (AnsFlg === 5'bx)); + assign divsqrtop = (OpCtrlVal == `SQRT_OPCTRL) | (OpCtrlVal == `DIV_OPCTRL); + assign FMAop = (OpCtrlVal == `FMAUNIT); + assign DivDone = OldFDivBusyE & ~FDivBusyE; - // Maybe change OpCtrl but for now just look at TEST for fma test - assign CheckNow = ((DivDone | ~divsqrtop) | (TEST == "add" | TEST == "fma" | TEST == "sub")) & (UnitVal !== `CVTINTUNIT) & (UnitVal !== `CMPUNIT); - if (~(ResMatch & FlagMatch) & CheckNow) begin + // Maybe change OpCtrl but for now just look at TEST for fma test + assign CheckNow = ((DivDone | ~divsqrtop) | (TEST == "add" | TEST == "fma" | TEST == "sub")) & (UnitVal !== `CVTINTUNIT) & (UnitVal !== `CMPUNIT); + if (~(ResMatch & FlagMatch) & CheckNow) begin + errors += 1; + $display("\nError in %s", Tests[TestNum]); + $display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]); + $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Expected: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg); + $stop; + end else if (((UnitVal === `CVTINTUNIT) | (UnitVal === `CMPUNIT)) & + ~(ResMatch & FlagMatch) & (Ans[0] !== 1'bx)) begin // Check for conversion and comparisons errors += 1; $display("\nError in %s", Tests[TestNum]); - $display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]); - $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Expected: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg); + $display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]); + $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg); $stop; - end else if (((UnitVal === `CVTINTUNIT) | (UnitVal === `CMPUNIT)) & - ~(ResMatch & FlagMatch) & (Ans[0] !== 1'bx)) begin // Check for conversion and comparisons - errors += 1; - $display("\nError in %s", Tests[TestNum]); - $display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]); - $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg); - $stop; - end end if (TestVectors[VectorNum][0] === 1'bx & Tests[TestNum] !== "") begin // if reached the eof - // increment the test - TestNum += 1; - // clear the vectors - for(int i=0; i<6133248; i++) TestVectors[i] = {P.FLEN*4+8{1'bx}}; - // read next files - $readmemh({`PATH, Tests[TestNum]}, TestVectors); - // set the vector index back to 0 - VectorNum = 0; - // incemet the operation if all the rounding modes have been tested - if (FrmNum === 4) OpCtrlNum += 1; - // increment the rounding mode or loop back to rne - if (FrmNum < 4) - FrmNum += 1; - else begin - FrmNum = 0; - // Add some time as a buffer between tests at the end of each test - repeat (10) - @(posedge clk); - end - // if no more Tests - finish - if (Tests[TestNum] === "") begin - $display("\nAll Tests completed with %d errors\n", errors); - $stop; - end - $display("Running %s vectors", Tests[TestNum]); + // increment the test + TestNum += 1; + // clear the vectors + for(int i=0; i<6133248; i++) TestVectors[i] = {P.FLEN*4+8{1'bx}}; + // read next files + $readmemh({`PATH, Tests[TestNum]}, TestVectors); + // set the vector index back to 0 + VectorNum = 0; + // incemet the operation if all the rounding modes have been tested + if (FrmNum === 4) OpCtrlNum += 1; + // increment the rounding mode or loop back to rne + if (FrmNum < 4) FrmNum += 1; + else begin + FrmNum = 0; + // Add some time as a buffer between tests at the end of each test + repeat (10) + @(posedge clk); + end + // if no more Tests - finish + if (Tests[TestNum] === "") begin + $display("\nAll Tests completed with %d errors\n", errors); + $stop; + end + $display("Running %s vectors", Tests[TestNum]); end end endmodule From 0235970313a7822614e2b1610dec2f82530f10c7 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 15 Jan 2024 13:40:12 -0800 Subject: [PATCH 3/9] Optimized away unused support for fmv with quads --- src/fpu/fpu.sv | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/src/fpu/fpu.sv b/src/fpu/fpu.sv index 14fc4259b..45af38c0c 100755 --- a/src/fpu/fpu.sv +++ b/src/fpu/fpu.sv @@ -263,23 +263,23 @@ module fpu import cvw::*; #(parameter cvw_t P) ( .ToInt(FWriteIntE), .XZero(XZeroE), .Fmt(FmtE), .Ce(CeE), .ShiftAmt(CvtShiftAmtE), .ResSubnormUf(CvtResSubnormUfE), .Cs(CsE), .IntZero(IntZeroE), .LzcIn(CvtLzcInE)); - // NaN Box SrcA to convert integer to requested FP size for fmv int->fp + // NaN Box SrcA to convert integer to requested FP size for fmv.*.x if(P.FPSIZES == 1) assign AlignedSrcAE = {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE}; else if(P.FPSIZES == 2) mux2 #(P.FLEN) SrcAMux ({{P.FLEN-P.LEN1{1'b1}}, ForwardedSrcAE[P.LEN1-1:0]}, {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE}, FmtE, AlignedSrcAE); else if(P.FPSIZES == 3 | P.FPSIZES == 4) begin localparam XD_LEN = P.D_LEN < P.XLEN ? P.D_LEN : P.XLEN; // shorter of D_LEN and XLEN - mux4 #(P.FLEN) SrcAMux ({{P.FLEN-P.S_LEN{1'b1}}, ForwardedSrcAE[P.S_LEN-1:0]}, + mux3 #(P.FLEN) SrcAMux ({{P.FLEN-P.S_LEN{1'b1}}, ForwardedSrcAE[P.S_LEN-1:0]}, {{P.FLEN-XD_LEN{1'b1}}, ForwardedSrcAE[XD_LEN-1:0]}, {{P.FLEN-P.H_LEN{1'b1}}, ForwardedSrcAE[P.H_LEN-1:0]}, - {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE}, FmtE, AlignedSrcAE); // NaN boxing zeroes + FmtE, AlignedSrcAE); // NaN boxing zeroes end // select a result that may be written to the FP register mux3 #(P.FLEN) FResMux(SgnResE, AlignedSrcAE, CmpFpResE, {OpCtrlE[2], &OpCtrlE[1:0]}, PreFpResE); assign PreNVE = CmpNVE&(OpCtrlE[2]|FWriteIntE); - // select the result that may be written to the integer register with fmv - to IEU + // select the result that may be written to the integer register with fmv.x.* if(P.FPSIZES == 1) begin assign mvsgn = XE[P.FLEN-1]; assign SgnExtXE = XE; @@ -288,16 +288,17 @@ module fpu import cvw::*; #(parameter cvw_t P) ( mux2 #(P.FLEN) sgnextmux ({{P.FLEN-P.LEN1{mvsgn}}, XE[P.LEN1-1:0]}, XE, FmtE, SgnExtXE); end else if(P.FPSIZES == 3 | P.FPSIZES == 4) begin mux4 #(1) sgnmux (XE[P.S_LEN-1], XE[P.D_LEN-1], XE[P.H_LEN-1], XE[P.LLEN-1], FmtE, mvsgn); - mux4 #(P.FLEN) sgnextmux ({{P.FLEN-P.S_LEN{mvsgn}}, XE[P.S_LEN-1:0]}, + mux3 #(P.FLEN) sgnextmux ({{P.FLEN-P.S_LEN{mvsgn}}, XE[P.S_LEN-1:0]}, {{P.FLEN-P.D_LEN{mvsgn}}, XE[P.D_LEN-1:0]}, {{P.FLEN-P.H_LEN{mvsgn}}, XE[P.H_LEN-1:0]}, - XE, FmtE, SgnExtXE); + FmtE, SgnExtXE); // Q not needed because there is no fmv.x.q end + // sign extend to XLEN if necessary if (P.FLEN>P.XLEN) assign IntSrcXE = SgnExtXE[P.XLEN-1:0]; else - assign IntSrcXE = {{P.XLEN-P.FLEN{mvsgn}}, SgnExtXE}; + assign IntSrcXE = {{P.XLEN-P.FLEN{mvsgn}}, SgnExtXE}; mux3 #(P.XLEN) IntResMux (ClassResE, IntSrcXE, CmpIntResE, {~FResSelE[1], FResSelE[0]}, FIntResE); // E/M pipe registers From bb3a7850c421c79eb8c2fdc470f506b597ad6e15 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 15 Jan 2024 17:48:41 -0800 Subject: [PATCH 4/9] Simplified floating-point parameters in config-shared --- config/shared/config-shared.vh | 46 ++++++++++++++++------------------ 1 file changed, 21 insertions(+), 25 deletions(-) diff --git a/config/shared/config-shared.vh b/config/shared/config-shared.vh index 55bca569f..86f9a0a9e 100644 --- a/config/shared/config-shared.vh +++ b/config/shared/config-shared.vh @@ -65,33 +65,29 @@ localparam H_NF = 32'd10; localparam H_BIAS = 32'd15; localparam H_FMT = 2'd2; -// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits -localparam FLEN = (Q_SUPPORTED ? Q_LEN : D_SUPPORTED ? D_LEN : S_LEN); -localparam NE = (Q_SUPPORTED ? Q_NE : D_SUPPORTED ? D_NE : S_NE); -localparam NF = (Q_SUPPORTED ? Q_NF : D_SUPPORTED ? D_NF : S_NF); -localparam FMT = (Q_SUPPORTED ? 2'd3 : D_SUPPORTED ? 2'd1 : 2'd0); -localparam BIAS = (Q_SUPPORTED ? Q_BIAS : D_SUPPORTED ? D_BIAS : S_BIAS); -/* Delete once tested dh 10/10/22 - -localparam FLEN = (Q_SUPPORTED ? Q_LEN : D_SUPPORTED ? D_LEN : F_SUPPORTED ? S_LEN : H_LEN); -localparam NE = (Q_SUPPORTED ? Q_NE : D_SUPPORTED ? D_NE : F_SUPPORTED ? S_NE : H_NE); -localparam NF = (Q_SUPPORTED ? Q_NF : D_SUPPORTED ? D_NF : F_SUPPORTED ? S_NF : H_NF); -localparam FMT = (Q_SUPPORTED ? 2'd3 : D_SUPPORTED ? 2'd1 : F_SUPPORTED ? 2'd0 : 2'd2); -localparam BIAS = (Q_SUPPORTED ? Q_BIAS : D_SUPPORTED ? D_BIAS : F_SUPPORTED ? S_BIAS : H_BIAS);*/ +// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits (for longest format supported) +localparam FLEN = Q_SUPPORTED ? Q_LEN : D_SUPPORTED ? D_LEN : S_LEN; +localparam NE = Q_SUPPORTED ? Q_NE : D_SUPPORTED ? D_NE : S_NE; +localparam NF = Q_SUPPORTED ? Q_NF : D_SUPPORTED ? D_NF : S_NF; +localparam FMT = Q_SUPPORTED ? 2'd3 : D_SUPPORTED ? 2'd1 : 2'd0; +localparam BIAS = Q_SUPPORTED ? Q_BIAS : D_SUPPORTED ? D_BIAS : S_BIAS; // Floating point constants needed for FPU paramerterization -localparam FPSIZES = ((32)'(Q_SUPPORTED)+(32)'(D_SUPPORTED)+(32)'(F_SUPPORTED)+(32)'(ZFH_SUPPORTED)); -localparam FMTBITS = ((32)'(FPSIZES>=3)+1); -localparam LEN1 = ((D_SUPPORTED & (FLEN != D_LEN)) ? D_LEN : (F_SUPPORTED & (FLEN != S_LEN)) ? S_LEN : H_LEN); -localparam NE1 = ((D_SUPPORTED & (FLEN != D_LEN)) ? D_NE : (F_SUPPORTED & (FLEN != S_LEN)) ? S_NE : H_NE); -localparam NF1 = ((D_SUPPORTED & (FLEN != D_LEN)) ? D_NF : (F_SUPPORTED & (FLEN != S_LEN)) ? S_NF : H_NF); -localparam FMT1 = ((D_SUPPORTED & (FLEN != D_LEN)) ? 2'd1 : (F_SUPPORTED & (FLEN != S_LEN)) ? 2'd0 : 2'd2); -localparam BIAS1 = ((D_SUPPORTED & (FLEN != D_LEN)) ? D_BIAS : (F_SUPPORTED & (FLEN != S_LEN)) ? S_BIAS : H_BIAS); -localparam LEN2 = ((F_SUPPORTED & (LEN1 != S_LEN)) ? S_LEN : H_LEN); -localparam NE2 = ((F_SUPPORTED & (LEN1 != S_LEN)) ? S_NE : H_NE); -localparam NF2 = ((F_SUPPORTED & (LEN1 != S_LEN)) ? S_NF : H_NF); -localparam FMT2 = ((F_SUPPORTED & (LEN1 != S_LEN)) ? 2'd0 : 2'd2); -localparam BIAS2 = ((F_SUPPORTED & (LEN1 != S_LEN)) ? S_BIAS : H_BIAS); +// LEN1/NE1/NF1/FNT1 is the size of the second longest supported format +localparam FPSIZES = (32)'(Q_SUPPORTED)+(32)'(D_SUPPORTED)+(32)'(F_SUPPORTED)+(32)'(ZFH_SUPPORTED); +localparam FMTBITS = (32)'(FPSIZES>=3)+1; +localparam LEN1 = (FLEN > D_LEN) ? D_LEN : (FLEN > S_LEN) ? S_LEN : H_LEN; +localparam NE1 = (FLEN > D_LEN) ? D_NE : (FLEN > S_LEN) ? S_NE : H_NE; +localparam NF1 = (FLEN > D_LEN) ? D_NF : (FLEN > S_LEN) ? S_NF : H_NF; +localparam FMT1 = (FLEN > D_LEN) ? 2'd1 : (FLEN > S_LEN) ? 2'd0 : 2'd2; +localparam BIAS1 = (FLEN > D_LEN) ? D_BIAS : (FLEN > S_LEN) ? S_BIAS : H_BIAS; + +// LEN2 etc is the size of the third longest supported format +localparam LEN2 = (LEN1 > S_LEN) ? S_LEN : H_LEN; +localparam NE2 = (LEN1 > S_LEN) ? S_NE : H_NE; +localparam NF2 = (LEN1 > S_LEN) ? S_NF : H_NF; +localparam FMT2 = (LEN1 > S_LEN) ? 2'd0 : 2'd2; +localparam BIAS2 = (LEN1 > S_LEN) ? S_BIAS : H_BIAS; // divider r and rk (bits per digit, bits per cycle) localparam LOGR = $clog2(RADIX); // r = log(R) bits per digit From abecc98563ccb7e4dfaa82bdbe009e58e54b322c Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 16 Jan 2024 10:26:00 -0800 Subject: [PATCH 5/9] Fixed spelling of precision --- src/fpu/fctrl.sv | 2 +- src/fpu/fcvt.sv | 4 ++-- src/fpu/postproc/fmashiftcalc.sv | 2 +- src/fpu/postproc/postprocess.sv | 4 ++-- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index 3d1a7bedd..d1e933142 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -38,7 +38,7 @@ module fctrl import cvw::*; #(parameter cvw_t P) ( input logic FDivBusyE, // is the divider busy // instruction input logic [31:0] InstrD, // the full instruction - input logic [6:0] Funct7D, // bits 31:25 of instruction - may contain percision + input logic [6:0] Funct7D, // bits 31:25 of instruction - may contain precision input logic [6:0] OpD, // bits 6:0 of instruction input logic [4:0] Rs2D, // bits 24:20 of instruction input logic [2:0] Funct3D, // bits 14:12 of instruction - may contain rounding mode diff --git a/src/fpu/fcvt.sv b/src/fpu/fcvt.sv index d396fee95..d721dbc2f 100644 --- a/src/fpu/fcvt.sv +++ b/src/fpu/fcvt.sv @@ -70,8 +70,8 @@ module fcvt import cvw::*; #(parameter cvw_t P) ( assign IntToFp = OpCtrl[2]; // choose the ouptut format depending on the opperation - // - fp -> fp: OpCtrl contains the percision of the output - // - int -> fp: Fmt contains the percision of the output + // - fp -> fp: OpCtrl contains the precision of the output + // - int -> fp: Fmt contains the precision of the output if (P.FPSIZES == 2) assign OutFmt = IntToFp ? Fmt : (OpCtrl[1:0] == P.FMT); else if (P.FPSIZES == 3 | P.FPSIZES == 4) diff --git a/src/fpu/postproc/fmashiftcalc.sv b/src/fpu/postproc/fmashiftcalc.sv index c80748061..0a8ac3035 100644 --- a/src/fpu/postproc/fmashiftcalc.sv +++ b/src/fpu/postproc/fmashiftcalc.sv @@ -50,7 +50,7 @@ module fmashiftcalc import cvw::*; #(parameter cvw_t P) ( // calculate the sum's exponent assign PreNormSumExp = FmaSe + {{P.NE+2-$unsigned($clog2(3*P.NF+5)){1'b1}}, ~FmaSCnt} + (P.NE+2)'(P.NF+3); - //convert the sum's exponent into the proper percision + //convert the sum's exponent into the proper precision if (P.FPSIZES == 1) begin assign NormSumExp = PreNormSumExp; end else if (P.FPSIZES == 2) begin diff --git a/src/fpu/postproc/postprocess.sv b/src/fpu/postproc/postprocess.sv index 05db352cd..ba897a5fd 100644 --- a/src/fpu/postproc/postprocess.sv +++ b/src/fpu/postproc/postprocess.sv @@ -128,8 +128,8 @@ module postprocess import cvw::*; #(parameter cvw_t P) ( assign NaNIn = XNaN|YNaN|ZNaN; // choose the ouptut format depending on the opperation - // - fp -> fp: OpCtrl contains the percision of the output - // - otherwise: Fmt contains the percision of the output + // - fp -> fp: OpCtrl contains the precision of the output + // - otherwise: Fmt contains the precision of the output if (P.FPSIZES == 2) assign OutFmt = IntToFp|~CvtOp ? Fmt : (OpCtrl[1:0] == P.FMT); else if (P.FPSIZES == 3 | P.FPSIZES == 4) From dcd40c6be702c274770a4d1fea488f152fa3fcf5 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 16 Jan 2024 10:27:31 -0800 Subject: [PATCH 6/9] Fixed spelling of output --- src/fpu/fcvt.sv | 2 +- src/fpu/postproc/postprocess.sv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/fpu/fcvt.sv b/src/fpu/fcvt.sv index d721dbc2f..ad767d2ef 100644 --- a/src/fpu/fcvt.sv +++ b/src/fpu/fcvt.sv @@ -69,7 +69,7 @@ module fcvt import cvw::*; #(parameter cvw_t P) ( assign Int64 = OpCtrl[1]; assign IntToFp = OpCtrl[2]; - // choose the ouptut format depending on the opperation + // choose the output format depending on the opperation // - fp -> fp: OpCtrl contains the precision of the output // - int -> fp: Fmt contains the precision of the output if (P.FPSIZES == 2) diff --git a/src/fpu/postproc/postprocess.sv b/src/fpu/postproc/postprocess.sv index ba897a5fd..c2de8644e 100644 --- a/src/fpu/postproc/postprocess.sv +++ b/src/fpu/postproc/postprocess.sv @@ -127,7 +127,7 @@ module postprocess import cvw::*; #(parameter cvw_t P) ( assign InfIn = XInf|YInf|ZInf; assign NaNIn = XNaN|YNaN|ZNaN; - // choose the ouptut format depending on the opperation + // choose the output format depending on the opperation // - fp -> fp: OpCtrl contains the precision of the output // - otherwise: Fmt contains the precision of the output if (P.FPSIZES == 2) From 1a77c08f6e614627c1570ab80662859b918049b6 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 16 Jan 2024 10:46:44 -0800 Subject: [PATCH 7/9] Fixed issues 575 and 477 about FPU tests failing when Zfh = 1. --- src/fpu/postproc/cvtshiftcalc.sv | 2 +- src/fpu/postproc/round.sv | 8 +-- testbench/tests.vh | 97 -------------------------------- 3 files changed, 5 insertions(+), 102 deletions(-) diff --git a/src/fpu/postproc/cvtshiftcalc.sv b/src/fpu/postproc/cvtshiftcalc.sv index 1150d4ecc..ff3d29b90 100644 --- a/src/fpu/postproc/cvtshiftcalc.sv +++ b/src/fpu/postproc/cvtshiftcalc.sv @@ -82,7 +82,7 @@ module cvtshiftcalc import cvw::*; #(parameter cvw_t P) ( P.FMT: ResNegNF = -($clog2(P.NF)+1)'(P.NF); P.FMT1: ResNegNF = -($clog2(P.NF)+1)'(P.NF1); P.FMT2: ResNegNF = -($clog2(P.NF)+1)'(P.NF2); - default: ResNegNF = 'x; + default: ResNegNF = 0; // Not used for floating-point so don't care, but convert to unsigned long has OutFmt = 11. endcase end else if (P.FPSIZES == 4) begin diff --git a/src/fpu/postproc/round.sv b/src/fpu/postproc/round.sv index e01ff376b..460786135 100644 --- a/src/fpu/postproc/round.sv +++ b/src/fpu/postproc/round.sv @@ -145,18 +145,18 @@ module round import cvw::*; #(parameter cvw_t P) ( end else if (P.FPSIZES == 3) begin // 1: XLEN > NF > NF1 - if (XLENPOS == 1) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF2-2:P.CORRSHIFTSZ-P.NF1-1]&FpRes&(OutFmt==P.FMT1)) | + if (XLENPOS == 1) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF2-2:P.CORRSHIFTSZ-P.NF1-1]&FpRes&(OutFmt==P.FMT2)) | (|Mf[P.CORRSHIFTSZ-P.NF1-2:P.CORRSHIFTSZ-P.NF-1]&FpRes&~(OutFmt==P.FMT)) | (|Mf[P.CORRSHIFTSZ-P.NF-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes) | (|Mf[P.CORRSHIFTSZ-P.XLEN-2:0]); // 2: NF > XLEN > NF1 - if (XLENPOS == 2) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF2-2:P.CORRSHIFTSZ-P.NF1-1]&FpRes&(OutFmt==P.FMT1)) | + if (XLENPOS == 2) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF2-2:P.CORRSHIFTSZ-P.NF1-1]&FpRes&(OutFmt==P.FMT2)) | (|Mf[P.CORRSHIFTSZ-P.NF1-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes&~(OutFmt==P.FMT)) | (|Mf[P.CORRSHIFTSZ-P.XLEN-2:P.CORRSHIFTSZ-P.NF-1]&(IntRes|~(OutFmt==P.FMT))) | (|Mf[P.CORRSHIFTSZ-P.NF-2:0]); // 3: NF > NF1 > XLEN - if (XLENPOS == 3) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF2-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes&(OutFmt==P.FMT1)) | - (|Mf[P.CORRSHIFTSZ-P.XLEN-2:P.CORRSHIFTSZ-P.NF1-1]&((OutFmt==P.FMT1)|IntRes)) | + if (XLENPOS == 3) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF2-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes&(OutFmt==P.FMT2)) | + (|Mf[P.CORRSHIFTSZ-P.XLEN-2:P.CORRSHIFTSZ-P.NF1-1]&((OutFmt==P.FMT2)|IntRes)) | (|Mf[P.CORRSHIFTSZ-P.NF1-2:P.CORRSHIFTSZ-P.NF-1]&(~(OutFmt==P.FMT)|IntRes)) | (|Mf[P.CORRSHIFTSZ-P.NF-2:0]); diff --git a/testbench/tests.vh b/testbench/tests.vh index 2eef6fc04..86f65eb14 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -1293,7 +1293,6 @@ string imperas32f[] = '{ string arch64zfh[] = '{ `RISCVARCHTEST, - "rv64i_m/Zfh/src/fmv.x.h_b1-01.S", "rv64i_m/Zfh/src/fadd_b10-01.S", "rv64i_m/Zfh/src/fadd_b1-01.S", "rv64i_m/Zfh/src/fadd_b11-01.S", @@ -1360,34 +1359,10 @@ string imperas32f[] = '{ "rv64i_m/Zfh/src/flt_b1-01.S", "rv64i_m/Zfh/src/flt_b19-01.S", "rv64i_m/Zfh/src/flh-align-01.S", -/* "rv64i_m/Zfh/src/fmadd_b1-01.S", - "rv64i_m/Zfh/src/fmadd_b14-01.S", - "rv64i_m/Zfh/src/fmadd_b16-01.S", - "rv64i_m/Zfh/src/fmadd_b17-01.S", - "rv64i_m/Zfh/src/fmadd_b18-01.S", - "rv64i_m/Zfh/src/fmadd_b2-01.S", - "rv64i_m/Zfh/src/fmadd_b3-01.S", - "rv64i_m/Zfh/src/fmadd_b4-01.S", - "rv64i_m/Zfh/src/fmadd_b5-01.S", - "rv64i_m/Zfh/src/fmadd_b6-01.S", - "rv64i_m/Zfh/src/fmadd_b7-01.S", - "rv64i_m/Zfh/src/fmadd_b8-01.S", */ "rv64i_m/Zfh/src/fmax_b1-01.S", "rv64i_m/Zfh/src/fmax_b19-01.S", "rv64i_m/Zfh/src/fmin_b1-01.S", "rv64i_m/Zfh/src/fmin_b19-01.S", -/* "rv64i_m/Zfh/src/fmsub_b1-01.S", - "rv64i_m/Zfh/src/fmsub_b14-01.S", - "rv64i_m/Zfh/src/fmsub_b16-01.S", - "rv64i_m/Zfh/src/fmsub_b17-01.S", - "rv64i_m/Zfh/src/fmsub_b18-01.S", - "rv64i_m/Zfh/src/fmsub_b2-01.S", - "rv64i_m/Zfh/src/fmsub_b3-01.S", - "rv64i_m/Zfh/src/fmsub_b4-01.S", - "rv64i_m/Zfh/src/fmsub_b5-01.S", - "rv64i_m/Zfh/src/fmsub_b6-01.S", - "rv64i_m/Zfh/src/fmsub_b7-01.S", - "rv64i_m/Zfh/src/fmsub_b8-01.S", */ "rv64i_m/Zfh/src/fmul_b1-01.S", "rv64i_m/Zfh/src/fmul_b2-01.S", "rv64i_m/Zfh/src/fmul_b3-01.S", @@ -1406,30 +1381,6 @@ string imperas32f[] = '{ "rv64i_m/Zfh/src/fmv.x.h_b27-01.S", "rv64i_m/Zfh/src/fmv.x.h_b28-01.S", "rv64i_m/Zfh/src/fmv.x.h_b29-01.S", -/* "rv64i_m/Zfh/src/fnmadd_b1-01.S", - "rv64i_m/Zfh/src/fnmadd_b14-01.S", - "rv64i_m/Zfh/src/fnmadd_b16-01.S", - "rv64i_m/Zfh/src/fnmadd_b17-01.S", - "rv64i_m/Zfh/src/fnmadd_b18-01.S", - "rv64i_m/Zfh/src/fnmadd_b2-01.S", - "rv64i_m/Zfh/src/fnmadd_b3-01.S", - "rv64i_m/Zfh/src/fnmadd_b4-01.S", - "rv64i_m/Zfh/src/fnmadd_b5-01.S", - "rv64i_m/Zfh/src/fnmadd_b6-01.S", - "rv64i_m/Zfh/src/fnmadd_b7-01.S", - "rv64i_m/Zfh/src/fnmadd_b8-01.S", - "rv64i_m/Zfh/src/fnmsub_b1-01.S", - "rv64i_m/Zfh/src/fnmsub_b14-01.S", - "rv64i_m/Zfh/src/fnmsub_b16-01.S", - "rv64i_m/Zfh/src/fnmsub_b17-01.S", - "rv64i_m/Zfh/src/fnmsub_b18-01.S", - "rv64i_m/Zfh/src/fnmsub_b2-01.S", - "rv64i_m/Zfh/src/fnmsub_b3-01.S", - "rv64i_m/Zfh/src/fnmsub_b4-01.S", - "rv64i_m/Zfh/src/fnmsub_b5-01.S", - "rv64i_m/Zfh/src/fnmsub_b6-01.S", - "rv64i_m/Zfh/src/fnmsub_b7-01.S", - "rv64i_m/Zfh/src/fnmsub_b8-01.S", */ "rv64i_m/Zfh/src/fsgnj_b1-01.S", "rv64i_m/Zfh/src/fsgnjn_b1-01.S", "rv64i_m/Zfh/src/fsgnjx_b1-01.S", @@ -1998,34 +1949,10 @@ string arch64zbs[] = '{ "rv32i_m/Zfh/src/flt_b1-01.S", "rv32i_m/Zfh/src/flt_b19-01.S", "rv32i_m/Zfh/src/flh-align-01.S", -/* "rv32i_m/Zfh/src/fmadd_b1-01.S", - "rv32i_m/Zfh/src/fmadd_b14-01.S", - "rv32i_m/Zfh/src/fmadd_b16-01.S", - "rv32i_m/Zfh/src/fmadd_b17-01.S", - "rv32i_m/Zfh/src/fmadd_b18-01.S", - "rv32i_m/Zfh/src/fmadd_b2-01.S", - "rv32i_m/Zfh/src/fmadd_b3-01.S", - "rv32i_m/Zfh/src/fmadd_b4-01.S", - "rv32i_m/Zfh/src/fmadd_b5-01.S", - "rv32i_m/Zfh/src/fmadd_b6-01.S", - "rv32i_m/Zfh/src/fmadd_b7-01.S", - "rv32i_m/Zfh/src/fmadd_b8-01.S", */ "rv32i_m/Zfh/src/fmax_b1-01.S", "rv32i_m/Zfh/src/fmax_b19-01.S", "rv32i_m/Zfh/src/fmin_b1-01.S", "rv32i_m/Zfh/src/fmin_b19-01.S", -/* "rv32i_m/Zfh/src/fmsub_b1-01.S", - "rv32i_m/Zfh/src/fmsub_b14-01.S", - "rv32i_m/Zfh/src/fmsub_b16-01.S", - "rv32i_m/Zfh/src/fmsub_b17-01.S", - "rv32i_m/Zfh/src/fmsub_b18-01.S", - "rv32i_m/Zfh/src/fmsub_b2-01.S", - "rv32i_m/Zfh/src/fmsub_b3-01.S", - "rv32i_m/Zfh/src/fmsub_b4-01.S", - "rv32i_m/Zfh/src/fmsub_b5-01.S", - "rv32i_m/Zfh/src/fmsub_b6-01.S", - "rv32i_m/Zfh/src/fmsub_b7-01.S", - "rv32i_m/Zfh/src/fmsub_b8-01.S", */ "rv32i_m/Zfh/src/fmul_b1-01.S", "rv32i_m/Zfh/src/fmul_b2-01.S", "rv32i_m/Zfh/src/fmul_b3-01.S", @@ -2044,30 +1971,6 @@ string arch64zbs[] = '{ "rv32i_m/Zfh/src/fmv.x.h_b27-01.S", "rv32i_m/Zfh/src/fmv.x.h_b28-01.S", "rv32i_m/Zfh/src/fmv.x.h_b29-01.S", -/* "rv32i_m/Zfh/src/fnmadd_b1-01.S", - "rv32i_m/Zfh/src/fnmadd_b14-01.S", - "rv32i_m/Zfh/src/fnmadd_b16-01.S", - "rv32i_m/Zfh/src/fnmadd_b17-01.S", - "rv32i_m/Zfh/src/fnmadd_b18-01.S", - "rv32i_m/Zfh/src/fnmadd_b2-01.S", - "rv32i_m/Zfh/src/fnmadd_b3-01.S", - "rv32i_m/Zfh/src/fnmadd_b4-01.S", - "rv32i_m/Zfh/src/fnmadd_b5-01.S", - "rv32i_m/Zfh/src/fnmadd_b6-01.S", - "rv32i_m/Zfh/src/fnmadd_b7-01.S", - "rv32i_m/Zfh/src/fnmadd_b8-01.S", - "rv32i_m/Zfh/src/fnmsub_b1-01.S", - "rv32i_m/Zfh/src/fnmsub_b14-01.S", - "rv32i_m/Zfh/src/fnmsub_b16-01.S", - "rv32i_m/Zfh/src/fnmsub_b17-01.S", - "rv32i_m/Zfh/src/fnmsub_b18-01.S", - "rv32i_m/Zfh/src/fnmsub_b2-01.S", - "rv32i_m/Zfh/src/fnmsub_b3-01.S", - "rv32i_m/Zfh/src/fnmsub_b4-01.S", - "rv32i_m/Zfh/src/fnmsub_b5-01.S", - "rv32i_m/Zfh/src/fnmsub_b6-01.S", - "rv32i_m/Zfh/src/fnmsub_b7-01.S", - "rv32i_m/Zfh/src/fnmsub_b8-01.S", */ "rv32i_m/Zfh/src/fsgnj_b1-01.S", "rv32i_m/Zfh/src/fsgnjn_b1-01.S", "rv32i_m/Zfh/src/fsgnjx_b1-01.S", From 846a0c4d50c1032ca787dddd9441f810267e725f Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 16 Jan 2024 11:12:06 -0800 Subject: [PATCH 8/9] Check fma operations don't support H precision --- src/fpu/fctrl.sv | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index d1e933142..999837889 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -84,8 +84,9 @@ module fctrl import cvw::*; #(parameter cvw_t P) ( assign Fmt = Funct7D[1:0]; assign Fmt2 = Rs2D[1:0]; // source format for fcvt fp->fp - assign SupportedFmt = (Fmt == 2'b00 | (Fmt == 2'b01 & P.D_SUPPORTED) | - (Fmt == 2'b10 & P.ZFH_SUPPORTED) | (Fmt == 2'b11 & P.Q_SUPPORTED)); + assign SupportedFmt = (Fmt == 2'b00 | (Fmt == 2'b01 & P.D_SUPPORTED) | + (Fmt == 2'b10 & P.ZFH_SUPPORTED & {OpD[6:4], OpD[1:0]} != 5'b10011) | // fma not supported for Zfh + (Fmt == 2'b11 & P.Q_SUPPORTED)); assign SupportedFmt2 = (Fmt2 == 2'b00 | (Fmt2 == 2'b01 & P.D_SUPPORTED) | (Fmt2 == 2'b10 & P.ZFH_SUPPORTED) | (Fmt2 == 2'b11 & P.Q_SUPPORTED)); From 60e09965d5484219e21a2be68dba720b46935c72 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 16 Jan 2024 11:14:43 -0800 Subject: [PATCH 9/9] Enabled Zfh support in rv64gc --- config/rv64gc/config.vh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh index af828589d..bb3e79659 100644 --- a/config/rv64gc/config.vh +++ b/config/rv64gc/config.vh @@ -40,7 +40,7 @@ localparam ZIFENCEI_SUPPORTED = 1; localparam COUNTERS = 12'd32; localparam ZICNTR_SUPPORTED = 1; localparam ZIHPM_SUPPORTED = 1; -localparam ZFH_SUPPORTED = 0; +localparam ZFH_SUPPORTED = 1; localparam ZFA_SUPPORTED = 0; localparam SSTC_SUPPORTED = 1; localparam ZICBOM_SUPPORTED = 1;