diff --git a/Makefile b/Makefile
index 7f085de40..fab22229d 100644
--- a/Makefile
+++ b/Makefile
@@ -44,7 +44,8 @@ imperasdv_cov:
 	echo "0" > ${WALLY}/sim/seed0.txt
 #	/opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --verbose --seed 0 --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m
 #	/opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${WALLY}/sim/seed0.txt --coverdb ${WALLY}/sim/cov/rv64gc_arch64i.ucdb --verbose
-	/opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${WALLY}/sim/seed0.txt --coverdb riscv.ucdb --verbose
+#	/opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${WALLY}/sim/seed0.txt --coverdb riscv.ucdb --verbose
+	run-elf-cov.bash --elf ${WALLY}/tests/output_folder/asm_test/riscv_arithmetic_basic_test_0.elf --seed ${WALLY}/sim/seed0.txt --coverdb riscv.ucdb --verbose
 	vcover report -details -html sim/riscv.ucdb
 
 funcovreg:
@@ -56,6 +57,58 @@ funcovreg:
 	iter-elf.bash --search ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I --cover
 	vcover report -details -html sim/riscv.ucdb
 
+# test_name=riscv_arithmetic_basic_test
+rvdv: sim/regression_logs sim/regression_ucdbs
+	python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/output_folder  --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gen			>> sim/regression_logs/${test_name}.log 2>&1
+	python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/output_folder  --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gcc_compile	>> sim/regression_logs/${test_name}.log 2>&1
+	python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/output_folder  --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps iss_sim		>> sim/regression_logs/${test_name}.log 2>&1
+#	run-elf.bash --seed ${WALLY}/sim/seed0.txt --verbose --elf ${WALLY}/tests/output_folder/asm_test/${test_name}_0.o													>> sim/regression_logs/${test_name}.log 2>&1
+	/home/qabid/scripts/run-elf-cov.bash --seed ${WALLY}/sim/seed0.txt --verbose --coverdb sim/riscv.ucdb --elf ${WALLY}/tests/output_folder/asm_test/${test_name}_0.o								>> sim/regression_logs/${test_name}.log 2>&1
+	cp sim/riscv.ucdb sim/regression_ucdbs/${test_name}.ucdb
+
+rvdv_regression:
+	mkdir -p sim/regression_logs
+	mkdir -p sim/regression_ucdbs
+	cd sim/regression_logs && rm -rf *
+	cd sim/regression_ucdbs && rm -rf *
+	make rvdv test_name=riscv_arithmetic_basic_test				>> sim/regression.log 2>&1
+	make rvdv test_name=riscv_amo_test							>> sim/regression.log 2>&1
+	make rvdv test_name=riscv_ebreak_debug_mode_test			>> sim/regression.log 2>&1
+	make rvdv test_name=riscv_ebreak_test						>> sim/regression.log 2>&1
+	make rvdv test_name=riscv_floating_point_arithmetic_test	>> sim/regression.log 2>&1
+	make rvdv test_name=riscv_floating_point_mmu_stress_test	>> sim/regression.log 2>&1
+	make rvdv test_name=riscv_floating_point_rand_test			>> sim/regression.log 2>&1
+	make rvdv test_name=riscv_full_interrupt_test				>> sim/regression.log 2>&1
+	make rvdv test_name=riscv_hint_instr_test					>> sim/regression.log 2>&1
+	make rvdv test_name=riscv_illegal_instr_test				>> sim/regression.log 2>&1
+	make rvdv test_name=riscv_invalid_csr_test					>> sim/regression.log 2>&1
+	make rvdv test_name=riscv_jump_stress_test					>> sim/regression.log 2>&1
+	make rvdv test_name=riscv_loop_test							>> sim/regression.log 2>&1
+	make rvdv test_name=riscv_machine_mode_rand_test			>> sim/regression.log 2>&1
+	make rvdv test_name=riscv_mmu_stress_test					>> sim/regression.log 2>&1
+	make rvdv test_name=riscv_no_fence_test						>> sim/regression.log 2>&1
+	make rvdv test_name=riscv_non_compressed_instr_test			>> sim/regression.log 2>&1
+	make rvdv test_name=riscv_pmp_test							>> sim/regression.log 2>&1
+	make rvdv test_name=riscv_privileged_mode_rand_test			>> sim/regression.log 2>&1
+	make rvdv test_name=riscv_rand_instr_test					>> sim/regression.log 2>&1
+	make rvdv test_name=riscv_rand_jump_test					>> sim/regression.log 2>&1
+	make rvdv test_name=riscv_sfence_exception_test				>> sim/regression.log 2>&1
+	make rvdv test_name=riscv_unaligned_load_store_test			>> sim/regression.log 2>&1
+
+rvdv_combine_coverage:
+	mkdir -p sim/regcov
+	cd sim/regcov && rm -rf *
+	vcover merge sim/regcov/regcov.ucdb  sim/regression_ucdbs/* -suppress 6854 -64
+	vcover report -details -html sim/regcov/regcov.ucdb
+	vcover report sim/regcov/regcov.ucdb -details -cvg > sim/regcov/regcov.ucdb.log
+	vcover report sim/regcov/regcov.ucdb -testdetails -cvg > sim/regcov/regcov.ucdb.testdetails.log
+	vcover report sim/regcov/regcov.ucdb -details -cvg -below 100 | egrep "Coverpoint|Covergroup|Cross" | grep -v Metric > sim/regcov/regcov.ucdb.summary.log
+	grep "Total Coverage By Instance" sim/regcov/regcov.ucdb.log
+
+remove_rvdv_artifacts:
+	rm sim/riscv.ucdb sim/regression.log covhtmlreport/ sim/regression_logs/ sim/regression_ucdbs/ sim/regcov/ -rf
+
+collect_riscvdv_regression_coverage: remove_rvdv_artifacts rvdv_regression rvdv_combine_coverage
 coverage:
 	regression-wally -coverage -fp