From 5f358d1af7e525fe16ed253b2d0c037a1fc93121 Mon Sep 17 00:00:00 2001 From: eroom1966 Date: Fri, 16 Jun 2023 16:43:53 +0100 Subject: [PATCH 1/6] add changes for latest IDV file layout --- sim/imperas.ic | 4 ++-- sim/wally-imperas-cov.do | 14 +++++++------- sim/wally-imperas-no-idv.do | 2 +- sim/wally-imperas.do | 14 +++++++------- sim/wally-linux-imperas.do | 14 +++++++------- testbench/testbench-linux-imperas.sv | 6 +++--- testbench/testbench_imperas.sv | 6 +++--- 7 files changed, 30 insertions(+), 30 deletions(-) diff --git a/sim/imperas.ic b/sim/imperas.ic index d561b22f2..ad19aaf68 100644 --- a/sim/imperas.ic +++ b/sim/imperas.ic @@ -1,7 +1,7 @@ #--mpdconsole #--gdbconsole ---showoverrides ---showcommands +#--showoverrides +#--showcommands # Core settings --override cpu/priv_version=1.12 diff --git a/sim/wally-imperas-cov.do b/sim/wally-imperas-cov.do index e39d9ef38..2309b01df 100644 --- a/sim/wally-imperas-cov.do +++ b/sim/wally-imperas-cov.do @@ -29,19 +29,19 @@ vlog +incdir+../config/$1 \ +define+USE_IMPERAS_DV \ +incdir+$env(IMPERAS_HOME)/ImpPublic/include/host \ +incdir+$env(IMPERAS_HOME)/ImpProprietary/include/host \ - $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-api-pkg.sv \ - $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-trace.sv \ - $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/rvvi-pkg.sv \ - $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/imperasDV-api-pkg.sv \ - $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2api.sv \ - $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2log.sv \ + $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviApiPkg.sv \ + $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviTrace.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvPkg.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvApiPkg.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2api.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2log.sv \ \ +define+INCLUDE_TRACE2COV +define+COVER_BASE_RV64I +define+COVER_LEVEL_DV_PR_EXT \ +define+COVER_RV64I \ +define+COVER_RV64C \ +define+COVER_RV64M \ +incdir+$env(IMPERAS_HOME)/ImpProprietary/source/host/riscvISACOV/source \ - $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2cov.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2cov.sv \ \ ../src/cvw.sv \ ../testbench/testbench_imperas.sv \ diff --git a/sim/wally-imperas-no-idv.do b/sim/wally-imperas-no-idv.do index bd07daee1..47d8bf07b 100644 --- a/sim/wally-imperas-no-idv.do +++ b/sim/wally-imperas-no-idv.do @@ -26,7 +26,7 @@ vlib work # *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN. For now just live with the warnings. vlog +incdir+../config/$1 \ +incdir+../config/shared \ - ../../external/ImperasDV-HMC/Imperas/ImpPublic/source/host/rvvi/rvvi-trace.sv \ + ../../external/ImperasDV-HMC/Imperas/ImpPublic/source/host/rvvi/rvviTrace.sv \ ../src/cvw.sv \ ../testbench/testbench_imperas.sv \ ../testbench/common/*.sv \ diff --git a/sim/wally-imperas.do b/sim/wally-imperas.do index 1120b8099..7f0b060e2 100644 --- a/sim/wally-imperas.do +++ b/sim/wally-imperas.do @@ -30,13 +30,13 @@ vlog +incdir+../config/$1 \ +define+USE_IMPERAS_DV \ +incdir+$env(IMPERAS_HOME)/ImpPublic/include/host \ +incdir+$env(IMPERAS_HOME)/ImpProprietary/include/host \ - $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-api-pkg.sv \ - $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-trace.sv \ - $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/rvvi-pkg.sv \ - $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/imperasDV-api-pkg.sv \ - $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2api.sv \ - $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2log.sv \ - $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2cov.sv \ + $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviApiPkg.sv \ + $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviTrace.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvPkg.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvApiPkg.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2api.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2log.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2cov.sv \ ../src/cvw.sv \ ../testbench/testbench_imperas.sv \ ../testbench/common/*.sv \ diff --git a/sim/wally-linux-imperas.do b/sim/wally-linux-imperas.do index 523d31a64..fcf6ceec4 100644 --- a/sim/wally-linux-imperas.do +++ b/sim/wally-linux-imperas.do @@ -53,13 +53,13 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { +incdir+../config/shared \ +incdir+$env(IMPERAS_HOME)/ImpPublic/include/host \ +incdir+$env(IMPERAS_HOME)/ImpProprietary/include/host \ - $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-api-pkg.sv \ - $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-trace.sv \ - $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/rvvi-pkg.sv \ - $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/imperasDV-api-pkg.sv \ - $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2api.sv \ - $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2log.sv \ - $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2cov.sv \ + $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviApiPkg.sv \ + $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviTrace.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvPkg.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvApiPkg.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2api.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2log.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2cov.sv \ ../src/cvw.sv \ ../testbench/testbench-linux-imperas.sv \ ../testbench/common/*.sv ../src/*/*.sv \ diff --git a/testbench/testbench-linux-imperas.sv b/testbench/testbench-linux-imperas.sv index 223e3529b..79b354cb0 100644 --- a/testbench/testbench-linux-imperas.sv +++ b/testbench/testbench-linux-imperas.sv @@ -30,7 +30,7 @@ // `define USE_IMPERAS_DV `ifdef USE_IMPERAS_DV - `include "rvvi/imperasDV.svh" + `include "idv/idv.svh" `endif `define DEBUG_TRACE 0 @@ -55,7 +55,7 @@ module testbench; `ifdef USE_IMPERAS_DV - import rvviPkg::*; + import idvPkg::*; import rvviApiPkg::*; import idvApiPkg::*; `endif @@ -302,7 +302,7 @@ module testbench; initial begin int iter; #1; - MAX_ERRS = 3; + IDV_MAX_ERRS = 3; // Initialize REF (do this before initializing the DUT) if (!rvviVersionCheck(RVVI_API_VERSION)) begin diff --git a/testbench/testbench_imperas.sv b/testbench/testbench_imperas.sv index 7aea61903..0ca45420a 100644 --- a/testbench/testbench_imperas.sv +++ b/testbench/testbench_imperas.sv @@ -32,7 +32,7 @@ // `define USE_IMPERAS_DV `ifdef USE_IMPERAS_DV - `include "rvvi/imperasDV.svh" + `include "idv/idv.svh" `endif import cvw::*; @@ -41,7 +41,7 @@ module testbench; parameter DEBUG=0; `ifdef USE_IMPERAS_DV - import rvviPkg::*; + import idvPkg::*; import rvviApiPkg::*; import idvApiPkg::*; `endif @@ -145,7 +145,7 @@ module testbench; initial begin - MAX_ERRS = 3; + IDV_MAX_ERRS = 3; // Initialize REF (do this before initializing the DUT) if (!rvviVersionCheck(RVVI_API_VERSION)) begin From c2913f49a3676839f577edef6f7c029e231662fa Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 16 Jun 2023 09:26:02 -0700 Subject: [PATCH 2/6] Added assertions for ZICNTR and ZIHPM --- testbench/common/riscvassertions.sv | 2 ++ 1 file changed, 2 insertions(+) diff --git a/testbench/common/riscvassertions.sv b/testbench/common/riscvassertions.sv index 24a7e223c..50577c37d 100644 --- a/testbench/common/riscvassertions.sv +++ b/testbench/common/riscvassertions.sv @@ -56,6 +56,8 @@ module riscvassertions import cvw::*; #(parameter cvw_t P); assert (P.IDIV_ON_FPU == 0 || P.F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED"); assert (P.SSTC_SUPPORTED == 0 || (P.S_SUPPORTED)) else $error("SSTC requires S_SUPPORTED"); assert ((P.ZMMUL_SUPPORTED == 0) || (P.M_SUPPORTED ==0)) else $error("At most one of ZMMUL_SUPPORTED and M_SUPPORTED can be enabled"); + assert ((P.ZICNTR_SUPPORTED == 0) || (P.ZICSR_SUPPORTED == 1)) else $error("ZICNTR_SUPPORTED requires ZICSR_SUPPORTED"); + assert ((P.ZIHPM_SUPPORTED == 0) || (P.ZICNTR_SUPPORTED == 1)) else $error("ZIPHM_SUPPORTED requires ZICNTR_SUPPORTED"); end endmodule From c383407d5c1b15de2caf821ca37fcdd6c324717c Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 16 Jun 2023 16:05:53 -0700 Subject: [PATCH 3/6] Removed redundant and not-covered atomic check from StoreStallD --- src/ieu/controller.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 2314cb81e..838560ed1 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -339,5 +339,6 @@ module controller import cvw::*; #(parameter cvw_t P) ( // the synchronous DTIM cannot read immediately after write // a cache cannot read or write immediately after a write - assign StoreStallD = MemRWE[0] & ((MemRWD[1] | (MemRWD[0] & P.DCACHE_SUPPORTED)) | (|AtomicD)); + // atomic operations are also detected as MemRWD[1] + assign StoreStallD = MemRWE[0] & ((MemRWD[1] | (MemRWD[0] & P.DCACHE_SUPPORTED))); endmodule From 2db94e7dddf8ebb336149cef573301ca5254ac54 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 16 Jun 2023 16:07:28 -0700 Subject: [PATCH 4/6] Replaced zext.h with zext.h_64 in rv64 tests because old one is obsolete --- testbench/tests.vh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testbench/tests.vh b/testbench/tests.vh index 54167f73c..38f5bc2d8 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -1466,7 +1466,7 @@ string arch64zbb[] = '{ "rv64i_m/B/src/andn-01.S", "rv64i_m/B/src/orn-01.S", "rv64i_m/B/src/xnor-01.S", - "rv64i_m/B/src/zext.h-01.S", + "rv64i_m/B/src/zext.h_64-01.S", "rv64i_m/B/src/sext.b-01.S", "rv64i_m/B/src/sext.h-01.S", "rv64i_m/B/src/clz-01.S", From d0183579145aab14cfccb13d6bfaed55d812baa8 Mon Sep 17 00:00:00 2001 From: harshinisrinath Date: Fri, 16 Jun 2023 16:09:48 -0700 Subject: [PATCH 5/6] Improve test coverage on ieu fw. --- tests/coverage/fpu.S | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tests/coverage/fpu.S b/tests/coverage/fpu.S index 7e67b8ab5..29ad9b418 100644 --- a/tests/coverage/fpu.S +++ b/tests/coverage/fpu.S @@ -156,6 +156,10 @@ main: .word 0x43007053 // illegal fcvt.d.* (bad Rs2D) .word 0x42207053 // illegal fcvt.d.* (bad Rs2D[1]) + # Test floating point convert to integer and using result + fcvt.w.s t0, f0 + add t1, t0, t0 + j done .section .data From 5d6eb40c2d4d4955fa9fa7070830d1e3aaae6213 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 17 Jun 2023 20:38:51 -0700 Subject: [PATCH 6/6] Fixed embench to run all tests, even ones not in 1.0 --- benchmarks/embench/Makefile | 8 ++++++++ testbench/tests.vh | 16 ++++++++-------- 2 files changed, 16 insertions(+), 8 deletions(-) diff --git a/benchmarks/embench/Makefile b/benchmarks/embench/Makefile index 538fb64f9..3dba4daaa 100644 --- a/benchmarks/embench/Makefile +++ b/benchmarks/embench/Makefile @@ -16,10 +16,18 @@ buildsize: build_speedopt_size build_sizeopt_size # uses the build_all.py python file to build the tests in addins/embench-iot/bd_speed/ optimized for speed and size build_speedopt_speed: $(embench_dir)/build_all.py --builddir=bd_speedopt_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S" --cflags="-O2 -nostartfiles" + # remove files not used in embench1.0 When changing to 2.0, restore these files + #rm -rf $(embench_dir)/bd_speedopt_speed/src/md5sum + #rm -rf $(embench_dir)/bd_speedopt_speed/src/tarfind + #rm -rf $(embench_dir)/bd_speedopt_speed/src/primecount find $(embench_dir)/bd_speedopt_speed/ -type f ! -name "*.*" | while read f; do cp "$$f" "$$f.elf"; done build_sizeopt_speed: $(embench_dir)/build_all.py --builddir=bd_sizeopt_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S" --cflags="-Os -nostartfiles" + # remove files not used in embench1.0 When changing to 2.0, restore these files + #rm -rf $(embench_dir)/bd_sizeopt_speed/src/md5sum + #rm -rf $(embench_dir)/bd_sizeopt_speed/src/tarfind + #rm -rf $(embench_dir)/bd_sizeopt_speed/src/primecount find $(embench_dir)/bd_sizeopt_speed/ -type f ! -name "*.*" | while read f; do cp "$$f" "$$f.elf"; done # uses the build_all.py python file to build the tests in addins/embench-iot/bd_speed/ optimized for speed and size diff --git a/testbench/tests.vh b/testbench/tests.vh index 38f5bc2d8..f38f28056 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -75,26 +75,26 @@ string tvpaths[] = '{ string embench[] = '{ `EMBENCH, - "bd_speedopt_speed/src/nsichneu/nsichneu", - "bd_speedopt_speed/src/cubic/cubic", // cubic is likely going to removed when embench 2.0 launches "bd_speedopt_speed/src/aha-mont64/aha-mont64", "bd_speedopt_speed/src/crc32/crc32", + "bd_speedopt_speed/src/cubic/cubic", // cubic is likely going to removed when embench 2.0 launches "bd_speedopt_speed/src/edn/edn", "bd_speedopt_speed/src/huffbench/huffbench", "bd_speedopt_speed/src/matmult-int/matmult-int", - // "bd_speedopt_speed/src/md5sum/md5sum", //commenting out tests from embench 2.0. When embench 2.0 launches stabilty, add these tests back + "bd_speedopt_speed/src/md5sum/md5sum", //commenting out tests from embench 2.0. When embench 2.0 launches stabilty, add these tests back "bd_speedopt_speed/src/minver/minver", "bd_speedopt_speed/src/nettle-aes/nettle-aes", "bd_speedopt_speed/src/nettle-sha256/nettle-sha256", + "bd_speedopt_speed/src/nsichneu/nsichneu", "bd_speedopt_speed/src/nbody/nbody", "bd_speedopt_speed/src/picojpeg/picojpeg", - // "bd_speedopt_speed/src/primecount/primecount", + "bd_speedopt_speed/src/primecount/primecount", "bd_speedopt_speed/src/qrduino/qrduino", "bd_speedopt_speed/src/sglib-combined/sglib-combined", "bd_speedopt_speed/src/slre/slre", "bd_speedopt_speed/src/st/st", "bd_speedopt_speed/src/statemate/statemate", - // "bd_speedopt_speed/src/tarfind/tarfind", + "bd_speedopt_speed/src/tarfind/tarfind", "bd_speedopt_speed/src/ud/ud", "bd_speedopt_speed/src/wikisort/wikisort", "bd_sizeopt_speed/src/aha-mont64/aha-mont64", @@ -103,20 +103,20 @@ string tvpaths[] = '{ "bd_sizeopt_speed/src/edn/edn", "bd_sizeopt_speed/src/huffbench/huffbench", "bd_sizeopt_speed/src/matmult-int/matmult-int", - // "bd_sizeopt_speed/src/md5sum/md5sum", + "bd_sizeopt_speed/src/md5sum/md5sum", "bd_sizeopt_speed/src/minver/minver", "bd_sizeopt_speed/src/nbody/nbody", "bd_sizeopt_speed/src/nettle-aes/nettle-aes", "bd_sizeopt_speed/src/nettle-sha256/nettle-sha256", "bd_sizeopt_speed/src/nsichneu/nsichneu", "bd_sizeopt_speed/src/picojpeg/picojpeg", - // "bd_sizeopt_speed/src/primecount/primecount", + "bd_sizeopt_speed/src/primecount/primecount", "bd_sizeopt_speed/src/qrduino/qrduino", "bd_sizeopt_speed/src/sglib-combined/sglib-combined", "bd_sizeopt_speed/src/slre/slre", "bd_sizeopt_speed/src/st/st", "bd_sizeopt_speed/src/statemate/statemate", - // "bd_sizeopt_speed/src/tarfind/tarfind", + "bd_sizeopt_speed/src/tarfind/tarfind", "bd_sizeopt_speed/src/ud/ud", "bd_sizeopt_speed/src/wikisort/wikisort" };