From f68b9c224aa0878bc151f568fd9b9b9a2d61f9fc Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 9 Jun 2023 15:24:26 -0700 Subject: [PATCH] Fixed WALLY-trap test case to use menvcfg --- testbench/common/wallyTracer.sv | 12 ++++++++++++ testbench/testbench-linux-imperas.sv | 2 ++ tests/coverage/csrwrites.S | 3 +++ .../rv32i_m/privilege/src/WALLY-TEST-LIB-32.h | 1 + .../rv64i_m/privilege/src/WALLY-TEST-LIB-64.h | 3 ++- 5 files changed, 20 insertions(+), 1 deletion(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 221c8d7f8..8801f5119 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -139,6 +139,7 @@ module wallyTracer(rvviTrace rvvi); CSRArray[12'h344] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW; CSRArray[12'h304] = testbench.dut.core.priv.priv.csr.csrm.MIE_REGW; CSRArray[12'h301] = testbench.dut.core.priv.priv.csr.csrm.MISA_REGW; + CSRArray[12'h30A] = testbench.dut.core.priv.priv.csr.csrm.MENVCFG_REGW; CSRArray[12'hF14] = testbench.dut.core.priv.priv.csr.csrm.MHARTID_REGW; CSRArray[12'h340] = testbench.dut.core.priv.priv.csr.csrm.MSCRATCH_REGW; CSRArray[12'h342] = testbench.dut.core.priv.priv.csr.csrm.MCAUSE_REGW; @@ -157,6 +158,7 @@ module wallyTracer(rvviTrace rvvi); CSRArray[12'h105] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVEC_REGW; CSRArray[12'h141] = testbench.dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW; CSRArray[12'h106] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW; + CSRArray[12'h10A] = testbench.dut.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW; CSRArray[12'h180] = testbench.dut.core.priv.priv.csr.csrs.csrs.SATP_REGW; CSRArray[12'h140] = testbench.dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW; CSRArray[12'h143] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW; @@ -189,6 +191,7 @@ module wallyTracer(rvviTrace rvvi); CSRArray[12'h344] = CSRArrayOld[12'h344]; CSRArray[12'h304] = CSRArrayOld[12'h304]; CSRArray[12'h301] = CSRArrayOld[12'h301]; + CSRArray[12'h30A] = CSRArrayOld[12'h30A]; CSRArray[12'hF14] = CSRArrayOld[12'hF14]; CSRArray[12'h340] = CSRArrayOld[12'h340]; CSRArray[12'h342] = CSRArrayOld[12'h342]; @@ -207,6 +210,7 @@ module wallyTracer(rvviTrace rvvi); CSRArray[12'h105] = CSRArrayOld[12'h105]; CSRArray[12'h141] = CSRArrayOld[12'h141]; CSRArray[12'h106] = CSRArrayOld[12'h106]; + CSRArray[12'h10A] = CSRArrayOld[12'h10A]; CSRArray[12'h180] = CSRArrayOld[12'h180]; CSRArray[12'h140] = CSRArrayOld[12'h140]; CSRArray[12'h143] = CSRArrayOld[12'h143]; @@ -308,6 +312,7 @@ module wallyTracer(rvviTrace rvvi); CSRArrayOld[12'h344] = CSRArray[12'h344]; CSRArrayOld[12'h304] = CSRArray[12'h304]; CSRArrayOld[12'h301] = CSRArray[12'h301]; + CSRArrayOld[12'h30A] = CSRArray[12'h30A]; CSRArrayOld[12'hF14] = CSRArray[12'hF14]; CSRArrayOld[12'h340] = CSRArray[12'h340]; CSRArrayOld[12'h342] = CSRArray[12'h342]; @@ -326,6 +331,7 @@ module wallyTracer(rvviTrace rvvi); CSRArrayOld[12'h105] = CSRArray[12'h105]; CSRArrayOld[12'h141] = CSRArray[12'h141]; CSRArrayOld[12'h106] = CSRArray[12'h106]; + CSRArrayOld[12'h10A] = CSRArray[12'h10A]; CSRArrayOld[12'h180] = CSRArray[12'h180]; CSRArrayOld[12'h140] = CSRArray[12'h140]; CSRArrayOld[12'h143] = CSRArray[12'h143]; @@ -352,6 +358,7 @@ module wallyTracer(rvviTrace rvvi); assign #2 CSR_W[12'h305] = (CSRArrayOld[12'h305] != CSRArray[12'h305]) ? 1 : 0; assign #2 CSR_W[12'h341] = (CSRArrayOld[12'h341] != CSRArray[12'h341]) ? 1 : 0; assign #2 CSR_W[12'h306] = (CSRArrayOld[12'h306] != CSRArray[12'h306]) ? 1 : 0; + assign #2 CSR_W[12'h30A] = (CSRArrayOld[12'h30A] != CSRArray[12'h30A]) ? 1 : 0; assign #2 CSR_W[12'h320] = (CSRArrayOld[12'h320] != CSRArray[12'h320]) ? 1 : 0; assign #2 CSR_W[12'h302] = (CSRArrayOld[12'h302] != CSRArray[12'h302]) ? 1 : 0; assign #2 CSR_W[12'h303] = (CSRArrayOld[12'h303] != CSRArray[12'h303]) ? 1 : 0; @@ -374,6 +381,7 @@ module wallyTracer(rvviTrace rvvi); assign #2 CSR_W[12'h105] = (CSRArrayOld[12'h105] != CSRArray[12'h105]) ? 1 : 0; assign #2 CSR_W[12'h141] = (CSRArrayOld[12'h141] != CSRArray[12'h141]) ? 1 : 0; assign #2 CSR_W[12'h106] = (CSRArrayOld[12'h106] != CSRArray[12'h106]) ? 1 : 0; + assign #2 CSR_W[12'h10A] = (CSRArrayOld[12'h10A] != CSRArray[12'h10A]) ? 1 : 0; assign #2 CSR_W[12'h180] = (CSRArrayOld[12'h180] != CSRArray[12'h180]) ? 1 : 0; assign #2 CSR_W[12'h140] = (CSRArrayOld[12'h140] != CSRArray[12'h140]) ? 1 : 0; assign #2 CSR_W[12'h143] = (CSRArrayOld[12'h143] != CSRArray[12'h143]) ? 1 : 0; @@ -394,6 +402,7 @@ module wallyTracer(rvviTrace rvvi); assign rvvi.csr_wb[0][0][12'h303] = CSR_W[12'h303]; assign rvvi.csr_wb[0][0][12'h344] = CSR_W[12'h344]; assign rvvi.csr_wb[0][0][12'h304] = CSR_W[12'h304]; + assign rvvi.csr_wb[0][0][12'h30A] = CSR_W[12'h30A]; assign rvvi.csr_wb[0][0][12'h301] = CSR_W[12'h301]; assign rvvi.csr_wb[0][0][12'hF14] = CSR_W[12'hF14]; assign rvvi.csr_wb[0][0][12'h340] = CSR_W[12'h340]; @@ -411,6 +420,7 @@ module wallyTracer(rvviTrace rvvi); assign rvvi.csr_wb[0][0][12'h105] = CSR_W[12'h105]; assign rvvi.csr_wb[0][0][12'h141] = CSR_W[12'h141]; assign rvvi.csr_wb[0][0][12'h106] = CSR_W[12'h106]; + assign rvvi.csr_wb[0][0][12'h10A] = CSR_W[12'h10A]; assign rvvi.csr_wb[0][0][12'h180] = CSR_W[12'h180]; assign rvvi.csr_wb[0][0][12'h140] = CSR_W[12'h140]; assign rvvi.csr_wb[0][0][12'h143] = CSR_W[12'h143]; @@ -431,6 +441,7 @@ module wallyTracer(rvviTrace rvvi); assign rvvi.csr[0][0][12'h303] = CSRArray[12'h303]; assign rvvi.csr[0][0][12'h344] = CSRArray[12'h344]; assign rvvi.csr[0][0][12'h304] = CSRArray[12'h304]; + assign rvvi.csr[0][0][12'h30A] = CSRArray[12'h30A]; assign rvvi.csr[0][0][12'h301] = CSRArray[12'h301]; assign rvvi.csr[0][0][12'hF14] = CSRArray[12'hF14]; assign rvvi.csr[0][0][12'h340] = CSRArray[12'h340]; @@ -448,6 +459,7 @@ module wallyTracer(rvviTrace rvvi); assign rvvi.csr[0][0][12'h105] = CSRArray[12'h105]; assign rvvi.csr[0][0][12'h141] = CSRArray[12'h141]; assign rvvi.csr[0][0][12'h106] = CSRArray[12'h106]; + assign rvvi.csr[0][0][12'h10A] = CSRArray[12'h10A]; assign rvvi.csr[0][0][12'h180] = CSRArray[12'h180]; assign rvvi.csr[0][0][12'h140] = CSRArray[12'h140]; assign rvvi.csr[0][0][12'h143] = CSRArray[12'h143]; diff --git a/testbench/testbench-linux-imperas.sv b/testbench/testbench-linux-imperas.sv index d3d71626f..223e3529b 100644 --- a/testbench/testbench-linux-imperas.sv +++ b/testbench/testbench-linux-imperas.sv @@ -866,10 +866,12 @@ module testbench; "medeleg": `checkCSR(`CSR_BASE.csrm.MEDELEG_REGW) "mepc": `checkCSR(`CSR_BASE.csrm.MEPC_REGW) "mtval": `checkCSR(`CSR_BASE.csrm.MTVAL_REGW) + "menvcfg": `checkCSR(`CSR_BASE.csrm.MENVCFG_REGW) "sepc": `checkCSR(`CSR_BASE.csrs.csrs.SEPC_REGW) "scause": `checkCSR(`CSR_BASE.csrs.csrs.SCAUSE_REGW) "stvec": `checkCSR(`CSR_BASE.csrs.csrs.STVEC_REGW) "stval": `checkCSR(`CSR_BASE.csrs.csrs.STVAL_REGW) + "senvcfg": `checkCSR(`CSR_BASE.csrs.SENVCFG_REGW) "mip": begin `checkCSR(`CSR_BASE.csrm.MIP_REGW) if(!NO_SPOOFING) begin diff --git a/tests/coverage/csrwrites.S b/tests/coverage/csrwrites.S index 41d211467..63ee00c38 100644 --- a/tests/coverage/csrwrites.S +++ b/tests/coverage/csrwrites.S @@ -33,5 +33,8 @@ main: csrrw t0, satp, zero csrrw t0, stvec, zero csrrw t0, sscratch, zero + li t0, -2 + csrrw t1, menvcfg, t0 + csrrw t2, senvcfg, t0 j done diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h index 277f67274..178ffc672 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h @@ -280,6 +280,7 @@ end_trap_triggers: la t4, 0x02004000 // MTIMECMP register in CLINT li t5, 0xFFFFFFFF sw t5, 0(t4) // set mtimecmp to 0xFFFFFFFF to really make sure time interrupts don't go off immediately after being enabled + csrw stimecmp, t5 // also set stimecmp to avoid an immediate supervisor timer interrupt j trap_handler_end_\MODE\() // skip the trap handler when it is being defined. diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h index 44a4ea66f..8961608dc 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h @@ -274,7 +274,8 @@ end_trap_triggers: la t4, 0x02004000 // MTIMECMP register in CLINT li t5, 0xFFFFFFFF sd t5, 0(t4) // set mtimecmp to 0xFFFFFFFF to really make sure time interrupts don't go off immediately after being enabled - + csrw stimecmp, t5 // also set stimecmp to avoid an immediate supervisor timer interrupt + j trap_handler_end_\MODE\() // skip the trap handler when it is being defined. // ---------------------------------------------------------------------------------------------