diff --git a/sim/questa/coverage-exclusions-rv64gc.do b/sim/questa/coverage-exclusions-rv64gc.do
index 20b915be7..fb33136b2 100644
--- a/sim/questa/coverage-exclusions-rv64gc.do
+++ b/sim/questa/coverage-exclusions-rv64gc.do
@@ -451,6 +451,12 @@ coverage exclude -scope /dut/core/priv/priv/csr/csru/csru -linerange [GetLineNum
 coverage exclude -scope /dut/core/priv/priv/csr/counters/counters/cntr[1] -linerange [GetLineNum ${SRC}/privileged/csrc.sv "MTIME traps"] -item e 1 -fecexprrow 2 4
 coverage exclude -scope /dut/core/priv/priv/csr/counters/counters/cntr[1] -linerange [GetLineNum ${SRC}/privileged/csrc.sv "assign NextHPMCOUNTERM"] -item b 1
 
+# attempting to write stimecmp with STCE=0 traps, causing CSRSWriteM to go low 
+coverage exclude -scope /dut/core/priv/priv/csr/csrs/csrs -linerange [GetLineNum ${SRC}/privileged/csrs.sv "assign WriteSTIMECMPM"] -item e 1 -fecexprrow 5
+
+# mode != m_mode and TVM = 1 causes a trap, causing CSRSWriteM to go low
+coverage exclude -scope /dut/core/priv/priv/csr/csrs/csrs -linerange [GetLineNum ${SRC}/privileged/csrs.sv "assign WriteSATPM"] -item e 1 -fecexprrow 5 8
+
 ####################
 # EBU
 ####################
diff --git a/tests/coverage/priv.S b/tests/coverage/priv.S
index 211e7d13a..9fdecaf6a 100644
--- a/tests/coverage/priv.S
+++ b/tests/coverage/priv.S
@@ -298,6 +298,18 @@ sretdone:
 
     wfi
 
+    ///////////////////
+    // writing user level CSR in u mode
+    ///////////////////
+    li a0, 3
+    ecall               # enter machine mode
+    # set mstatus.FS to 01 to enable fp
+    li t0,0x4000
+    csrs mstatus, t0
+    li a0, 0
+    ecall               # enter user mode
+    li t0, 5
+    csrw frm, t0
 
 
     # Test uncovered privdec instructions