From f91fb7a388e01898ab135707850d379b296e11f0 Mon Sep 17 00:00:00 2001
From: Skylar Litz <slitz@hmc.edu>
Date: Sat, 26 Mar 2022 21:28:57 +0000
Subject: [PATCH] add AtemptedInstructionCount signal

---
 pipelined/regression/linux-wave.do     | 4 +---
 pipelined/testbench/testbench-linux.sv | 6 ++++++
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/pipelined/regression/linux-wave.do b/pipelined/regression/linux-wave.do
index 1d59dcbf0..770b3d340 100644
--- a/pipelined/regression/linux-wave.do
+++ b/pipelined/regression/linux-wave.do
@@ -4,6 +4,7 @@ add wave -noupdate /testbench/clk
 add wave -noupdate /testbench/reset
 add wave -noupdate /testbench/reset_ext
 add wave -noupdate -radix unsigned /testbench/InstrCountW
+add wave -noupdate -radix unsigned /testbench/AttemptedInstructionCount
 add wave -noupdate /testbench/dut/core/SATP_REGW
 add wave -noupdate /testbench/dut/core/IllegalFPUInstrD
 add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPPredWrongE
@@ -388,7 +389,6 @@ add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/cor
 add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PTE
 add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/ITLBMissF
 add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/ITLBMissOrDAFaultF
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBMissM
 add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBWriteF
 add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBWriteM
 add wave -noupdate -group AHB -color Gold /testbench/dut/core/ebu/BusState
@@ -526,9 +526,7 @@ add wave -noupdate /testbench/dut/core/ifu/SpillSupport/spillsupport/TakeSpillF
 add wave -noupdate /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillF
 add wave -noupdate /testbench/dut/core/ifu/SpillSupport/spillsupport/IFUCacheBusStallF
 add wave -noupdate -color Yellow /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DAPageFault
-add wave -noupdate /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/OtherPageFault
 add wave -noupdate /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/ITLBMissF
-add wave -noupdate /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/Accessed
 add wave -noupdate /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/WriteAccess
 add wave -noupdate /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/TLBPageFault
 TreeUpdate [SetDefaultTree]
diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv
index 12950b637..da6233150 100644
--- a/pipelined/testbench/testbench-linux.sv
+++ b/pipelined/testbench/testbench-linux.sv
@@ -176,6 +176,7 @@ module testbench;
   integer           CheckMIPFutureM;
   integer           CheckSIPFutureE;
   integer           CheckSIPFutureM;
+  logic [`XLEN-1:0] AttemptedInstructionCount;
   // Useful Aliases
   `define RF          dut.core.ieu.dp.regf.rf
   `define PC          dut.core.ifu.pcreg.q
@@ -380,11 +381,13 @@ module testbench;
       traceFileM = $fopen({testvectorDir,"all.txt"}, "r");
       traceFileE = $fopen({testvectorDir,"all.txt"}, "r");
       InstrCountW = '0;
+      AttemptedInstructionCount = '0;
     end else begin // checkpoint
       //$readmemh({checkpointDir,"ram.txt"}, dut.uncore.ram.ram.RAM);
       traceFileE = $fopen({checkpointDir,"all.txt"}, "r");
       traceFileM = $fopen({checkpointDir,"all.txt"}, "r");
       InstrCountW = CHECKPOINT;
+      AttemptedInstructionCount = CHECKPOINT;
       // manual checkpoint initializations that don't neatly fit into MACRO
       force {`STATUS_TSR,`STATUS_TW,`STATUS_TVM,`STATUS_MXR,`STATUS_SUM,`STATUS_MPRV} = initMSTATUS[0][22:17];
       force {`STATUS_FS,`STATUS_MPP} = initMSTATUS[0][14:11];
@@ -440,6 +443,9 @@ module testbench;
       for(index``STAGE = 0; index``STAGE < line``STAGE.len(); index``STAGE++) begin \
         //$display("char = %s", line``STAGE[index]); \
         if (line``STAGE[index``STAGE] == " " | line``STAGE[index``STAGE] == "\n") begin \
+          if (line``STAGE[index``STAGE] == "\n" & `"STAGE`"=="M") begin \
+            AttemptedInstructionCount += 1; \
+          end \
           EndIndex``STAGE = index``STAGE; \
           ExpectedTokens``STAGE[TokenIndex``STAGE] = line``STAGE.substr(StartIndex``STAGE, EndIndex``STAGE-1); \
           //$display("In Tokenizer %s", line``STAGE.substr(StartIndex, EndIndex-1)); \