From 23d524b43945446418aa296cce9d2e473edc1b1a Mon Sep 17 00:00:00 2001 From: DTowersM Date: Fri, 3 Jun 2022 22:07:14 +0000 Subject: [PATCH 1/7] testbench now reads begin_signature addr from .objdump.addr instead of from tests.vh --- pipelined/testbench/testbench.sv | 28 +- pipelined/testbench/tests.vh | 2778 +++++++++++++++--------------- 2 files changed, 1413 insertions(+), 1393 deletions(-) diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 0ebab1cf9..211dae08c 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -129,7 +129,7 @@ logic [3:0] dummy; end string signame, memfilename, pathname, objdumpfilename, adrstr, outputfile; - integer outputFilePointer; + integer outputFilePointer, ProgramLabelMap, ProgramAddrMap; logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn; logic UARTSin, UARTSout; @@ -217,8 +217,27 @@ logic [3:0] dummy; // Termination condition (i.e. we finished running current test) if (DCacheFlushDone) begin // Gets the memory location of begin_signature - testadr = (`RAM_BASE+tests[test+1].atohex())/(`XLEN/8); - testadrNoBase = (tests[test+1].atohex())/(`XLEN/8); + adrstr = "0"; + ProgramLabelMap = $fopen(ProgramLabelMapFile, "r"); + ProgramAddrMap = $fopen(ProgramAddrMapFile, "r"); + while (!$feof(ProgramLabelMap)) begin + string addr, label; + integer returncode; + returncode = $fgets(label, ProgramLabelMap); + returncode = $fgets(addr, ProgramAddrMap); + if (label == "begin_signature\n") begin + adrstr = addr[4:7]; + if (DEBUG) $display("adrstr: %s", adrstr); + end + end + if (adrstr == "0") begin + $display("begin_signature addr not found in %s", ProgramLabelMapFile); + end + $fclose(ProgramLabelMap); + $fclose(ProgramAddrMap); + + testadr = (`RAM_BASE+adrstr.atohex())/(`XLEN/8); + testadrNoBase = (adrstr.atohex())/(`XLEN/8); #600; // give time for instructions in pipeline to finish if (TEST == "embench") begin // Writes contents of begin_signature to .sim.output file @@ -296,7 +315,8 @@ logic [3:0] dummy; end end // move onto the next test, check to see if we're done - test = test + 2; + // test = test + 2; + test = test + 1; if (test == tests.size()) begin if (totalerrors == 0) $display("SUCCESS! All tests ran without failures."); else $display("FAIL: %d test programs had errors", totalerrors); diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index d907d9a2f..985958c5b 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -45,47 +45,47 @@ string tvpaths[] = '{ // *** make sure these are somewhere string coremark[] = '{ `COREMARK, - "coremark.bare.riscv", "100000" + "coremark.bare.riscv" }; string embench[] = '{ `EMBENCH, - "aha-mont64/aha-mont64", "1080", - "crc32/crc32", "1080", - "cubic/cubic", "9080", - "edn/edn", "1080", - "huffbench/huffbench", "5080", - "matmult-int/matmult-int", "1080", - "md5sum/md5sum", "4080", - "minver/minver", "2080", - "nbody/nbody", "2080", - "nettle-aes/nettle-aes", "1080", - "nettle-sha256/nettle-sha256", "2080", - "nsichneu/nsichneu", "4080", - "picojpeg/picojpeg", "3080", - "primecount/primecount", "1080", - "qrduino/qrduino", "6080", - "sglib-combined/sglib-combined", "5080", - "slre/slre", "1080", - "st/st", "2080", - "statemate/statemate", "2080", - "tarfind/tarfind", "4080", - "ud/ud", "1080", - "wikisort/wikisort", "3080" + "aha-mont64/aha-mont64", + "crc32/crc32", + "cubic/cubic", + "edn/edn", + "huffbench/huffbench", + "matmult-int/matmult-int", + "md5sum/md5sum", + "minver/minver", + "nbody/nbody", + "nettle-aes/nettle-aes", + "nettle-sha256/nettle-sha256", + "nsichneu/nsichneu", + "picojpeg/picojpeg", + "primecount/primecount", + "qrduino/qrduino", + "sglib-combined/sglib-combined", + "slre/slre", + "st/st", + "statemate/statemate", + "tarfind/tarfind", + "ud/ud", + "wikisort/wikisort" }; string wally64a[] = '{ `WALLYTEST, - "rv64i_m/privilege/WALLY-amo", "2210", - "rv64i_m/privilege/WALLY-lrsc", "2410", - "rv64i_m/privilege/WALLY-status-fp-enabled-01", "50a0" + "rv64i_m/privilege/WALLY-amo", + "rv64i_m/privilege/WALLY-lrsc", + "rv64i_m/privilege/WALLY-status-fp-enabled-01" }; string wally32a[] = '{ `WALLYTEST, - "rv32i_m/privilege/WALLY-amo", "2310", - "rv32i_m/privilege/WALLY-lrsc", "2310", - "rv32i_m/privilege/WALLY-status-fp-enabled-01", "5080" + "rv32i_m/privilege/WALLY-amo", + "rv32i_m/privilege/WALLY-lrsc", + "rv32i_m/privilege/WALLY-status-fp-enabled-01" }; @@ -93,1494 +93,1494 @@ string tvpaths[] = '{ string extra64i[] = '{ `MYIMPERASTEST, - "rv64i_m/I/WALLY-ADD", "4000", - "rv64i_m/I/WALLY-SUB", "4000", - "rv64i_m/I/WALLY-ADDI", "3000", - "rv64i_m/I/WALLY-ANDI", "3000", - "rv64i_m/I/WALLY-ORI", "3000", - "rv64i_m/I/WALLY-XORI", "3000", - "rv64i_m/I/WALLY-SLTI", "3000", - "rv64i_m/I/WALLY-SLTIU", "3000", - "rv64i_m/I/WALLY-SLLI", "3000", - "rv64i_m/I/WALLY-SRLI", "3000", - "rv64i_m/I/WALLY-SRAI", "3000", - "rv64i_m/I/WALLY-JAL", "4000", - "rv64i_m/I/WALLY-JALR", "3000", - "rv64i_m/I/WALLY-STORE", "3000", - "rv64i_m/I/WALLY-ADDIW", "3000", - "rv64i_m/I/WALLY-SLLIW", "3000", - "rv64i_m/I/WALLY-SRLIW", "3000", - "rv64i_m/I/WALLY-SRAIW", "3000", - "rv64i_m/I/WALLY-ADDW", "4000", - "rv64i_m/I/WALLY-SUBW", "4000", - "rv64i_m/I/WALLY-SLLW", "3000", - "rv64i_m/I/WALLY-SRLW", "3000", - "rv64i_m/I/WALLY-SRAW", "3000", - "rv64i_m/I/WALLY-BEQ" ,"5000", - "rv64i_m/I/WALLY-BNE", "5000 ", - "rv64i_m/I/WALLY-BLTU", "5000 ", - "rv64i_m/I/WALLY-BLT", "5000", - "rv64i_m/I/WALLY-BGE", "5000 ", - "rv64i_m/I/WALLY-BGEU", "5000 ", - "rv64i_m/I/WALLY-CSRRW", "4000", - "rv64i_m/I/WALLY-CSRRS", "4000", - "rv64i_m/I/WALLY-CSRRC", "5000", - "rv64i_m/I/WALLY-CSRRWI", "4000", - "rv64i_m/I/WALLY-CSRRSI", "4000", - "rv64i_m/I/WALLY-CSRRCI", "4000" + "rv64i_m/I/WALLY-ADD", + "rv64i_m/I/WALLY-SUB", + "rv64i_m/I/WALLY-ADDI", + "rv64i_m/I/WALLY-ANDI", + "rv64i_m/I/WALLY-ORI", + "rv64i_m/I/WALLY-XORI", + "rv64i_m/I/WALLY-SLTI", + "rv64i_m/I/WALLY-SLTIU", + "rv64i_m/I/WALLY-SLLI", + "rv64i_m/I/WALLY-SRLI", + "rv64i_m/I/WALLY-SRAI", + "rv64i_m/I/WALLY-JAL", + "rv64i_m/I/WALLY-JALR", + "rv64i_m/I/WALLY-STORE", + "rv64i_m/I/WALLY-ADDIW", + "rv64i_m/I/WALLY-SLLIW", + "rv64i_m/I/WALLY-SRLIW", + "rv64i_m/I/WALLY-SRAIW", + "rv64i_m/I/WALLY-ADDW", + "rv64i_m/I/WALLY-SUBW", + "rv64i_m/I/WALLY-SLLW", + "rv64i_m/I/WALLY-SRLW", + "rv64i_m/I/WALLY-SRAW", + "rv64i_m/I/WALLY-BEQ", + "rv64i_m/I/WALLY-BNE", + "rv64i_m/I/WALLY-BLTU", + "rv64i_m/I/WALLY-BLT", + "rv64i_m/I/WALLY-BGE", + "rv64i_m/I/WALLY-BGEU", + "rv64i_m/I/WALLY-CSRRW", + "rv64i_m/I/WALLY-CSRRS", + "rv64i_m/I/WALLY-CSRRC", + "rv64i_m/I/WALLY-CSRRWI", + "rv64i_m/I/WALLY-CSRRSI", + "rv64i_m/I/WALLY-CSRRCI" }; string imperas32f[] = '{ `IMPERASTEST, - "rv32i_m/F/FADD-S-DYN-RDN-01", "002010", - "rv32i_m/F/FADD-S-DYN-RMM-01", "002010", - "rv32i_m/F/FADD-S-DYN-RNE-01", "002010", - "rv32i_m/F/FADD-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FADD-S-DYN-RUP-01", "002010", - "rv32i_m/F/FADD-S-RDN-01", "002010", - "rv32i_m/F/FADD-S-RMM-01", "002010", - "rv32i_m/F/FADD-S-RNE-01", "002010", - "rv32i_m/F/FADD-S-RTZ-01", "002010", - "rv32i_m/F/FADD-S-RUP-01", "002010", - "rv32i_m/F/FCLASS-S-01", "002010", - "rv32i_m/F/FCVT-S-W-DYN-RDN-01", "002010", - "rv32i_m/F/FCVT-S-W-DYN-RMM-01", "002010", - "rv32i_m/F/FCVT-S-W-DYN-RNE-01", "002010", - "rv32i_m/F/FCVT-S-W-DYN-RTZ-01", "002010", - "rv32i_m/F/FCVT-S-W-DYN-RUP-01", "002010", - "rv32i_m/F/FCVT-S-W-RDN-01", "002010", - "rv32i_m/F/FCVT-S-W-RMM-01", "002010", - "rv32i_m/F/FCVT-S-W-RNE-01", "002010", - "rv32i_m/F/FCVT-S-W-RTZ-01", "002010", - "rv32i_m/F/FCVT-S-W-RUP-01", "002010", - "rv32i_m/F/FCVT-S-WU-DYN-RDN-01", "002010", - "rv32i_m/F/FCVT-S-WU-DYN-RMM-01", "002010", - "rv32i_m/F/FCVT-S-WU-DYN-RNE-01", "002010", - "rv32i_m/F/FCVT-S-WU-DYN-RTZ-01", "002010", - "rv32i_m/F/FCVT-S-WU-DYN-RUP-01", "002010", - "rv32i_m/F/FCVT-S-WU-RDN-01", "002010", - "rv32i_m/F/FCVT-S-WU-RMM-01", "002010", - "rv32i_m/F/FCVT-S-WU-RNE-01", "002010", - "rv32i_m/F/FCVT-S-WU-RTZ-01", "002010", - "rv32i_m/F/FCVT-S-WU-RUP-01", "002010", - "rv32i_m/F/FCVT-W-S-DYN-RDN-01", "002010", - "rv32i_m/F/FCVT-W-S-DYN-RMM-01", "002010", - "rv32i_m/F/FCVT-W-S-DYN-RNE-01", "002010", - "rv32i_m/F/FCVT-W-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FCVT-W-S-DYN-RUP-01", "002010", - "rv32i_m/F/FCVT-W-S-RDN-01", "002010", - "rv32i_m/F/FCVT-W-S-RMM-01", "002010", - "rv32i_m/F/FCVT-W-S-RNE-01", "002010", - "rv32i_m/F/FCVT-W-S-RTZ-01", "002010", - "rv32i_m/F/FCVT-W-S-RUP-01", "002010", - "rv32i_m/F/FCVT-WU-S-DYN-RDN-01", "002010", - "rv32i_m/F/FCVT-WU-S-DYN-RMM-01", "002010", - "rv32i_m/F/FCVT-WU-S-DYN-RNE-01", "002010", - "rv32i_m/F/FCVT-WU-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FCVT-WU-S-DYN-RUP-01", "002010", - "rv32i_m/F/FCVT-WU-S-RDN-01", "002010", - "rv32i_m/F/FCVT-WU-S-RMM-01", "002010", - "rv32i_m/F/FCVT-WU-S-RNE-01", "002010", - "rv32i_m/F/FCVT-WU-S-RTZ-01", "002010", - "rv32i_m/F/FCVT-WU-S-RUP-01", "002010", - // "rv32i_m/F/FDIV-S-DYN-RDN-01", "002010", - // "rv32i_m/F/FDIV-S-DYN-RMM-01", "002010", - // "rv32i_m/F/FDIV-S-DYN-RNE-01", "002010", - // "rv32i_m/F/FDIV-S-DYN-RTZ-01", "002010", - // "rv32i_m/F/FDIV-S-DYN-RUP-01", "002010", - // "rv32i_m/F/FDIV-S-RDN-01", "002010", - // "rv32i_m/F/FDIV-S-RMM-01", "002010", - // "rv32i_m/F/FDIV-S-RNE-01", "002010", - // "rv32i_m/F/FDIV-S-RTZ-01", "002010", - // "rv32i_m/F/FDIV-S-RUP-01", "002010", - "rv32i_m/F/FEQ-S-01", "002010", - "rv32i_m/F/FLE-S-01", "002010", - "rv32i_m/F/FLT-S-01", "002010", - "rv32i_m/F/FLW-01", "002120", - "rv32i_m/F/FMADD-S-DYN-RDN-01", "002010", - "rv32i_m/F/FMADD-S-DYN-RMM-01", "002010", - "rv32i_m/F/FMADD-S-DYN-RNE-01", "002010", - "rv32i_m/F/FMADD-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FMADD-S-DYN-RUP-01", "002010", - "rv32i_m/F/FMADD-S-RDN-01", "002010", - "rv32i_m/F/FMADD-S-RMM-01", "002010", - "rv32i_m/F/FMADD-S-RNE-01", "002010", - "rv32i_m/F/FMADD-S-RTZ-01", "002010", - "rv32i_m/F/FMADD-S-RUP-01", "002010", - "rv32i_m/F/FMAX-S-01", "002010", - "rv32i_m/F/FMIN-S-01", "002010", - "rv32i_m/F/FMSUB-S-DYN-RDN-01", "002010", - "rv32i_m/F/FMSUB-S-DYN-RMM-01", "002010", - "rv32i_m/F/FMSUB-S-DYN-RNE-01", "002010", - "rv32i_m/F/FMSUB-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FMSUB-S-DYN-RUP-01", "002010", - "rv32i_m/F/FMSUB-S-RDN-01", "002010", - "rv32i_m/F/FMSUB-S-RMM-01", "002010", - "rv32i_m/F/FMSUB-S-RNE-01", "002010", - "rv32i_m/F/FMSUB-S-RTZ-01", "002010", - "rv32i_m/F/FMSUB-S-RUP-01", "002010", - "rv32i_m/F/FMUL-S-DYN-RDN-01", "002010", - "rv32i_m/F/FMUL-S-DYN-RMM-01", "002010", - "rv32i_m/F/FMUL-S-DYN-RNE-01", "002010", - "rv32i_m/F/FMUL-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FMUL-S-DYN-RUP-01", "002010", - "rv32i_m/F/FMUL-S-RDN-01", "002010", - "rv32i_m/F/FMUL-S-RMM-01", "002010", - "rv32i_m/F/FMUL-S-RNE-01", "002010", - "rv32i_m/F/FMUL-S-RTZ-01", "002010", - "rv32i_m/F/FMUL-S-RUP-01", "002010", - "rv32i_m/F/FMV-W-X-01", "002010", - "rv32i_m/F/FMV-X-W-01", "002010", - "rv32i_m/F/FNMADD-S-DYN-RDN-01", "002010", - "rv32i_m/F/FNMADD-S-DYN-RMM-01", "002010", - "rv32i_m/F/FNMADD-S-DYN-RNE-01", "002010", - "rv32i_m/F/FNMADD-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FNMADD-S-DYN-RUP-01", "002010", - "rv32i_m/F/FNMADD-S-RDN-01", "002010", - "rv32i_m/F/FNMADD-S-RMM-01", "002010", - "rv32i_m/F/FNMADD-S-RNE-01", "002010", - "rv32i_m/F/FNMADD-S-RTZ-01", "002010", - "rv32i_m/F/FNMADD-S-RUP-01", "002010", - "rv32i_m/F/FNMSUB-S-DYN-RDN-01", "002010", - "rv32i_m/F/FNMSUB-S-DYN-RMM-01", "002010", - "rv32i_m/F/FNMSUB-S-DYN-RNE-01", "002010", - "rv32i_m/F/FNMSUB-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FNMSUB-S-DYN-RUP-01", "002010", - "rv32i_m/F/FNMSUB-S-RDN-01", "002010", - "rv32i_m/F/FNMSUB-S-RMM-01", "002010", - "rv32i_m/F/FNMSUB-S-RNE-01", "002010", - "rv32i_m/F/FNMSUB-S-RTZ-01", "002010", - "rv32i_m/F/FNMSUB-S-RUP-01", "002010", - "rv32i_m/F/FSGNJN-S-01", "002010", - "rv32i_m/F/FSGNJ-S-01", "002010", - "rv32i_m/F/FSGNJX-S-01", "002010", - // "rv32i_m/F/FSQRT-S-DYN-RDN-01", "002010", - // "rv32i_m/F/FSQRT-S-DYN-RMM-01", "002010", - // "rv32i_m/F/FSQRT-S-DYN-RNE-01", "002010", - // "rv32i_m/F/FSQRT-S-DYN-RTZ-01", "002010", - // "rv32i_m/F/FSQRT-S-DYN-RUP-01", "002010", - // "rv32i_m/F/FSQRT-S-RDN-01", "002010", - // "rv32i_m/F/FSQRT-S-RMM-01", "002010", - // "rv32i_m/F/FSQRT-S-RNE-01", "002010", - // "rv32i_m/F/FSQRT-S-RTZ-01", "002010", - // "rv32i_m/F/FSQRT-S-RUP-01", "002010", - "rv32i_m/F/FSUB-S-DYN-RDN-01", "002010", - "rv32i_m/F/FSUB-S-DYN-RMM-01", "002010", - "rv32i_m/F/FSUB-S-DYN-RNE-01", "002010", - "rv32i_m/F/FSUB-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FSUB-S-DYN-RUP-01", "002010", - "rv32i_m/F/FSUB-S-RDN-01", "002010", - "rv32i_m/F/FSUB-S-RMM-01", "002010", - "rv32i_m/F/FSUB-S-RNE-01", "002010", - "rv32i_m/F/FSUB-S-RTZ-01", "002010", - "rv32i_m/F/FSUB-S-RUP-01", "002010", - "rv32i_m/F/FSW-01", "002010" + "rv32i_m/F/FADD-S-DYN-RDN-01", + "rv32i_m/F/FADD-S-DYN-RMM-01", + "rv32i_m/F/FADD-S-DYN-RNE-01", + "rv32i_m/F/FADD-S-DYN-RTZ-01", + "rv32i_m/F/FADD-S-DYN-RUP-01", + "rv32i_m/F/FADD-S-RDN-01", + "rv32i_m/F/FADD-S-RMM-01", + "rv32i_m/F/FADD-S-RNE-01", + "rv32i_m/F/FADD-S-RTZ-01", + "rv32i_m/F/FADD-S-RUP-01", + "rv32i_m/F/FCLASS-S-01", + "rv32i_m/F/FCVT-S-W-DYN-RDN-01", + "rv32i_m/F/FCVT-S-W-DYN-RMM-01", + "rv32i_m/F/FCVT-S-W-DYN-RNE-01", + "rv32i_m/F/FCVT-S-W-DYN-RTZ-01", + "rv32i_m/F/FCVT-S-W-DYN-RUP-01", + "rv32i_m/F/FCVT-S-W-RDN-01", + "rv32i_m/F/FCVT-S-W-RMM-01", + "rv32i_m/F/FCVT-S-W-RNE-01", + "rv32i_m/F/FCVT-S-W-RTZ-01", + "rv32i_m/F/FCVT-S-W-RUP-01", + "rv32i_m/F/FCVT-S-WU-DYN-RDN-01", + "rv32i_m/F/FCVT-S-WU-DYN-RMM-01", + "rv32i_m/F/FCVT-S-WU-DYN-RNE-01", + "rv32i_m/F/FCVT-S-WU-DYN-RTZ-01", + "rv32i_m/F/FCVT-S-WU-DYN-RUP-01", + "rv32i_m/F/FCVT-S-WU-RDN-01", + "rv32i_m/F/FCVT-S-WU-RMM-01", + "rv32i_m/F/FCVT-S-WU-RNE-01", + "rv32i_m/F/FCVT-S-WU-RTZ-01", + "rv32i_m/F/FCVT-S-WU-RUP-01", + "rv32i_m/F/FCVT-W-S-DYN-RDN-01", + "rv32i_m/F/FCVT-W-S-DYN-RMM-01", + "rv32i_m/F/FCVT-W-S-DYN-RNE-01", + "rv32i_m/F/FCVT-W-S-DYN-RTZ-01", + "rv32i_m/F/FCVT-W-S-DYN-RUP-01", + "rv32i_m/F/FCVT-W-S-RDN-01", + "rv32i_m/F/FCVT-W-S-RMM-01", + "rv32i_m/F/FCVT-W-S-RNE-01", + "rv32i_m/F/FCVT-W-S-RTZ-01", + "rv32i_m/F/FCVT-W-S-RUP-01", + "rv32i_m/F/FCVT-WU-S-DYN-RDN-01", + "rv32i_m/F/FCVT-WU-S-DYN-RMM-01", + "rv32i_m/F/FCVT-WU-S-DYN-RNE-01", + "rv32i_m/F/FCVT-WU-S-DYN-RTZ-01", + "rv32i_m/F/FCVT-WU-S-DYN-RUP-01", + "rv32i_m/F/FCVT-WU-S-RDN-01", + "rv32i_m/F/FCVT-WU-S-RMM-01", + "rv32i_m/F/FCVT-WU-S-RNE-01", + "rv32i_m/F/FCVT-WU-S-RTZ-01", + "rv32i_m/F/FCVT-WU-S-RUP-01", + // "rv32i_m/F/FDIV-S-DYN-RDN-01", + // "rv32i_m/F/FDIV-S-DYN-RMM-01", + // "rv32i_m/F/FDIV-S-DYN-RNE-01", + // "rv32i_m/F/FDIV-S-DYN-RTZ-01", + // "rv32i_m/F/FDIV-S-DYN-RUP-01", + // "rv32i_m/F/FDIV-S-RDN-01", + // "rv32i_m/F/FDIV-S-RMM-01", + // "rv32i_m/F/FDIV-S-RNE-01", + // "rv32i_m/F/FDIV-S-RTZ-01", + // "rv32i_m/F/FDIV-S-RUP-01", + "rv32i_m/F/FEQ-S-01", + "rv32i_m/F/FLE-S-01", + "rv32i_m/F/FLT-S-01", + "rv32i_m/F/FLW-01", + "rv32i_m/F/FMADD-S-DYN-RDN-01", + "rv32i_m/F/FMADD-S-DYN-RMM-01", + "rv32i_m/F/FMADD-S-DYN-RNE-01", + "rv32i_m/F/FMADD-S-DYN-RTZ-01", + "rv32i_m/F/FMADD-S-DYN-RUP-01", + "rv32i_m/F/FMADD-S-RDN-01", + "rv32i_m/F/FMADD-S-RMM-01", + "rv32i_m/F/FMADD-S-RNE-01", + "rv32i_m/F/FMADD-S-RTZ-01", + "rv32i_m/F/FMADD-S-RUP-01", + "rv32i_m/F/FMAX-S-01", + "rv32i_m/F/FMIN-S-01", + "rv32i_m/F/FMSUB-S-DYN-RDN-01", + "rv32i_m/F/FMSUB-S-DYN-RMM-01", + "rv32i_m/F/FMSUB-S-DYN-RNE-01", + "rv32i_m/F/FMSUB-S-DYN-RTZ-01", + "rv32i_m/F/FMSUB-S-DYN-RUP-01", + "rv32i_m/F/FMSUB-S-RDN-01", + "rv32i_m/F/FMSUB-S-RMM-01", + "rv32i_m/F/FMSUB-S-RNE-01", + "rv32i_m/F/FMSUB-S-RTZ-01", + "rv32i_m/F/FMSUB-S-RUP-01", + "rv32i_m/F/FMUL-S-DYN-RDN-01", + "rv32i_m/F/FMUL-S-DYN-RMM-01", + "rv32i_m/F/FMUL-S-DYN-RNE-01", + "rv32i_m/F/FMUL-S-DYN-RTZ-01", + "rv32i_m/F/FMUL-S-DYN-RUP-01", + "rv32i_m/F/FMUL-S-RDN-01", + "rv32i_m/F/FMUL-S-RMM-01", + "rv32i_m/F/FMUL-S-RNE-01", + "rv32i_m/F/FMUL-S-RTZ-01", + "rv32i_m/F/FMUL-S-RUP-01", + "rv32i_m/F/FMV-W-X-01", + "rv32i_m/F/FMV-X-W-01", + "rv32i_m/F/FNMADD-S-DYN-RDN-01", + "rv32i_m/F/FNMADD-S-DYN-RMM-01", + "rv32i_m/F/FNMADD-S-DYN-RNE-01", + "rv32i_m/F/FNMADD-S-DYN-RTZ-01", + "rv32i_m/F/FNMADD-S-DYN-RUP-01", + "rv32i_m/F/FNMADD-S-RDN-01", + "rv32i_m/F/FNMADD-S-RMM-01", + "rv32i_m/F/FNMADD-S-RNE-01", + "rv32i_m/F/FNMADD-S-RTZ-01", + "rv32i_m/F/FNMADD-S-RUP-01", + "rv32i_m/F/FNMSUB-S-DYN-RDN-01", + "rv32i_m/F/FNMSUB-S-DYN-RMM-01", + "rv32i_m/F/FNMSUB-S-DYN-RNE-01", + "rv32i_m/F/FNMSUB-S-DYN-RTZ-01", + "rv32i_m/F/FNMSUB-S-DYN-RUP-01", + "rv32i_m/F/FNMSUB-S-RDN-01", + "rv32i_m/F/FNMSUB-S-RMM-01", + "rv32i_m/F/FNMSUB-S-RNE-01", + "rv32i_m/F/FNMSUB-S-RTZ-01", + "rv32i_m/F/FNMSUB-S-RUP-01", + "rv32i_m/F/FSGNJN-S-01", + "rv32i_m/F/FSGNJ-S-01", + "rv32i_m/F/FSGNJX-S-01", + // "rv32i_m/F/FSQRT-S-DYN-RDN-01", + // "rv32i_m/F/FSQRT-S-DYN-RMM-01", + // "rv32i_m/F/FSQRT-S-DYN-RNE-01", + // "rv32i_m/F/FSQRT-S-DYN-RTZ-01", + // "rv32i_m/F/FSQRT-S-DYN-RUP-01", + // "rv32i_m/F/FSQRT-S-RDN-01", + // "rv32i_m/F/FSQRT-S-RMM-01", + // "rv32i_m/F/FSQRT-S-RNE-01", + // "rv32i_m/F/FSQRT-S-RTZ-01", + // "rv32i_m/F/FSQRT-S-RUP-01", + "rv32i_m/F/FSUB-S-DYN-RDN-01", + "rv32i_m/F/FSUB-S-DYN-RMM-01", + "rv32i_m/F/FSUB-S-DYN-RNE-01", + "rv32i_m/F/FSUB-S-DYN-RTZ-01", + "rv32i_m/F/FSUB-S-DYN-RUP-01", + "rv32i_m/F/FSUB-S-RDN-01", + "rv32i_m/F/FSUB-S-RMM-01", + "rv32i_m/F/FSUB-S-RNE-01", + "rv32i_m/F/FSUB-S-RTZ-01", + "rv32i_m/F/FSUB-S-RUP-01", + "rv32i_m/F/FSW-01" }; string imperas64f[] = '{ `IMPERASTEST, - "rv64i_m/F/FADD-S-DYN-RDN-01", "002010", - "rv64i_m/F/FADD-S-DYN-RMM-01", "002010", - "rv64i_m/F/FADD-S-DYN-RNE-01", "002010", - "rv64i_m/F/FADD-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FADD-S-DYN-RUP-01", "002010", - "rv64i_m/F/FADD-S-RDN-01", "002010", - "rv64i_m/F/FADD-S-RMM-01", "002010", - "rv64i_m/F/FADD-S-RNE-01", "002010", - "rv64i_m/F/FADD-S-RTZ-01", "002010", - "rv64i_m/F/FADD-S-RUP-01", "002010", - "rv64i_m/F/FCLASS-S-01", "002010", - "rv64i_m/F/FCVT-L-S-DYN-RDN-01", "002010", - "rv64i_m/F/FCVT-L-S-DYN-RMM-01", "002010", - "rv64i_m/F/FCVT-L-S-DYN-RNE-01", "002010", - "rv64i_m/F/FCVT-L-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FCVT-L-S-DYN-RUP-01", "002010", - "rv64i_m/F/FCVT-L-S-RDN-01", "002010", - "rv64i_m/F/FCVT-L-S-RMM-01", "002010", - "rv64i_m/F/FCVT-L-S-RNE-01", "002010", - "rv64i_m/F/FCVT-L-S-RTZ-01", "002010", - "rv64i_m/F/FCVT-L-S-RUP-01", "002010", - "rv64i_m/F/FCVT-LU-S-DYN-RDN-01", "002010", - "rv64i_m/F/FCVT-LU-S-DYN-RMM-01", "002010", - "rv64i_m/F/FCVT-LU-S-DYN-RNE-01", "002010", - "rv64i_m/F/FCVT-LU-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FCVT-LU-S-DYN-RUP-01", "002010", - "rv64i_m/F/FCVT-LU-S-RDN-01", "002010", - "rv64i_m/F/FCVT-LU-S-RMM-01", "002010", - "rv64i_m/F/FCVT-LU-S-RNE-01", "002010", - "rv64i_m/F/FCVT-LU-S-RTZ-01", "002010", - "rv64i_m/F/FCVT-LU-S-RUP-01", "002010", - "rv64i_m/F/FCVT-S-L-DYN-RDN-01", "002010", - "rv64i_m/F/FCVT-S-L-DYN-RMM-01", "002010", - "rv64i_m/F/FCVT-S-L-DYN-RNE-01", "002010", - "rv64i_m/F/FCVT-S-L-DYN-RTZ-01", "002010", - "rv64i_m/F/FCVT-S-L-DYN-RUP-01", "002010", - "rv64i_m/F/FCVT-S-L-RDN-01", "002010", - "rv64i_m/F/FCVT-S-L-RMM-01", "002010", - "rv64i_m/F/FCVT-S-L-RNE-01", "002010", - "rv64i_m/F/FCVT-S-L-RTZ-01", "002010", - "rv64i_m/F/FCVT-S-L-RUP-01", "002010", - "rv64i_m/F/FCVT-S-LU-DYN-RDN-01", "002010", - "rv64i_m/F/FCVT-S-LU-DYN-RMM-01", "002010", - "rv64i_m/F/FCVT-S-LU-DYN-RNE-01", "002010", - "rv64i_m/F/FCVT-S-LU-DYN-RTZ-01", "002010", - "rv64i_m/F/FCVT-S-LU-DYN-RUP-01", "002010", - "rv64i_m/F/FCVT-S-LU-RDN-01", "002010", - "rv64i_m/F/FCVT-S-LU-RMM-01", "002010", - "rv64i_m/F/FCVT-S-LU-RNE-01", "002010", - "rv64i_m/F/FCVT-S-LU-RTZ-01", "002010", - "rv64i_m/F/FCVT-S-LU-RUP-01", "002010", - "rv64i_m/F/FCVT-S-W-DYN-RDN-01", "002010", - "rv64i_m/F/FCVT-S-W-DYN-RMM-01", "002010", - "rv64i_m/F/FCVT-S-W-DYN-RNE-01", "002010", - "rv64i_m/F/FCVT-S-W-DYN-RTZ-01", "002010", - "rv64i_m/F/FCVT-S-W-DYN-RUP-01", "002010", - "rv64i_m/F/FCVT-S-W-RDN-01", "002010", - "rv64i_m/F/FCVT-S-W-RMM-01", "002010", - "rv64i_m/F/FCVT-S-W-RNE-01", "002010", - "rv64i_m/F/FCVT-S-W-RTZ-01", "002010", - "rv64i_m/F/FCVT-S-W-RUP-01", "002010", - "rv64i_m/F/FCVT-S-WU-DYN-RDN-01", "002010", - "rv64i_m/F/FCVT-S-WU-DYN-RMM-01", "002010", - "rv64i_m/F/FCVT-S-WU-DYN-RNE-01", "002010", - "rv64i_m/F/FCVT-S-WU-DYN-RTZ-01", "002010", - "rv64i_m/F/FCVT-S-WU-DYN-RUP-01", "002010", - "rv64i_m/F/FCVT-S-WU-RDN-01", "002010", - "rv64i_m/F/FCVT-S-WU-RMM-01", "002010", - "rv64i_m/F/FCVT-S-WU-RNE-01", "002010", - "rv64i_m/F/FCVT-S-WU-RTZ-01", "002010", - "rv64i_m/F/FCVT-S-WU-RUP-01", "002010", - "rv64i_m/F/FCVT-W-S-DYN-RDN-01", "002010", - "rv64i_m/F/FCVT-W-S-DYN-RMM-01", "002010", - "rv64i_m/F/FCVT-W-S-DYN-RNE-01", "002010", - "rv64i_m/F/FCVT-W-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FCVT-W-S-DYN-RUP-01", "002010", - "rv64i_m/F/FCVT-W-S-RDN-01", "002010", - "rv64i_m/F/FCVT-W-S-RMM-01", "002010", - "rv64i_m/F/FCVT-W-S-RNE-01", "002010", - "rv64i_m/F/FCVT-W-S-RTZ-01", "002010", - "rv64i_m/F/FCVT-W-S-RUP-01", "002010", - "rv64i_m/F/FCVT-WU-S-DYN-RDN-01", "002010", - "rv64i_m/F/FCVT-WU-S-DYN-RMM-01", "002010", - "rv64i_m/F/FCVT-WU-S-DYN-RNE-01", "002010", - "rv64i_m/F/FCVT-WU-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FCVT-WU-S-DYN-RUP-01", "002010", - "rv64i_m/F/FCVT-WU-S-RDN-01", "002010", - "rv64i_m/F/FCVT-WU-S-RMM-01", "002010", - "rv64i_m/F/FCVT-WU-S-RNE-01", "002010", - "rv64i_m/F/FCVT-WU-S-RTZ-01", "002010", - "rv64i_m/F/FCVT-WU-S-RUP-01", "002010", - // "rv64i_m/F/FDIV-S-DYN-RDN-01", "002010", - // "rv64i_m/F/FDIV-S-DYN-RMM-01", "002010", - // "rv64i_m/F/FDIV-S-DYN-RNE-01", "002010", - // "rv64i_m/F/FDIV-S-DYN-RTZ-01", "002010", - // "rv64i_m/F/FDIV-S-DYN-RUP-01", "002010", - // "rv64i_m/F/FDIV-S-RDN-01", "002010", - // "rv64i_m/F/FDIV-S-RMM-01", "002010", - // "rv64i_m/F/FDIV-S-RNE-01", "002010", - // "rv64i_m/F/FDIV-S-RTZ-01", "002010", - // "rv64i_m/F/FDIV-S-RUP-01", "002010", - "rv64i_m/F/FEQ-S-01", "002010", - "rv64i_m/F/FLE-S-01", "002010", - "rv64i_m/F/FLT-S-01", "002010", - "rv64i_m/F/FLW-01", "002210", - "rv64i_m/F/FMADD-S-DYN-RDN-01", "002010", - "rv64i_m/F/FMADD-S-DYN-RMM-01", "002010", - "rv64i_m/F/FMADD-S-DYN-RNE-01", "002010", - "rv64i_m/F/FMADD-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FMADD-S-DYN-RUP-01", "002010", - "rv64i_m/F/FMADD-S-RDN-01", "002010", - "rv64i_m/F/FMADD-S-RMM-01", "002010", - "rv64i_m/F/FMADD-S-RNE-01", "002010", - "rv64i_m/F/FMADD-S-RTZ-01", "002010", - "rv64i_m/F/FMADD-S-RUP-01", "002010", - "rv64i_m/F/FMAX-S-01", "002010", - "rv64i_m/F/FMIN-S-01", "002010", - "rv64i_m/F/FMSUB-S-DYN-RDN-01", "002010", - "rv64i_m/F/FMSUB-S-DYN-RMM-01", "002010", - "rv64i_m/F/FMSUB-S-DYN-RNE-01", "002010", - "rv64i_m/F/FMSUB-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FMSUB-S-DYN-RUP-01", "002010", - "rv64i_m/F/FMSUB-S-RDN-01", "002010", - "rv64i_m/F/FMSUB-S-RMM-01", "002010", - "rv64i_m/F/FMSUB-S-RNE-01", "002010", - "rv64i_m/F/FMSUB-S-RTZ-01", "002010", - "rv64i_m/F/FMSUB-S-RUP-01", "002010", - "rv64i_m/F/FMUL-S-DYN-RDN-01", "002010", - "rv64i_m/F/FMUL-S-DYN-RMM-01", "002010", - "rv64i_m/F/FMUL-S-DYN-RNE-01", "002010", - "rv64i_m/F/FMUL-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FMUL-S-DYN-RUP-01", "002010", - "rv64i_m/F/FMUL-S-RDN-01", "002010", - "rv64i_m/F/FMUL-S-RMM-01", "002010", - "rv64i_m/F/FMUL-S-RNE-01", "002010", - "rv64i_m/F/FMUL-S-RTZ-01", "002010", - "rv64i_m/F/FMUL-S-RUP-01", "002010", - "rv64i_m/F/FMV-W-X-01", "002010", - "rv64i_m/F/FMV-X-W-01", "002010", - "rv64i_m/F/FNMADD-S-DYN-RDN-01", "002010", - "rv64i_m/F/FNMADD-S-DYN-RMM-01", "002010", - "rv64i_m/F/FNMADD-S-DYN-RNE-01", "002010", - "rv64i_m/F/FNMADD-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FNMADD-S-DYN-RUP-01", "002010", - "rv64i_m/F/FNMADD-S-RDN-01", "002010", - "rv64i_m/F/FNMADD-S-RMM-01", "002010", - "rv64i_m/F/FNMADD-S-RNE-01", "002010", - "rv64i_m/F/FNMADD-S-RTZ-01", "002010", - "rv64i_m/F/FNMADD-S-RUP-01", "002010", - "rv64i_m/F/FNMSUB-S-DYN-RDN-01", "002010", - "rv64i_m/F/FNMSUB-S-DYN-RMM-01", "002010", - "rv64i_m/F/FNMSUB-S-DYN-RNE-01", "002010", - "rv64i_m/F/FNMSUB-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FNMSUB-S-DYN-RUP-01", "002010", - "rv64i_m/F/FNMSUB-S-RDN-01", "002010", - "rv64i_m/F/FNMSUB-S-RMM-01", "002010", - "rv64i_m/F/FNMSUB-S-RNE-01", "002010", - "rv64i_m/F/FNMSUB-S-RTZ-01", "002010", - "rv64i_m/F/FNMSUB-S-RUP-01", "002010", - "rv64i_m/F/FSGNJN-S-01", "002010", - "rv64i_m/F/FSGNJ-S-01", "002010", - "rv64i_m/F/FSGNJX-S-01", "002010", - // "rv64i_m/F/FSQRT-S-DYN-RDN-01", "002010", - // "rv64i_m/F/FSQRT-S-DYN-RMM-01", "002010", - // "rv64i_m/F/FSQRT-S-DYN-RNE-01", "002010", - // "rv64i_m/F/FSQRT-S-DYN-RTZ-01", "002010", - // "rv64i_m/F/FSQRT-S-DYN-RUP-01", "002010", - // "rv64i_m/F/FSQRT-S-RDN-01", "002010", - // "rv64i_m/F/FSQRT-S-RMM-01", "002010", - // "rv64i_m/F/FSQRT-S-RNE-01", "002010", - // "rv64i_m/F/FSQRT-S-RTZ-01", "002010", - // "rv64i_m/F/FSQRT-S-RUP-01", "002010", - "rv64i_m/F/FSUB-S-DYN-RDN-01", "002010", - "rv64i_m/F/FSUB-S-DYN-RMM-01", "002010", - "rv64i_m/F/FSUB-S-DYN-RNE-01", "002010", - "rv64i_m/F/FSUB-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FSUB-S-DYN-RUP-01", "002010", - "rv64i_m/F/FSUB-S-RDN-01", "002010", - "rv64i_m/F/FSUB-S-RMM-01", "002010", - "rv64i_m/F/FSUB-S-RNE-01", "002010", - "rv64i_m/F/FSUB-S-RTZ-01", "002010", - "rv64i_m/F/FSUB-S-RUP-01", "002010", - "rv64i_m/F/FSW-01", "002010" + "rv64i_m/F/FADD-S-DYN-RDN-01", + "rv64i_m/F/FADD-S-DYN-RMM-01", + "rv64i_m/F/FADD-S-DYN-RNE-01", + "rv64i_m/F/FADD-S-DYN-RTZ-01", + "rv64i_m/F/FADD-S-DYN-RUP-01", + "rv64i_m/F/FADD-S-RDN-01", + "rv64i_m/F/FADD-S-RMM-01", + "rv64i_m/F/FADD-S-RNE-01", + "rv64i_m/F/FADD-S-RTZ-01", + "rv64i_m/F/FADD-S-RUP-01", + "rv64i_m/F/FCLASS-S-01", + "rv64i_m/F/FCVT-L-S-DYN-RDN-01", + "rv64i_m/F/FCVT-L-S-DYN-RMM-01", + "rv64i_m/F/FCVT-L-S-DYN-RNE-01", + "rv64i_m/F/FCVT-L-S-DYN-RTZ-01", + "rv64i_m/F/FCVT-L-S-DYN-RUP-01", + "rv64i_m/F/FCVT-L-S-RDN-01", + "rv64i_m/F/FCVT-L-S-RMM-01", + "rv64i_m/F/FCVT-L-S-RNE-01", + "rv64i_m/F/FCVT-L-S-RTZ-01", + "rv64i_m/F/FCVT-L-S-RUP-01", + "rv64i_m/F/FCVT-LU-S-DYN-RDN-01", + "rv64i_m/F/FCVT-LU-S-DYN-RMM-01", + "rv64i_m/F/FCVT-LU-S-DYN-RNE-01", + "rv64i_m/F/FCVT-LU-S-DYN-RTZ-01", + "rv64i_m/F/FCVT-LU-S-DYN-RUP-01", + "rv64i_m/F/FCVT-LU-S-RDN-01", + "rv64i_m/F/FCVT-LU-S-RMM-01", + "rv64i_m/F/FCVT-LU-S-RNE-01", + "rv64i_m/F/FCVT-LU-S-RTZ-01", + "rv64i_m/F/FCVT-LU-S-RUP-01", + "rv64i_m/F/FCVT-S-L-DYN-RDN-01", + "rv64i_m/F/FCVT-S-L-DYN-RMM-01", + "rv64i_m/F/FCVT-S-L-DYN-RNE-01", + "rv64i_m/F/FCVT-S-L-DYN-RTZ-01", + "rv64i_m/F/FCVT-S-L-DYN-RUP-01", + "rv64i_m/F/FCVT-S-L-RDN-01", + "rv64i_m/F/FCVT-S-L-RMM-01", + "rv64i_m/F/FCVT-S-L-RNE-01", + "rv64i_m/F/FCVT-S-L-RTZ-01", + "rv64i_m/F/FCVT-S-L-RUP-01", + "rv64i_m/F/FCVT-S-LU-DYN-RDN-01", + "rv64i_m/F/FCVT-S-LU-DYN-RMM-01", + "rv64i_m/F/FCVT-S-LU-DYN-RNE-01", + "rv64i_m/F/FCVT-S-LU-DYN-RTZ-01", + "rv64i_m/F/FCVT-S-LU-DYN-RUP-01", + "rv64i_m/F/FCVT-S-LU-RDN-01", + "rv64i_m/F/FCVT-S-LU-RMM-01", + "rv64i_m/F/FCVT-S-LU-RNE-01", + "rv64i_m/F/FCVT-S-LU-RTZ-01", + "rv64i_m/F/FCVT-S-LU-RUP-01", + "rv64i_m/F/FCVT-S-W-DYN-RDN-01", + "rv64i_m/F/FCVT-S-W-DYN-RMM-01", + "rv64i_m/F/FCVT-S-W-DYN-RNE-01", + "rv64i_m/F/FCVT-S-W-DYN-RTZ-01", + "rv64i_m/F/FCVT-S-W-DYN-RUP-01", + "rv64i_m/F/FCVT-S-W-RDN-01", + "rv64i_m/F/FCVT-S-W-RMM-01", + "rv64i_m/F/FCVT-S-W-RNE-01", + "rv64i_m/F/FCVT-S-W-RTZ-01", + "rv64i_m/F/FCVT-S-W-RUP-01", + "rv64i_m/F/FCVT-S-WU-DYN-RDN-01", + "rv64i_m/F/FCVT-S-WU-DYN-RMM-01", + "rv64i_m/F/FCVT-S-WU-DYN-RNE-01", + "rv64i_m/F/FCVT-S-WU-DYN-RTZ-01", + "rv64i_m/F/FCVT-S-WU-DYN-RUP-01", + "rv64i_m/F/FCVT-S-WU-RDN-01", + "rv64i_m/F/FCVT-S-WU-RMM-01", + "rv64i_m/F/FCVT-S-WU-RNE-01", + "rv64i_m/F/FCVT-S-WU-RTZ-01", + "rv64i_m/F/FCVT-S-WU-RUP-01", + "rv64i_m/F/FCVT-W-S-DYN-RDN-01", + "rv64i_m/F/FCVT-W-S-DYN-RMM-01", + "rv64i_m/F/FCVT-W-S-DYN-RNE-01", + "rv64i_m/F/FCVT-W-S-DYN-RTZ-01", + "rv64i_m/F/FCVT-W-S-DYN-RUP-01", + "rv64i_m/F/FCVT-W-S-RDN-01", + "rv64i_m/F/FCVT-W-S-RMM-01", + "rv64i_m/F/FCVT-W-S-RNE-01", + "rv64i_m/F/FCVT-W-S-RTZ-01", + "rv64i_m/F/FCVT-W-S-RUP-01", + "rv64i_m/F/FCVT-WU-S-DYN-RDN-01", + "rv64i_m/F/FCVT-WU-S-DYN-RMM-01", + "rv64i_m/F/FCVT-WU-S-DYN-RNE-01", + "rv64i_m/F/FCVT-WU-S-DYN-RTZ-01", + "rv64i_m/F/FCVT-WU-S-DYN-RUP-01", + "rv64i_m/F/FCVT-WU-S-RDN-01", + "rv64i_m/F/FCVT-WU-S-RMM-01", + "rv64i_m/F/FCVT-WU-S-RNE-01", + "rv64i_m/F/FCVT-WU-S-RTZ-01", + "rv64i_m/F/FCVT-WU-S-RUP-01", + // "rv64i_m/F/FDIV-S-DYN-RDN-01", + // "rv64i_m/F/FDIV-S-DYN-RMM-01", + // "rv64i_m/F/FDIV-S-DYN-RNE-01", + // "rv64i_m/F/FDIV-S-DYN-RTZ-01", + // "rv64i_m/F/FDIV-S-DYN-RUP-01", + // "rv64i_m/F/FDIV-S-RDN-01", + // "rv64i_m/F/FDIV-S-RMM-01", + // "rv64i_m/F/FDIV-S-RNE-01", + // "rv64i_m/F/FDIV-S-RTZ-01", + // "rv64i_m/F/FDIV-S-RUP-01", + "rv64i_m/F/FEQ-S-01", + "rv64i_m/F/FLE-S-01", + "rv64i_m/F/FLT-S-01", + "rv64i_m/F/FLW-01", + "rv64i_m/F/FMADD-S-DYN-RDN-01", + "rv64i_m/F/FMADD-S-DYN-RMM-01", + "rv64i_m/F/FMADD-S-DYN-RNE-01", + "rv64i_m/F/FMADD-S-DYN-RTZ-01", + "rv64i_m/F/FMADD-S-DYN-RUP-01", + "rv64i_m/F/FMADD-S-RDN-01", + "rv64i_m/F/FMADD-S-RMM-01", + "rv64i_m/F/FMADD-S-RNE-01", + "rv64i_m/F/FMADD-S-RTZ-01", + "rv64i_m/F/FMADD-S-RUP-01", + "rv64i_m/F/FMAX-S-01", + "rv64i_m/F/FMIN-S-01", + "rv64i_m/F/FMSUB-S-DYN-RDN-01", + "rv64i_m/F/FMSUB-S-DYN-RMM-01", + "rv64i_m/F/FMSUB-S-DYN-RNE-01", + "rv64i_m/F/FMSUB-S-DYN-RTZ-01", + "rv64i_m/F/FMSUB-S-DYN-RUP-01", + "rv64i_m/F/FMSUB-S-RDN-01", + "rv64i_m/F/FMSUB-S-RMM-01", + "rv64i_m/F/FMSUB-S-RNE-01", + "rv64i_m/F/FMSUB-S-RTZ-01", + "rv64i_m/F/FMSUB-S-RUP-01", + "rv64i_m/F/FMUL-S-DYN-RDN-01", + "rv64i_m/F/FMUL-S-DYN-RMM-01", + "rv64i_m/F/FMUL-S-DYN-RNE-01", + "rv64i_m/F/FMUL-S-DYN-RTZ-01", + "rv64i_m/F/FMUL-S-DYN-RUP-01", + "rv64i_m/F/FMUL-S-RDN-01", + "rv64i_m/F/FMUL-S-RMM-01", + "rv64i_m/F/FMUL-S-RNE-01", + "rv64i_m/F/FMUL-S-RTZ-01", + "rv64i_m/F/FMUL-S-RUP-01", + "rv64i_m/F/FMV-W-X-01", + "rv64i_m/F/FMV-X-W-01", + "rv64i_m/F/FNMADD-S-DYN-RDN-01", + "rv64i_m/F/FNMADD-S-DYN-RMM-01", + "rv64i_m/F/FNMADD-S-DYN-RNE-01", + "rv64i_m/F/FNMADD-S-DYN-RTZ-01", + "rv64i_m/F/FNMADD-S-DYN-RUP-01", + "rv64i_m/F/FNMADD-S-RDN-01", + "rv64i_m/F/FNMADD-S-RMM-01", + "rv64i_m/F/FNMADD-S-RNE-01", + "rv64i_m/F/FNMADD-S-RTZ-01", + "rv64i_m/F/FNMADD-S-RUP-01", + "rv64i_m/F/FNMSUB-S-DYN-RDN-01", + "rv64i_m/F/FNMSUB-S-DYN-RMM-01", + "rv64i_m/F/FNMSUB-S-DYN-RNE-01", + "rv64i_m/F/FNMSUB-S-DYN-RTZ-01", + "rv64i_m/F/FNMSUB-S-DYN-RUP-01", + "rv64i_m/F/FNMSUB-S-RDN-01", + "rv64i_m/F/FNMSUB-S-RMM-01", + "rv64i_m/F/FNMSUB-S-RNE-01", + "rv64i_m/F/FNMSUB-S-RTZ-01", + "rv64i_m/F/FNMSUB-S-RUP-01", + "rv64i_m/F/FSGNJN-S-01", + "rv64i_m/F/FSGNJ-S-01", + "rv64i_m/F/FSGNJX-S-01", + // "rv64i_m/F/FSQRT-S-DYN-RDN-01", + // "rv64i_m/F/FSQRT-S-DYN-RMM-01", + // "rv64i_m/F/FSQRT-S-DYN-RNE-01", + // "rv64i_m/F/FSQRT-S-DYN-RTZ-01", + // "rv64i_m/F/FSQRT-S-DYN-RUP-01", + // "rv64i_m/F/FSQRT-S-RDN-01", + // "rv64i_m/F/FSQRT-S-RMM-01", + // "rv64i_m/F/FSQRT-S-RNE-01", + // "rv64i_m/F/FSQRT-S-RTZ-01", + // "rv64i_m/F/FSQRT-S-RUP-01", + "rv64i_m/F/FSUB-S-DYN-RDN-01", + "rv64i_m/F/FSUB-S-DYN-RMM-01", + "rv64i_m/F/FSUB-S-DYN-RNE-01", + "rv64i_m/F/FSUB-S-DYN-RTZ-01", + "rv64i_m/F/FSUB-S-DYN-RUP-01", + "rv64i_m/F/FSUB-S-RDN-01", + "rv64i_m/F/FSUB-S-RMM-01", + "rv64i_m/F/FSUB-S-RNE-01", + "rv64i_m/F/FSUB-S-RTZ-01", + "rv64i_m/F/FSUB-S-RUP-01", + "rv64i_m/F/FSW-01" }; string imperas64d[] = '{ `IMPERASTEST, - "rv64i_m/D/FADD-D-DYN-RDN-01", "002010", - "rv64i_m/D/FADD-D-DYN-RMM-01", "002010", - "rv64i_m/D/FADD-D-DYN-RNE-01", "002010", - "rv64i_m/D/FADD-D-DYN-RTZ-01", "002010", - "rv64i_m/D/FADD-D-DYN-RUP-01", "002010", - "rv64i_m/D/FADD-D-RDN-01", "002010", - "rv64i_m/D/FADD-D-RMM-01", "002010", - "rv64i_m/D/FADD-D-RNE-01", "002010", - "rv64i_m/D/FADD-D-RTZ-01", "002010", - "rv64i_m/D/FADD-D-RUP-01", "002010", - "rv64i_m/D/FCLASS-D-01", "002010", - "rv64i_m/D/FCVT-D-L-DYN-RDN-01", "002010", - "rv64i_m/D/FCVT-D-L-DYN-RMM-01", "002010", - "rv64i_m/D/FCVT-D-L-DYN-RNE-01", "002010", - "rv64i_m/D/FCVT-D-L-DYN-RTZ-01", "002010", - "rv64i_m/D/FCVT-D-L-DYN-RUP-01", "002010", - "rv64i_m/D/FCVT-D-L-RDN-01", "002010", - "rv64i_m/D/FCVT-D-L-RMM-01", "002010", - "rv64i_m/D/FCVT-D-L-RNE-01", "002010", - "rv64i_m/D/FCVT-D-L-RTZ-01", "002010", - "rv64i_m/D/FCVT-D-L-RUP-01", "002010", - "rv64i_m/D/FCVT-D-LU-DYN-RDN-01", "002010", - "rv64i_m/D/FCVT-D-LU-DYN-RMM-01", "002010", - "rv64i_m/D/FCVT-D-LU-DYN-RNE-01", "002010", - "rv64i_m/D/FCVT-D-LU-DYN-RTZ-01", "002010", - "rv64i_m/D/FCVT-D-LU-DYN-RUP-01", "002010", - "rv64i_m/D/FCVT-D-LU-RDN-01", "002010", - "rv64i_m/D/FCVT-D-LU-RMM-01", "002010", - "rv64i_m/D/FCVT-D-LU-RNE-01", "002010", - "rv64i_m/D/FCVT-D-LU-RTZ-01", "002010", - "rv64i_m/D/FCVT-D-LU-RUP-01", "002010", - "rv64i_m/D/FCVT-D-S-01", "002010", - "rv64i_m/D/FCVT-D-W-01", "002010", - "rv64i_m/D/FCVT-D-WU-01", "002010", - "rv64i_m/D/FCVT-L-D-DYN-RDN-01", "002010", - "rv64i_m/D/FCVT-L-D-DYN-RMM-01", "002010", - "rv64i_m/D/FCVT-L-D-DYN-RNE-01", "002010", - "rv64i_m/D/FCVT-L-D-DYN-RTZ-01", "002010", - "rv64i_m/D/FCVT-L-D-DYN-RUP-01", "002010", - "rv64i_m/D/FCVT-L-D-RDN-01", "002010", - "rv64i_m/D/FCVT-L-D-RMM-01", "002010", - "rv64i_m/D/FCVT-L-D-RNE-01", "002010", - "rv64i_m/D/FCVT-L-D-RTZ-01", "002010", - "rv64i_m/D/FCVT-L-D-RUP-01", "002010", - "rv64i_m/D/FCVT-LU-D-DYN-RDN-01", "002010", - "rv64i_m/D/FCVT-LU-D-DYN-RMM-01", "002010", - "rv64i_m/D/FCVT-LU-D-DYN-RNE-01", "002010", - "rv64i_m/D/FCVT-LU-D-DYN-RTZ-01", "002010", - "rv64i_m/D/FCVT-LU-D-DYN-RUP-01", "002010", - "rv64i_m/D/FCVT-LU-D-RDN-01", "002010", - "rv64i_m/D/FCVT-LU-D-RMM-01", "002010", - "rv64i_m/D/FCVT-LU-D-RNE-01", "002010", - "rv64i_m/D/FCVT-LU-D-RTZ-01", "002010", - "rv64i_m/D/FCVT-LU-D-RUP-01", "002010", - "rv64i_m/D/FCVT-S-D-DYN-RDN-01", "002010", - "rv64i_m/D/FCVT-S-D-DYN-RMM-01", "002010", - "rv64i_m/D/FCVT-S-D-DYN-RNE-01", "002010", - "rv64i_m/D/FCVT-S-D-DYN-RTZ-01", "002010", - "rv64i_m/D/FCVT-S-D-DYN-RUP-01", "002010", - "rv64i_m/D/FCVT-S-D-RDN-01", "002010", - "rv64i_m/D/FCVT-S-D-RMM-01", "002010", - "rv64i_m/D/FCVT-S-D-RNE-01", "002010", - "rv64i_m/D/FCVT-S-D-RTZ-01", "002010", - "rv64i_m/D/FCVT-S-D-RUP-01", "002010", - "rv64i_m/D/FCVT-W-D-DYN-RDN-01", "002010", - "rv64i_m/D/FCVT-W-D-DYN-RMM-01", "002010", - "rv64i_m/D/FCVT-W-D-DYN-RNE-01", "002010", - "rv64i_m/D/FCVT-W-D-DYN-RTZ-01", "002010", - "rv64i_m/D/FCVT-W-D-DYN-RUP-01", "002010", - "rv64i_m/D/FCVT-W-D-RDN-01", "002010", - "rv64i_m/D/FCVT-W-D-RMM-01", "002010", - "rv64i_m/D/FCVT-W-D-RNE-01", "002010", - "rv64i_m/D/FCVT-W-D-RTZ-01", "002010", - "rv64i_m/D/FCVT-W-D-RUP-01", "002010", - "rv64i_m/D/FCVT-WU-D-DYN-RDN-01", "002010", - "rv64i_m/D/FCVT-WU-D-DYN-RMM-01", "002010", - "rv64i_m/D/FCVT-WU-D-DYN-RNE-01", "002010", - "rv64i_m/D/FCVT-WU-D-DYN-RTZ-01", "002010", - "rv64i_m/D/FCVT-WU-D-DYN-RUP-01", "002010", - "rv64i_m/D/FCVT-WU-D-RDN-01", "002010", - "rv64i_m/D/FCVT-WU-D-RMM-01", "002010", - "rv64i_m/D/FCVT-WU-D-RNE-01", "002010", - "rv64i_m/D/FCVT-WU-D-RTZ-01", "002010", - "rv64i_m/D/FCVT-WU-D-RUP-01", "002010", - // "rv64i_m/D/FDIV-D-DYN-RDN-01", "002010", - // "rv64i_m/D/FDIV-D-DYN-RMM-01", "002010", - // "rv64i_m/D/FDIV-D-DYN-RNE-01", "002010", - // "rv64i_m/D/FDIV-D-DYN-RTZ-01", "002010", - // "rv64i_m/D/FDIV-D-DYN-RUP-01", "002010", - // "rv64i_m/D/FDIV-D-RDN-01", "002010", - // "rv64i_m/D/FDIV-D-RMM-01", "002010", - // "rv64i_m/D/FDIV-D-RNE-01", "002010", - // "rv64i_m/D/FDIV-D-RTZ-01", "002010", - // "rv64i_m/D/FDIV-D-RUP-01", "002010", - "rv64i_m/D/FEQ-D-01", "002010", - "rv64i_m/D/FLD-01", "002520", - "rv64i_m/D/FLE-D-01", "002010", - "rv64i_m/D/FLT-D-01", "002010", - "rv64i_m/D/FMADD-D-DYN-RDN-01", "003010", - "rv64i_m/D/FMADD-D-DYN-RMM-01", "003010", - "rv64i_m/D/FMADD-D-DYN-RNE-01", "003010", - "rv64i_m/D/FMADD-D-DYN-RTZ-01", "003010", - "rv64i_m/D/FMADD-D-DYN-RUP-01", "003010", - "rv64i_m/D/FMADD-D-RDN-01", "003010", - "rv64i_m/D/FMADD-D-RMM-01", "003010", - "rv64i_m/D/FMADD-D-RNE-01", "003010", - "rv64i_m/D/FMADD-D-RTZ-01", "003010", - "rv64i_m/D/FMADD-D-RUP-01", "003010", - "rv64i_m/D/FMAX-D-01", "002010", - "rv64i_m/D/FMIN-D-01", "002010", - "rv64i_m/D/FMSUB-D-DYN-RDN-01", "003010", - "rv64i_m/D/FMSUB-D-DYN-RMM-01", "003010", - "rv64i_m/D/FMSUB-D-DYN-RNE-01", "003010", - "rv64i_m/D/FMSUB-D-DYN-RTZ-01", "003010", - "rv64i_m/D/FMSUB-D-DYN-RUP-01", "003010", - "rv64i_m/D/FMSUB-D-RDN-01", "003010", - "rv64i_m/D/FMSUB-D-RMM-01", "003010", - "rv64i_m/D/FMSUB-D-RNE-01", "003010", - "rv64i_m/D/FMSUB-D-RTZ-01", "003010", - "rv64i_m/D/FMSUB-D-RUP-01", "003010", - "rv64i_m/D/FMUL-D-DYN-RDN-01", "002010", - "rv64i_m/D/FMUL-D-DYN-RMM-01", "002010", - "rv64i_m/D/FMUL-D-DYN-RNE-01", "002010", - "rv64i_m/D/FMUL-D-DYN-RTZ-01", "002010", - "rv64i_m/D/FMUL-D-DYN-RUP-01", "002010", - "rv64i_m/D/FMUL-D-RDN-01", "002010", - "rv64i_m/D/FMUL-D-RMM-01", "002010", - "rv64i_m/D/FMUL-D-RNE-01", "002010", - "rv64i_m/D/FMUL-D-RTZ-01", "002010", - "rv64i_m/D/FMUL-D-RUP-01", "002010", - "rv64i_m/D/FMV-D-X-01", "002010", - "rv64i_m/D/FMV-X-D-01", "002010", - "rv64i_m/D/FNMADD-D-DYN-RDN-01", "003010", - "rv64i_m/D/FNMADD-D-DYN-RMM-01", "003010", - "rv64i_m/D/FNMADD-D-DYN-RNE-01", "003010", - "rv64i_m/D/FNMADD-D-DYN-RTZ-01", "003010", - "rv64i_m/D/FNMADD-D-DYN-RUP-01", "003010", - "rv64i_m/D/FNMADD-D-RDN-01", "003010", - "rv64i_m/D/FNMADD-D-RMM-01", "003010", - "rv64i_m/D/FNMADD-D-RNE-01", "003010", - "rv64i_m/D/FNMADD-D-RTZ-01", "003010", - "rv64i_m/D/FNMADD-D-RUP-01", "003010", - "rv64i_m/D/FNMSUB-D-DYN-RDN-01", "003010", - "rv64i_m/D/FNMSUB-D-DYN-RMM-01", "003010", - "rv64i_m/D/FNMSUB-D-DYN-RNE-01", "003010", - "rv64i_m/D/FNMSUB-D-DYN-RTZ-01", "003010", - "rv64i_m/D/FNMSUB-D-DYN-RUP-01", "003010", - "rv64i_m/D/FNMSUB-D-RDN-01", "003010", - "rv64i_m/D/FNMSUB-D-RMM-01", "003010", - "rv64i_m/D/FNMSUB-D-RNE-01", "003010", - "rv64i_m/D/FNMSUB-D-RTZ-01", "003010", - "rv64i_m/D/FNMSUB-D-RUP-01", "003010", - "rv64i_m/D/FSD-01", "002010", - "rv64i_m/D/FSGNJ-D-01", "002010", - "rv64i_m/D/FSGNJN-D-01", "002010", - "rv64i_m/D/FSGNJX-D-01", "002010", - // "rv64i_m/D/FSQRT-D-DYN-RDN-01", "002010", - // "rv64i_m/D/FSQRT-D-DYN-RMM-01", "002010", - // "rv64i_m/D/FSQRT-D-DYN-RNE-01", "002010", - // "rv64i_m/D/FSQRT-D-DYN-RTZ-01", "002010", - // "rv64i_m/D/FSQRT-D-DYN-RUP-01", "002010", - // "rv64i_m/D/FSQRT-D-RDN-01", "002010", - // "rv64i_m/D/FSQRT-D-RMM-01", "002010", - // "rv64i_m/D/FSQRT-D-RNE-01", "002010", - // "rv64i_m/D/FSQRT-D-RTZ-01", "002010", - // "rv64i_m/D/FSQRT-D-RUP-01", "002010", - "rv64i_m/D/FSUB-D-DYN-RDN-01", "002010", - "rv64i_m/D/FSUB-D-DYN-RMM-01", "002010", - "rv64i_m/D/FSUB-D-DYN-RNE-01", "002010", - "rv64i_m/D/FSUB-D-DYN-RTZ-01", "002010", - "rv64i_m/D/FSUB-D-DYN-RUP-01", "002010", - "rv64i_m/D/FSUB-D-RDN-01", "002010", - "rv64i_m/D/FSUB-D-RMM-01", "002010", - "rv64i_m/D/FSUB-D-RNE-01", "002010", - "rv64i_m/D/FSUB-D-RTZ-01", "002010", - "rv64i_m/D/FSUB-D-RUP-01", "002010" + "rv64i_m/D/FADD-D-DYN-RDN-01", + "rv64i_m/D/FADD-D-DYN-RMM-01", + "rv64i_m/D/FADD-D-DYN-RNE-01", + "rv64i_m/D/FADD-D-DYN-RTZ-01", + "rv64i_m/D/FADD-D-DYN-RUP-01", + "rv64i_m/D/FADD-D-RDN-01", + "rv64i_m/D/FADD-D-RMM-01", + "rv64i_m/D/FADD-D-RNE-01", + "rv64i_m/D/FADD-D-RTZ-01", + "rv64i_m/D/FADD-D-RUP-01", + "rv64i_m/D/FCLASS-D-01", + "rv64i_m/D/FCVT-D-L-DYN-RDN-01", + "rv64i_m/D/FCVT-D-L-DYN-RMM-01", + "rv64i_m/D/FCVT-D-L-DYN-RNE-01", + "rv64i_m/D/FCVT-D-L-DYN-RTZ-01", + "rv64i_m/D/FCVT-D-L-DYN-RUP-01", + "rv64i_m/D/FCVT-D-L-RDN-01", + "rv64i_m/D/FCVT-D-L-RMM-01", + "rv64i_m/D/FCVT-D-L-RNE-01", + "rv64i_m/D/FCVT-D-L-RTZ-01", + "rv64i_m/D/FCVT-D-L-RUP-01", + "rv64i_m/D/FCVT-D-LU-DYN-RDN-01", + "rv64i_m/D/FCVT-D-LU-DYN-RMM-01", + "rv64i_m/D/FCVT-D-LU-DYN-RNE-01", + "rv64i_m/D/FCVT-D-LU-DYN-RTZ-01", + "rv64i_m/D/FCVT-D-LU-DYN-RUP-01", + "rv64i_m/D/FCVT-D-LU-RDN-01", + "rv64i_m/D/FCVT-D-LU-RMM-01", + "rv64i_m/D/FCVT-D-LU-RNE-01", + "rv64i_m/D/FCVT-D-LU-RTZ-01", + "rv64i_m/D/FCVT-D-LU-RUP-01", + "rv64i_m/D/FCVT-D-S-01", + "rv64i_m/D/FCVT-D-W-01", + "rv64i_m/D/FCVT-D-WU-01", + "rv64i_m/D/FCVT-L-D-DYN-RDN-01", + "rv64i_m/D/FCVT-L-D-DYN-RMM-01", + "rv64i_m/D/FCVT-L-D-DYN-RNE-01", + "rv64i_m/D/FCVT-L-D-DYN-RTZ-01", + "rv64i_m/D/FCVT-L-D-DYN-RUP-01", + "rv64i_m/D/FCVT-L-D-RDN-01", + "rv64i_m/D/FCVT-L-D-RMM-01", + "rv64i_m/D/FCVT-L-D-RNE-01", + "rv64i_m/D/FCVT-L-D-RTZ-01", + "rv64i_m/D/FCVT-L-D-RUP-01", + "rv64i_m/D/FCVT-LU-D-DYN-RDN-01", + "rv64i_m/D/FCVT-LU-D-DYN-RMM-01", + "rv64i_m/D/FCVT-LU-D-DYN-RNE-01", + "rv64i_m/D/FCVT-LU-D-DYN-RTZ-01", + "rv64i_m/D/FCVT-LU-D-DYN-RUP-01", + "rv64i_m/D/FCVT-LU-D-RDN-01", + "rv64i_m/D/FCVT-LU-D-RMM-01", + "rv64i_m/D/FCVT-LU-D-RNE-01", + "rv64i_m/D/FCVT-LU-D-RTZ-01", + "rv64i_m/D/FCVT-LU-D-RUP-01", + "rv64i_m/D/FCVT-S-D-DYN-RDN-01", + "rv64i_m/D/FCVT-S-D-DYN-RMM-01", + "rv64i_m/D/FCVT-S-D-DYN-RNE-01", + "rv64i_m/D/FCVT-S-D-DYN-RTZ-01", + "rv64i_m/D/FCVT-S-D-DYN-RUP-01", + "rv64i_m/D/FCVT-S-D-RDN-01", + "rv64i_m/D/FCVT-S-D-RMM-01", + "rv64i_m/D/FCVT-S-D-RNE-01", + "rv64i_m/D/FCVT-S-D-RTZ-01", + "rv64i_m/D/FCVT-S-D-RUP-01", + "rv64i_m/D/FCVT-W-D-DYN-RDN-01", + "rv64i_m/D/FCVT-W-D-DYN-RMM-01", + "rv64i_m/D/FCVT-W-D-DYN-RNE-01", + "rv64i_m/D/FCVT-W-D-DYN-RTZ-01", + "rv64i_m/D/FCVT-W-D-DYN-RUP-01", + "rv64i_m/D/FCVT-W-D-RDN-01", + "rv64i_m/D/FCVT-W-D-RMM-01", + "rv64i_m/D/FCVT-W-D-RNE-01", + "rv64i_m/D/FCVT-W-D-RTZ-01", + "rv64i_m/D/FCVT-W-D-RUP-01", + "rv64i_m/D/FCVT-WU-D-DYN-RDN-01", + "rv64i_m/D/FCVT-WU-D-DYN-RMM-01", + "rv64i_m/D/FCVT-WU-D-DYN-RNE-01", + "rv64i_m/D/FCVT-WU-D-DYN-RTZ-01", + "rv64i_m/D/FCVT-WU-D-DYN-RUP-01", + "rv64i_m/D/FCVT-WU-D-RDN-01", + "rv64i_m/D/FCVT-WU-D-RMM-01", + "rv64i_m/D/FCVT-WU-D-RNE-01", + "rv64i_m/D/FCVT-WU-D-RTZ-01", + "rv64i_m/D/FCVT-WU-D-RUP-01", + // "rv64i_m/D/FDIV-D-DYN-RDN-01", + // "rv64i_m/D/FDIV-D-DYN-RMM-01", + // "rv64i_m/D/FDIV-D-DYN-RNE-01", + // "rv64i_m/D/FDIV-D-DYN-RTZ-01", + // "rv64i_m/D/FDIV-D-DYN-RUP-01", + // "rv64i_m/D/FDIV-D-RDN-01", + // "rv64i_m/D/FDIV-D-RMM-01", + // "rv64i_m/D/FDIV-D-RNE-01", + // "rv64i_m/D/FDIV-D-RTZ-01", + // "rv64i_m/D/FDIV-D-RUP-01", + "rv64i_m/D/FEQ-D-01", + "rv64i_m/D/FLD-01", + "rv64i_m/D/FLE-D-01", + "rv64i_m/D/FLT-D-01", + "rv64i_m/D/FMADD-D-DYN-RDN-01", + "rv64i_m/D/FMADD-D-DYN-RMM-01", + "rv64i_m/D/FMADD-D-DYN-RNE-01", + "rv64i_m/D/FMADD-D-DYN-RTZ-01", + "rv64i_m/D/FMADD-D-DYN-RUP-01", + "rv64i_m/D/FMADD-D-RDN-01", + "rv64i_m/D/FMADD-D-RMM-01", + "rv64i_m/D/FMADD-D-RNE-01", + "rv64i_m/D/FMADD-D-RTZ-01", + "rv64i_m/D/FMADD-D-RUP-01", + "rv64i_m/D/FMAX-D-01", + "rv64i_m/D/FMIN-D-01", + "rv64i_m/D/FMSUB-D-DYN-RDN-01", + "rv64i_m/D/FMSUB-D-DYN-RMM-01", + "rv64i_m/D/FMSUB-D-DYN-RNE-01", + "rv64i_m/D/FMSUB-D-DYN-RTZ-01", + "rv64i_m/D/FMSUB-D-DYN-RUP-01", + "rv64i_m/D/FMSUB-D-RDN-01", + "rv64i_m/D/FMSUB-D-RMM-01", + "rv64i_m/D/FMSUB-D-RNE-01", + "rv64i_m/D/FMSUB-D-RTZ-01", + "rv64i_m/D/FMSUB-D-RUP-01", + "rv64i_m/D/FMUL-D-DYN-RDN-01", + "rv64i_m/D/FMUL-D-DYN-RMM-01", + "rv64i_m/D/FMUL-D-DYN-RNE-01", + "rv64i_m/D/FMUL-D-DYN-RTZ-01", + "rv64i_m/D/FMUL-D-DYN-RUP-01", + "rv64i_m/D/FMUL-D-RDN-01", + "rv64i_m/D/FMUL-D-RMM-01", + "rv64i_m/D/FMUL-D-RNE-01", + "rv64i_m/D/FMUL-D-RTZ-01", + "rv64i_m/D/FMUL-D-RUP-01", + "rv64i_m/D/FMV-D-X-01", + "rv64i_m/D/FMV-X-D-01", + "rv64i_m/D/FNMADD-D-DYN-RDN-01", + "rv64i_m/D/FNMADD-D-DYN-RMM-01", + "rv64i_m/D/FNMADD-D-DYN-RNE-01", + "rv64i_m/D/FNMADD-D-DYN-RTZ-01", + "rv64i_m/D/FNMADD-D-DYN-RUP-01", + "rv64i_m/D/FNMADD-D-RDN-01", + "rv64i_m/D/FNMADD-D-RMM-01", + "rv64i_m/D/FNMADD-D-RNE-01", + "rv64i_m/D/FNMADD-D-RTZ-01", + "rv64i_m/D/FNMADD-D-RUP-01", + "rv64i_m/D/FNMSUB-D-DYN-RDN-01", + "rv64i_m/D/FNMSUB-D-DYN-RMM-01", + "rv64i_m/D/FNMSUB-D-DYN-RNE-01", + "rv64i_m/D/FNMSUB-D-DYN-RTZ-01", + "rv64i_m/D/FNMSUB-D-DYN-RUP-01", + "rv64i_m/D/FNMSUB-D-RDN-01", + "rv64i_m/D/FNMSUB-D-RMM-01", + "rv64i_m/D/FNMSUB-D-RNE-01", + "rv64i_m/D/FNMSUB-D-RTZ-01", + "rv64i_m/D/FNMSUB-D-RUP-01", + "rv64i_m/D/FSD-01", + "rv64i_m/D/FSGNJ-D-01", + "rv64i_m/D/FSGNJN-D-01", + "rv64i_m/D/FSGNJX-D-01", + // "rv64i_m/D/FSQRT-D-DYN-RDN-01", + // "rv64i_m/D/FSQRT-D-DYN-RMM-01", + // "rv64i_m/D/FSQRT-D-DYN-RNE-01", + // "rv64i_m/D/FSQRT-D-DYN-RTZ-01", + // "rv64i_m/D/FSQRT-D-DYN-RUP-01", + // "rv64i_m/D/FSQRT-D-RDN-01", + // "rv64i_m/D/FSQRT-D-RMM-01", + // "rv64i_m/D/FSQRT-D-RNE-01", + // "rv64i_m/D/FSQRT-D-RTZ-01", + // "rv64i_m/D/FSQRT-D-RUP-01", + "rv64i_m/D/FSUB-D-DYN-RDN-01", + "rv64i_m/D/FSUB-D-DYN-RMM-01", + "rv64i_m/D/FSUB-D-DYN-RNE-01", + "rv64i_m/D/FSUB-D-DYN-RTZ-01", + "rv64i_m/D/FSUB-D-DYN-RUP-01", + "rv64i_m/D/FSUB-D-RDN-01", + "rv64i_m/D/FSUB-D-RMM-01", + "rv64i_m/D/FSUB-D-RNE-01", + "rv64i_m/D/FSUB-D-RTZ-01", + "rv64i_m/D/FSUB-D-RUP-01" }; string imperas64m[] = '{ `IMPERASTEST, - "rv64i_m/M/DIV-01", "004010", - "rv64i_m/M/DIVU-01", "004010", - "rv64i_m/M/DIVUW-01", "003010", - "rv64i_m/M/DIVW-01", "003010", - "rv64i_m/M/MUL-01", "004010", - "rv64i_m/M/MULH-01", "004010", - "rv64i_m/M/MULHSU-01", "004010", - "rv64i_m/M/MULHU-01", "004010", - "rv64i_m/M/MULW-01", "003010", - "rv64i_m/M/REM-01", "004010", - "rv64i_m/M/REMU-01", "004010", - "rv64i_m/M/REMUW-01", "003010", - "rv64i_m/M/REMW-01", "003010" + "rv64i_m/M/DIV-01", + "rv64i_m/M/DIVU-01", + "rv64i_m/M/DIVUW-01", + "rv64i_m/M/DIVW-01", + "rv64i_m/M/MUL-01", + "rv64i_m/M/MULH-01", + "rv64i_m/M/MULHSU-01", + "rv64i_m/M/MULHU-01", + "rv64i_m/M/MULW-01", + "rv64i_m/M/REM-01", + "rv64i_m/M/REMU-01", + "rv64i_m/M/REMUW-01", + "rv64i_m/M/REMW-01" }; string imperas64c[] = '{ `IMPERASTEST, - "rv64i_m/C/C-ADD-01", "003010", - "rv64i_m/C/C-ADDI-01", "003010", - "rv64i_m/C/C-ADDI16SP-01", "003010", - "rv64i_m/C/C-ADDI4SPN-01", "003010", - "rv64i_m/C/C-ADDIW-01", "003010", - "rv64i_m/C/C-ADDW-01", "003010", - "rv64i_m/C/C-AND-01", "003010", - "rv64i_m/C/C-ANDI-01", "003010", - "rv64i_m/C/C-BEQZ-01", "004010", - "rv64i_m/C/C-BNEZ-01", "004010", - "rv64i_m/C/C-J-01", "003010", - "rv64i_m/C/C-JALR-01", "004010", - "rv64i_m/C/C-JR-01", "004010", - "rv64i_m/C/C-LD-01", "003520", - "rv64i_m/C/C-LDSP-01", "003520", - "rv64i_m/C/C-LI-01", "003010", - "rv64i_m/C/C-LUI-01", "002010", - "rv64i_m/C/C-LW-01", "003210", - "rv64i_m/C/C-LWSP-01", "003210", - "rv64i_m/C/C-MV-01", "003010", - "rv64i_m/C/C-OR-01", "003010", - "rv64i_m/C/C-SD-01", "003010", - "rv64i_m/C/C-SDSP-01", "003010", - "rv64i_m/C/C-SLLI-01", "003010", - "rv64i_m/C/C-SRAI-01", "003010", - "rv64i_m/C/C-SRLI-01", "003010", - "rv64i_m/C/C-SUB-01", "003010", - "rv64i_m/C/C-SUBW-01", "003010", - "rv64i_m/C/C-SW-01", "003010", - "rv64i_m/C/C-SWSP-01", "003010", - "rv64i_m/C/C-XOR-01", "003010", - "rv64i_m/C/I-C-EBREAK-01", "002000", - "rv64i_m/C/I-C-NOP-01", "002000" + "rv64i_m/C/C-ADD-01", + "rv64i_m/C/C-ADDI-01", + "rv64i_m/C/C-ADDI16SP-01", + "rv64i_m/C/C-ADDI4SPN-01", + "rv64i_m/C/C-ADDIW-01", + "rv64i_m/C/C-ADDW-01", + "rv64i_m/C/C-AND-01", + "rv64i_m/C/C-ANDI-01", + "rv64i_m/C/C-BEQZ-01", + "rv64i_m/C/C-BNEZ-01", + "rv64i_m/C/C-J-01", + "rv64i_m/C/C-JALR-01", + "rv64i_m/C/C-JR-01", + "rv64i_m/C/C-LD-01", + "rv64i_m/C/C-LDSP-01", + "rv64i_m/C/C-LI-01", + "rv64i_m/C/C-LUI-01", + "rv64i_m/C/C-LW-01", + "rv64i_m/C/C-LWSP-01", + "rv64i_m/C/C-MV-01", + "rv64i_m/C/C-OR-01", + "rv64i_m/C/C-SD-01", + "rv64i_m/C/C-SDSP-01", + "rv64i_m/C/C-SLLI-01", + "rv64i_m/C/C-SRAI-01", + "rv64i_m/C/C-SRLI-01", + "rv64i_m/C/C-SUB-01", + "rv64i_m/C/C-SUBW-01", + "rv64i_m/C/C-SW-01", + "rv64i_m/C/C-SWSP-01", + "rv64i_m/C/C-XOR-01", + "rv64i_m/C/I-C-EBREAK-01", + "rv64i_m/C/I-C-NOP-01" }; string imperas64iNOc[] = { `IMPERASTEST, - "rv64i_m/I/I-MISALIGN_JMP-01", "002000" + "rv64i_m/I/I-MISALIGN_JMP-01" }; string imperas64i[] = '{ `IMPERASTEST, - "rv64i_m/I/I-DELAY_SLOTS-01", "002010", - "rv64i_m/I/ADD-01", "004010", - "rv64i_m/I/ADDI-01", "003010", - "rv64i_m/I/ADDIW-01", "003010", - "rv64i_m/I/ADDW-01", "003010", - "rv64i_m/I/AND-01", "004010", - "rv64i_m/I/ANDI-01", "003010", - "rv64i_m/I/AUIPC-01", "003010", - "rv64i_m/I/BEQ-01", "005010", - "rv64i_m/I/BGE-01", "005010", - "rv64i_m/I/BGEU-01", "005010", - "rv64i_m/I/BLT-01", "005010", - "rv64i_m/I/BLTU-01", "005010", - "rv64i_m/I/BNE-01", "005010", - "rv64i_m/I/I-DELAY_SLOTS-01", "002010", - "rv64i_m/I/I-EBREAK-01", "002010", - "rv64i_m/I/I-ECALL-01", "002010", - "rv64i_m/I/I-ENDIANESS-01", "002010", - "rv64i_m/I/I-IO-01", "002050", -// "rv64i_m/I/I-MISALIGN_JMP-01", "002000", - "rv64i_m/I/I-MISALIGN_LDST-01", "002010", - "rv64i_m/I/I-NOP-01", "002000", - "rv64i_m/I/I-RF_size-01", "002000", - "rv64i_m/I/I-RF_width-01", "002000", - "rv64i_m/I/I-RF_x0-01", "002010", - "rv64i_m/I/JAL-01", "004010", - "rv64i_m/I/JALR-01", "005010", - "rv64i_m/I/LB-01", "004120", - "rv64i_m/I/LBU-01", "004120", - "rv64i_m/I/LD-01", "004520", - "rv64i_m/I/LH-01", "004150", - "rv64i_m/I/LHU-01", "004150", - "rv64i_m/I/LUI-01", "002010", - "rv64i_m/I/LW-01", "004210", - "rv64i_m/I/LWU-01", "004210", - "rv64i_m/I/OR-01", "004010", - "rv64i_m/I/ORI-01", "003010", - "rv64i_m/I/SB-01", "004010", - "rv64i_m/I/SD-01", "004010", - "rv64i_m/I/SH-01", "004010", - "rv64i_m/I/SLL-01", "003010", - "rv64i_m/I/SLLI-01", "003010", - "rv64i_m/I/SLLIW-01", "003010", - "rv64i_m/I/SLLW-01", "003010", - "rv64i_m/I/SLT-01", "004010", - "rv64i_m/I/SLTI-01", "003010", - "rv64i_m/I/SLTIU-01", "003010", - "rv64i_m/I/SLTU-01", "004010", - "rv64i_m/I/SRA-01", "003010", - "rv64i_m/I/SRAI-01", "003010", - "rv64i_m/I/SRAIW-01", "003010", - "rv64i_m/I/SRAW-01", "003010", - "rv64i_m/I/SRL-01", "003010", - "rv64i_m/I/SRLI-01", "003010", - "rv64i_m/I/SRLIW-01", "003010", - "rv64i_m/I/SRLW-01", "003010", - "rv64i_m/I/SUB-01", "004010", - "rv64i_m/I/SUBW-01", "003010", - "rv64i_m/I/SW-01", "004010", - "rv64i_m/I/XOR-01", "004010", - "rv64i_m/I/XORI-01", "003010" + "rv64i_m/I/I-DELAY_SLOTS-01", + "rv64i_m/I/ADD-01", + "rv64i_m/I/ADDI-01", + "rv64i_m/I/ADDIW-01", + "rv64i_m/I/ADDW-01", + "rv64i_m/I/AND-01", + "rv64i_m/I/ANDI-01", + "rv64i_m/I/AUIPC-01", + "rv64i_m/I/BEQ-01", + "rv64i_m/I/BGE-01", + "rv64i_m/I/BGEU-01", + "rv64i_m/I/BLT-01", + "rv64i_m/I/BLTU-01", + "rv64i_m/I/BNE-01", + "rv64i_m/I/I-DELAY_SLOTS-01", + "rv64i_m/I/I-EBREAK-01", + "rv64i_m/I/I-ECALL-01", + "rv64i_m/I/I-ENDIANESS-01", + "rv64i_m/I/I-IO-01", +// "rv64i_m/I/I-MISALIGN_JMP-01", + "rv64i_m/I/I-MISALIGN_LDST-01", + "rv64i_m/I/I-NOP-01", + "rv64i_m/I/I-RF_size-01", + "rv64i_m/I/I-RF_width-01", + "rv64i_m/I/I-RF_x0-01", + "rv64i_m/I/JAL-01", + "rv64i_m/I/JALR-01", + "rv64i_m/I/LB-01", + "rv64i_m/I/LBU-01", + "rv64i_m/I/LD-01", + "rv64i_m/I/LH-01", + "rv64i_m/I/LHU-01", + "rv64i_m/I/LUI-01", + "rv64i_m/I/LW-01", + "rv64i_m/I/LWU-01", + "rv64i_m/I/OR-01", + "rv64i_m/I/ORI-01", + "rv64i_m/I/SB-01", + "rv64i_m/I/SD-01", + "rv64i_m/I/SH-01", + "rv64i_m/I/SLL-01", + "rv64i_m/I/SLLI-01", + "rv64i_m/I/SLLIW-01", + "rv64i_m/I/SLLW-01", + "rv64i_m/I/SLT-01", + "rv64i_m/I/SLTI-01", + "rv64i_m/I/SLTIU-01", + "rv64i_m/I/SLTU-01", + "rv64i_m/I/SRA-01", + "rv64i_m/I/SRAI-01", + "rv64i_m/I/SRAIW-01", + "rv64i_m/I/SRAW-01", + "rv64i_m/I/SRL-01", + "rv64i_m/I/SRLI-01", + "rv64i_m/I/SRLIW-01", + "rv64i_m/I/SRLW-01", + "rv64i_m/I/SUB-01", + "rv64i_m/I/SUBW-01", + "rv64i_m/I/SW-01", + "rv64i_m/I/XOR-01", + "rv64i_m/I/XORI-01" }; string imperas32m[] = '{ `IMPERASTEST, - "rv32i_m/M/DIV-01", "002010", - "rv32i_m/M/DIVU-01", "002010", - "rv32i_m/M/MUL-01", "002010", - "rv32i_m/M/MULH-01", "002010", - "rv32i_m/M/MULHSU-01", "002010", - "rv32i_m/M/MULHU-01", "002010", - "rv32i_m/M/REM-01", "002010", - "rv32i_m/M/REMU-01", "002010" + "rv32i_m/M/DIV-01", + "rv32i_m/M/DIVU-01", + "rv32i_m/M/MUL-01", + "rv32i_m/M/MULH-01", + "rv32i_m/M/MULHSU-01", + "rv32i_m/M/MULHU-01", + "rv32i_m/M/REM-01", + "rv32i_m/M/REMU-01" }; string imperas32c[] = '{ `IMPERASTEST, - "rv32i_m/C/C-ADD-01", "002010", - "rv32i_m/C/C-ADDI-01", "002010", - "rv32i_m/C/C-ADDI16SP-01", "002010", - "rv32i_m/C/C-ADDI4SPN-01", "002010", - "rv32i_m/C/C-AND-01", "002010", - "rv32i_m/C/C-ANDI-01", "002010", - "rv32i_m/C/C-BEQZ-01", "003010", - "rv32i_m/C/C-BNEZ-01", "003010", - "rv32i_m/C/C-J-01", "002010", - "rv32i_m/C/C-JAL-01", "002010", - "rv32i_m/C/C-JALR-01", "003010", - "rv32i_m/C/C-JR-01", "003010", - "rv32i_m/C/C-LI-01", "002010", - "rv32i_m/C/C-LUI-01", "002010", - "rv32i_m/C/C-LW-01", "002120", - "rv32i_m/C/C-LWSP-01", "002120", - "rv32i_m/C/C-MV-01", "002010", - "rv32i_m/C/C-OR-01", "002010", - "rv32i_m/C/C-SLLI-01", "002010", - "rv32i_m/C/C-SRAI-01", "002010", - "rv32i_m/C/C-SRLI-01", "002010", - "rv32i_m/C/C-SUB-01", "002010", - "rv32i_m/C/C-SW-01", "002010", - "rv32i_m/C/C-SWSP-01", "002010", - "rv32i_m/C/C-XOR-01", "002010", - "rv32i_m/C/I-C-EBREAK-01", "002000", - "rv32i_m/C/I-C-NOP-01", "002000" + "rv32i_m/C/C-ADD-01", + "rv32i_m/C/C-ADDI-01", + "rv32i_m/C/C-ADDI16SP-01", + "rv32i_m/C/C-ADDI4SPN-01", + "rv32i_m/C/C-AND-01", + "rv32i_m/C/C-ANDI-01", + "rv32i_m/C/C-BEQZ-01", + "rv32i_m/C/C-BNEZ-01", + "rv32i_m/C/C-J-01", + "rv32i_m/C/C-JAL-01", + "rv32i_m/C/C-JALR-01", + "rv32i_m/C/C-JR-01", + "rv32i_m/C/C-LI-01", + "rv32i_m/C/C-LUI-01", + "rv32i_m/C/C-LW-01", + "rv32i_m/C/C-LWSP-01", + "rv32i_m/C/C-MV-01", + "rv32i_m/C/C-OR-01", + "rv32i_m/C/C-SLLI-01", + "rv32i_m/C/C-SRAI-01", + "rv32i_m/C/C-SRLI-01", + "rv32i_m/C/C-SUB-01", + "rv32i_m/C/C-SW-01", + "rv32i_m/C/C-SWSP-01", + "rv32i_m/C/C-XOR-01", + "rv32i_m/C/I-C-EBREAK-01", + "rv32i_m/C/I-C-NOP-01" }; string imperas32iNOc[] = { `IMPERASTEST, - "rv32i_m/I/I-MISALIGN_JMP-01", "002000" + "rv32i_m/I/I-MISALIGN_JMP-01" }; string imperas32i[] = { `IMPERASTEST, - "rv32i_m/I/ADD-01", "002010", - "rv32i_m/I/ADDI-01", "002010", - "rv32i_m/I/AND-01", "002010", - "rv32i_m/I/ANDI-01", "002010", - "rv32i_m/I/AUIPC-01", "002010", - "rv32i_m/I/BEQ-01", "003010", - "rv32i_m/I/BGE-01", "003010", - "rv32i_m/I/BGEU-01", "003010", - "rv32i_m/I/BLT-01", "003010", - "rv32i_m/I/BLTU-01", "003010", - "rv32i_m/I/BNE-01", "003010", - "rv32i_m/I/I-DELAY_SLOTS-01", "002010", - "rv32i_m/I/I-EBREAK-01", "002010", - "rv32i_m/I/I-ECALL-01", "002010", - "rv32i_m/I/I-ENDIANESS-01", "002010", - "rv32i_m/I/I-IO-01", "002030", -// "rv32i_m/I/I-MISALIGN_JMP-01", "002000", - "rv32i_m/I/I-MISALIGN_LDST-01", "002010", - "rv32i_m/I/I-NOP-01", "002000", - "rv32i_m/I/I-RF_size-01", "002000", - "rv32i_m/I/I-RF_width-01", "002000", - "rv32i_m/I/I-RF_x0-01", "002010", - "rv32i_m/I/JAL-01", "003010", - "rv32i_m/I/JALR-01", "003010", - "rv32i_m/I/LB-01", "003030", - "rv32i_m/I/LBU-01", "003030", - "rv32i_m/I/LH-01", "003060", - "rv32i_m/I/LHU-01", "003060", - "rv32i_m/I/LUI-01", "002010", - "rv32i_m/I/LW-01", "003120", - "rv32i_m/I/OR-01", "002010", - "rv32i_m/I/ORI-01", "002010", - "rv32i_m/I/SB-01", "003010", - "rv32i_m/I/SH-01", "003010", - "rv32i_m/I/SLL-01", "002010", - "rv32i_m/I/SLLI-01", "002010", - "rv32i_m/I/SLT-01", "002010", - "rv32i_m/I/SLTI-01", "002010", - "rv32i_m/I/SLTIU-01", "002010", - "rv32i_m/I/SLTU-01", "002010", - "rv32i_m/I/SRA-01", "002010", - "rv32i_m/I/SRAI-01", "002010", - "rv32i_m/I/SRL-01", "002010", - "rv32i_m/I/SRLI-01", "002010", - "rv32i_m/I/SUB-01", "002010", - "rv32i_m/I/SW-01", "003010", - "rv32i_m/I/XOR-01", "002010", - "rv32i_m/I/XORI-01", "002010" + "rv32i_m/I/ADD-01", + "rv32i_m/I/ADDI-01", + "rv32i_m/I/AND-01", + "rv32i_m/I/ANDI-01", + "rv32i_m/I/AUIPC-01", + "rv32i_m/I/BEQ-01", + "rv32i_m/I/BGE-01", + "rv32i_m/I/BGEU-01", + "rv32i_m/I/BLT-01", + "rv32i_m/I/BLTU-01", + "rv32i_m/I/BNE-01", + "rv32i_m/I/I-DELAY_SLOTS-01", + "rv32i_m/I/I-EBREAK-01", + "rv32i_m/I/I-ECALL-01", + "rv32i_m/I/I-ENDIANESS-01", + "rv32i_m/I/I-IO-01", +// "rv32i_m/I/I-MISALIGN_JMP-01", + "rv32i_m/I/I-MISALIGN_LDST-01", + "rv32i_m/I/I-NOP-01", + "rv32i_m/I/I-RF_size-01", + "rv32i_m/I/I-RF_width-01", + "rv32i_m/I/I-RF_x0-01", + "rv32i_m/I/JAL-01", + "rv32i_m/I/JALR-01", + "rv32i_m/I/LB-01", + "rv32i_m/I/LBU-01", + "rv32i_m/I/LH-01", + "rv32i_m/I/LHU-01", + "rv32i_m/I/LUI-01", + "rv32i_m/I/LW-01", + "rv32i_m/I/OR-01", + "rv32i_m/I/ORI-01", + "rv32i_m/I/SB-01", + "rv32i_m/I/SH-01", + "rv32i_m/I/SLL-01", + "rv32i_m/I/SLLI-01", + "rv32i_m/I/SLT-01", + "rv32i_m/I/SLTI-01", + "rv32i_m/I/SLTIU-01", + "rv32i_m/I/SLTU-01", + "rv32i_m/I/SRA-01", + "rv32i_m/I/SRAI-01", + "rv32i_m/I/SRL-01", + "rv32i_m/I/SRLI-01", + "rv32i_m/I/SUB-01", + "rv32i_m/I/SW-01", + "rv32i_m/I/XOR-01", + "rv32i_m/I/XORI-01" }; string testsBP64[] = '{ `IMPERASTEST, - "rv64BP/simple", "10000", - "rv64BP/mmm", "1000000", - "rv64BP/linpack_bench", "1000000", - "rv64BP/sieve", "1000000", - "rv64BP/qsort", "1000000", - "rv64BP/dhrystone", "1000000" + "rv64BP/simple", + "rv64BP/mmm", + "rv64BP/linpack_bench", + "rv64BP/sieve", + "rv64BP/qsort", + "rv64BP/dhrystone" }; string imperas32p[] = '{ `MYIMPERASTEST, - "rv32p/WALLY-MSTATUS", "2000", - "rv32p/WALLY-MCAUSE", "3000", - "rv32p/WALLY-SCAUSE", "2000", - "rv32p/WALLY-MEPC", "5000", - "rv32p/WALLY-SEPC", "4000", - "rv32p/WALLY-MTVAL", "5000", - "rv32p/WALLY-STVAL", "4000", - "rv32p/WALLY-MARCHID", "4000", - "rv32p/WALLY-MIMPID", "4000", - "rv32p/WALLY-MHARTID", "4000", - "rv32p/WALLY-MVENDORID", "4000", - "rv32p/WALLY-MTVEC", "2000", - "rv32p/WALLY-STVEC", "2000", - "rv32p/WALLY-MIE", "3000", - "rv32p/WALLY-MEDELEG", "4000", - "rv32p/WALLY-IP", "3000", - "rv32p/WALLY-CSR-PERMISSIONS-M", "5000", - "rv32p/WALLY-CSR-PERMISSIONS-S", "3000" + "rv32p/WALLY-MSTATUS", + "rv32p/WALLY-MCAUSE", + "rv32p/WALLY-SCAUSE", + "rv32p/WALLY-MEPC", + "rv32p/WALLY-SEPC", + "rv32p/WALLY-MTVAL", + "rv32p/WALLY-STVAL", + "rv32p/WALLY-MARCHID", + "rv32p/WALLY-MIMPID", + "rv32p/WALLY-MHARTID", + "rv32p/WALLY-MVENDORID", + "rv32p/WALLY-MTVEC", + "rv32p/WALLY-STVEC", + "rv32p/WALLY-MIE", + "rv32p/WALLY-MEDELEG", + "rv32p/WALLY-IP", + "rv32p/WALLY-CSR-PERMISSIONS-M", + "rv32p/WALLY-CSR-PERMISSIONS-S" }; string arch64priv[] = '{ `RISCVARCHTEST, - "rv64i_m/privilege/ebreak", "2090", - "rv64i_m/privilege/ecall", "2090", - "rv64i_m/privilege/misalign-beq-01", "20a0", - "rv64i_m/privilege/misalign-bge-01", "20a0", - "rv64i_m/privilege/misalign-bgeu-01", "20a0", - "rv64i_m/privilege/misalign-blt-01", "20a0", - "rv64i_m/privilege/misalign-bltu-01", "20a0", - "rv64i_m/privilege/misalign-bne-01", "20a0", - "rv64i_m/privilege/misalign-jal-01", "20a0", - "rv64i_m/privilege/misalign-ld-01", "20a0", - "rv64i_m/privilege/misalign-lh-01", "20a0", - "rv64i_m/privilege/misalign-lhu-01", "20a0", - "rv64i_m/privilege/misalign-lw-01", "20a0", - "rv64i_m/privilege/misalign-lwu-01", "20a0", - "rv64i_m/privilege/misalign-sd-01", "20a0", - "rv64i_m/privilege/misalign-sh-01", "20a0", - "rv64i_m/privilege/misalign-sw-01", "20a0", - "rv64i_m/privilege/misalign1-jalr-01", "20a0", - "rv64i_m/privilege/misalign2-jalr-01", "20a0" + "rv64i_m/privilege/ebreak", + "rv64i_m/privilege/ecall", + "rv64i_m/privilege/misalign-beq-01", + "rv64i_m/privilege/misalign-bge-01", + "rv64i_m/privilege/misalign-bgeu-01", + "rv64i_m/privilege/misalign-blt-01", + "rv64i_m/privilege/misalign-bltu-01", + "rv64i_m/privilege/misalign-bne-01", + "rv64i_m/privilege/misalign-jal-01", + "rv64i_m/privilege/misalign-ld-01", + "rv64i_m/privilege/misalign-lh-01", + "rv64i_m/privilege/misalign-lhu-01", + "rv64i_m/privilege/misalign-lw-01", + "rv64i_m/privilege/misalign-lwu-01", + "rv64i_m/privilege/misalign-sd-01", + "rv64i_m/privilege/misalign-sh-01", + "rv64i_m/privilege/misalign-sw-01", + "rv64i_m/privilege/misalign1-jalr-01", + "rv64i_m/privilege/misalign2-jalr-01" }; string arch64m[] = '{ `RISCVARCHTEST, - "rv64i_m/M/div-01", "9010", - "rv64i_m/M/divu-01", "a010", - "rv64i_m/M/divuw-01", "a010", - "rv64i_m/M/divw-01", "9010", - "rv64i_m/M/mul-01", "9010", - "rv64i_m/M/mulh-01", "9010", - "rv64i_m/M/mulhsu-01", "9010", - "rv64i_m/M/mulhu-01", "a010", - "rv64i_m/M/mulw-01", "9010", - "rv64i_m/M/rem-01", "9010", - "rv64i_m/M/remu-01", "a010", - "rv64i_m/M/remuw-01", "a010", - "rv64i_m/M/remw-01", "9010" + "rv64i_m/M/div-01", + "rv64i_m/M/divu-01", + "rv64i_m/M/divuw-01", + "rv64i_m/M/divw-01", + "rv64i_m/M/mul-01", + "rv64i_m/M/mulh-01", + "rv64i_m/M/mulhsu-01", + "rv64i_m/M/mulhu-01", + "rv64i_m/M/mulw-01", + "rv64i_m/M/rem-01", + "rv64i_m/M/remu-01", + "rv64i_m/M/remuw-01", + "rv64i_m/M/remw-01" }; string arch64c[] = '{ `RISCVARCHTEST, - "rv64i_m/C/cadd-01", "8010", - "rv64i_m/C/caddi-01", "4010", - "rv64i_m/C/caddi16sp-01", "2010", - "rv64i_m/C/caddi4spn-01", "2010", - "rv64i_m/C/caddiw-01", "4010", - "rv64i_m/C/caddw-01", "8010", - "rv64i_m/C/cand-01", "8010", - "rv64i_m/C/candi-01", "4010", - "rv64i_m/C/cbeqz-01", "4010", - "rv64i_m/C/cbnez-01", "5010", - "rv64i_m/C/cj-01", "3010", - "rv64i_m/C/cjalr-01", "2010", - "rv64i_m/C/cjr-01", "2010", - "rv64i_m/C/cld-01", "2010", - "rv64i_m/C/cldsp-01", "2010", - "rv64i_m/C/cli-01", "2010", - "rv64i_m/C/clui-01", "2010", - "rv64i_m/C/clw-01", "2010", - "rv64i_m/C/clwsp-01", "2010", - "rv64i_m/C/cmv-01", "2010", - "rv64i_m/C/cnop-01", "2010", - "rv64i_m/C/cor-01", "8010", - "rv64i_m/C/csd-01", "3010", - "rv64i_m/C/csdsp-01", "3010", - "rv64i_m/C/cslli-01", "2010", - "rv64i_m/C/csrai-01", "2010", - "rv64i_m/C/csrli-01", "2010", - "rv64i_m/C/csub-01", "8010", - "rv64i_m/C/csubw-01", "8010", - "rv64i_m/C/csw-01", "3010", - "rv64i_m/C/cswsp-01", "3010", - "rv64i_m/C/cxor-01", "8010" + "rv64i_m/C/cadd-01", + "rv64i_m/C/caddi-01", + "rv64i_m/C/caddi16sp-01", + "rv64i_m/C/caddi4spn-01", + "rv64i_m/C/caddiw-01", + "rv64i_m/C/caddw-01", + "rv64i_m/C/cand-01", + "rv64i_m/C/candi-01", + "rv64i_m/C/cbeqz-01", + "rv64i_m/C/cbnez-01", + "rv64i_m/C/cj-01", + "rv64i_m/C/cjalr-01", + "rv64i_m/C/cjr-01", + "rv64i_m/C/cld-01", + "rv64i_m/C/cldsp-01", + "rv64i_m/C/cli-01", + "rv64i_m/C/clui-01", + "rv64i_m/C/clw-01", + "rv64i_m/C/clwsp-01", + "rv64i_m/C/cmv-01", + "rv64i_m/C/cnop-01", + "rv64i_m/C/cor-01", + "rv64i_m/C/csd-01", + "rv64i_m/C/csdsp-01", + "rv64i_m/C/cslli-01", + "rv64i_m/C/csrai-01", + "rv64i_m/C/csrli-01", + "rv64i_m/C/csub-01", + "rv64i_m/C/csubw-01", + "rv64i_m/C/csw-01", + "rv64i_m/C/cswsp-01", + "rv64i_m/C/cxor-01" }; string arch64cpriv[] = '{ // `RISCVARCHTEST, - "rv64i_m/C/cebreak-01", "2070" + "rv64i_m/C/cebreak-01" }; string arch64i[] = '{ `RISCVARCHTEST, - "rv64i_m/I/add-01", "9010", - "rv64i_m/I/addi-01", "6010", - "rv64i_m/I/addiw-01", "6010", - "rv64i_m/I/addw-01", "9010", - "rv64i_m/I/and-01", "9010", - "rv64i_m/I/andi-01", "6010", - "rv64i_m/I/auipc-01", "2010", - "rv64i_m/I/beq-01", "47010", - "rv64i_m/I/bge-01", "47010", - "rv64i_m/I/bgeu-01", "56010", - "rv64i_m/I/blt-01", "4d010", - "rv64i_m/I/bltu-01", "57010", - "rv64i_m/I/bne-01", "43010", - "rv64i_m/I/fence-01", "2010", - "rv64i_m/I/jal-01", "122010", - "rv64i_m/I/jalr-01", "2010", - "rv64i_m/I/lb-align-01", "2010", - "rv64i_m/I/lbu-align-01", "2010", - "rv64i_m/I/ld-align-01", "2010", - "rv64i_m/I/lh-align-01", "2010", - "rv64i_m/I/lhu-align-01", "2010", - "rv64i_m/I/lui-01", "2010", - "rv64i_m/I/lw-align-01", "2010", - "rv64i_m/I/lwu-align-01", "2010", - "rv64i_m/I/or-01", "9010", - "rv64i_m/I/ori-01", "6010", - "rv64i_m/I/sb-align-01", "3010", - "rv64i_m/I/sd-align-01", "3010", - "rv64i_m/I/sh-align-01", "3010", - "rv64i_m/I/sll-01", "3010", - "rv64i_m/I/slli-01", "2010", - "rv64i_m/I/slliw-01", "2010", - "rv64i_m/I/sllw-01", "3010", - "rv64i_m/I/slt-01", "9010", - "rv64i_m/I/slti-01", "6010", - "rv64i_m/I/sltiu-01", "6010", - "rv64i_m/I/sltu-01", "a010", - "rv64i_m/I/sra-01", "3010", - "rv64i_m/I/srai-01", "2010", - "rv64i_m/I/sraiw-01", "2010", - "rv64i_m/I/sraw-01", "3010", - "rv64i_m/I/srl-01", "3010", - "rv64i_m/I/srli-01", "2010", - "rv64i_m/I/srliw-01", "2010", - "rv64i_m/I/srlw-01", "3010", - "rv64i_m/I/sub-01", "9010", - "rv64i_m/I/subw-01", "9010", - "rv64i_m/I/sw-align-01", "3010", - "rv64i_m/I/xor-01", "9010", - "rv64i_m/I/xori-01", "6010" + "rv64i_m/I/add-01", + "rv64i_m/I/addi-01", + "rv64i_m/I/addiw-01", + "rv64i_m/I/addw-01", + "rv64i_m/I/and-01", + "rv64i_m/I/andi-01", + "rv64i_m/I/auipc-01", + "rv64i_m/I/beq-01", + "rv64i_m/I/bge-01", + "rv64i_m/I/bgeu-01", + "rv64i_m/I/blt-01", + "rv64i_m/I/bltu-01", + "rv64i_m/I/bne-01", + "rv64i_m/I/fence-01", + "rv64i_m/I/jal-01", + "rv64i_m/I/jalr-01", + "rv64i_m/I/lb-align-01", + "rv64i_m/I/lbu-align-01", + "rv64i_m/I/ld-align-01", + "rv64i_m/I/lh-align-01", + "rv64i_m/I/lhu-align-01", + "rv64i_m/I/lui-01", + "rv64i_m/I/lw-align-01", + "rv64i_m/I/lwu-align-01", + "rv64i_m/I/or-01", + "rv64i_m/I/ori-01", + "rv64i_m/I/sb-align-01", + "rv64i_m/I/sd-align-01", + "rv64i_m/I/sh-align-01", + "rv64i_m/I/sll-01", + "rv64i_m/I/slli-01", + "rv64i_m/I/slliw-01", + "rv64i_m/I/sllw-01", + "rv64i_m/I/slt-01", + "rv64i_m/I/slti-01", + "rv64i_m/I/sltiu-01", + "rv64i_m/I/sltu-01", + "rv64i_m/I/sra-01", + "rv64i_m/I/srai-01", + "rv64i_m/I/sraiw-01", + "rv64i_m/I/sraw-01", + "rv64i_m/I/srl-01", + "rv64i_m/I/srli-01", + "rv64i_m/I/srliw-01", + "rv64i_m/I/srlw-01", + "rv64i_m/I/sub-01", + "rv64i_m/I/subw-01", + "rv64i_m/I/sw-align-01", + "rv64i_m/I/xor-01", + "rv64i_m/I/xori-01" }; string arch64d[] = '{ `RISCVARCHTEST, - "rv64i_m/D/d_fadd_b10-01", "8690", - "rv64i_m/D/d_fadd_b1-01", "8430", - "rv64i_m/D/d_fadd_b11-01", "74da0", - "rv64i_m/D/d_fadd_b12-01", "2350", - "rv64i_m/D/d_fadd_b13-01", "3cb0", - "rv64i_m/D/d_fadd_b2-01", "5160", - "rv64i_m/D/d_fadd_b3-01", "d640", - "rv64i_m/D/d_fadd_b4-01", "3900", - "rv64i_m/D/d_fadd_b5-01", "3d50", - "rv64i_m/D/d_fadd_b7-01", "5530", - "rv64i_m/D/d_fadd_b8-01", "11c10", - "rv64i_m/D/d_fclass_b1-01", "2110", - "rv64i_m/D/d_fcvt.d.l_b25-01", "2110", - "rv64i_m/D/d_fcvt.d.l_b26-01", "2220", - "rv64i_m/D/d_fcvt.d.lu_b25-01", "2110", - "rv64i_m/D/d_fcvt.d.lu_b26-01", "2220", - "rv64i_m/D/d_fcvt.d.s_b1-01", "2110", - "rv64i_m/D/d_fcvt.d.s_b22-01", "2110", - "rv64i_m/D/d_fcvt.d.s_b23-01", "2110", - "rv64i_m/D/d_fcvt.d.s_b24-01", "2110", - "rv64i_m/D/d_fcvt.d.s_b27-01", "2110", - "rv64i_m/D/d_fcvt.d.s_b28-01", "2110", - "rv64i_m/D/d_fcvt.d.s_b29-01", "2110", - "rv64i_m/D/d_fcvt.d.w_b25-01", "2120", - "rv64i_m/D/d_fcvt.d.w_b26-01", "2220", - "rv64i_m/D/d_fcvt.d.wu_b25-01", "2110", - "rv64i_m/D/d_fcvt.d.wu_b26-01", "2220", - "rv64i_m/D/d_fcvt.l.d_b1-01", "2120", - "rv64i_m/D/d_fcvt.l.d_b22-01", "2260", - "rv64i_m/D/d_fcvt.l.d_b23-01", "2180", - "rv64i_m/D/d_fcvt.l.d_b24-01", "2360", - "rv64i_m/D/d_fcvt.l.d_b27-01", "2110", - "rv64i_m/D/d_fcvt.l.d_b28-01", "2120", - "rv64i_m/D/d_fcvt.l.d_b29-01", "22a0", - "rv64i_m/D/d_fcvt.lu.d_b1-01", "2120", - "rv64i_m/D/d_fcvt.lu.d_b22-01", "2260", - "rv64i_m/D/d_fcvt.lu.d_b23-01", "2180", - "rv64i_m/D/d_fcvt.lu.d_b24-01", "2360", - "rv64i_m/D/d_fcvt.lu.d_b27-01", "2120", - "rv64i_m/D/d_fcvt.lu.d_b28-01", "2120", - "rv64i_m/D/d_fcvt.lu.d_b29-01", "22a0", - "rv64i_m/D/d_fcvt.s.d_b1-01", "2110", - "rv64i_m/D/d_fcvt.s.d_b22-01", "2110", - "rv64i_m/D/d_fcvt.s.d_b23-01", "2180", - "rv64i_m/D/d_fcvt.s.d_b24-01", "2360", - "rv64i_m/D/d_fcvt.s.d_b27-01", "2110", - "rv64i_m/D/d_fcvt.s.d_b28-01", "2110", - "rv64i_m/D/d_fcvt.s.d_b29-01", "22a0", - "rv64i_m/D/d_fcvt.w.d_b1-01", "2120", - "rv64i_m/D/d_fcvt.w.d_b22-01", "2160", - "rv64i_m/D/d_fcvt.w.d_b23-01", "2180", - "rv64i_m/D/d_fcvt.w.d_b24-01", "2360", - "rv64i_m/D/d_fcvt.w.d_b27-01", "2120", - "rv64i_m/D/d_fcvt.w.d_b28-01", "2120", - "rv64i_m/D/d_fcvt.w.d_b29-01", "22a0", - "rv64i_m/D/d_fcvt.wu.d_b1-01", "2120", - "rv64i_m/D/d_fcvt.wu.d_b22-01", "2160", - "rv64i_m/D/d_fcvt.wu.d_b23-01", "2180", - "rv64i_m/D/d_fcvt.wu.d_b24-01", "2360", - "rv64i_m/D/d_fcvt.wu.d_b27-01", "2120", - "rv64i_m/D/d_fcvt.wu.d_b28-01", "2120", - "rv64i_m/D/d_fcvt.wu.d_b29-01", "22a0", - // "rv64i_m/D/d_fdiv_b1-01", "8430", // RV NaNs need to be positive - // "rv64i_m/D/d_fdiv_b20-01", "3fa0", // looks like flags - // "rv64i_m/D/d_fdiv_b2-01", "5170", // also flags - // "rv64i_m/D/d_fdiv_b21-01", "8a70", // positive NaNs again - "rv64i_m/D/d_fdiv_b3-01", "d630", - // "rv64i_m/D/d_fdiv_b4-01", "38f0", // flags - "rv64i_m/D/d_fdiv_b5-01", "3d50", - // "rv64i_m/D/d_fdiv_b6-01", "38f0", // flags - "rv64i_m/D/d_fdiv_b7-01", "5530", - // "rv64i_m/D/d_fdiv_b8-01", "11c10", // flags - // "rv64i_m/D/d_fdiv_b9-01", "1b0f0", might be a flag too - "rv64i_m/D/d_feq_b1-01", "7430", - "rv64i_m/D/d_feq_b19-01", "c4c0", - "rv64i_m/D/d_fld-align-01", "2010", - "rv64i_m/D/d_fle_b1-01", "7430", - "rv64i_m/D/d_fle_b19-01", "c4c0", - "rv64i_m/D/d_flt_b1-01", "7430", - "rv64i_m/D/d_flt_b19-01", "d800", - "rv64i_m/D/d_fmadd_b14-01", "3fd0", - "rv64i_m/D/d_fmadd_b16-01", "43b0", - "rv64i_m/D/d_fmadd_b17-01", "43b0", - "rv64i_m/D/d_fmadd_b18-01", "5a20", - "rv64i_m/D/d_fmadd_b2-01", "5ab0", - "rv64i_m/D/d_fmadd_b3-01", "119d0", - "rv64i_m/D/d_fmadd_b4-01", "3df0", - "rv64i_m/D/d_fmadd_b5-01", "4480", - "rv64i_m/D/d_fmadd_b6-01", "3df0", - "rv64i_m/D/d_fmadd_b7-01", "6050", - "rv64i_m/D/d_fmadd_b8-01", "15aa0", - "rv64i_m/D/d_fmax_b1-01", "8430", - "rv64i_m/D/d_fmax_b19-01", "d5c0", - "rv64i_m/D/d_fmin_b1-01", "8430", - "rv64i_m/D/d_fmin_b19-01", "d4b0", - "rv64i_m/D/d_fmsub_b14-01", "3fd0", - "rv64i_m/D/d_fmsub_b16-01", "43b0", - "rv64i_m/D/d_fmsub_b17-01", "43b0", - "rv64i_m/D/d_fmsub_b18-01", "5a20", - "rv64i_m/D/d_fmsub_b2-01", "5ab0", - "rv64i_m/D/d_fmsub_b3-01", "119f0", - "rv64i_m/D/d_fmsub_b4-01", "3df0", - "rv64i_m/D/d_fmsub_b5-01", "4480", - "rv64i_m/D/d_fmsub_b6-01", "3df0", - "rv64i_m/D/d_fmsub_b7-01", "6050", - "rv64i_m/D/d_fmsub_b8-01", "15aa0", - "rv64i_m/D/d_fmul_b1-01", "8430", - "rv64i_m/D/d_fmul_b2-01", "5180", - "rv64i_m/D/d_fmul_b3-01", "d640", - "rv64i_m/D/d_fmul_b4-01", "38f0", - "rv64i_m/D/d_fmul_b5-01", "3d50", - "rv64i_m/D/d_fmul_b6-01", "38f0", - "rv64i_m/D/d_fmul_b7-01", "5540", - "rv64i_m/D/d_fmul_b8-01", "11c10", - "rv64i_m/D/d_fmul_b9-01", "1b0f0", - "rv64i_m/D/d_fmv.d.x_b25-01", "2110", - "rv64i_m/D/d_fmv.d.x_b26-01", "2220", - "rv64i_m/D/d_fmv.x.d_b1-01", "2120", - "rv64i_m/D/d_fmv.x.d_b22-01", "2110", - "rv64i_m/D/d_fmv.x.d_b23-01", "2110", - "rv64i_m/D/d_fmv.x.d_b24-01", "2120", - "rv64i_m/D/d_fmv.x.d_b27-01", "2120", - "rv64i_m/D/d_fmv.x.d_b28-01", "2110", - "rv64i_m/D/d_fmv.x.d_b29-01", "2120", - "rv64i_m/D/d_fnmadd_b14-01", "3fd0", - "rv64i_m/D/d_fnmadd_b16-01", "4390", - "rv64i_m/D/d_fnmadd_b17-01", "4390", - "rv64i_m/D/d_fnmadd_b18-01", "5a20", - "rv64i_m/D/d_fnmadd_b2-01", "5ab0", - "rv64i_m/D/d_fnmadd_b3-01", "119d0", - "rv64i_m/D/d_fnmadd_b4-01", "3df0", - "rv64i_m/D/d_fnmadd_b5-01", "4480", - "rv64i_m/D/d_fnmadd_b6-01", "3df0", - "rv64i_m/D/d_fnmadd_b7-01", "6050", - "rv64i_m/D/d_fnmadd_b8-01", "15aa0", - "rv64i_m/D/d_fnmsub_b14-01", "3fd0", - "rv64i_m/D/d_fnmsub_b16-01", "4390", - "rv64i_m/D/d_fnmsub_b17-01", "4390", - "rv64i_m/D/d_fnmsub_b18-01", "5a20", - "rv64i_m/D/d_fnmsub_b2-01", "5aa0", - "rv64i_m/D/d_fnmsub_b3-01", "119d0", - "rv64i_m/D/d_fnmsub_b4-01", "3e20", - "rv64i_m/D/d_fnmsub_b5-01", "4480", - "rv64i_m/D/d_fnmsub_b6-01", "3e10", - "rv64i_m/D/d_fnmsub_b7-01", "6050", - "rv64i_m/D/d_fnmsub_b8-01", "15aa0", - "rv64i_m/D/d_fsd-align-01", "2010", - "rv64i_m/D/d_fsgnj_b1-01", "8430", - "rv64i_m/D/d_fsgnjn_b1-01", "8430", - "rv64i_m/D/d_fsgnjx_b1-01", "8430", - // "rv64i_m/D/d_fsqrt_b1-01", "2110", // flg - // "rv64i_m/D/d_fsqrt_b20-01", "3460", // flg - // "rv64i_m/D/d_fsqrt_b2-01", "2190", // flg - I'm going to stop here with the sqrt - // "rv64i_m/D/d_fsqrt_b3-01", "2120", - // "rv64i_m/D/d_fsqrt_b4-01", "2110", - // "rv64i_m/D/d_fsqrt_b5-01", "2110", - // "rv64i_m/D/d_fsqrt_b7-01", "2110", - // "rv64i_m/D/d_fsqrt_b8-01", "2110", - // "rv64i_m/D/d_fsqrt_b9-01", "4c10", - "rv64i_m/D/d_fsub_b10-01", "8660", - "rv64i_m/D/d_fsub_b1-01", "8440", - "rv64i_m/D/d_fsub_b11-01", "74da0", - "rv64i_m/D/d_fsub_b12-01", "2350", - "rv64i_m/D/d_fsub_b13-01", "3cb0", - "rv64i_m/D/d_fsub_b2-01", "5160", - "rv64i_m/D/d_fsub_b3-01", "d630", - "rv64i_m/D/d_fsub_b4-01", "38f0", - "rv64i_m/D/d_fsub_b5-01", "3d50", - "rv64i_m/D/d_fsub_b7-01", "5530", - "rv64i_m/D/d_fsub_b8-01", "11c10" + "rv64i_m/D/d_fadd_b10-01", + "rv64i_m/D/d_fadd_b1-01", + "rv64i_m/D/d_fadd_b11-01", + "rv64i_m/D/d_fadd_b12-01", + "rv64i_m/D/d_fadd_b13-01", + "rv64i_m/D/d_fadd_b2-01", + "rv64i_m/D/d_fadd_b3-01", + "rv64i_m/D/d_fadd_b4-01", + "rv64i_m/D/d_fadd_b5-01", + "rv64i_m/D/d_fadd_b7-01", + "rv64i_m/D/d_fadd_b8-01", + "rv64i_m/D/d_fclass_b1-01", + "rv64i_m/D/d_fcvt.d.l_b25-01", + "rv64i_m/D/d_fcvt.d.l_b26-01", + "rv64i_m/D/d_fcvt.d.lu_b25-01", + "rv64i_m/D/d_fcvt.d.lu_b26-01", + "rv64i_m/D/d_fcvt.d.s_b1-01", + "rv64i_m/D/d_fcvt.d.s_b22-01", + "rv64i_m/D/d_fcvt.d.s_b23-01", + "rv64i_m/D/d_fcvt.d.s_b24-01", + "rv64i_m/D/d_fcvt.d.s_b27-01", + "rv64i_m/D/d_fcvt.d.s_b28-01", + "rv64i_m/D/d_fcvt.d.s_b29-01", + "rv64i_m/D/d_fcvt.d.w_b25-01", + "rv64i_m/D/d_fcvt.d.w_b26-01", + "rv64i_m/D/d_fcvt.d.wu_b25-01", + "rv64i_m/D/d_fcvt.d.wu_b26-01", + "rv64i_m/D/d_fcvt.l.d_b1-01", + "rv64i_m/D/d_fcvt.l.d_b22-01", + "rv64i_m/D/d_fcvt.l.d_b23-01", + "rv64i_m/D/d_fcvt.l.d_b24-01", + "rv64i_m/D/d_fcvt.l.d_b27-01", + "rv64i_m/D/d_fcvt.l.d_b28-01", + "rv64i_m/D/d_fcvt.l.d_b29-01", + "rv64i_m/D/d_fcvt.lu.d_b1-01", + "rv64i_m/D/d_fcvt.lu.d_b22-01", + "rv64i_m/D/d_fcvt.lu.d_b23-01", + "rv64i_m/D/d_fcvt.lu.d_b24-01", + "rv64i_m/D/d_fcvt.lu.d_b27-01", + "rv64i_m/D/d_fcvt.lu.d_b28-01", + "rv64i_m/D/d_fcvt.lu.d_b29-01", + "rv64i_m/D/d_fcvt.s.d_b1-01", + "rv64i_m/D/d_fcvt.s.d_b22-01", + "rv64i_m/D/d_fcvt.s.d_b23-01", + "rv64i_m/D/d_fcvt.s.d_b24-01", + "rv64i_m/D/d_fcvt.s.d_b27-01", + "rv64i_m/D/d_fcvt.s.d_b28-01", + "rv64i_m/D/d_fcvt.s.d_b29-01", + "rv64i_m/D/d_fcvt.w.d_b1-01", + "rv64i_m/D/d_fcvt.w.d_b22-01", + "rv64i_m/D/d_fcvt.w.d_b23-01", + "rv64i_m/D/d_fcvt.w.d_b24-01", + "rv64i_m/D/d_fcvt.w.d_b27-01", + "rv64i_m/D/d_fcvt.w.d_b28-01", + "rv64i_m/D/d_fcvt.w.d_b29-01", + "rv64i_m/D/d_fcvt.wu.d_b1-01", + "rv64i_m/D/d_fcvt.wu.d_b22-01", + "rv64i_m/D/d_fcvt.wu.d_b23-01", + "rv64i_m/D/d_fcvt.wu.d_b24-01", + "rv64i_m/D/d_fcvt.wu.d_b27-01", + "rv64i_m/D/d_fcvt.wu.d_b28-01", + "rv64i_m/D/d_fcvt.wu.d_b29-01", + // "rv64i_m/D/d_fdiv_b1-01", // RV NaNs need to be positive + // "rv64i_m/D/d_fdiv_b20-01", // looks like flags + // "rv64i_m/D/d_fdiv_b2-01", // also flags + // "rv64i_m/D/d_fdiv_b21-01", // positive NaNs again + "rv64i_m/D/d_fdiv_b3-01", + // "rv64i_m/D/d_fdiv_b4-01", // flags + "rv64i_m/D/d_fdiv_b5-01", + // "rv64i_m/D/d_fdiv_b6-01", // flags + "rv64i_m/D/d_fdiv_b7-01", + // "rv64i_m/D/d_fdiv_b8-01", // flags + // "rv64i_m/D/d_fdiv_b9-01", might be a flag too + "rv64i_m/D/d_feq_b1-01", + "rv64i_m/D/d_feq_b19-01", + "rv64i_m/D/d_fld-align-01", + "rv64i_m/D/d_fle_b1-01", + "rv64i_m/D/d_fle_b19-01", + "rv64i_m/D/d_flt_b1-01", + "rv64i_m/D/d_flt_b19-01", + "rv64i_m/D/d_fmadd_b14-01", + "rv64i_m/D/d_fmadd_b16-01", + "rv64i_m/D/d_fmadd_b17-01", + "rv64i_m/D/d_fmadd_b18-01", + "rv64i_m/D/d_fmadd_b2-01", + "rv64i_m/D/d_fmadd_b3-01", + "rv64i_m/D/d_fmadd_b4-01", + "rv64i_m/D/d_fmadd_b5-01", + "rv64i_m/D/d_fmadd_b6-01", + "rv64i_m/D/d_fmadd_b7-01", + "rv64i_m/D/d_fmadd_b8-01", + "rv64i_m/D/d_fmax_b1-01", + "rv64i_m/D/d_fmax_b19-01", + "rv64i_m/D/d_fmin_b1-01", + "rv64i_m/D/d_fmin_b19-01", + "rv64i_m/D/d_fmsub_b14-01", + "rv64i_m/D/d_fmsub_b16-01", + "rv64i_m/D/d_fmsub_b17-01", + "rv64i_m/D/d_fmsub_b18-01", + "rv64i_m/D/d_fmsub_b2-01", + "rv64i_m/D/d_fmsub_b3-01", + "rv64i_m/D/d_fmsub_b4-01", + "rv64i_m/D/d_fmsub_b5-01", + "rv64i_m/D/d_fmsub_b6-01", + "rv64i_m/D/d_fmsub_b7-01", + "rv64i_m/D/d_fmsub_b8-01", + "rv64i_m/D/d_fmul_b1-01", + "rv64i_m/D/d_fmul_b2-01", + "rv64i_m/D/d_fmul_b3-01", + "rv64i_m/D/d_fmul_b4-01", + "rv64i_m/D/d_fmul_b5-01", + "rv64i_m/D/d_fmul_b6-01", + "rv64i_m/D/d_fmul_b7-01", + "rv64i_m/D/d_fmul_b8-01", + "rv64i_m/D/d_fmul_b9-01", + "rv64i_m/D/d_fmv.d.x_b25-01", + "rv64i_m/D/d_fmv.d.x_b26-01", + "rv64i_m/D/d_fmv.x.d_b1-01", + "rv64i_m/D/d_fmv.x.d_b22-01", + "rv64i_m/D/d_fmv.x.d_b23-01", + "rv64i_m/D/d_fmv.x.d_b24-01", + "rv64i_m/D/d_fmv.x.d_b27-01", + "rv64i_m/D/d_fmv.x.d_b28-01", + "rv64i_m/D/d_fmv.x.d_b29-01", + "rv64i_m/D/d_fnmadd_b14-01", + "rv64i_m/D/d_fnmadd_b16-01", + "rv64i_m/D/d_fnmadd_b17-01", + "rv64i_m/D/d_fnmadd_b18-01", + "rv64i_m/D/d_fnmadd_b2-01", + "rv64i_m/D/d_fnmadd_b3-01", + "rv64i_m/D/d_fnmadd_b4-01", + "rv64i_m/D/d_fnmadd_b5-01", + "rv64i_m/D/d_fnmadd_b6-01", + "rv64i_m/D/d_fnmadd_b7-01", + "rv64i_m/D/d_fnmadd_b8-01", + "rv64i_m/D/d_fnmsub_b14-01", + "rv64i_m/D/d_fnmsub_b16-01", + "rv64i_m/D/d_fnmsub_b17-01", + "rv64i_m/D/d_fnmsub_b18-01", + "rv64i_m/D/d_fnmsub_b2-01", + "rv64i_m/D/d_fnmsub_b3-01", + "rv64i_m/D/d_fnmsub_b4-01", + "rv64i_m/D/d_fnmsub_b5-01", + "rv64i_m/D/d_fnmsub_b6-01", + "rv64i_m/D/d_fnmsub_b7-01", + "rv64i_m/D/d_fnmsub_b8-01", + "rv64i_m/D/d_fsd-align-01", + "rv64i_m/D/d_fsgnj_b1-01", + "rv64i_m/D/d_fsgnjn_b1-01", + "rv64i_m/D/d_fsgnjx_b1-01", + // "rv64i_m/D/d_fsqrt_b1-01", // flg + // "rv64i_m/D/d_fsqrt_b20-01", // flg + // "rv64i_m/D/d_fsqrt_b2-01", // flg - I'm going to stop here with the sqrt + // "rv64i_m/D/d_fsqrt_b3-01", + // "rv64i_m/D/d_fsqrt_b4-01", + // "rv64i_m/D/d_fsqrt_b5-01", + // "rv64i_m/D/d_fsqrt_b7-01", + // "rv64i_m/D/d_fsqrt_b8-01", + // "rv64i_m/D/d_fsqrt_b9-01", + "rv64i_m/D/d_fsub_b10-01", + "rv64i_m/D/d_fsub_b1-01", + "rv64i_m/D/d_fsub_b11-01", + "rv64i_m/D/d_fsub_b12-01", + "rv64i_m/D/d_fsub_b13-01", + "rv64i_m/D/d_fsub_b2-01", + "rv64i_m/D/d_fsub_b3-01", + "rv64i_m/D/d_fsub_b4-01", + "rv64i_m/D/d_fsub_b5-01", + "rv64i_m/D/d_fsub_b7-01", + "rv64i_m/D/d_fsub_b8-01" }; string arch32priv[] = '{ `RISCVARCHTEST, - "rv32i_m/privilege/ebreak", "2070", - "rv32i_m/privilege/ecall", "2070", - "rv32i_m/privilege/misalign-beq-01", "2080", - "rv32i_m/privilege/misalign-bge-01", "2080", - "rv32i_m/privilege/misalign-bgeu-01", "2080", - "rv32i_m/privilege/misalign-blt-01", "2080", - "rv32i_m/privilege/misalign-bltu-01", "2080", - "rv32i_m/privilege/misalign-bne-01", "2080", - "rv32i_m/privilege/misalign-jal-01", "2080", - "rv32i_m/privilege/misalign-lh-01", "2080", - "rv32i_m/privilege/misalign-lhu-01", "2080", - "rv32i_m/privilege/misalign-lw-01", "2080", - "rv32i_m/privilege/misalign-sh-01", "2080", - "rv32i_m/privilege/misalign-sw-01", "2080", - "rv32i_m/privilege/misalign1-jalr-01", "2080", - "rv32i_m/privilege/misalign2-jalr-01", "2080" + "rv32i_m/privilege/ebreak", + "rv32i_m/privilege/ecall", + "rv32i_m/privilege/misalign-beq-01", + "rv32i_m/privilege/misalign-bge-01", + "rv32i_m/privilege/misalign-bgeu-01", + "rv32i_m/privilege/misalign-blt-01", + "rv32i_m/privilege/misalign-bltu-01", + "rv32i_m/privilege/misalign-bne-01", + "rv32i_m/privilege/misalign-jal-01", + "rv32i_m/privilege/misalign-lh-01", + "rv32i_m/privilege/misalign-lhu-01", + "rv32i_m/privilege/misalign-lw-01", + "rv32i_m/privilege/misalign-sh-01", + "rv32i_m/privilege/misalign-sw-01", + "rv32i_m/privilege/misalign1-jalr-01", + "rv32i_m/privilege/misalign2-jalr-01" }; string arch32m[] = '{ `RISCVARCHTEST, - "rv32i_m/M/div-01", "5010", - "rv32i_m/M/divu-01", "5010", - "rv32i_m/M/mul-01", "5010", - "rv32i_m/M/mulh-01", "5010", - "rv32i_m/M/mulhsu-01", "5010", - "rv32i_m/M/mulhu-01", "5010", - "rv32i_m/M/rem-01", "5010", - "rv32i_m/M/remu-01", "5010" + "rv32i_m/M/div-01", + "rv32i_m/M/divu-01", + "rv32i_m/M/mul-01", + "rv32i_m/M/mulh-01", + "rv32i_m/M/mulhsu-01", + "rv32i_m/M/mulhu-01", + "rv32i_m/M/rem-01", + "rv32i_m/M/remu-01" }; string arch32f[] = '{ `RISCVARCHTEST, - "rv32i_m/F/fadd_b1-01", "7220", - "rv32i_m/F/fadd_b10-01", "2270", - "rv32i_m/F/fadd_b11-01", "3fb40", - "rv32i_m/F/fadd_b12-01", "21b0", - "rv32i_m/F/fadd_b13-01", "3660", - "rv32i_m/F/fadd_b2-01", "38b0", - "rv32i_m/F/fadd_b3-01", "b320", - "rv32i_m/F/fadd_b4-01", "3480", - "rv32i_m/F/fadd_b5-01", "3700", - "rv32i_m/F/fadd_b7-01", "3520", - "rv32i_m/F/fadd_b8-01", "104a0", - "rv32i_m/F/fclass_b1-01", "2090", - "rv32i_m/F/fcvt.s.w_b25-01", "20a0", - "rv32i_m/F/fcvt.s.w_b26-01", "3290", - "rv32i_m/F/fcvt.s.wu_b25-01", "20a0", - "rv32i_m/F/fcvt.s.wu_b26-01", "3290", - "rv32i_m/F/fcvt.w.s_b1-01", "2090", - "rv32i_m/F/fcvt.w.s_b22-01", "20b0", - "rv32i_m/F/fcvt.w.s_b23-01", "20c0", - "rv32i_m/F/fcvt.w.s_b24-01", "21b0", - "rv32i_m/F/fcvt.w.s_b27-01", "2090", - "rv32i_m/F/fcvt.w.s_b28-01", "2090", - "rv32i_m/F/fcvt.w.s_b29-01", "2150", - "rv32i_m/F/fcvt.wu.s_b1-01", "2090", - "rv32i_m/F/fcvt.wu.s_b22-01", "20b0", - "rv32i_m/F/fcvt.wu.s_b23-01", "20c0", - "rv32i_m/F/fcvt.wu.s_b24-01", "21b0", - "rv32i_m/F/fcvt.wu.s_b27-01", "2090", - "rv32i_m/F/fcvt.wu.s_b28-01", "2090", - "rv32i_m/F/fcvt.wu.s_b29-01", "2150", - // "rv32i_m/F/fdiv_b1-01", "7220", // NaN i'm going to skip div, probably the same problems as the double version - // "rv32i_m/F/fdiv_b2-01", "2350", - // "rv32i_m/F/fdiv_b20-01", "38c0", - // "rv32i_m/F/fdiv_b21-01", "7540", - // "rv32i_m/F/fdiv_b3-01", "b320", - // "rv32i_m/F/fdiv_b4-01", "3480", - // "rv32i_m/F/fdiv_b5-01", "3700", - // "rv32i_m/F/fdiv_b6-01", "3480", - // "rv32i_m/F/fdiv_b7-01", "3520", - // "rv32i_m/F/fdiv_b8-01", "104a0", - // "rv32i_m/F/fdiv_b9-01", "d960", - "rv32i_m/F/feq_b1-01", "6220", - "rv32i_m/F/feq_b19-01", "a190", - "rv32i_m/F/fle_b1-01", "6220", - "rv32i_m/F/fle_b19-01", "a190", - "rv32i_m/F/flt_b1-01", "6220", - "rv32i_m/F/flt_b19-01", "8ee0", - "rv32i_m/F/flw-align-01", "2010", - "rv32i_m/F/fmadd_b1-01", "96860", - "rv32i_m/F/fmadd_b14-01", "23d0", -// --passes but is timeconsuming "rv32i_m/F/fmadd_b15-01", "19bb30", - "rv32i_m/F/fmadd_b16-01", "39d0", - "rv32i_m/F/fmadd_b17-01", "39d0", - "rv32i_m/F/fmadd_b18-01", "4d10", - "rv32i_m/F/fmadd_b2-01", "4d60", - "rv32i_m/F/fmadd_b3-01", "d4f0", - "rv32i_m/F/fmadd_b4-01", "3700", - "rv32i_m/F/fmadd_b5-01", "3ac0", - "rv32i_m/F/fmadd_b6-01", "3700", - "rv32i_m/F/fmadd_b7-01", "37f0", - "rv32i_m/F/fmadd_b8-01", "13f30", - "rv32i_m/F/fmax_b1-01", "7220", - "rv32i_m/F/fmax_b19-01", "9e00", - "rv32i_m/F/fmin_b1-01", "7220", - "rv32i_m/F/fmin_b19-01", "9f20", - "rv32i_m/F/fmsub_b1-01", "96860", - "rv32i_m/F/fmsub_b14-01", "23d0", - "rv32i_m/F/fmsub_b15-01", "19bb30", - "rv32i_m/F/fmsub_b16-01", "39d0", - "rv32i_m/F/fmsub_b17-01", "39d0", - "rv32i_m/F/fmsub_b18-01", "4d20", - "rv32i_m/F/fmsub_b2-01", "4d60", - "rv32i_m/F/fmsub_b3-01", "d4f0", - "rv32i_m/F/fmsub_b4-01", "3700", - "rv32i_m/F/fmsub_b5-01", "3ac0", - "rv32i_m/F/fmsub_b6-01", "3700", - "rv32i_m/F/fmsub_b7-01", "37f0", - "rv32i_m/F/fmsub_b8-01", "13f30", - "rv32i_m/F/fmul_b1-01", "7220", - "rv32i_m/F/fmul_b2-01", "38c0", - "rv32i_m/F/fmul_b3-01", "b320", - "rv32i_m/F/fmul_b4-01", "3480", - "rv32i_m/F/fmul_b5-01", "3700", - "rv32i_m/F/fmul_b6-01", "3480", - "rv32i_m/F/fmul_b7-01", "3520", - "rv32i_m/F/fmul_b8-01", "104a0", - "rv32i_m/F/fmul_b9-01", "d960", - "rv32i_m/F/fmv.w.x_b25-01", "2090", - "rv32i_m/F/fmv.w.x_b26-01", "2090", - "rv32i_m/F/fmv.x.w_b1-01", "2090", - "rv32i_m/F/fmv.x.w_b22-01", "2090", - "rv32i_m/F/fmv.x.w_b23-01", "2090", - "rv32i_m/F/fmv.x.w_b24-01", "2090", - "rv32i_m/F/fmv.x.w_b27-01", "2090", - "rv32i_m/F/fmv.x.w_b28-01", "2090", - "rv32i_m/F/fmv.x.w_b29-01", "2090", - "rv32i_m/F/fnmadd_b1-01", "96870", - "rv32i_m/F/fnmadd_b14-01", "23d0", -// timeconsuming "rv32i_m/F/fnmadd_b15-01", "19bb40", - "rv32i_m/F/fnmadd_b16-01", "39d0", - "rv32i_m/F/fnmadd_b17-01", "39d0", - "rv32i_m/F/fnmadd_b18-01", "4d10", - "rv32i_m/F/fnmadd_b2-01", "4d60", - "rv32i_m/F/fnmadd_b3-01", "d4f0", - "rv32i_m/F/fnmadd_b4-01", "3700", - "rv32i_m/F/fnmadd_b5-01", "3ac0", - "rv32i_m/F/fnmadd_b6-01", "3700", - "rv32i_m/F/fnmadd_b7-01", "37f0", - "rv32i_m/F/fnmadd_b8-01", "13f30", - "rv32i_m/F/fnmsub_b1-01", "96870", - "rv32i_m/F/fnmsub_b14-01", "23d0", -// timeconsuming "rv32i_m/F/fnmsub_b15-01", "19bb30", - "rv32i_m/F/fnmsub_b16-01", "39d0", - "rv32i_m/F/fnmsub_b17-01", "39d0", - "rv32i_m/F/fnmsub_b18-01", "4d10", - "rv32i_m/F/fnmsub_b2-01", "4d60", - "rv32i_m/F/fnmsub_b3-01", "d4f0", - "rv32i_m/F/fnmsub_b4-01", "3700", - "rv32i_m/F/fnmsub_b5-01", "3ac0", - "rv32i_m/F/fnmsub_b6-01", "3700", - "rv32i_m/F/fnmsub_b7-01", "37f0", - "rv32i_m/F/fnmsub_b8-01", "13f30", - "rv32i_m/F/fsgnj_b1-01", "7220", - "rv32i_m/F/fsgnjn_b1-01", "7220", - "rv32i_m/F/fsgnjx_b1-01", "7220", - // "rv32i_m/F/fsqrt_b1-01", "2090", // flag i am skiping sqrt - // "rv32i_m/F/fsqrt_b2-01", "2090", - // "rv32i_m/F/fsqrt_b20-01", "2090", - // "rv32i_m/F/fsqrt_b3-01", "2090", - // "rv32i_m/F/fsqrt_b4-01", "2090", - // "rv32i_m/F/fsqrt_b5-01", "2090", - // "rv32i_m/F/fsqrt_b7-01", "2090", - // "rv32i_m/F/fsqrt_b8-01", "2090", - // "rv32i_m/F/fsqrt_b9-01", "3310", - "rv32i_m/F/fsub_b1-01", "7220", - "rv32i_m/F/fsub_b10-01", "2250", - "rv32i_m/F/fsub_b11-01", "3fb40", - "rv32i_m/F/fsub_b12-01", "21b0", - "rv32i_m/F/fsub_b13-01", "3660", - "rv32i_m/F/fsub_b2-01", "38b0", - "rv32i_m/F/fsub_b3-01", "b320", - "rv32i_m/F/fsub_b4-01", "3480", - "rv32i_m/F/fsub_b5-01", "3700", - "rv32i_m/F/fsub_b7-01", "3520", - "rv32i_m/F/fsub_b8-01", "104a0", - "rv32i_m/F/fsw-align-01", "2010" + "rv32i_m/F/fadd_b1-01", + "rv32i_m/F/fadd_b10-01", + "rv32i_m/F/fadd_b11-01", + "rv32i_m/F/fadd_b12-01", + "rv32i_m/F/fadd_b13-01", + "rv32i_m/F/fadd_b2-01", + "rv32i_m/F/fadd_b3-01", + "rv32i_m/F/fadd_b4-01", + "rv32i_m/F/fadd_b5-01", + "rv32i_m/F/fadd_b7-01", + "rv32i_m/F/fadd_b8-01", + "rv32i_m/F/fclass_b1-01", + "rv32i_m/F/fcvt.s.w_b25-01", + "rv32i_m/F/fcvt.s.w_b26-01", + "rv32i_m/F/fcvt.s.wu_b25-01", + "rv32i_m/F/fcvt.s.wu_b26-01", + "rv32i_m/F/fcvt.w.s_b1-01", + "rv32i_m/F/fcvt.w.s_b22-01", + "rv32i_m/F/fcvt.w.s_b23-01", + "rv32i_m/F/fcvt.w.s_b24-01", + "rv32i_m/F/fcvt.w.s_b27-01", + "rv32i_m/F/fcvt.w.s_b28-01", + "rv32i_m/F/fcvt.w.s_b29-01", + "rv32i_m/F/fcvt.wu.s_b1-01", + "rv32i_m/F/fcvt.wu.s_b22-01", + "rv32i_m/F/fcvt.wu.s_b23-01", + "rv32i_m/F/fcvt.wu.s_b24-01", + "rv32i_m/F/fcvt.wu.s_b27-01", + "rv32i_m/F/fcvt.wu.s_b28-01", + "rv32i_m/F/fcvt.wu.s_b29-01", + // "rv32i_m/F/fdiv_b1-01", // NaN i'm going to skip div, probably the same problems as the double version + // "rv32i_m/F/fdiv_b2-01", + // "rv32i_m/F/fdiv_b20-01", + // "rv32i_m/F/fdiv_b21-01", + // "rv32i_m/F/fdiv_b3-01", + // "rv32i_m/F/fdiv_b4-01", + // "rv32i_m/F/fdiv_b5-01", + // "rv32i_m/F/fdiv_b6-01", + // "rv32i_m/F/fdiv_b7-01", + // "rv32i_m/F/fdiv_b8-01", + // "rv32i_m/F/fdiv_b9-01", + "rv32i_m/F/feq_b1-01", + "rv32i_m/F/feq_b19-01", + "rv32i_m/F/fle_b1-01", + "rv32i_m/F/fle_b19-01", + "rv32i_m/F/flt_b1-01", + "rv32i_m/F/flt_b19-01", + "rv32i_m/F/flw-align-01", + "rv32i_m/F/fmadd_b1-01", + "rv32i_m/F/fmadd_b14-01", +// --passes but is timeconsuming "rv32i_m/F/fmadd_b15-01", + "rv32i_m/F/fmadd_b16-01", + "rv32i_m/F/fmadd_b17-01", + "rv32i_m/F/fmadd_b18-01", + "rv32i_m/F/fmadd_b2-01", + "rv32i_m/F/fmadd_b3-01", + "rv32i_m/F/fmadd_b4-01", + "rv32i_m/F/fmadd_b5-01", + "rv32i_m/F/fmadd_b6-01", + "rv32i_m/F/fmadd_b7-01", + "rv32i_m/F/fmadd_b8-01", + "rv32i_m/F/fmax_b1-01", + "rv32i_m/F/fmax_b19-01", + "rv32i_m/F/fmin_b1-01", + "rv32i_m/F/fmin_b19-01", + "rv32i_m/F/fmsub_b1-01", + "rv32i_m/F/fmsub_b14-01", + "rv32i_m/F/fmsub_b15-01", + "rv32i_m/F/fmsub_b16-01", + "rv32i_m/F/fmsub_b17-01", + "rv32i_m/F/fmsub_b18-01", + "rv32i_m/F/fmsub_b2-01", + "rv32i_m/F/fmsub_b3-01", + "rv32i_m/F/fmsub_b4-01", + "rv32i_m/F/fmsub_b5-01", + "rv32i_m/F/fmsub_b6-01", + "rv32i_m/F/fmsub_b7-01", + "rv32i_m/F/fmsub_b8-01", + "rv32i_m/F/fmul_b1-01", + "rv32i_m/F/fmul_b2-01", + "rv32i_m/F/fmul_b3-01", + "rv32i_m/F/fmul_b4-01", + "rv32i_m/F/fmul_b5-01", + "rv32i_m/F/fmul_b6-01", + "rv32i_m/F/fmul_b7-01", + "rv32i_m/F/fmul_b8-01", + "rv32i_m/F/fmul_b9-01", + "rv32i_m/F/fmv.w.x_b25-01", + "rv32i_m/F/fmv.w.x_b26-01", + "rv32i_m/F/fmv.x.w_b1-01", + "rv32i_m/F/fmv.x.w_b22-01", + "rv32i_m/F/fmv.x.w_b23-01", + "rv32i_m/F/fmv.x.w_b24-01", + "rv32i_m/F/fmv.x.w_b27-01", + "rv32i_m/F/fmv.x.w_b28-01", + "rv32i_m/F/fmv.x.w_b29-01", + "rv32i_m/F/fnmadd_b1-01", + "rv32i_m/F/fnmadd_b14-01", +// timeconsuming "rv32i_m/F/fnmadd_b15-01", + "rv32i_m/F/fnmadd_b16-01", + "rv32i_m/F/fnmadd_b17-01", + "rv32i_m/F/fnmadd_b18-01", + "rv32i_m/F/fnmadd_b2-01", + "rv32i_m/F/fnmadd_b3-01", + "rv32i_m/F/fnmadd_b4-01", + "rv32i_m/F/fnmadd_b5-01", + "rv32i_m/F/fnmadd_b6-01", + "rv32i_m/F/fnmadd_b7-01", + "rv32i_m/F/fnmadd_b8-01", + "rv32i_m/F/fnmsub_b1-01", + "rv32i_m/F/fnmsub_b14-01", +// timeconsuming "rv32i_m/F/fnmsub_b15-01", + "rv32i_m/F/fnmsub_b16-01", + "rv32i_m/F/fnmsub_b17-01", + "rv32i_m/F/fnmsub_b18-01", + "rv32i_m/F/fnmsub_b2-01", + "rv32i_m/F/fnmsub_b3-01", + "rv32i_m/F/fnmsub_b4-01", + "rv32i_m/F/fnmsub_b5-01", + "rv32i_m/F/fnmsub_b6-01", + "rv32i_m/F/fnmsub_b7-01", + "rv32i_m/F/fnmsub_b8-01", + "rv32i_m/F/fsgnj_b1-01", + "rv32i_m/F/fsgnjn_b1-01", + "rv32i_m/F/fsgnjx_b1-01", + // "rv32i_m/F/fsqrt_b1-01", // flag i am skiping sqrt + // "rv32i_m/F/fsqrt_b2-01", + // "rv32i_m/F/fsqrt_b20-01", + // "rv32i_m/F/fsqrt_b3-01", + // "rv32i_m/F/fsqrt_b4-01", + // "rv32i_m/F/fsqrt_b5-01", + // "rv32i_m/F/fsqrt_b7-01", + // "rv32i_m/F/fsqrt_b8-01", + // "rv32i_m/F/fsqrt_b9-01", + "rv32i_m/F/fsub_b1-01", + "rv32i_m/F/fsub_b10-01", + "rv32i_m/F/fsub_b11-01", + "rv32i_m/F/fsub_b12-01", + "rv32i_m/F/fsub_b13-01", + "rv32i_m/F/fsub_b2-01", + "rv32i_m/F/fsub_b3-01", + "rv32i_m/F/fsub_b4-01", + "rv32i_m/F/fsub_b5-01", + "rv32i_m/F/fsub_b7-01", + "rv32i_m/F/fsub_b8-01", + "rv32i_m/F/fsw-align-01" }; string arch32c[] = '{ `RISCVARCHTEST, - "rv32i_m/C/cadd-01", "4010", - "rv32i_m/C/caddi-01", "3010", - "rv32i_m/C/caddi16sp-01", "2010", - "rv32i_m/C/caddi4spn-01", "2010", - "rv32i_m/C/cand-01", "4010", - "rv32i_m/C/candi-01", "3010", - "rv32i_m/C/cbeqz-01", "3010", - "rv32i_m/C/cbnez-01", "3010", - "rv32i_m/C/cj-01", "3010", - "rv32i_m/C/cjal-01", "3010", - "rv32i_m/C/cjalr-01", "2010", - "rv32i_m/C/cjr-01", "2010", - "rv32i_m/C/cli-01", "2010", - "rv32i_m/C/clui-01", "2010", - "rv32i_m/C/clw-01", "2010", - "rv32i_m/C/clwsp-01", "2010", - "rv32i_m/C/cmv-01", "2010", - "rv32i_m/C/cnop-01", "2010", - "rv32i_m/C/cor-01", "4010", - "rv32i_m/C/cslli-01", "2010", - "rv32i_m/C/csrai-01", "2010", - "rv32i_m/C/csrli-01", "2010", - "rv32i_m/C/csub-01", "4010", - "rv32i_m/C/csw-01", "2010", - "rv32i_m/C/cswsp-01", "2010", - "rv32i_m/C/cxor-01", "4010" + "rv32i_m/C/cadd-01", + "rv32i_m/C/caddi-01", + "rv32i_m/C/caddi16sp-01", + "rv32i_m/C/caddi4spn-01", + "rv32i_m/C/cand-01", + "rv32i_m/C/candi-01", + "rv32i_m/C/cbeqz-01", + "rv32i_m/C/cbnez-01", + "rv32i_m/C/cj-01", + "rv32i_m/C/cjal-01", + "rv32i_m/C/cjalr-01", + "rv32i_m/C/cjr-01", + "rv32i_m/C/cli-01", + "rv32i_m/C/clui-01", + "rv32i_m/C/clw-01", + "rv32i_m/C/clwsp-01", + "rv32i_m/C/cmv-01", + "rv32i_m/C/cnop-01", + "rv32i_m/C/cor-01", + "rv32i_m/C/cslli-01", + "rv32i_m/C/csrai-01", + "rv32i_m/C/csrli-01", + "rv32i_m/C/csub-01", + "rv32i_m/C/csw-01", + "rv32i_m/C/cswsp-01", + "rv32i_m/C/cxor-01" }; string arch32cpriv[] = '{ // `RISCVARCHTEST, - "rv32i_m/C/cebreak-01", "2050" + "rv32i_m/C/cebreak-01" }; string arch32i[] = '{ `RISCVARCHTEST, - "rv32i_m/I/add-01", "5010", - "rv32i_m/I/addi-01", "4010", - "rv32i_m/I/and-01", "5010", - "rv32i_m/I/andi-01", "4010", - "rv32i_m/I/auipc-01", "2010", - "rv32i_m/I/beq-01", "39010", - "rv32i_m/I/bge-01", "3a010", - "rv32i_m/I/bgeu-01", "4a010", - "rv32i_m/I/blt-01", "38010", - "rv32i_m/I/bltu-01", "4b010", - "rv32i_m/I/bne-01", "39010", - "rv32i_m/I/fence-01", "2010", - "rv32i_m/I/jal-01", "1ad010", - "rv32i_m/I/jalr-01", "2010", - "rv32i_m/I/lb-align-01", "2010", - "rv32i_m/I/lbu-align-01", "2010", - "rv32i_m/I/lh-align-01", "2010", - "rv32i_m/I/lhu-align-01", "2010", - "rv32i_m/I/lui-01", "2010", - "rv32i_m/I/lw-align-01", "2010", - "rv32i_m/I/or-01", "5010", - "rv32i_m/I/ori-01", "4010", - "rv32i_m/I/sb-align-01", "2010", - "rv32i_m/I/sh-align-01", "2010", - "rv32i_m/I/sll-01", "2010", - "rv32i_m/I/slli-01", "2010", - "rv32i_m/I/slt-01", "5010", - "rv32i_m/I/slti-01", "4010", - "rv32i_m/I/sltiu-01", "4010", - "rv32i_m/I/sltu-01", "5010", - "rv32i_m/I/sra-01", "2010", - "rv32i_m/I/srai-01", "2010", - "rv32i_m/I/srl-01", "2010", - "rv32i_m/I/srli-01", "2010", - "rv32i_m/I/sub-01", "5010", - "rv32i_m/I/sw-align-01", "2010", - "rv32i_m/I/xor-01", "5010", - "rv32i_m/I/xori-01", "4010" + "rv32i_m/I/add-01", + "rv32i_m/I/addi-01", + "rv32i_m/I/and-01", + "rv32i_m/I/andi-01", + "rv32i_m/I/auipc-01", + "rv32i_m/I/beq-01", + "rv32i_m/I/bge-01", + "rv32i_m/I/bgeu-01", + "rv32i_m/I/blt-01", + "rv32i_m/I/bltu-01", + "rv32i_m/I/bne-01", + "rv32i_m/I/fence-01", + "rv32i_m/I/jal-01", + "rv32i_m/I/jalr-01", + "rv32i_m/I/lb-align-01", + "rv32i_m/I/lbu-align-01", + "rv32i_m/I/lh-align-01", + "rv32i_m/I/lhu-align-01", + "rv32i_m/I/lui-01", + "rv32i_m/I/lw-align-01", + "rv32i_m/I/or-01", + "rv32i_m/I/ori-01", + "rv32i_m/I/sb-align-01", + "rv32i_m/I/sh-align-01", + "rv32i_m/I/sll-01", + "rv32i_m/I/slli-01", + "rv32i_m/I/slt-01", + "rv32i_m/I/slti-01", + "rv32i_m/I/sltiu-01", + "rv32i_m/I/sltu-01", + "rv32i_m/I/sra-01", + "rv32i_m/I/srai-01", + "rv32i_m/I/srl-01", + "rv32i_m/I/srli-01", + "rv32i_m/I/sub-01", + "rv32i_m/I/sw-align-01", + "rv32i_m/I/xor-01", + "rv32i_m/I/xori-01" }; string wally64i[] = '{ `WALLYTEST, - "rv64i_m/I/WALLY-ADD", "002010", - "rv64i_m/I/WALLY-SLT", "002010", - "rv64i_m/I/WALLY-SLTU", "002010", - "rv64i_m/I/WALLY-SUB", "002010", - "rv64i_m/I/WALLY-XOR", "002010" + "rv64i_m/I/WALLY-ADD", + "rv64i_m/I/WALLY-SLT", + "rv64i_m/I/WALLY-SLTU", + "rv64i_m/I/WALLY-SUB", + "rv64i_m/I/WALLY-XOR" }; string wally64priv[] = '{ `WALLYTEST, - "rv64i_m/privilege/WALLY-status-tw-01", "0050a0", - "rv64i_m/privilege/WALLY-csr-permission-s-01", "0060a0", - "rv64i_m/privilege/WALLY-csr-permission-u-01", "0060a0", - "rv64i_m/privilege/WALLY-minfo-01", "0050a0", - "rv64i_m/privilege/WALLY-misa-01", "0050a0", - "rv64i_m/privilege/WALLY-mmu-sv39", "0050a0", - "rv64i_m/privilege/WALLY-mmu-sv48", "0050a0", - "rv64i_m/privilege/WALLY-pma", "0050a0", - "rv64i_m/privilege/WALLY-pmp", "0050a0", - "rv64i_m/privilege/WALLY-trap-01", "0050a0", - "rv64i_m/privilege/WALLY-trap-s-01", "0050a0", - "rv64i_m/privilege/WALLY-trap-u-01", "0050a0", - "rv64i_m/privilege/WALLY-mie-01", "0050a0", - "rv64i_m/privilege/WALLY-sie-01", "0050a0", - "rv64i_m/privilege/WALLY-mtvec-01", "0050a0", - "rv64i_m/privilege/WALLY-stvec-01", "0050a0", - "rv64i_m/privilege/WALLY-status-mie-01", "0050a0", - "rv64i_m/privilege/WALLY-status-sie-01", "0050a0", - "rv64i_m/privilege/WALLY-trap-sret-01", "0050a0", - "rv64i_m/privilege/WALLY-status-tw-01", "0050a0", - "rv64i_m/privilege/WALLY-wfi-01", "0050a0" + "rv64i_m/privilege/WALLY-status-tw-01", + "rv64i_m/privilege/WALLY-csr-permission-s-01", + "rv64i_m/privilege/WALLY-csr-permission-u-01", + "rv64i_m/privilege/WALLY-minfo-01", + "rv64i_m/privilege/WALLY-misa-01", + "rv64i_m/privilege/WALLY-mmu-sv39", + "rv64i_m/privilege/WALLY-mmu-sv48", + "rv64i_m/privilege/WALLY-pma", + "rv64i_m/privilege/WALLY-pmp", + "rv64i_m/privilege/WALLY-trap-01", + "rv64i_m/privilege/WALLY-trap-s-01", + "rv64i_m/privilege/WALLY-trap-u-01", + "rv64i_m/privilege/WALLY-mie-01", + "rv64i_m/privilege/WALLY-sie-01", + "rv64i_m/privilege/WALLY-mtvec-01", + "rv64i_m/privilege/WALLY-stvec-01", + "rv64i_m/privilege/WALLY-status-mie-01", + "rv64i_m/privilege/WALLY-status-sie-01", + "rv64i_m/privilege/WALLY-trap-sret-01", + "rv64i_m/privilege/WALLY-status-tw-01", + "rv64i_m/privilege/WALLY-wfi-01" }; string wally64periph[] = '{ `WALLYTEST, - "rv64i_m/privilege/WALLY-periph", "3310" + "rv64i_m/privilege/WALLY-periph" }; string wally32e[] = '{ `WALLYTEST, - "rv32i_m/I/E-add-01", "005010", - "rv32i_m/I/E-addi-01", "004010", - "rv32i_m/I/E-and-01", "005010", - "rv32i_m/I/E-andi-01", "004010", - "rv32i_m/I/E-auipc-01", "002010", - "rv32i_m/I/E-bge-01", "034010", - "rv32i_m/I/E-bgeu-01", "047010", - "rv32i_m/I/E-blt-01", "038010", - "rv32i_m/I/E-bltu-01", "03e010", - "rv32i_m/I/E-bne-01", "038010", - "rv32i_m/I/E-jal-01", "e02010", - "rv32i_m/I/E-jalr-01", "002010", - "rv32i_m/I/E-lb-align-01", "002010", - "rv32i_m/I/E-lbu-align-01", "002010", - "rv32i_m/I/E-lh-align-01", "002010", - "rv32i_m/I/E-lhu-align-01", "002010", - "rv32i_m/I/E-lui-01", "002010", - "rv32i_m/I/E-lw-align-01", "002010", - "rv32i_m/I/E-or-01", "005010", - "rv32i_m/I/E-ori-01", "004010", - "rv32i_m/I/E-sb-align-01", "002010", - "rv32i_m/I/E-sh-align-01", "002010", - "rv32i_m/I/E-sll-01", "002010", - "rv32i_m/I/E-slli-01", "002010", - "rv32i_m/I/E-slt-01", "005010", - "rv32i_m/I/E-slti-01", "004010", - "rv32i_m/I/E-sltiu-01", "004010", - "rv32i_m/I/E-sltu-01", "005010", - "rv32i_m/I/E-sra-01", "002010", - "rv32i_m/I/E-srai-01", "002010", - "rv32i_m/I/E-srl-01", "002010", - "rv32i_m/I/E-srli-01", "002010", - "rv32i_m/I/E-sub-01", "005010", - "rv32i_m/I/E-sw-align-01", "002010", - "rv32i_m/I/E-xor-01", "005010", - "rv32i_m/I/E-xori-01", "004010" + "rv32i_m/I/E-add-01", + "rv32i_m/I/E-addi-01", + "rv32i_m/I/E-and-01", + "rv32i_m/I/E-andi-01", + "rv32i_m/I/E-auipc-01", + "rv32i_m/I/E-bge-01", + "rv32i_m/I/E-bgeu-01", + "rv32i_m/I/E-blt-01", + "rv32i_m/I/E-bltu-01", + "rv32i_m/I/E-bne-01", + "rv32i_m/I/E-jal-01", + "rv32i_m/I/E-jalr-01", + "rv32i_m/I/E-lb-align-01", + "rv32i_m/I/E-lbu-align-01", + "rv32i_m/I/E-lh-align-01", + "rv32i_m/I/E-lhu-align-01", + "rv32i_m/I/E-lui-01", + "rv32i_m/I/E-lw-align-01", + "rv32i_m/I/E-or-01", + "rv32i_m/I/E-ori-01", + "rv32i_m/I/E-sb-align-01", + "rv32i_m/I/E-sh-align-01", + "rv32i_m/I/E-sll-01", + "rv32i_m/I/E-slli-01", + "rv32i_m/I/E-slt-01", + "rv32i_m/I/E-slti-01", + "rv32i_m/I/E-sltiu-01", + "rv32i_m/I/E-sltu-01", + "rv32i_m/I/E-sra-01", + "rv32i_m/I/E-srai-01", + "rv32i_m/I/E-srl-01", + "rv32i_m/I/E-srli-01", + "rv32i_m/I/E-sub-01", + "rv32i_m/I/E-sw-align-01", + "rv32i_m/I/E-xor-01", + "rv32i_m/I/E-xori-01" }; string wally32i[] = '{ `WALLYTEST, - "rv32i_m/I/WALLY-ADD", "002010", - "rv32i_m/I/WALLY-SLT", "002010", - "rv32i_m/I/WALLY-SLTU", "002010", - "rv32i_m/I/WALLY-SUB", "002010", - "rv32i_m/I/WALLY-XOR", "002010" + "rv32i_m/I/WALLY-ADD", + "rv32i_m/I/WALLY-SLT", + "rv32i_m/I/WALLY-SLTU", + "rv32i_m/I/WALLY-SUB", + "rv32i_m/I/WALLY-XOR" }; string wally32priv[] = '{ `WALLYTEST, - "rv32i_m/privilege/WALLY-csr-permission-s-01", "6080", - "rv32i_m/privilege/WALLY-csr-permission-u-01", "6080", - "rv32i_m/privilege/WALLY-minfo-01", "5080", - "rv32i_m/privilege/WALLY-misa-01", "5080", - "rv32i_m/privilege/WALLY-mmu-sv32", "5080", - "rv32i_m/privilege/WALLY-pma", "5080", - "rv32i_m/privilege/WALLY-pmp", "5080", - "rv32i_m/privilege/WALLY-trap-01", "5080", - "rv32i_m/privilege/WALLY-trap-s-01", "5080", - "rv32i_m/privilege/WALLY-trap-u-01", "5080", - "rv32i_m/privilege/WALLY-mie-01", "5080", - "rv32i_m/privilege/WALLY-sie-01", "5080", - "rv32i_m/privilege/WALLY-mtvec-01", "5080", - "rv32i_m/privilege/WALLY-stvec-01", "5080", - "rv32i_m/privilege/WALLY-status-mie-01", "5080", - "rv32i_m/privilege/WALLY-status-sie-01", "5080", - "rv32i_m/privilege/WALLY-trap-sret-01", "5080", - "rv32i_m/privilege/WALLY-status-tw-01", "5080", - "rv32i_m/privilege/WALLY-wfi-01", "5080" + "rv32i_m/privilege/WALLY-csr-permission-s-01", + "rv32i_m/privilege/WALLY-csr-permission-u-01", + "rv32i_m/privilege/WALLY-minfo-01", + "rv32i_m/privilege/WALLY-misa-01", + "rv32i_m/privilege/WALLY-mmu-sv32", + "rv32i_m/privilege/WALLY-pma", + "rv32i_m/privilege/WALLY-pmp", + "rv32i_m/privilege/WALLY-trap-01", + "rv32i_m/privilege/WALLY-trap-s-01", + "rv32i_m/privilege/WALLY-trap-u-01", + "rv32i_m/privilege/WALLY-mie-01", + "rv32i_m/privilege/WALLY-sie-01", + "rv32i_m/privilege/WALLY-mtvec-01", + "rv32i_m/privilege/WALLY-stvec-01", + "rv32i_m/privilege/WALLY-status-mie-01", + "rv32i_m/privilege/WALLY-status-sie-01", + "rv32i_m/privilege/WALLY-trap-sret-01", + "rv32i_m/privilege/WALLY-status-tw-01", + "rv32i_m/privilege/WALLY-wfi-01" }; string wally32periph[] = '{ From 0e308cfcccc8354e087c1c5c86fa15187fdfd266 Mon Sep 17 00:00:00 2001 From: cturek Date: Sat, 4 Jun 2022 00:14:10 +0000 Subject: [PATCH 2/7] Added integer division in srt, parametrized everything to work with integers and floating points, parametrized testbench. --- pipelined/srt/srt.do | 2 +- pipelined/srt/srt.sv | 208 +++++++++++++++++++------------------ pipelined/srt/testbench.sv | 27 +++-- 3 files changed, 122 insertions(+), 115 deletions(-) diff --git a/pipelined/srt/srt.do b/pipelined/srt/srt.do index 8be358057..6097cf47d 100644 --- a/pipelined/srt/srt.do +++ b/pipelined/srt/srt.do @@ -17,7 +17,7 @@ if [file exists work] { } vlib work -vlog +incdir+../config/rv64gc +incdir+../config/shared srt.sv testbench.sv ../src/generic/flop/flop*.sv ../src/generic/mux.sv +vlog +incdir+../config/rv64gc +incdir+../config/shared srt.sv testbench.sv ../src/generic/flop/flop*.sv ../src/generic/mux.sv ../src/generic/lzc.sv vopt +acc work.testbench -o workopt vsim workopt diff --git a/pipelined/srt/srt.sv b/pipelined/srt/srt.sv index 2275b93ed..e40f27589 100644 --- a/pipelined/srt/srt.sv +++ b/pipelined/srt/srt.sv @@ -30,7 +30,11 @@ `include "wally-config.vh" -module srt #(parameter Nf=52) ( +`define DIVLEN ((`NF<(`XLEN+1)) ? (`XLEN + 1) : `NF) +`define EXTRAFRACBITS ((`NF<(`XLEN+1)) ? (`XLEN - `NF + 1) : 0) +`define EXTRAINTBITS ((`NF<(`XLEN+1)) ? 0 : (`NF - `XLEN)) + +module srt ( input logic clk, input logic Start, input logic Stall, // *** multiple pipe stages @@ -39,7 +43,7 @@ module srt #(parameter Nf=52) ( // later add exponents, signs, special cases input logic XSign, YSign, input logic [`NE-1:0] XExp, YExp, - input logic [Nf-1:0] SrcXFrac, SrcYFrac, + input logic [`NF-1:0] SrcXFrac, SrcYFrac, input logic [`XLEN-1:0] SrcA, SrcB, input logic [1:0] Fmt, // Floats: 00 = 16 bit, 01 = 32 bit, 10 = 64 bit, 11 = 128 bit input logic W64, // 32-bit ints on XLEN=64 @@ -47,7 +51,7 @@ module srt #(parameter Nf=52) ( input logic Int, // Choose integer inputs input logic Sqrt, // perform square root, not divide output logic rsign, - output logic [Nf-1:0] Quot, Rem, QuotOTFC, // *** later handle integers + output logic [`DIVLEN-1:0] Quot, Rem, QuotOTFC, // *** later handle integers output logic [`NE-1:0] rExp, output logic [3:0] Flags ); @@ -55,38 +59,40 @@ module srt #(parameter Nf=52) ( logic qp, qz, qm; // quotient is +1, 0, or -1 logic [`NE-1:0] calcExp; logic calcSign; - logic [Nf-1:0] X, Dpreproc; - logic [Nf+3:0] WS, WSA, WSN, WC, WCA, WCN, D, Db, Dsel; - logic [Nf+2:0] rp, rm; + logic [`DIVLEN-1:0] X, Dpreproc; + logic [`DIVLEN+3:0] WS, WSA, WSN, WC, WCA, WCN, D, Db, Dsel; + logic [`DIVLEN+2:0] rp, rm; + logic [$clog2(`XLEN+1)-1:0] intExp; + logic intSign; - srtpreproc #(Nf) preproc(SrcA, SrcB, SrcXFrac, SrcYFrac, Fmt, W64, Signed, Int, Sqrt, X, Dpreproc); + srtpreproc preproc(SrcA, SrcB, SrcXFrac, SrcYFrac, Fmt, W64, Signed, Int, Sqrt, X, Dpreproc, intExp, intSign); // Top Muxes and Registers // When start is asserted, the inputs are loaded into the divider. // Otherwise, the divisor is retained and the partial remainder // is fed back for the next iteration. - mux2 #(Nf+4) wsmux({WSA[54:0], 1'b0}, {4'b0001, X}, Start, WSN); - flop #(Nf+4) wsflop(clk, WSN, WS); - mux2 #(Nf+4) wcmux({WCA[54:0], 1'b0}, 56'b0, Start, WCN); - flop #(Nf+4) wcflop(clk, WCN, WC); - flopen #(Nf+4) dflop(clk, Start, {4'b0001, Dpreproc}, D); + mux2 #(`DIVLEN+4) wsmux({WSA[`DIVLEN+2:0], 1'b0}, {4'b0001, X}, Start, WSN); + flop #(`DIVLEN+4) wsflop(clk, WSN, WS); + mux2 #(`DIVLEN+4) wcmux({WCA[`DIVLEN+2:0], 1'b0}, {(`DIVLEN+4){1'b0}}, Start, WCN); + flop #(`DIVLEN+4) wcflop(clk, WCN, WC); + flopen #(`DIVLEN+4) dflop(clk, Start, {4'b0001, Dpreproc}, D); // Quotient Selection logic // Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm) - // Accumulate quotient digits in a shift register - qsel #(Nf) qsel(WS[55:52], WC[55:52], qp, qz, qm); - qacc #(Nf+3) qacc(clk, Start, qp, qz, qm, rp, rm); + qsel2 qsel2(WS[`DIVLEN+3:`DIVLEN], WC[`DIVLEN+3:`DIVLEN], qp, qz, qm); + // Accumulate quotient digits in a shift register (now done in OTFC) + qacc #(`DIVLEN+3) qacc(clk, Start, qp, qz, qm, rp, rm); flopen #(`NE) expflop(clk, Start, calcExp, rExp); flopen #(1) signflop(clk, Start, calcSign, rsign); // Divisor Selection logic inv dinv(D, Db); - mux3onehot divisorsel(Db, 56'b0, D, qp, qz, qm, Dsel); + mux3onehot #(`DIVLEN) divisorsel(Db, {(`DIVLEN+4){1'b0}}, D, qp, qz, qm, Dsel); // Partial Product Generation - csa csa(WS, WC, Dsel, qp, WSA, WCA); + csa #(`DIVLEN+4) csa(WS, WC, Dsel, qp, WSA, WCA); - otfc2 otfc2(clk, Start, qp, qz, qm, QuotOTFC); + otfc2 #(`DIVLEN) otfc2(clk, Start, qp, qz, qm, QuotOTFC); expcalc expcalc(.XExp, .YExp, .calcExp); @@ -95,70 +101,60 @@ module srt #(parameter Nf=52) ( srtpostproc postproc(rp, rm, Quot); endmodule -module srtpostproc #(parameter N=52) ( - input [N+2:0] rp, rm, - output [N-1:0] Quot -); +//////////////// +// Submodules // +//////////////// - //assign Quot = rp - rm; - finaladd finaladd(rp, rm, Quot); -endmodule - -module srtpreproc #(parameter Nf=52) ( +/////////////////// +// Preprocessing // +/////////////////// +module srtpreproc ( input logic [`XLEN-1:0] SrcA, SrcB, - input logic [Nf-1:0] SrcXFrac, SrcYFrac, + input logic [`NF-1:0] SrcXFrac, SrcYFrac, input logic [1:0] Fmt, // Floats: 00 = 16 bit, 01 = 32 bit, 10 = 64 bit, 11 = 128 bit input logic W64, // 32-bit ints on XLEN=64 input logic Signed, // Interpret integers as signed 2's complement - input logic Int, // Choose integer inputss + input logic Int, // Choose integer inputs input logic Sqrt, // perform square root, not divide - output logic [Nf-1:0] X, D + output logic [`DIVLEN-1:0] X, D, + output logic [$clog2(`XLEN+1)-1:0] intExp, // Quotient integer exponent + output logic intSign // Quotient integer sign ); - // Initial: just pass X and Y through for simple fp division - assign X = SrcXFrac; - assign D = SrcYFrac; + logic [$clog2(`XLEN+1)-1:0] zeroCntA, zeroCntB; + logic [`XLEN-1:0] PosA, PosB; + logic [`DIVLEN-1:0] ExtraA, ExtraB, PreprocA, PreprocB, PreprocX, PreprocY; + + assign PosA = (Signed & SrcA[`XLEN - 1]) ? -SrcA : SrcA; + assign PosB = (Signed & SrcB[`XLEN - 1]) ? -SrcB : SrcB; + + lzc #(`XLEN) lzcA (PosA, zeroCntA); + lzc #(`XLEN) lzcB (PosB, zeroCntB); + + assign ExtraA = {1'b0, PosA, {`EXTRAINTBITS{1'b0}}}; + assign ExtraB = {1'b0, PosB, {`EXTRAINTBITS{1'b0}}}; + + assign PreprocA = ExtraA << zeroCntA; + assign PreprocB = ExtraB << (zeroCntB + 1); + assign PreprocX = {SrcXFrac, {`EXTRAFRACBITS{1'b0}}}; + assign PreprocY = {SrcYFrac, {`EXTRAFRACBITS{1'b0}}}; + + + assign X = Int ? PreprocA : PreprocX; + assign D = Int ? PreprocB : PreprocY; + assign intExp = zeroCntB - zeroCntA + 1; + assign intSign = Signed & (SrcA[`XLEN - 1] ^ SrcB[`XLEN - 1]); endmodule -/* - -////////// -// mux2 // -////////// -module mux2(input logic [55:0] in0, in1, - input logic sel, - output logic [55:0] out); - - assign #1 out = sel ? in1 : in0; -endmodule - -////////// -// flop // -////////// -module flop(clk, in, out); - input clk; - input [55:0] in; - output [55:0] out; - - logic [55:0] state; - - always @(posedge clk) - state <= #1 in; - - assign #1 out = state; -endmodule - -*/ - -////////// -// qsel // -////////// -module qsel #(parameter Nf=52) ( // *** eventually just change to 4 bits - input logic [Nf+3:Nf] ps, pc, +///////////////////////////////// +// Quotient Selection, Radix 2 // +///////////////////////////////// +module qsel2 ( // *** eventually just change to 4 bits + input logic [`DIVLEN+3:`DIVLEN] ps, pc, output logic qp, qz, qm ); - logic [Nf+3:Nf] p, g; + logic [`DIVLEN+3:`DIVLEN] p, g; logic magnitude, sign, cout; // The quotient selection logic is presented for simplicity, not @@ -169,9 +165,9 @@ module qsel #(parameter Nf=52) ( // *** eventually just change to 4 bits assign p = ps ^ pc; assign g = ps & pc; - assign #1 magnitude = ~(&p[54:52]); - assign #1 cout = g[54] | (p[54] & (g[53] | p[53] & g[52])); - assign #1 sign = p[55] ^ cout; + assign #1 magnitude = ~(&p[`DIVLEN+2:`DIVLEN]); + assign #1 cout = g[`DIVLEN+2] | (p[`DIVLEN+2] & (g[`DIVLEN+1] | p[`DIVLEN+1] & g[`DIVLEN])); + assign #1 sign = p[`DIVLEN+3] ^ cout; /* assign #1 magnitude = ~((ps[54]^pc[54]) & (ps[53]^pc[53]) & (ps[52]^pc[52])); assign #1 sign = (ps[55]^pc[55])^ @@ -188,15 +184,16 @@ endmodule ////////// // qacc // ////////// -module qacc #(parameter N=55) ( +// To be replaced by OTFC +module qacc #(parameter N=68) ( input logic clk, input logic req, input logic qp, qz, qm, output logic [N-1:0] rp, rm ); - flopr #(N) rmreg(clk, req, {rm[53:0], qm}, rm); - flopr #(N) rpreg(clk, req, {rp[53:0], qp}, rp); + flopr #(N) rmreg(clk, req, {rm[N-2:0], qm}, rm); + flopr #(N) rpreg(clk, req, {rp[N-2:0], qp}, rp); /* always @(posedge clk) begin if (req) @@ -212,11 +209,10 @@ module qacc #(parameter N=55) ( end */ endmodule -////////// -// otfc // -////////// - -module otfc2 #(parameter N=52) ( +/////////////////////////////////// +// On-The-Fly Converter, Radix 2 // +/////////////////////////////////// +module otfc2 #(parameter N=65) ( input logic clk, input logic Start, input logic qp, qz, qm, @@ -255,16 +251,15 @@ module otfc2 #(parameter N=52) ( QMNext = {QMR, 1'b0}; end end - assign r = Q[54] ? Q[53:2] : Q[52:1]; + assign r = Q[N+2] ? Q[N+1:2] : Q[N:1]; endmodule ///////// // inv // ///////// - -module inv(input logic [55:0] in, - output logic [55:0] out); +module inv(input logic [`DIVLEN+3:0] in, + output logic [`DIVLEN+3:0] out); assign #1 out = ~in; endmodule @@ -272,14 +267,11 @@ endmodule ////////// // mux3 // ////////// -module mux3onehot(in0, in1, in2, sel0, sel1, sel2, out); - input [55:0] in0; - input [55:0] in1; - input [55:0] in2; - input sel0; - input sel1; - input sel2; - output [55:0] out; +module mux3onehot #(parameter N=65) ( + input logic [N+3:0] in0, in1, in2, + input logic sel0, sel1, sel2, + output logic [N+3:0] out +); // lazy inspection of the selects // really we should make sure selects are mutually exclusive @@ -290,7 +282,7 @@ endmodule ///////// // csa // ///////// -module csa #(parameter N=56) ( +module csa #(parameter N=69) ( input logic [N-1:0] in1, in2, in3, input logic cin, output logic [N-1:0] out1, out2 @@ -305,28 +297,26 @@ module csa #(parameter N=56) ( // insert cin. assign #1 out1 = in1 ^ in2 ^ in3; - assign #1 out2 = {in1[54:0] & (in2[54:0] | in3[54:0]) | - (in2[54:0] & in3[54:0]), cin}; + assign #1 out2 = {in1[N-2:0] & (in2[N-2:0] | in3[N-2:0]) | + (in2[N-2:0] & in3[N-2:0]), cin}; endmodule ////////////// // expcalc // ////////////// - module expcalc( input logic [`NE-1:0] XExp, YExp, output logic [`NE-1:0] calcExp ); - assign calcExp = XExp - YExp + 11'b01111111111; + assign calcExp = XExp - YExp + (`NE)'(`BIAS); endmodule ////////////// // signcalc // ////////////// - module signcalc( input logic XSign, YSign, output logic calcSign @@ -336,15 +326,27 @@ module signcalc( endmodule +//////////////////// +// Postprocessing // +//////////////////// +module srtpostproc ( + input [`DIVLEN+2:0] rp, rm, + output [`DIVLEN-1:0] Quot +); + + //assign Quot = rp - rm; + finaladd #(`DIVLEN+3) finaladd(rp, rm, Quot); +endmodule + ////////////// // finaladd // ////////////// -module finaladd( - input logic [54:0] rp, rm, - output logic [51:0] r +module finaladd #(parameter N=68) ( + input logic [N-1:0] rp, rm, + output logic [N-4:0] r ); - logic [54:0] diff; + logic [N-1:0] diff; // this magic block performs the final addition for you // to convert the positive and negative quotient digits @@ -359,6 +361,6 @@ module finaladd( // The checker ignores such an error. assign #1 diff = rp - rm; - assign #1 r = diff[54] ? diff[53:2] : diff[52:1]; + assign #1 r = diff[N-1] ? diff[N-2:2] : diff[N-3:1]; endmodule diff --git a/pipelined/srt/testbench.sv b/pipelined/srt/testbench.sv index 108b2244b..d4143f20b 100644 --- a/pipelined/srt/testbench.sv +++ b/pipelined/srt/testbench.sv @@ -1,3 +1,5 @@ +`define DIVLEN 65 + ///////////// // counter // ///////////// @@ -37,15 +39,16 @@ endmodule // testbench // ////////// module testbench; - logic clk; - logic req; - logic done; - logic [63:0] a, b; - logic [51:0] afrac, bfrac; - logic [10:0] aExp, bExp; - logic asign, bsign; - logic [51:0] r, rOTFC; - logic [54:0] rp, rm; // positive quotient digits + logic clk; + logic req; + logic done; + logic [63:0] a, b; + logic [51:0] afrac, bfrac; + logic [10:0] aExp, bExp; + logic asign, bsign; + logic [51:0] r, rOTFC; + logic [`DIVLEN-1:0] Quot, QuotOTFC; + logic [54:0] rp, rm; // positive quotient digits // Test parameters parameter MEM_SIZE = 40000; @@ -65,14 +68,14 @@ module testbench; integer testnum, errors; // Divider - srt #(52) srt(.clk, .Start(req), + srt srt(.clk, .Start(req), .Stall(1'b0), .Flush(1'b0), .XExp(aExp), .YExp(bExp), .rExp, .XSign(asign), .YSign(bsign), .rsign, .SrcXFrac(afrac), .SrcYFrac(bfrac), .SrcA('0), .SrcB('0), .Fmt(2'b00), .W64(1'b0), .Signed(1'b0), .Int(1'b0), .Sqrt(1'b0), - .Quot(r), .QuotOTFC(rOTFC), .Rem(), .Flags()); + .Quot, .QuotOTFC, .Rem(), .Flags()); // Counter counter counter(clk, req, done); @@ -98,6 +101,8 @@ module testbench; b = Vec[`memb]; {bsign, bExp, bfrac} = b; nextr = Vec[`memr]; + r = Quot[`DIVLEN:`DIVLEN - 52]; + rOTFC = QuotOTFC[`DIVLEN:`DIVLEN - 52]; req <= #5 1; end From 8c3d7b404bcbae98e3cbbf13c617f6ce098c5bad Mon Sep 17 00:00:00 2001 From: slmnemo Date: Fri, 3 Jun 2022 18:56:24 -0700 Subject: [PATCH 3/7] Fixed recurrent issue with testbench where it would never stop --- pipelined/testbench/testbench-linux.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv index bf87eeb1d..feec46d10 100644 --- a/pipelined/testbench/testbench-linux.sv +++ b/pipelined/testbench/testbench-linux.sv @@ -666,7 +666,7 @@ module testbench; // turn on waves if (AttemptedInstructionCount == INSTR_WAVEON) $stop; // end sim - if ((AttemptedInstructionCount == INSTR_LIMIT) & (INSTR_LIMIT!=0)) $stop; + if ((AttemptedInstructionCount == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $stop; $stop; end fault = 0; if (`DEBUG_TRACE >= 1) begin `checkEQ("PCW",PCW,ExpectedPCW) From 83bca570ae4c451f13f5ceb21b90d1fc09119887 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 4 Jun 2022 14:39:55 -0500 Subject: [PATCH 4/7] Modified debugger for updated rtl. --- fpga/constraints/debug2.xdc | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 85552d6e4..c9345ee16 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -327,7 +327,7 @@ connect_debug_port u_ila_0/probe72 [get_nets [list wallypipelinedsoc/core/hzu/BP create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe73] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe73] -connect_debug_port u_ila_0/probe73 [get_nets [list wallypipelinedsoc/core/hzu/CSRWritePendingDEM ]] +connect_debug_port u_ila_0/probe73 [get_nets [list wallypipelinedsoc/core/hzu/CSRWriteFencePendingDEM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe74] @@ -402,7 +402,7 @@ connect_debug_port u_ila_0/probe87 [get_nets [list wallypipelinedsoc/core/hzu/Br create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe88] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe88] -connect_debug_port u_ila_0/probe88 [get_nets [list wallypipelinedsoc/core/hzu/InvalidateICacheM ]] +connect_debug_port u_ila_0/probe88 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/RXerrIP} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe89] @@ -433,7 +433,8 @@ connect_debug_port u_ila_0/probe93 [get_nets [list wallypipelinedsoc/core/hzu/St create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe94] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe94] -connect_debug_port u_ila_0/probe94 [get_nets [list wallypipelinedsoc/core/hzu/FlushF ]] +connect_debug_port u_ila_0/probe94 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/RXerrIP} ]] + create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe95] @@ -835,8 +836,4 @@ set_property port_width 4 [get_debug_ports u_ila_0/probe171] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe171] connect_debug_port u_ila_0/probe171 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/rxfifotail[0]} {wallypipelinedsoc/uncore/uart.uart/u/rxfifotail[1]} {wallypipelinedsoc/uncore/uart.uart/u/rxfifotail[2]} {wallypipelinedsoc/uncore/uart.uart/u/rxfifotail[3]} ]] -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe172] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe172] -connect_debug_port u_ila_0/probe172 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/RXerrIP} ]] From eb93bd46d71a40671d8c8fafe632855b533df509 Mon Sep 17 00:00:00 2001 From: Katherine Parry Date: Mon, 6 Jun 2022 16:06:04 +0000 Subject: [PATCH 5/7] fma synth warnings and errors removed --- pipelined/config/rv64fp/wally-config.vh | 3 +- pipelined/config/shared/wally-shared.vh | 58 +++--- pipelined/regression/lint-wally | 2 +- pipelined/regression/sim-wally | 2 +- pipelined/src/fpu/fctrl.sv | 2 +- pipelined/src/fpu/fcvt.sv | 39 ++-- pipelined/src/fpu/fma.sv | 20 +- pipelined/src/fpu/fpu.sv | 46 +++-- pipelined/src/fpu/unpack.sv | 10 +- pipelined/testbench/testbench-fp.sv | 232 ++++++++++++------------ 10 files changed, 217 insertions(+), 197 deletions(-) diff --git a/pipelined/config/rv64fp/wally-config.vh b/pipelined/config/rv64fp/wally-config.vh index d7ad9d3c8..dd5a6b492 100644 --- a/pipelined/config/rv64fp/wally-config.vh +++ b/pipelined/config/rv64fp/wally-config.vh @@ -38,7 +38,8 @@ `define IEEE754 0 // MISA RISC-V configuration per specification -`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 ) +// ZYXWVUTSRQPONMLKJIHGFEDCBA +`define MISA 32'b0000000000101000001000100101101 `define ZICSR_SUPPORTED 1 `define ZIFENCEI_SUPPORTED 1 `define COUNTERS 32 diff --git a/pipelined/config/shared/wally-shared.vh b/pipelined/config/shared/wally-shared.vh index 7d1ad1129..e2d5cf75e 100644 --- a/pipelined/config/shared/wally-shared.vh +++ b/pipelined/config/shared/wally-shared.vh @@ -51,43 +51,45 @@ `define PMPCFG_ENTRIES (`PMP_ENTRIES/8) // Floating point constants for Quad, Double, Single, and Half precisions -`define Q_LEN 128 -`define Q_NE 15 -`define Q_NF 112 -`define Q_BIAS 16383 -`define D_LEN 64 -`define D_NE 11 -`define D_NF 52 -`define D_BIAS 1023 -`define S_LEN 32 -`define S_NE 8 -`define S_NF 23 -`define S_BIAS 127 -`define H_LEN 16 -`define H_NE 5 -`define H_NF 10 -`define H_BIAS 15 +`define Q_LEN 32'd128 +`define Q_NE 32'd15 +`define Q_NF 32'd112 +`define Q_BIAS 32'd16383 +`define D_LEN 32'd64 +`define D_NE 32'd11 +`define D_NF 32'd52 +`define D_BIAS 32'd1023 +`define D_FMT 32'd1 +`define S_LEN 32'd32 +`define S_NE 32'd8 +`define S_NF 32'd23 +`define S_BIAS 32'd127 +`define S_FMT 32'd1 +`define H_LEN 32'd16 +`define H_NE 32'd5 +`define H_NF 32'd10 +`define H_BIAS 32'd15 // Floating point length FLEN and number of exponent (NE) and fraction (NF) bits `define FLEN (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `F_SUPPORTED ? `S_LEN : `H_LEN) `define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `F_SUPPORTED ? `S_NE : `H_NE) `define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `F_SUPPORTED ? `S_NF : `H_NF) -`define FMT (`Q_SUPPORTED ? 3 : `D_SUPPORTED ? 1 : `F_SUPPORTED ? 0 : 2) +`define FMT (`Q_SUPPORTED ? 2'd3 : `D_SUPPORTED ? 2'd1 : `F_SUPPORTED ? 2'd0 : 2'd2) `define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `F_SUPPORTED ? `S_BIAS : `H_BIAS) // Floating point constants needed for FPU paramerterization -`define FPSIZES ((3)'(`Q_SUPPORTED)+(3)'(`D_SUPPORTED)+(3)'(`F_SUPPORTED)+(3)'(`ZFH_SUPPORTED)) -`define FMTBITS (((`FPSIZES==3'b011)|(`FPSIZES==3'b100)) ? 2 : 1) -`define LEN1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_LEN : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_LEN : `H_LEN) -`define NE1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NE : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NE : `H_NE) -`define NF1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NF : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NF : `H_NF) -`define FMT1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? 1 : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? 0 : 2) -`define BIAS1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_BIAS : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_BIAS : `H_BIAS) -`define LEN2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_LEN : `H_LEN) +`define FPSIZES ((32)'(`Q_SUPPORTED)+(32)'(`D_SUPPORTED)+(32)'(`F_SUPPORTED)+(32)'(`ZFH_SUPPORTED)) +`define FMTBITS ((`FPSIZES>=3)+1) +`define LEN1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_LEN : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_LEN : `H_LEN) +`define NE1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NE : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NE : `H_NE) +`define NF1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NF : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NF : `H_NF) +`define FMT1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? 2'd1 : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? 2'd0 : 2'd2) +`define BIAS1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_BIAS : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_BIAS : `H_BIAS) +`define LEN2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_LEN : `H_LEN) `define NE2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NE : `H_NE) -`define NF2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NF : `H_NF) -`define FMT2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? 0 : 2) -`define BIAS2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_BIAS : `H_BIAS) +`define NF2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NF : `H_NF) +`define FMT2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? 2'd0 : 2'd2) +`define BIAS2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_BIAS : `H_BIAS) // Disable spurious Verilator warnings diff --git a/pipelined/regression/lint-wally b/pipelined/regression/lint-wally index 1bf23bd87..2b5288d51 100755 --- a/pipelined/regression/lint-wally +++ b/pipelined/regression/lint-wally @@ -5,7 +5,7 @@ export PATH=$PATH:/usr/local/bin/ verilator=`which verilator` basepath=$(dirname $0)/.. -for config in rv64fp rv32e rv64gc rv32gc rv32ic; do +for config in rv64fp rv64fpquad rv32e rv64gc rv32gc rv32ic; do echo "$config linting..." if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes); then echo "Exiting after $config lint due to errors or warnings" diff --git a/pipelined/regression/sim-wally b/pipelined/regression/sim-wally index 22d539ea5..a7dffc9ed 100755 --- a/pipelined/regression/sim-wally +++ b/pipelined/regression/sim-wally @@ -1,2 +1,2 @@ -vsim -do "do wally-pipelined.do rv32e imperas64d" +vsim -do "do wally-pipelined.do rv32gc arch32f" diff --git a/pipelined/src/fpu/fctrl.sv b/pipelined/src/fpu/fctrl.sv index 108d923c1..406c0ec34 100755 --- a/pipelined/src/fpu/fctrl.sv +++ b/pipelined/src/fpu/fctrl.sv @@ -122,7 +122,7 @@ module fctrl ( else if (`FPSIZES == 2)begin logic [1:0] FmtTmp; assign FmtTmp = (FResultSelD == 2'b00) ? {~Funct3D[1], ~(Funct3D[1]^Funct3D[0])} : ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : Funct7D[1:0]; - assign FmtD = `FMT == FmtTmp; + assign FmtD = (`FMT == FmtTmp); end else if (`FPSIZES == 3|`FPSIZES == 4) assign FmtD = (FResultSelD == 2'b00) ? {~Funct3D[1], ~(Funct3D[1]^Funct3D[0])} : ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : Funct7D[1:0]; diff --git a/pipelined/src/fpu/fcvt.sv b/pipelined/src/fpu/fcvt.sv index b8b5a1072..d9fbe77c3 100644 --- a/pipelined/src/fpu/fcvt.sv +++ b/pipelined/src/fpu/fcvt.sv @@ -2,6 +2,7 @@ `include "wally-config.vh" // largest length in IEU/FPU `define LGLEN ((`NF<`XLEN) ? `XLEN : `NF) +`define LOGLGLEN $unsigned($clog2(`LGLEN+1)) module fcvt ( input logic XSgnE, // input's sign @@ -42,7 +43,7 @@ module fcvt ( logic [`XLEN-1:0] TrimInt; // integer trimmed to the correct size logic [`LGLEN-1:0] LzcIn; // input to the Leading Zero Counter (priority encoder) logic [`NE:0] CalcExp; // the calculated expoent - logic [$clog2(`LGLEN+1)-1:0] ShiftAmt; // how much to shift by + logic [`LOGLGLEN-1:0] ShiftAmt; // how much to shift by logic [`LGLEN+`NF:0] ShiftIn; // number to be shifted logic ResDenormUf;// does the result underflow or is denormalized logic ResUf; // does the result underflow @@ -72,7 +73,7 @@ module fcvt ( logic Int64; // is the integer 64 bits? logic IntToFp; // is the opperation an int->fp conversion? logic ToInt; // is the opperation an fp->int conversion? - logic [$clog2(`LGLEN+1)-1:0] ZeroCnt; // output from the LZC + logic [`LOGLGLEN-1:0] ZeroCnt; // output from the LZC // seperate OpCtrl for code readability @@ -143,9 +144,9 @@ module fcvt ( // - only shift fp -> fp if the intital value is denormalized // - this is a problem because the input to the lzc was the fraction rather than the mantissa // - rather have a few and-gates than an extra bit in the priority encoder??? *** is this true? - assign ShiftAmt = ToInt ? CalcExp[$clog2(`LGLEN+1)-1:0]&{$clog2(`LGLEN+1){~CalcExp[`NE]}} : - ResDenormUf&~IntToFp ? ($clog2(`LGLEN+1))'(`NF-1)+CalcExp[$clog2(`LGLEN+1)-1:0] : - (ZeroCnt+1)&{$clog2(`LGLEN+1){XDenormE|IntToFp}}; + assign ShiftAmt = ToInt ? CalcExp[`LOGLGLEN-1:0]&{`LOGLGLEN{~CalcExp[`NE]}} : + ResDenormUf&~IntToFp ? (`LOGLGLEN)'(`NF-1)+CalcExp[`LOGLGLEN-1:0] : + (ZeroCnt+1)&{`LOGLGLEN{XDenormE|IntToFp}}; // shift // fp -> int: | `XLEN zeros | Mantissa | 0's if nessisary | << CalcExp @@ -261,34 +262,34 @@ module fcvt ( // - shift left to normilize (-1-ZeroCnt) // - newBias to make the biased exponent // - assign CalcExp = {1'b0, OldExp} - (`NE+1)'(`BIAS) + {2'b0, NewBias} - {{`NE{1'b0}}, XDenormE|IntToFp} - {{`NE-$clog2(`LGLEN+1)+1{1'b0}}, (ZeroCnt&{$clog2(`LGLEN+1){XDenormE|IntToFp}})}; + assign CalcExp = {1'b0, OldExp} - (`NE+1)'(`BIAS) + {2'b0, NewBias} - {{`NE{1'b0}}, XDenormE|IntToFp} - {{`NE-`LOGLGLEN+1{1'b0}}, (ZeroCnt&{`LOGLGLEN{XDenormE|IntToFp}})}; // find if the result is dnormal or underflows // - if Calculated expoenent is 0 or negitive (and the input/result is not exactaly 0) // - can't underflow an integer to Fp conversion assign ResDenormUf = (~|CalcExp | CalcExp[`NE])&~XZeroE&~IntToFp; // choose the negative of the fraction size if (`FPSIZES == 1) begin - assign ResNegNF = -`NF; + assign ResNegNF = -($clog2(`NF)+1)'(`NF); end else if (`FPSIZES == 2) begin - assign ResNegNF = OutFmt ? -`NF : -`NF1; + assign ResNegNF = OutFmt ? -($clog2(`NF)+1)'(`NF) : -($clog2(`NF)+1)'(`NF1); end else if (`FPSIZES == 3) begin always_comb case (OutFmt) - `FMT: ResNegNF = -`NF; - `FMT1: ResNegNF = -`NF1; - `FMT2: ResNegNF = -`NF2; + `FMT: ResNegNF = -($clog2(`NF)+1)'(`NF); + `FMT1: ResNegNF = -($clog2(`NF)+1)'(`NF1); + `FMT2: ResNegNF = -($clog2(`NF)+1)'(`NF2); default: ResNegNF = 1'bx; endcase end else if (`FPSIZES == 4) begin always_comb case (OutFmt) - 2'h3: ResNegNF = -`Q_NF; - 2'h1: ResNegNF = -`D_NF; - 2'h0: ResNegNF = -`S_NF; - 2'h2: ResNegNF = -`H_NF; + 2'h3: ResNegNF = -($clog2(`NF)+1)'(`Q_NF); + 2'h1: ResNegNF = -($clog2(`NF)+1)'(`D_NF); + 2'h0: ResNegNF = -($clog2(`NF)+1)'(`S_NF); + 2'h2: ResNegNF = -($clog2(`NF)+1)'(`H_NF); endcase end // determine if the result underflows ??? -> fp @@ -453,10 +454,10 @@ module fcvt ( // find the maximum exponent (the exponent and larger overflows) if (`FPSIZES == 1) begin - assign MaxExp = ToInt ? Int64 ? 65 : 33 : {`NE{1'b1}}; + assign MaxExp = ToInt ? Int64 ? (`NE)'(65) : (`NE)'(33) : {`NE{1'b1}}; end else if (`FPSIZES == 2) begin - assign MaxExp = ToInt ? Int64 ? 65 : 33 : + assign MaxExp = ToInt ? Int64 ? (`NE)'($unsigned(65)) : (`NE)'($unsigned(33)) : OutFmt ? {`NE{1'b1}} : {{`NE-`NE1{1'b0}}, {`NE1{1'b1}}}; end else if (`FPSIZES == 3) begin @@ -476,7 +477,7 @@ module fcvt ( MaxExpFp = 1'bx; end endcase - assign MaxExp = ToInt ? Int64 ? 65 : 33 : MaxExpFp; + assign MaxExp = ToInt ? Int64 ? (`NE)'(65) : (`NE)'(33) : MaxExpFp; end else if (`FPSIZES == 4) begin logic [`NE-1:0] MaxExpFp; @@ -495,7 +496,7 @@ module fcvt ( MaxExpFp = {{`Q_NE-`H_NE{1'b0}}, {`H_NE{1'b1}}}; end endcase - assign MaxExp = ToInt ? Int64 ? 65 : 33 : MaxExpFp; + assign MaxExp = ToInt ? Int64 ? (`NE)'(65) : (`NE)'(33) : MaxExpFp; end // if the result exponent is larger then the maximum possible exponent diff --git a/pipelined/src/fpu/fma.sv b/pipelined/src/fpu/fma.sv index 1658a0645..0cb2c064d 100644 --- a/pipelined/src/fpu/fma.sv +++ b/pipelined/src/fpu/fma.sv @@ -81,7 +81,7 @@ module fma( // E/M pipeline registers flopenrc #(3*`NF+6) EMRegFma2(clk, reset, FlushM, ~StallM, SumE, SumM); - flopenrc #(13) EMRegFma3(clk, reset, FlushM, ~StallM, ProdExpE, ProdExpM); + flopenrc #(`NE+2) EMRegFma3(clk, reset, FlushM, ~StallM, ProdExpE, ProdExpM); flopenrc #($clog2(3*`NF+7)+8) EMRegFma4(clk, reset, FlushM, ~StallM, {AddendStickyE, KillProdE, InvZE, NormCntE, NegSumE, ZSgnEffE, PSgnE, FOpCtrlE[2]&~FOpCtrlE[1]&~FOpCtrlE[0], ZDenormE}, {AddendStickyM, KillProdM, InvZM, NormCntM, NegSumM, ZSgnEffM, PSgnM, Mult, ZDenormM}); @@ -237,7 +237,7 @@ module align( // - positive means the product is larger, so shift Z right // *** can we use ProdExpE instead of XExp/YExp to save an adder? DH 5/12/22 // KP- yes we used ProdExpE originally but we did this for timing - assign AlignCnt = XZeroE|YZeroE ? -1 : {2'b0, XExpE} + {2'b0, YExpE} - {2'b0, (`NE)'(`BIAS)} + `NF+3 - {2'b0, ZExpE}; + assign AlignCnt = XZeroE|YZeroE ? -(`NE+2)'($unsigned(1)) : {2'b0, XExpE} + {2'b0, YExpE} - {2'b0, (`NE)'(`BIAS)} + (`NE+2)'(`NF)+3 - {2'b0, ZExpE}; // Defualt Addition without shifting // | 54'b0 | 106'b(product) | 2'b0 | @@ -320,7 +320,7 @@ module add( // Do the addition // - calculate a positive and negitive sum in parallel - assign PreSum = AlignedAddendInv + {55'b0, ProdManKilled, 2'b0} + {{3*`NF+6{1'b0}}, InvZE}; + assign PreSum = AlignedAddendInv + {{`NF+3{1'b0}}, ProdManKilled, 2'b0} + {{3*`NF+6{1'b0}}, InvZE}; assign NegPreSum = XZeroE|YZeroE|KillProdE ? {1'b0, AlignedAddendE} : {1'b0, AlignedAddendE} + {{`NF+3{1'b1}}, ~ProdManKilled, 2'b0} + {(3*`NF+7)'(4)}; // Is the sum negitive @@ -543,7 +543,7 @@ module normalize( assign SumZero = ~(|SumM); // calculate the sum's exponent - assign SumExpTmpTmp = KillProdM ? {2'b0, ZExpM[`NE-1:1], ZExpM[0]&~ZDenormM} : ProdExpM + -({4'b0, NormCntM} + 1 - (`NF+4)); + assign SumExpTmpTmp = KillProdM ? {2'b0, ZExpM[`NE-1:1], ZExpM[0]&~ZDenormM} : ProdExpM + -({{`NE+2-$unsigned($clog2(3*`NF+7)){1'b0}}, NormCntM} + 1 - (`NE+2)'(`NF+4)); //convert the sum's exponent into the propper percision if (`FPSIZES == 1) begin @@ -556,8 +556,8 @@ module normalize( always_comb begin case (FmtM) `FMT: SumExpTmp = SumExpTmpTmp; - `FMT1: SumExpTmp = (SumExpTmpTmp-`BIAS+`BIAS1)&{`NE+2{|SumExpTmpTmp}}; - `FMT2: SumExpTmp = (SumExpTmpTmp-`BIAS+`BIAS2)&{`NE+2{|SumExpTmpTmp}}; + `FMT1: SumExpTmp = (SumExpTmpTmp-(`NE+2)'(`BIAS)+(`NE+2)'(`BIAS1))&{`NE+2{|SumExpTmpTmp}}; + `FMT2: SumExpTmp = (SumExpTmpTmp-(`NE+2)'(`BIAS)+(`NE+2)'(`BIAS2))&{`NE+2{|SumExpTmpTmp}}; default: SumExpTmp = `NE+2'bx; endcase end @@ -566,9 +566,9 @@ module normalize( always_comb begin case (FmtM) 2'h3: SumExpTmp = SumExpTmpTmp; - 2'h1: SumExpTmp = (SumExpTmpTmp-`BIAS+`D_BIAS)&{`NE+2{|SumExpTmpTmp}}; - 2'h0: SumExpTmp = (SumExpTmpTmp-`BIAS+`S_BIAS)&{`NE+2{|SumExpTmpTmp}}; - 2'h2: SumExpTmp = (SumExpTmpTmp-`BIAS+`H_BIAS)&{`NE+2{|SumExpTmpTmp}}; + 2'h1: SumExpTmp = (SumExpTmpTmp-(`NE+2)'(`BIAS)+(`NE+2)'(`D_BIAS))&{`NE+2{|SumExpTmpTmp}}; + 2'h0: SumExpTmp = (SumExpTmpTmp-(`NE+2)'(`BIAS)+(`NE+2)'(`S_BIAS))&{`NE+2{|SumExpTmpTmp}}; + 2'h2: SumExpTmp = (SumExpTmpTmp-(`NE+2)'(`BIAS)+(`NE+2)'(`H_BIAS))&{`NE+2{|SumExpTmpTmp}}; endcase end @@ -674,7 +674,7 @@ module normalize( // Determine sum's exponent // if plus1 If plus2 if said denorm but norm plus 1 if said denorm but norm plus 2 - assign SumExp = (SumExpTmp+{12'b0, LZAPlus1&~KillProdM}+{11'b0, LZAPlus2&~KillProdM, 1'b0}+{12'b0, ~ResultDenorm&PreResultDenorm&~KillProdM}+{12'b0, &SumExpTmp&SumShifted[3*`NF+6]&~KillProdM}) & {`NE+2{~(SumZero|ResultDenorm)}}; + assign SumExp = (SumExpTmp+{{`NE+1{1'b0}}, LZAPlus1&~KillProdM}+{{`NE{1'b0}}, LZAPlus2&~KillProdM, 1'b0}+{{`NE+1{1'b0}}, ~ResultDenorm&PreResultDenorm&~KillProdM}+{{`NE+1{1'b0}}, &SumExpTmp&SumShifted[3*`NF+6]&~KillProdM}) & {`NE+2{~(SumZero|ResultDenorm)}}; // recalculate if the result is denormalized assign ResultDenorm = PreResultDenorm&~SumShifted[3*`NF+6]&~SumShifted[3*`NF+7]; diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index a45e2bbea..c8d1e3c62 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -107,7 +107,7 @@ module fpu ( logic FOpCtrlQ; // result and flag signals - logic [`FLEN-1:0] FDivResM, FDivResW; // divide/squareroot result + logic [63:0] FDivResM, FDivResW; // divide/squareroot result logic [4:0] FDivFlgM; // divide/squareroot flags logic [`FLEN-1:0] FMAResM, FMAResW; // FMA/multiply result logic [4:0] FMAFlgM; // FMA/multiply result @@ -125,7 +125,7 @@ module fpu ( logic [`FLEN-1:0] FPUResultW; // final FP result being written to the FP register // other signals logic FDivSqrtDoneE; // is divide done - logic [`FLEN-1:0] DivInput1E, DivInput2E; // inputs to divide/squareroot unit + logic [63:0] DivInput1E, DivInput2E; // inputs to divide/squareroot unit logic load_preload; // enable for FF on fpdivsqrt logic [`FLEN-1:0] AlignedSrcAE; // align SrcA to the floating point format logic [`FLEN-1:0] BoxedZeroE; // Zero value for Z for multiplication, with NaN boxing if needed @@ -184,11 +184,11 @@ module fpu ( generate if(`FPSIZES == 1) assign BoxedZeroE = 0; else if(`FPSIZES == 2) - mux2 #(`FLEN) fmulzeromux ({{`FLEN-`LEN1{1'b1}}, {`FLEN-`LEN1{1'b0}}}, (`FLEN)'(0), FmtE, BoxedZeroE); // NaN boxing zeroes + mux2 #(`FLEN) fmulzeromux ({{`FLEN-`LEN1{1'b1}}, {`LEN1{1'b0}}}, (`FLEN)'(0), FmtE, BoxedZeroE); // NaN boxing zeroes else if(`FPSIZES == 3 | `FPSIZES == 4) - mux4 #(`FLEN) fmulzeromux ({{`FLEN-`S_LEN{1'b1}}, (`FLEN-`S_LEN)'(0)}, - {{`FLEN-`D_LEN{1'b1}}, (`FLEN-`D_LEN)'(0)}, - {{`FLEN-`H_LEN{1'b1}}, (`FLEN-`H_LEN)'(0)}, + mux4 #(`FLEN) fmulzeromux ({{`FLEN-`S_LEN{1'b1}}, {`S_LEN{1'b0}}}, + {{`FLEN-`D_LEN{1'b1}}, {`D_LEN{1'b0}}}, + {{`FLEN-`H_LEN{1'b1}}, {`H_LEN{1'b0}}}, (`FLEN)'(0), FmtE, BoxedZeroE); // NaN boxing zeroes endgenerate @@ -218,17 +218,27 @@ module fpu ( .FMAFlgM, .FMAResM); // fpdivsqrt using Goldschmidt's iteration - flopenrc #(`FLEN) reg_input1 (.d({XSgnE, XExpE, XManE[51:0]}), .q(DivInput1E), + if(`FLEN == 64) begin + flopenrc #(64) reg_input1 (.d({FSrcXE[63:0]}), .q(DivInput1E), .clear(FDivSqrtDoneE), .en(load_preload), .reset(reset), .clk(clk)); - flopenrc #(`FLEN) reg_input2 (.d({YSgnE, YExpE, YManE[51:0]}), .q(DivInput2E), + flopenrc #(64) reg_input2 (.d({FSrcYE[63:0]}), .q(DivInput2E), .clear(FDivSqrtDoneE), .en(load_preload), .reset(reset), .clk(clk)); - flopenrc #(8+int'(`FMTBITS-1)) reg_input3 (.d({XNaNE, YNaNE, XInfE, YInfE, XZeroE, YZeroE, FmtE, FOpCtrlE[0]}), + end + else if (`FLEN == 32) begin + flopenrc #(64) reg_input1 (.d({32'b0, FSrcXE[31:0]}), .q(DivInput1E), + .clear(FDivSqrtDoneE), .en(load_preload), + .reset(reset), .clk(clk)); + flopenrc #(64) reg_input2 (.d({32'b0, FSrcYE[31:0]}), .q(DivInput2E), + .clear(FDivSqrtDoneE), .en(load_preload), + .reset(reset), .clk(clk)); + end + flopenrc #(8) reg_input3 (.d({XNaNE, YNaNE, XInfE, YInfE, XZeroE, YZeroE, FmtE[0], FOpCtrlE[0]}), .q({XNaNQ, YNaNQ, XInfQ, YInfQ, XZeroQ, YZeroQ, FmtQ, FOpCtrlQ}), .clear(FDivSqrtDoneE), .en(load_preload), .reset(reset), .clk(clk)); - fpdiv_pipe fdivsqrt (.op1(DivInput1E), .op2(DivInput2E), .rm(FrmE[1:0]), .op_type(FOpCtrlQ), + fpdiv_pipe fdivsqrt (.op1(DivInput1E[63:0]), .op2(DivInput2E[63:0]), .rm(FrmE[1:0]), .op_type(FOpCtrlQ), .reset, .clk(clk), .start(FDivStartE), .P(~FmtQ), .OvEn(1'b1), .UnEn(1'b1), .XNaNQ, .YNaNQ, .XInfQ, .YInfQ, .XZeroQ, .YZeroQ, .load_preload, .FDivBusyE, .done(FDivSqrtDoneE), .AS_Result(FDivResM), .Flags(FDivFlgM)); @@ -244,7 +254,8 @@ module fpu ( // data to be stored in memory - to IEU // - FP uses NaN-blocking format // - if there are any unsused bits the most significant bits are filled with 1s - assign FWriteDataE = FSrcYE[`XLEN-1:0]; + if (`FLEN>`XLEN) assign FWriteDataE = FSrcYE[`XLEN-1:0]; + else assign FWriteDataE = {{`XLEN-`FLEN{FSrcYE[`FLEN-1]}}, FSrcYE}; // NaN Block SrcA generate @@ -262,8 +273,12 @@ module fpu ( mux4 #(5) FFlgMux(5'b0, 5'b0, {CmpNVE, 4'b0}, CvtFlgE, FResSelE, FFlgE); // select the result that may be written to the integer register - to IEU - mux4 #(`XLEN) IntResMux(CmpResE[`XLEN-1:0], FSrcXE[`XLEN-1:0], ClassResE, - CvtIntResE, FIntResSelE, FIntResE); + if (`FLEN>`XLEN) + mux4 #(`XLEN) IntResMux(CmpResE[`XLEN-1:0], FSrcXE[`XLEN-1:0], ClassResE, + CvtIntResE, FIntResSelE, FIntResE); + else + mux4 #(`XLEN) IntResMux({{`XLEN-`FLEN{CmpResE[`FLEN-1:0]}}, CmpResE}, {{`XLEN-`FLEN{FSrcXE[`FLEN-1:0]}}, FSrcXE}, ClassResE, + CvtIntResE, FIntResSelE, FIntResE); // *** DH 5/25/22: CvtRes will move to mem stage. Premux in execute to save area, then make sure stalls are ok // *** make sure the fpu matches the chapter diagram @@ -290,7 +305,7 @@ module fpu ( // M/W pipe registers flopenrc #(`FLEN) MWRegFma(clk, reset, FlushW, ~StallW, FMAResM, FMAResW); - flopenrc #(`FLEN) MWRegDiv(clk, reset, FlushW, ~StallW, FDivResM, FDivResW); + flopenrc #(64) MWRegDiv(clk, reset, FlushW, ~StallW, FDivResM, FDivResW); flopenrc #(`FLEN) MWRegClass(clk, reset, FlushW, ~StallW, FResM, FResW); flopenrc #(4+int'(`FMTBITS-1)) MWCtrlReg(clk, reset, FlushW, ~StallW, {FRegWriteM, FResultSelM, FmtM}, @@ -313,5 +328,6 @@ module fpu ( endgenerate // select the result to be written to the FP register - mux4 #(`FLEN) FPUResultMux (ReadResW, FMAResW, FDivResW, FResW, FResultSelW, FPUResultW); + if(`FLEN>=64) + mux4 #(`FLEN) FPUResultMux (ReadResW, FMAResW, {{`FLEN-64{1'b0}},FDivResW}, FResW, FResultSelW, FPUResultW); endmodule // fpu diff --git a/pipelined/src/fpu/unpack.sv b/pipelined/src/fpu/unpack.sv index 73b867aa2..506109da4 100644 --- a/pipelined/src/fpu/unpack.sv +++ b/pipelined/src/fpu/unpack.sv @@ -1,11 +1,11 @@ `include "wally-config.vh" module unpack ( - input logic [$signed(`FLEN)-$signed(1):0] X, Y, Z, // inputs from register file - input logic [$signed(`FMTBITS)-$signed(1):0] FmtE, // format signal 00 - single 01 - double 11 - quad 10 - half + input logic [`FLEN-1:0] X, Y, Z, // inputs from register file + input logic [`FMTBITS-1:0] FmtE, // format signal 00 - single 01 - double 11 - quad 10 - half output logic XSgnE, YSgnE, ZSgnE, // sign bits of XYZ - output logic [$signed(`NE)-$signed(1):0] XExpE, YExpE, ZExpE, // exponents of XYZ (converted to largest supported precision) - output logic [$signed(`NF):0] XManE, YManE, ZManE, // mantissas of XYZ (converted to largest supported precision) + output logic [`NE-1:0] XExpE, YExpE, ZExpE, // exponents of XYZ (converted to largest supported precision) + output logic [`NF:0] XManE, YManE, ZManE, // mantissas of XYZ (converted to largest supported precision) output logic XNaNE, YNaNE, ZNaNE, // is XYZ a NaN output logic XSNaNE, YSNaNE, ZSNaNE, // is XYZ a signaling NaN output logic XDenormE, ZDenormE, // is XYZ denormalized @@ -14,7 +14,7 @@ module unpack ( output logic XExpMaxE // does X have the maximum exponent (NaN or Inf) ); - logic [$signed(`NF)-$signed(1):0] XFracE, YFracE, ZFracE; //Fraction of XYZ + logic [`NF-1:0] XFracE, YFracE, ZFracE; //Fraction of XYZ logic XExpNonZero, YExpNonZero, ZExpNonZero; // is the exponent of XYZ non-zero logic XFracZero, YFracZero, ZFracZero; // is the fraction zero logic YExpMaxE, ZExpMaxE; // is the exponent all 1s diff --git a/pipelined/testbench/testbench-fp.sv b/pipelined/testbench/testbench-fp.sv index e74dd45bb..1a27c833b 100644 --- a/pipelined/testbench/testbench-fp.sv +++ b/pipelined/testbench/testbench-fp.sv @@ -261,26 +261,26 @@ module testbenchfp; Fmt = {Fmt, 2'b11}; end end - if (TEST === "div" | TEST === "all") begin // if division is being tested - // add the divide tests/op-ctrls/unit/fmt - Tests = {Tests, f128div}; - OpCtrl = {OpCtrl, `DIV_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `DIVUNIT}; - Fmt = {Fmt, 2'b11}; - end - end - if (TEST === "sqrt" | TEST === "all") begin // if square-root is being tested - // add the square-root tests/op-ctrls/unit/fmt - Tests = {Tests, f128sqrt}; - OpCtrl = {OpCtrl, `SQRT_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `DIVUNIT}; - Fmt = {Fmt, 2'b11}; - end - end + // if (TEST === "div" | TEST === "all") begin // if division is being tested + // // add the divide tests/op-ctrls/unit/fmt + // Tests = {Tests, f128div}; + // OpCtrl = {OpCtrl, `DIV_OPCTRL}; + // WriteInt = {WriteInt, 1'b0}; + // for(int i = 0; i<5; i++) begin + // Unit = {Unit, `DIVUNIT}; + // Fmt = {Fmt, 2'b11}; + // end + // end + // if (TEST === "sqrt" | TEST === "all") begin // if square-root is being tested + // // add the square-root tests/op-ctrls/unit/fmt + // Tests = {Tests, f128sqrt}; + // OpCtrl = {OpCtrl, `SQRT_OPCTRL}; + // WriteInt = {WriteInt, 1'b0}; + // for(int i = 0; i<5; i++) begin + // Unit = {Unit, `DIVUNIT}; + // Fmt = {Fmt, 2'b11}; + // end + // end if (TEST === "fma" | TEST === "all") begin // if fused-mutliply-add is being tested // add each rounding mode to it's own list of tests // - fma tests are very long, so run all rounding modes in parallel @@ -390,26 +390,26 @@ module testbenchfp; Fmt = {Fmt, 2'b01}; end end - if (TEST === "div" | TEST === "all") begin // if division is being tested - // add the correct tests/op-ctrls/unit/fmt to their lists - Tests = {Tests, f64div}; - OpCtrl = {OpCtrl, `DIV_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `DIVUNIT}; - Fmt = {Fmt, 2'b01}; - end - end - if (TEST === "sqrt" | TEST === "all") begin // if square-root is being tessted - // add the correct tests/op-ctrls/unit/fmt to their lists - Tests = {Tests, f64sqrt}; - OpCtrl = {OpCtrl, `SQRT_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `DIVUNIT}; - Fmt = {Fmt, 2'b01}; - end - end + // if (TEST === "div" | TEST === "all") begin // if division is being tested + // // add the correct tests/op-ctrls/unit/fmt to their lists + // Tests = {Tests, f64div}; + // OpCtrl = {OpCtrl, `DIV_OPCTRL}; + // WriteInt = {WriteInt, 1'b0}; + // for(int i = 0; i<5; i++) begin + // Unit = {Unit, `DIVUNIT}; + // Fmt = {Fmt, 2'b01}; + // end + // end + // if (TEST === "sqrt" | TEST === "all") begin // if square-root is being tessted + // // add the correct tests/op-ctrls/unit/fmt to their lists + // Tests = {Tests, f64sqrt}; + // OpCtrl = {OpCtrl, `SQRT_OPCTRL}; + // WriteInt = {WriteInt, 1'b0}; + // for(int i = 0; i<5; i++) begin + // Unit = {Unit, `DIVUNIT}; + // Fmt = {Fmt, 2'b01}; + // end + // end if (TEST === "fma" | TEST === "all") begin // if the fused multiply add is being tested // add each rounding mode to it's own list of tests // - fma tests are very long, so run all rounding modes in parallel @@ -502,26 +502,26 @@ module testbenchfp; Fmt = {Fmt, 2'b00}; end end - if (TEST === "div" | TEST === "all") begin // if division is being tested - // add the correct tests/op-ctrls/unit/fmt to their lists - Tests = {Tests, f32div}; - OpCtrl = {OpCtrl, `DIV_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `DIVUNIT}; - Fmt = {Fmt, 2'b00}; - end - end - if (TEST === "sqrt" | TEST === "all") begin // if sqrt is being tested - // add the correct tests/op-ctrls/unit/fmt to their lists - Tests = {Tests, f32sqrt}; - OpCtrl = {OpCtrl, `SQRT_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `DIVUNIT}; - Fmt = {Fmt, 2'b00}; - end - end + // if (TEST === "div" | TEST === "all") begin // if division is being tested + // // add the correct tests/op-ctrls/unit/fmt to their lists + // Tests = {Tests, f32div}; + // OpCtrl = {OpCtrl, `DIV_OPCTRL}; + // WriteInt = {WriteInt, 1'b0}; + // for(int i = 0; i<5; i++) begin + // Unit = {Unit, `DIVUNIT}; + // Fmt = {Fmt, 2'b00}; + // end + // end + // if (TEST === "sqrt" | TEST === "all") begin // if sqrt is being tested + // // add the correct tests/op-ctrls/unit/fmt to their lists + // Tests = {Tests, f32sqrt}; + // OpCtrl = {OpCtrl, `SQRT_OPCTRL}; + // WriteInt = {WriteInt, 1'b0}; + // for(int i = 0; i<5; i++) begin + // Unit = {Unit, `DIVUNIT}; + // Fmt = {Fmt, 2'b00}; + // end + // end if (TEST === "fma" | TEST === "all") begin // if fma is being tested // add each rounding mode to it's own list of tests // - fma tests are very long, so run all rounding modes in parallel @@ -596,26 +596,26 @@ module testbenchfp; Fmt = {Fmt, 2'b10}; end end - if (TEST === "div" | TEST === "all") begin // if division is being tested - // add the correct tests/op-ctrls/unit/fmt to their lists - Tests = {Tests, f16div}; - OpCtrl = {OpCtrl, `DIV_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `DIVUNIT}; - Fmt = {Fmt, 2'b10}; - end - end - if (TEST === "sqrt" | TEST === "all") begin // if sqrt is being tested - // add the correct tests/op-ctrls/unit/fmt to their lists - Tests = {Tests, f16sqrt}; - OpCtrl = {OpCtrl, `SQRT_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `DIVUNIT}; - Fmt = {Fmt, 2'b10}; - end - end + // if (TEST === "div" | TEST === "all") begin // if division is being tested + // // add the correct tests/op-ctrls/unit/fmt to their lists + // Tests = {Tests, f16div}; + // OpCtrl = {OpCtrl, `DIV_OPCTRL}; + // WriteInt = {WriteInt, 1'b0}; + // for(int i = 0; i<5; i++) begin + // Unit = {Unit, `DIVUNIT}; + // Fmt = {Fmt, 2'b10}; + // end + // end + // if (TEST === "sqrt" | TEST === "all") begin // if sqrt is being tested + // // add the correct tests/op-ctrls/unit/fmt to their lists + // Tests = {Tests, f16sqrt}; + // OpCtrl = {OpCtrl, `SQRT_OPCTRL}; + // WriteInt = {WriteInt, 1'b0}; + // for(int i = 0; i<5; i++) begin + // Unit = {Unit, `DIVUNIT}; + // Fmt = {Fmt, 2'b10}; + // end + // end if (TEST === "fma" | TEST === "all") begin // if fma is being tested // add each rounding mode to it's own list of tests // - fma tests are very long, so run all rounding modes in parallel @@ -673,10 +673,10 @@ module testbenchfp; // - 1 for the larger precision // - 0 for the smaller precision always_comb begin - if(`FMTBITS == 2) ModFmt = FmtVal; - else ModFmt = FmtVal === `FMT; - if(`FMTBITS == 2) FmaModFmt = FmaFmtVal; - else FmaModFmt = FmaFmtVal === `FMT; + if(`FMTBITS == 1) ModFmt = FmtVal == `FMT; + else ModFmt = FmtVal; + if(`FMTBITS == 1) FmaModFmt = FmaFmtVal == `FMT; + else FmaModFmt = FmaFmtVal; end // extract the inputs (X, Y, Z, SrcA) and the output (Ans, AnsFlg) from the current test vector @@ -1028,111 +1028,111 @@ end // - the sign of the NaN does not matter for the opperations being tested // - when 2 or more NaNs are inputed the NaN that is propigated doesn't matter case (FmaFmtVal) - 4'b11: FmaRneNaNGood =(((`IEEE754==0)&(FmaRneRes === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + 4'b11: FmaRneNaNGood =(((`IEEE754==0)&FmaRneAnsNaN&(FmaRneRes === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | (FmaRneAnsFlg[4]&(FmaRneRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | (FmaRneXNaN&(FmaRneRes[`Q_LEN-2:0] === {FmaRneX[`Q_LEN-2:`Q_NF],1'b1,FmaRneX[`Q_NF-2:0]})) | (FmaRneYNaN&(FmaRneRes[`Q_LEN-2:0] === {FmaRneY[`Q_LEN-2:`Q_NF],1'b1,FmaRneY[`Q_NF-2:0]})) | (FmaRneZNaN&(FmaRneRes[`Q_LEN-2:0] === {FmaRneZ[`Q_LEN-2:`Q_NF],1'b1,FmaRneZ[`Q_NF-2:0]}))); - 4'b01: FmaRneNaNGood =(((`IEEE754==0)&(FmaRneRes === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + 4'b01: FmaRneNaNGood =(((`IEEE754==0)&FmaRneAnsNaN&(FmaRneRes[`D_LEN-1:0] === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | (FmaRneAnsFlg[4]&(FmaRneRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | (FmaRneXNaN&(FmaRneRes[`D_LEN-2:0] === {FmaRneX[`D_LEN-2:`D_NF],1'b1,FmaRneX[`D_NF-2:0]})) | (FmaRneYNaN&(FmaRneRes[`D_LEN-2:0] === {FmaRneY[`D_LEN-2:`D_NF],1'b1,FmaRneY[`D_NF-2:0]})) | (FmaRneZNaN&(FmaRneRes[`D_LEN-2:0] === {FmaRneZ[`D_LEN-2:`D_NF],1'b1,FmaRneZ[`D_NF-2:0]}))); - 4'b00: FmaRneNaNGood =(((`IEEE754==0)&(FmaRneRes === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + 4'b00: FmaRneNaNGood =(((`IEEE754==0)&FmaRneAnsNaN&(FmaRneRes[`S_LEN-1:0] === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | (FmaRneAnsFlg[4]&(FmaRneRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | (FmaRneXNaN&(FmaRneRes[`S_LEN-2:0] === {FmaRneX[`S_LEN-2:`S_NF],1'b1,FmaRneX[`S_NF-2:0]})) | (FmaRneYNaN&(FmaRneRes[`S_LEN-2:0] === {FmaRneY[`S_LEN-2:`S_NF],1'b1,FmaRneY[`S_NF-2:0]})) | (FmaRneZNaN&(FmaRneRes[`S_LEN-2:0] === {FmaRneZ[`S_LEN-2:`S_NF],1'b1,FmaRneZ[`S_NF-2:0]}))); - 4'b10: FmaRneNaNGood =(((`IEEE754==0)&(FmaRneRes === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + 4'b10: FmaRneNaNGood =(((`IEEE754==0)&FmaRneAnsNaN&(FmaRneRes[`H_LEN-1:0] === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | (FmaRneAnsFlg[4]&(FmaRneRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | (FmaRneXNaN&(FmaRneRes[`H_LEN-2:0] === {FmaRneX[`H_LEN-2:`H_NF],1'b1,FmaRneX[`H_NF-2:0]})) | (FmaRneYNaN&(FmaRneRes[`H_LEN-2:0] === {FmaRneY[`H_LEN-2:`H_NF],1'b1,FmaRneY[`H_NF-2:0]})) | (FmaRneZNaN&(FmaRneRes[`H_LEN-2:0] === {FmaRneZ[`H_LEN-2:`H_NF],1'b1,FmaRneZ[`H_NF-2:0]}))); endcase case (FmaFmtVal) - 4'b11: FmaRzNaNGood = (((`IEEE754==0)&(FmaRneRes === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + 4'b11: FmaRzNaNGood = (((`IEEE754==0)&FmaRzAnsNaN&(FmaRzRes === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | (FmaRzAnsFlg[4]&(FmaRzRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | (FmaRzXNaN&(FmaRzRes[`Q_LEN-2:0] === {FmaRzX[`Q_LEN-2:`Q_NF],1'b1,FmaRzX[`Q_NF-2:0]})) | (FmaRzYNaN&(FmaRzRes[`Q_LEN-2:0] === {FmaRzY[`Q_LEN-2:`Q_NF],1'b1,FmaRzY[`Q_NF-2:0]})) | (FmaRzZNaN&(FmaRzRes[`Q_LEN-2:0] === {FmaRzZ[`Q_LEN-2:`Q_NF],1'b1,FmaRzZ[`Q_NF-2:0]}))); - 4'b01: FmaRzNaNGood = (((`IEEE754==0)&(FmaRneRes === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + 4'b01: FmaRzNaNGood = (((`IEEE754==0)&FmaRzAnsNaN&(FmaRzRes[`D_LEN-1:0] === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | (FmaRzAnsFlg[4]&(FmaRzRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | (FmaRzXNaN&(FmaRzRes[`D_LEN-2:0] === {FmaRzX[`D_LEN-2:`D_NF],1'b1,FmaRzX[`D_NF-2:0]})) | (FmaRzYNaN&(FmaRzRes[`D_LEN-2:0] === {FmaRzY[`D_LEN-2:`D_NF],1'b1,FmaRzY[`D_NF-2:0]})) | (FmaRzZNaN&(FmaRzRes[`D_LEN-2:0] === {FmaRzZ[`D_LEN-2:`D_NF],1'b1,FmaRzZ[`D_NF-2:0]}))); - 4'b00: FmaRzNaNGood = (((`IEEE754==0)&(FmaRneRes === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + 4'b00: FmaRzNaNGood = (((`IEEE754==0)&FmaRzAnsNaN&(FmaRzRes[`S_LEN-1:0] === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | (FmaRzAnsFlg[4]&(FmaRzRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | (FmaRzXNaN&(FmaRzRes[`S_LEN-2:0] === {FmaRzX[`S_LEN-2:`S_NF],1'b1,FmaRzX[`S_NF-2:0]})) | (FmaRzYNaN&(FmaRzRes[`S_LEN-2:0] === {FmaRzY[`S_LEN-2:`S_NF],1'b1,FmaRzY[`S_NF-2:0]})) | (FmaRzZNaN&(FmaRzRes[`S_LEN-2:0] === {FmaRzZ[`S_LEN-2:`S_NF],1'b1,FmaRzZ[`S_NF-2:0]}))); - 4'b10: FmaRzNaNGood = (((`IEEE754==0)&(FmaRneRes === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + 4'b10: FmaRzNaNGood = (((`IEEE754==0)&FmaRzAnsNaN&(FmaRzRes[`H_LEN-1:0] === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | (FmaRzAnsFlg[4]&(FmaRzRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | (FmaRzXNaN&(FmaRzRes[`H_LEN-2:0] === {FmaRzX[`H_LEN-2:`H_NF],1'b1,FmaRzX[`H_NF-2:0]})) | (FmaRzYNaN&(FmaRzRes[`H_LEN-2:0] === {FmaRzY[`H_LEN-2:`H_NF],1'b1,FmaRzY[`H_NF-2:0]})) | (FmaRzZNaN&(FmaRzRes[`H_LEN-2:0] === {FmaRzZ[`H_LEN-2:`H_NF],1'b1,FmaRzZ[`H_NF-2:0]}))); endcase case (FmaFmtVal) - 4'b11: FmaRuNaNGood = (((`IEEE754==0)&(FmaRneRes === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + 4'b11: FmaRuNaNGood = (((`IEEE754==0)&FmaRuAnsNaN&(FmaRuRes === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | (FmaRuAnsFlg[4]&(FmaRuRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | (FmaRuXNaN&(FmaRuRes[`Q_LEN-2:0] === {FmaRuX[`Q_LEN-2:`Q_NF],1'b1,FmaRuX[`Q_NF-2:0]})) | (FmaRuYNaN&(FmaRuRes[`Q_LEN-2:0] === {FmaRuY[`Q_LEN-2:`Q_NF],1'b1,FmaRuY[`Q_NF-2:0]})) | (FmaRuZNaN&(FmaRuRes[`Q_LEN-2:0] === {FmaRuZ[`Q_LEN-2:`Q_NF],1'b1,FmaRuZ[`Q_NF-2:0]}))); - 4'b01: FmaRuNaNGood = (((`IEEE754==0)&(FmaRneRes === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + 4'b01: FmaRuNaNGood = (((`IEEE754==0)&FmaRuAnsNaN&(FmaRuRes[`D_LEN-1:0] === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | (FmaRuAnsFlg[4]&(FmaRuRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | (FmaRuAnsFlg[4]&(FmaRuRes[`Q_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF{1'b0}}})) | (FmaRuXNaN&(FmaRuRes[`D_LEN-2:0] === {FmaRuX[`D_LEN-2:`D_NF],1'b1,FmaRuX[`D_NF-2:0]})) | (FmaRuYNaN&(FmaRuRes[`D_LEN-2:0] === {FmaRuY[`D_LEN-2:`D_NF],1'b1,FmaRuY[`D_NF-2:0]})) | (FmaRuZNaN&(FmaRuRes[`D_LEN-2:0] === {FmaRuZ[`D_LEN-2:`D_NF],1'b1,FmaRuZ[`D_NF-2:0]}))); - 4'b00: FmaRuNaNGood = (((`IEEE754==0)&(FmaRneRes === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + 4'b00: FmaRuNaNGood = (((`IEEE754==0)&FmaRuAnsNaN&(FmaRuRes[`S_LEN-1:0] === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | (FmaRuAnsFlg[4]&(FmaRuRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | (FmaRuXNaN&(FmaRuRes[`S_LEN-2:0] === {FmaRuX[`S_LEN-2:`S_NF],1'b1,FmaRuX[`S_NF-2:0]})) | (FmaRuYNaN&(FmaRuRes[`S_LEN-2:0] === {FmaRuY[`S_LEN-2:`S_NF],1'b1,FmaRuY[`S_NF-2:0]})) | (FmaRuZNaN&(FmaRuRes[`S_LEN-2:0] === {FmaRuZ[`S_LEN-2:`S_NF],1'b1,FmaRuZ[`S_NF-2:0]}))); - 4'b10: FmaRuNaNGood = (((`IEEE754==0)&(FmaRneRes === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + 4'b10: FmaRuNaNGood = (((`IEEE754==0)&FmaRuAnsNaN&(FmaRuRes[`H_LEN-1:0] === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | (FmaRuAnsFlg[4]&(FmaRuRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | (FmaRuXNaN&(FmaRuRes[`H_LEN-2:0] === {FmaRuX[`H_LEN-2:`H_NF],1'b1,FmaRuX[`H_NF-2:0]})) | (FmaRuYNaN&(FmaRuRes[`H_LEN-2:0] === {FmaRuY[`H_LEN-2:`H_NF],1'b1,FmaRuY[`H_NF-2:0]})) | (FmaRuZNaN&(FmaRuRes[`H_LEN-2:0] === {FmaRuZ[`H_LEN-2:`H_NF],1'b1,FmaRuZ[`H_NF-2:0]}))); endcase case (FmaFmtVal) - 4'b11: FmaRdNaNGood = (((`IEEE754==0)&(FmaRneRes === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + 4'b11: FmaRdNaNGood = (((`IEEE754==0)&FmaRdAnsNaN&(FmaRdRes === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | (FmaRdAnsFlg[4]&(FmaRdRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | (FmaRdXNaN&(FmaRdRes[`Q_LEN-2:0] === {FmaRdX[`Q_LEN-2:`Q_NF],1'b1,FmaRdX[`Q_NF-2:0]})) | (FmaRdYNaN&(FmaRdRes[`Q_LEN-2:0] === {FmaRdY[`Q_LEN-2:`Q_NF],1'b1,FmaRdY[`Q_NF-2:0]})) | (FmaRdZNaN&(FmaRdRes[`Q_LEN-2:0] === {FmaRdZ[`Q_LEN-2:`Q_NF],1'b1,FmaRdZ[`Q_NF-2:0]}))); - 4'b01: FmaRdNaNGood = (((`IEEE754==0)&(FmaRneRes === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + 4'b01: FmaRdNaNGood = (((`IEEE754==0)&FmaRdAnsNaN&(FmaRdRes[`D_LEN-1:0] === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | (FmaRdAnsFlg[4]&(FmaRdRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | (FmaRdXNaN&(FmaRdRes[`D_LEN-2:0] === {FmaRdX[`D_LEN-2:`D_NF],1'b1,FmaRdX[`D_NF-2:0]})) | (FmaRdYNaN&(FmaRdRes[`D_LEN-2:0] === {FmaRdY[`D_LEN-2:`D_NF],1'b1,FmaRdY[`D_NF-2:0]})) | (FmaRdZNaN&(FmaRdRes[`D_LEN-2:0] === {FmaRdZ[`D_LEN-2:`D_NF],1'b1,FmaRdZ[`D_NF-2:0]}))); - 4'b00: FmaRdNaNGood = (((`IEEE754==0)&(FmaRneRes === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + 4'b00: FmaRdNaNGood = (((`IEEE754==0)&FmaRdAnsNaN&(FmaRdRes[`S_LEN-1:0] === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | (FmaRdAnsFlg[4]&(FmaRdRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | (FmaRdXNaN&(FmaRdRes[`S_LEN-2:0] === {FmaRdX[`S_LEN-2:`S_NF],1'b1,FmaRdX[`S_NF-2:0]})) | (FmaRdYNaN&(FmaRdRes[`S_LEN-2:0] === {FmaRdY[`S_LEN-2:`S_NF],1'b1,FmaRdY[`S_NF-2:0]})) | (FmaRdZNaN&(FmaRdRes[`S_LEN-2:0] === {FmaRdZ[`S_LEN-2:`S_NF],1'b1,FmaRdZ[`S_NF-2:0]}))); - 4'b10: FmaRdNaNGood = (((`IEEE754==0)&(FmaRneRes === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + 4'b10: FmaRdNaNGood = (((`IEEE754==0)&FmaRdAnsNaN&(FmaRdRes[`H_LEN-1:0] === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | (FmaRdAnsFlg[4]&(FmaRdRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | (FmaRdXNaN&(FmaRdRes[`H_LEN-2:0] === {FmaRdX[`H_LEN-2:`H_NF],1'b1,FmaRdX[`H_NF-2:0]})) | (FmaRdYNaN&(FmaRdRes[`H_LEN-2:0] === {FmaRdY[`H_LEN-2:`H_NF],1'b1,FmaRdY[`H_NF-2:0]})) | (FmaRdZNaN&(FmaRdRes[`H_LEN-2:0] === {FmaRdZ[`H_LEN-2:`H_NF],1'b1,FmaRdZ[`H_NF-2:0]}))); endcase case (FmaFmtVal) - 4'b11: FmaRnmNaNGood =(((`IEEE754==0)&(FmaRneRes === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + 4'b11: FmaRnmNaNGood =(((`IEEE754==0)&FmaRnmAnsNaN&(FmaRnmRes === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | (FmaRnmAnsFlg[4]&(FmaRnmRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | (FmaRnmXNaN&(FmaRnmRes[`Q_LEN-2:0] === {FmaRnmX[`Q_LEN-2:`Q_NF],1'b1,FmaRnmX[`Q_NF-2:0]})) | (FmaRnmYNaN&(FmaRnmRes[`Q_LEN-2:0] === {FmaRnmY[`Q_LEN-2:`Q_NF],1'b1,FmaRnmY[`Q_NF-2:0]})) | (FmaRnmZNaN&(FmaRnmRes[`Q_LEN-2:0] === {FmaRnmZ[`Q_LEN-2:`Q_NF],1'b1,FmaRnmZ[`Q_NF-2:0]}))); - 4'b01: FmaRnmNaNGood =(((`IEEE754==0)&(FmaRneRes === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + 4'b01: FmaRnmNaNGood =(((`IEEE754==0)&FmaRnmAnsNaN&(FmaRnmRes[`D_LEN-1:0] === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | (FmaRnmAnsFlg[4]&(FmaRnmRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | (FmaRnmXNaN&(FmaRnmRes[`D_LEN-2:0] === {FmaRnmX[`D_LEN-2:`D_NF],1'b1,FmaRnmX[`D_NF-2:0]})) | (FmaRnmYNaN&(FmaRnmRes[`D_LEN-2:0] === {FmaRnmY[`D_LEN-2:`D_NF],1'b1,FmaRnmY[`D_NF-2:0]})) | (FmaRnmZNaN&(FmaRnmRes[`D_LEN-2:0] === {FmaRnmZ[`D_LEN-2:`D_NF],1'b1,FmaRnmZ[`D_NF-2:0]}))); - 4'b00: FmaRnmNaNGood =(((`IEEE754==0)&(FmaRneRes === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + 4'b00: FmaRnmNaNGood =(((`IEEE754==0)&FmaRnmAnsNaN&(FmaRnmRes[`S_LEN-1:0] === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | (FmaRnmAnsFlg[4]&(FmaRnmRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | (FmaRnmXNaN&(FmaRnmRes[`S_LEN-2:0] === {FmaRnmX[`S_LEN-2:`S_NF],1'b1,FmaRnmX[`S_NF-2:0]})) | (FmaRnmYNaN&(FmaRnmRes[`S_LEN-2:0] === {FmaRnmY[`S_LEN-2:`S_NF],1'b1,FmaRnmY[`S_NF-2:0]})) | (FmaRnmZNaN&(FmaRnmRes[`S_LEN-2:0] === {FmaRnmZ[`S_LEN-2:`S_NF],1'b1,FmaRnmZ[`S_NF-2:0]}))); - 4'b10: FmaRnmNaNGood =(((`IEEE754==0)&(FmaRneRes === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + 4'b10: FmaRnmNaNGood =(((`IEEE754==0)&FmaRnmAnsNaN&(FmaRnmRes[`H_LEN-1:0] === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | (FmaRnmAnsFlg[4]&(FmaRnmRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | (FmaRnmXNaN&(FmaRnmRes[`H_LEN-2:0] === {FmaRnmX[`H_LEN-2:`H_NF],1'b1,FmaRnmX[`H_NF-2:0]})) | (FmaRnmYNaN&(FmaRnmRes[`H_LEN-2:0] === {FmaRnmY[`H_LEN-2:`H_NF],1'b1,FmaRnmY[`H_NF-2:0]})) | @@ -1140,22 +1140,22 @@ end endcase if (UnitVal !== `CVTFPUNIT & UnitVal !== `CVTINTUNIT) case (FmtVal) - 4'b11: NaNGood = (((`IEEE754==0)&(Res === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + 4'b11: NaNGood = (((`IEEE754==0)&AnsNaN&(Res === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | (AnsFlg[4]&(Res[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | (XNaN&(Res[`Q_LEN-2:0] === {X[`Q_LEN-2:`Q_NF],1'b1,X[`Q_NF-2:0]})) | (YNaN&(Res[`Q_LEN-2:0] === {Y[`Q_LEN-2:`Q_NF],1'b1,Y[`Q_NF-2:0]})) | (ZNaN&(Res[`Q_LEN-2:0] === {Z[`Q_LEN-2:`Q_NF],1'b1,Z[`Q_NF-2:0]}))); - 4'b01: NaNGood = (((`IEEE754==0)&(Res === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + 4'b01: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`D_LEN-1:0] === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | (AnsFlg[4]&(Res[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | (XNaN&(Res[`D_LEN-2:0] === {X[`D_LEN-2:`D_NF],1'b1,X[`D_NF-2:0]})) | (YNaN&(Res[`D_LEN-2:0] === {Y[`D_LEN-2:`D_NF],1'b1,Y[`D_NF-2:0]})) | (ZNaN&(Res[`D_LEN-2:0] === {Z[`D_LEN-2:`D_NF],1'b1,Z[`D_NF-2:0]}))); - 4'b00: NaNGood = (((`IEEE754==0)&(Res === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + 4'b00: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`S_LEN-1:0] === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | (AnsFlg[4]&(Res[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | (XNaN&(Res[`S_LEN-2:0] === {X[`S_LEN-2:`S_NF],1'b1,X[`S_NF-2:0]})) | (YNaN&(Res[`S_LEN-2:0] === {Y[`S_LEN-2:`S_NF],1'b1,Y[`S_NF-2:0]})) | (ZNaN&(Res[`S_LEN-2:0] === {Z[`S_LEN-2:`S_NF],1'b1,Z[`S_NF-2:0]}))); - 4'b10: NaNGood = (((`IEEE754==0)&(Res === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + 4'b10: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`H_LEN-1:0] === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | (AnsFlg[4]&(Res[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | (XNaN&(Res[`H_LEN-2:0] === {X[`H_LEN-2:`H_NF],1'b1,X[`H_NF-2:0]})) | (YNaN&(Res[`H_LEN-2:0] === {Y[`H_LEN-2:`H_NF],1'b1,Y[`H_NF-2:0]})) | @@ -1163,22 +1163,22 @@ end endcase else if (UnitVal === `CVTFPUNIT) // if converting from floating point to floating point OpCtrl contains the final FP format case (OpCtrlVal[1:0]) - 2'b11: NaNGood = (((`IEEE754==0)&(Res === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + 2'b11: NaNGood = (((`IEEE754==0)&AnsNaN&(Res === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | (AnsFlg[4]&(Res[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | (AnsNaN&(Res[`Q_LEN-2:0] === Ans[`Q_LEN-2:0])) | (XNaN&(Res[`Q_LEN-2:0] === {X[`Q_LEN-2:`Q_NF],1'b1,X[`Q_NF-2:0]})) | (YNaN&(Res[`Q_LEN-2:0] === {Y[`Q_LEN-2:`Q_NF],1'b1,Y[`Q_NF-2:0]}))); - 2'b01: NaNGood = (((`IEEE754==0)&(Res === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + 2'b01: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`D_LEN-1:0] === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | (AnsFlg[4]&(Res[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | (AnsNaN&(Res[`D_LEN-2:0] === Ans[`D_LEN-2:0])) | (XNaN&(Res[`D_LEN-2:0] === {X[`D_LEN-2:`D_NF],1'b1,X[`D_NF-2:0]})) | (YNaN&(Res[`D_LEN-2:0] === {Y[`D_LEN-2:`D_NF],1'b1,Y[`D_NF-2:0]}))); - 2'b00: NaNGood = (((`IEEE754==0)&(Res === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + 2'b00: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`S_LEN-1:0] === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | (AnsFlg[4]&(Res[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | (AnsNaN&(Res[`S_LEN-2:0] === Ans[`S_LEN-2:0])) | (XNaN&(Res[`S_LEN-2:0] === {X[`S_LEN-2:`S_NF],1'b1,X[`S_NF-2:0]})) | (YNaN&(Res[`S_LEN-2:0] === {Y[`S_LEN-2:`S_NF],1'b1,Y[`S_NF-2:0]}))); - 2'b10: NaNGood = (((`IEEE754==0)&(Res === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + 2'b10: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`H_LEN-1:0] === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | (AnsFlg[4]&(Res[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | (AnsNaN&(Res[`H_LEN-2:0] === Ans[`H_LEN-2:0])) | (XNaN&(Res[`H_LEN-2:0] === {X[`H_LEN-2:`H_NF],1'b1,X[`H_NF-2:0]})) | @@ -1452,14 +1452,14 @@ module readvectors ( case (Fmt) 2'b11: begin // quad X = TestVector[8+3*(`Q_LEN)-1:8+2*(`Q_LEN)]; - if(OpCtrl === `MUL_OPCTRL) Y = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; else Y = {2'b0, {`Q_NE-1{1'b1}}, `Q_NF'h0}; + if(OpCtrl === `MUL_OPCTRL) Y = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; else Y = {2'b0, {`Q_NE-1{1'b1}}, (`Q_NF)'(0)}; if(OpCtrl === `MUL_OPCTRL) Z = 0; else Z = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; Ans = TestVector[8+(`Q_LEN-1):8]; end 2'b01: begin // double X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+3*(`D_LEN)-1:8+2*(`D_LEN)]}; if(OpCtrl === `MUL_OPCTRL) Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]}; - else Y = {{`FLEN-`D_LEN{1'b1}}, 2'b0, {`D_NE-1{1'b1}}, `D_NF'h0}; + else Y = {{`FLEN-`D_LEN{1'b1}}, 2'b0, {`D_NE-1{1'b1}}, (`D_NF)'(0)}; if(OpCtrl === `MUL_OPCTRL) Z = {{`FLEN-`D_LEN{1'b1}}, {`D_LEN{1'b0}}}; else Z = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]}; Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; @@ -1467,7 +1467,7 @@ module readvectors ( 2'b00: begin // single X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+3*(`S_LEN)-1:8+2*(`S_LEN)]}; if(OpCtrl === `MUL_OPCTRL) Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+(`S_LEN)]}; - else Y = {{`FLEN-`S_LEN{1'b1}}, 2'b0, {`S_NE-1{1'b1}}, `S_NF'h0}; + else Y = {{`FLEN-`S_LEN{1'b1}}, 2'b0, {`S_NE-1{1'b1}}, (`S_NF)'(0)}; if(OpCtrl === `MUL_OPCTRL) Z = {{`FLEN-`S_LEN{1'b1}}, {`S_LEN{1'b0}}}; else Z = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+(`S_LEN)]}; Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; @@ -1475,7 +1475,7 @@ module readvectors ( 2'b10: begin // half X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+3*(`H_LEN)-1:8+2*(`H_LEN)]}; if(OpCtrl === `MUL_OPCTRL) Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]}; - else Y = {{`FLEN-`H_LEN{1'b1}}, 2'b0, {`H_NE-1{1'b1}}, `H_NF'h0}; + else Y = {{`FLEN-`H_LEN{1'b1}}, 2'b0, {`H_NE-1{1'b1}}, (`H_NF)'(0)}; if(OpCtrl === `MUL_OPCTRL) Z = {{`FLEN-`H_LEN{1'b1}}, {`H_LEN{1'b0}}}; else Z = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]}; Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; From 0e7630dc0379a56b6bede046540baf3a6650559e Mon Sep 17 00:00:00 2001 From: DTowersM Date: Mon, 6 Jun 2022 22:39:22 +0000 Subject: [PATCH 6/7] simplified makefile. Now can call modelsim to run embench runs. Additionally added spike builds to be able to run the embench tests on spike. typing make now builds all necessary files and starts the simulator on the embench --- benchmarks/embench/Makefile | 64 +++++++++++++++++++++---------------- 1 file changed, 36 insertions(+), 28 deletions(-) diff --git a/benchmarks/embench/Makefile b/benchmarks/embench/Makefile index 4a4875dfa..1525a2b82 100644 --- a/benchmarks/embench/Makefile +++ b/benchmarks/embench/Makefile @@ -2,39 +2,56 @@ # Expanded and developed by dtorres@hmc.edu # Compile Embench for Wally -all: build sim +all: sim size allClean: clean all build: buildspeed buildsize +# uses the build_all.py python file to build the tests in addins/embench-iot/bd_speed/ optimized for speed buildspeed: - ../../addins/embench-iot/build_all.py --builddir=bd_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S" --cflags="-nostartfiles" + ../../addins/embench-iot/build_all.py --builddir=bd_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S" --cflags="-O2 -nostartfiles" find ../../addins/embench-iot/bd_speed/ -type f ! -name "*.*" | while read f; do cp "$$f" "$$f.elf"; done +# uses the build_all.py python file to build the tests in addins/embench-iot/bd_speed/ optimized for size buildsize: - ../../addins/embench-iot/build_all.py --builddir=bd_size --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostdlib -nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/dummy.S" --cflags="-msave-restore" --dummy-libs="libgcc libm libc crt0" + ../../addins/embench-iot/build_all.py --builddir=bd_size --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostdlib -nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/dummy.S" --cflags="-Os -msave-restore" --dummy-libs="libgcc libm libc crt0" -sim: modelSimBuild speed +# builds dependencies, then launches modelsim and finally runs python wrapper script to present results +sim: modelsim_build_memfile modelsim_run speed -# vsim: -# cd ../../pipelined/regression/ -# vsim -c -do "do wally-pipelined-batch.do rv32gc embench" -# cd ../../benchmarks/embench/ - -modelSimBuild: buildspeed objdump - find ../../addins/embench-iot/bd_speed/ -type f -name "*.elf" | while read f; do riscv64-unknown-elf-elf2hex --bit-width 32 --input "$$f" --output "$$f.memfile"; done - find ../../addins/embench-iot/bd_speed/ -type f -name "*.elf.objdump" | while read f; do extractFunctionRadix.sh $$f; done - -size: - ../../addins/embench-iot/benchmark_size.py --builddir=bd_size - -speed: - ../../addins/embench-iot/benchmark_speed.py --builddir=bd_speed --target-module run_wally --cpu-mhz=1 +# launches modelsim to simulate tests on wally +modelsim_run: + (cd ../../pipelined/regression/ && vsim -c -do "do wally-pipelined-batch.do rv32gc embench") + cd ../../benchmarks/embench/ +# builds the objdump based on the compiled c elf files objdump: buildspeed find ../../addins/embench-iot/bd_speed/ -type f -name "*.elf" | while read f; do riscv64-unknown-elf-objdump -S -D "$$f" > "$$f.objdump"; done +# build memfiles, objdump.lab and objdump.addr files +modelsim_build_memfile: objdump + find ../../addins/embench-iot/bd_speed/ -type f -name "*.elf" | while read f; do riscv64-unknown-elf-elf2hex --bit-width 32 --input "$$f" --output "$$f.memfile"; done + find ../../addins/embench-iot/bd_speed/ -type f -name "*.elf.objdump" | while read f; do extractFunctionRadix.sh $$f; done + +# builds the tests for speed, runs them on spike and then launches python script to present results +# note that the speed python script benchmark_speed.py can get confused if there's both a .output file created from spike and modelsim +# you'll need to manually remove one of the two .output files, or run make clean +spike: buildspeed spikecmd speed + +# command to run spike on all of the benchmarks +spike_run: buildspeed + find ../../addins/embench-iot/bd_speed/ -type f -name "*.elf" | while read f; do spike --isa=rv32imac +signature=$$f.spike.output +signature-granularity=4 $$f; done + +# python wrapper to present results of embench size benchmark +size: buildsize + ../../addins/embench-iot/benchmark_size.py --builddir=bd_size + +# python wrapper to present results of embench speed benchmark +speed: + ../../addins/embench-iot/benchmark_speed.py --builddir=bd_speed --target-module run_wally --cpu-mhz=1 + +# deletes all files clean: rm -rf ../../addins/embench-iot/bd_speed/ rm -rf ../../addins/embench-iot/bd_size/ @@ -42,13 +59,4 @@ clean: allclean: clean rm -rf ../../addins/embench-iot/logs/ -# std: -# ../../addins/embench-iot/build_all.py --builddir=bd_std --arch riscv32 --chip generic --board rv32wallyverilog --cc riscv64-unknown-elf-gcc --cflags="-v -c -O2 -ffunction-sections -march=rv32imac -mabi=ilp32" --ldflags="-Wl,-gc-sections -v -march=rv32imac -mabi=ilp32 ../../../../../benchmarks/embench/tohost.S -T../../../config/riscv32/boards/rv32wallyverilog/link.ld" --user-libs="-lm" -# riscv64-unknown-elf-objdump -D ../../addins/embench-iot/bd_std/src/aha-mont64/aha-mont64 > ../../addins/embench-iot/bd_std/src/aha-mont64/aha-mont64.objdump -# --dummy-libs="libgcc libm libc" -# --cflags "-O2 -g -nostartfiles" -# ../../addins/embench-iot/build_all.py --arch riscv32 --chip generic --board rv32wallyverilog --cc riscv64-unknown-elf-gcc --cflags="-c -Os -ffunction-sections -nostdlib -march=rv32imac -mabi=ilp32" --ldflags="-Wl,-gc-sections -nostdlib -march=rv32imac -mabi=ilp32 -T../../../config/riscv32/boards/rv32wallyverilog/link.ld" --dummy-libs="libgcc libm libc" -# --user-libs="-lm" -# riscv64-unknown-elf-gcc -O2 -g -nostartfiles -I/home/harris/riscv-wally/addins/embench-iot/support -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32/boards/ri5cyverilator -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32/chips/generic -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32 -DCPU_MHZ=1 -DWARMUP_HEAT=1 -o main.o /home/harris/riscv-wally/addins/embench-iot/support/main.c - -# find ../../addins/embench-iot/bd_speed/ -type f -name "*.elf.objdump.lab" | while read f; do grep -n "begin_signature" $f | cut -f1 -d: +# riscv64-unknown-elf-gcc -O2 -g -nostartfiles -I/home/harris/riscv-wally/addins/embench-iot/support -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32/boards/ri5cyverilator -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32/chips/generic -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32 -DCPU_MHZ=1 -DWARMUP_HEAT=1 -o main.o /home/harris/riscv-wally/addins/embench-iot/support/main.c \ No newline at end of file From fbfae61ba876a7c1db544ca0ae31bc1914665e51 Mon Sep 17 00:00:00 2001 From: DTowersM Date: Tue, 7 Jun 2022 06:02:23 +0000 Subject: [PATCH 7/7] added support for 64 bit rv tests --- pipelined/testbench/testbench.sv | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 211dae08c..09c3aac28 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -220,14 +220,18 @@ logic [3:0] dummy; adrstr = "0"; ProgramLabelMap = $fopen(ProgramLabelMapFile, "r"); ProgramAddrMap = $fopen(ProgramAddrMapFile, "r"); - while (!$feof(ProgramLabelMap)) begin - string addr, label; - integer returncode; - returncode = $fgets(label, ProgramLabelMap); - returncode = $fgets(addr, ProgramAddrMap); - if (label == "begin_signature\n") begin - adrstr = addr[4:7]; - if (DEBUG) $display("adrstr: %s", adrstr); + if (ProgramLabelMap & ProgramAddrMap) begin // check we found both files + while (!$feof(ProgramLabelMap)) begin + string addr, label; + integer returncode; + returncode = $fgets(label, ProgramLabelMap); + returncode = $fgets(addr, ProgramAddrMap); + if (label == "begin_signature\n") begin + adrstr = addr[1:7]; + if (adrstr=="0000000") // if running on rv64 we get the address at a later + adrstr = addr[9:15]; + if (DEBUG) $display("%s begin_signature adrstr: %s", TEST, adrstr); + end end end if (adrstr == "0") begin