From fdb7abec067db7de3d0f800d6f47a1d541adbdbc Mon Sep 17 00:00:00 2001
From: harshinisrinath <harshini.srinath@gmail.com>
Date: Sun, 20 Aug 2023 15:40:02 -0700
Subject: [PATCH] tried to improve testing of csri in privileged module

---
 testbench/tests.vh    |  2 +-
 tests/coverage/priv.S | 12 ++++++++++++
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/testbench/tests.vh b/testbench/tests.vh
index 116d39424..06c7e5f62 100644
--- a/testbench/tests.vh
+++ b/testbench/tests.vh
@@ -44,10 +44,10 @@ string tvpaths[] = '{
 
   string coverage64gc[] = '{
     `COVERAGE,
+    "priv",
     "ieu",
     "ebu",
     "csrwrites",
-    "priv",
     "ifu",
     "fpu",
     "lsu",
diff --git a/tests/coverage/priv.S b/tests/coverage/priv.S
index 0dff00f37..a8eacb9cc 100644
--- a/tests/coverage/priv.S
+++ b/tests/coverage/priv.S
@@ -59,11 +59,23 @@ sretdone:
     # 1st is when MENVCFG_STCE is cleared
     li a0, 3
     ecall # starts in M-mode
+    li t1, -3
+    csrw stimecmp, t1 # sets stimecmp to large value to prevent it from interrupting immediately
+    li t0, 2 
+    csrs mstatus, t0 # enables sie
+    li t0, 32
+    csrs sie, t0 # enables sie.stie
     csrw menvcfg, x0
     li a0, 1
     ecall   # enter S-mode
     csrw stimecmp, zero
     li a0, 3
+    ecall # in M-mode
+    li t0, 32
+    csrs sip, t0
+    li a0, 1
+    ecall # in S-mode and expects stimer interrupt to occur
+    li a0, 3
     ecall   # return to M-mode
     csrsi mcounteren, 2 # mcounteren_tm = 1
     li a0, 1