// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version   : 0.5.1
// timestamp : Mon Aug  2 08:58:53 2021 GMT
// usage     : riscv_ctg \
//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
//                  --base-isa rv32e \
//                  --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the lw instruction of the RISC-V E extension for the lw-align covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32E")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",lw-align)

RVTEST_SIGBASE( x2,signature_x2_1)

inst_0:
// rs1 != rd, rs1==x11, rd==x1, ea_align == 0 and (imm_val % 4) == 0, imm_val < 0
// opcode:lw op1:x11; dest:x1; immval:-0x400; align:0
TEST_LOAD(x2,x6,0,x11,x1,-0x400,0,lw,0)

inst_1:
// rs1 == rd, rs1==x14, rd==x14, ea_align == 0 and (imm_val % 4) == 1, 
// opcode:lw op1:x14; dest:x14; immval:-0x3; align:0
TEST_LOAD(x2,x6,0,x14,x14,-0x3,4,lw,0)

inst_2:
// rs1==x4, rd==x8, ea_align == 0 and (imm_val % 4) == 2, 
// opcode:lw op1:x4; dest:x8; immval:-0x556; align:0
TEST_LOAD(x2,x6,0,x4,x8,-0x556,8,lw,0)

inst_3:
// rs1==x1, rd==x10, ea_align == 0 and (imm_val % 4) == 3, 
// opcode:lw op1:x1; dest:x10; immval:-0x5; align:0
TEST_LOAD(x2,x6,0,x1,x10,-0x5,12,lw,0)

inst_4:
// rs1==x12, rd==x15, imm_val == 0, 
// opcode:lw op1:x12; dest:x15; immval:0x0; align:0
TEST_LOAD(x2,x6,0,x12,x15,0x0,16,lw,0)

inst_5:
// rs1==x7, rd==x13, imm_val > 0, 
// opcode:lw op1:x7; dest:x13; immval:0x20; align:0
TEST_LOAD(x2,x6,0,x7,x13,0x20,20,lw,0)

inst_6:
// rs1==x5, rd==x3, 
// opcode:lw op1:x5; dest:x3; immval:-0x800; align:0
TEST_LOAD(x2,x6,0,x5,x3,-0x800,24,lw,0)
RVTEST_SIGBASE( x1,signature_x1_0)

inst_7:
// rs1==x8, rd==x0, 
// opcode:lw op1:x8; dest:x0; immval:-0x800; align:0
TEST_LOAD(x1,x11,0,x8,x0,-0x800,0,lw,0)

inst_8:
// rs1==x3, rd==x12, 
// opcode:lw op1:x3; dest:x12; immval:-0x800; align:0
TEST_LOAD(x1,x11,0,x3,x12,-0x800,4,lw,0)

inst_9:
// rs1==x13, rd==x4, 
// opcode:lw op1:x13; dest:x4; immval:-0x800; align:0
TEST_LOAD(x1,x11,0,x13,x4,-0x800,8,lw,0)

inst_10:
// rs1==x15, rd==x7, 
// opcode:lw op1:x15; dest:x7; immval:-0x800; align:0
TEST_LOAD(x1,x11,0,x15,x7,-0x800,12,lw,0)

inst_11:
// rs1==x9, rd==x5, 
// opcode:lw op1:x9; dest:x5; immval:-0x800; align:0
TEST_LOAD(x1,x11,0,x9,x5,-0x800,16,lw,0)

inst_12:
// rs1==x6, rd==x9, 
// opcode:lw op1:x6; dest:x9; immval:-0x800; align:0
TEST_LOAD(x1,x11,0,x6,x9,-0x800,20,lw,0)

inst_13:
// rs1==x10, rd==x2, 
// opcode:lw op1:x10; dest:x2; immval:-0x800; align:0
TEST_LOAD(x1,x11,0,x10,x2,-0x800,24,lw,0)
RVTEST_SIGBASE( x1,signature_x1_1)

inst_14:
// rs1==x2, rd==x6, 
// opcode:lw op1:x2; dest:x6; immval:-0x800; align:0
TEST_LOAD(x1,x3,0,x2,x6,-0x800,0,lw,0)

inst_15:
// rd==x11, 
// opcode:lw op1:x5; dest:x11; immval:-0x800; align:0
TEST_LOAD(x1,x3,0,x5,x11,-0x800,4,lw,0)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4

rvtest_data:
.word 0xbabecafe
.word 0xbabecafe
.word 0xbabecafe
.word 0xbabecafe
RVTEST_DATA_END


RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;


signature_x2_0:
    .fill 0*(XLEN/32),4,0xdeadbeef


signature_x2_1:
    .fill 7*(XLEN/32),4,0xdeadbeef


signature_x1_0:
    .fill 7*(XLEN/32),4,0xdeadbeef


signature_x1_1:
    .fill 2*(XLEN/32),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*(XLEN/32),4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
