CRC32 Calculator Testbench
==========================

This is a primitive testbench to check the basic functionality of the CRC32
primitive. It is not intended as a full verification environment.

It is built via fusesoc (from repository root)

  ```sh
  fusesoc --cores-root=. run --target=sim --setup --build lowrisc:prim:crc32_sim
  ./build/lowrisc_prim_crc32_sim_0/sim-verilator/Vprim_crc32_sim
  ```

`predv_expected.txt` contains the expected output which can be generated by the
`expected_out.py` python script.  This is simply a dump of expected CRC values
as test data is fed in.

The `run_predv.sh` script will build and run the simulator and diff the output
against the expected output, producing an error if this results in a mismatch or
any other part of the process fails.
