// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version   : 0.5.1
// timestamp : Wed Aug  4 06:39:00 2021 GMT
// usage     : riscv_ctg \
//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
//                  --base-isa rv32e \
//                  --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.jr instruction of the RISC-V C extension for the cjr covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cjr)

RVTEST_SIGBASE( x1,signature_x1_1)

inst_0:
// rs1==x6, 
// opcode: c.jr; op1:x6
TEST_CJR_OP(x7, x6, x1, 0)

inst_1:
// rs1==x15, 
// opcode: c.jr; op1:x15
TEST_CJR_OP(x7, x15, x1, 4)

inst_2:
// rs1==x14, 
// opcode: c.jr; op1:x14
TEST_CJR_OP(x7, x14, x1, 8)

inst_3:
// rs1==x13, 
// opcode: c.jr; op1:x13
TEST_CJR_OP(x7, x13, x1, 12)

inst_4:
// rs1==x3, 
// opcode: c.jr; op1:x3
TEST_CJR_OP(x7, x3, x1, 16)

inst_5:
// rs1==x8, 
// opcode: c.jr; op1:x8
TEST_CJR_OP(x7, x8, x1, 20)

inst_6:
// rs1==x2, 
// opcode: c.jr; op1:x2
TEST_CJR_OP(x7, x2, x1, 24)

inst_7:
// rs1==x4, 
// opcode: c.jr; op1:x4
TEST_CJR_OP(x7, x4, x1, 28)

inst_8:
// rs1==x12, 
// opcode: c.jr; op1:x12
TEST_CJR_OP(x7, x12, x1, 32)

inst_9:
// rs1==x5, 
// opcode: c.jr; op1:x5
TEST_CJR_OP(x7, x5, x1, 36)

inst_10:
// rs1==x7, 
// opcode: c.jr; op1:x7
TEST_CJR_OP(x3, x7, x1, 40)
RVTEST_SIGBASE( x2,signature_x2_0)

inst_11:
// rs1==x9, 
// opcode: c.jr; op1:x9
TEST_CJR_OP(x3, x9, x2, 0)

inst_12:
// rs1==x1, 
// opcode: c.jr; op1:x1
TEST_CJR_OP(x3, x1, x2, 4)

inst_13:
// rs1==x11, 
// opcode: c.jr; op1:x11
TEST_CJR_OP(x3, x11, x2, 8)

inst_14:
// rs1==x10, 
// opcode: c.jr; op1:x10
TEST_CJR_OP(x3, x10, x2, 12)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4

rvtest_data:
.word 0xbabecafe
.word 0xbabecafe
.word 0xbabecafe
.word 0xbabecafe
RVTEST_DATA_END


RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;


signature_x1_0:
    .fill 0*(XLEN/32),4,0xdeadbeef


signature_x1_1:
    .fill 11*(XLEN/32),4,0xdeadbeef


signature_x2_0:
    .fill 4*(XLEN/32),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*(XLEN/32),4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
