
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version   : 0.4.1
// timestamp : Tue Dec 15 15:36:11 2020 GMT
// usage     : riscv_ctg \
//                  -- cgf ('/scratch/git-repo/incoresemi/riscv-compliance/riscv_ctg/sample_cgfs/dataset.cgf', '/scratch/git-repo/incoresemi/riscv-compliance/riscv_ctg/sample_cgfs/rv32i.cgf') \
//                  -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the lw instruction of the RISC-V I extension for the lw-align covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I")

.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",lw-align)

RVTEST_SIGBASE( x12,signature_x12_1)

inst_0:
// rs1 != rd, rs1==x6, rd==x24, ea_align == 0 and (imm_val % 4) == 0, imm_val < 0
// opcode:lw op1:x6; dest:x24; immval:-0x4; align:0
TEST_LOAD(x12,x17,0,x6,x24,-0x4,0,lw,0)

inst_1:
// rs1 == rd, rs1==x4, rd==x4, ea_align == 0 and (imm_val % 4) == 1, 
// opcode:lw op1:x4; dest:x4; immval:-0x3; align:0
TEST_LOAD(x12,x17,0,x4,x4,-0x3,4,lw,0)

inst_2:
// rs1==x21, rd==x15, ea_align == 0 and (imm_val % 4) == 2, 
// opcode:lw op1:x21; dest:x15; immval:-0xa; align:0
TEST_LOAD(x12,x17,0,x21,x15,-0xa,8,lw,0)

inst_3:
// rs1==x26, rd==x8, ea_align == 0 and (imm_val % 4) == 3, imm_val > 0
// opcode:lw op1:x26; dest:x8; immval:0x7; align:0
TEST_LOAD(x12,x17,0,x26,x8,0x7,12,lw,0)

inst_4:
// rs1==x27, rd==x26, imm_val == 0, 
// opcode:lw op1:x27; dest:x26; immval:0x0; align:0
TEST_LOAD(x12,x17,0,x27,x26,0x0,16,lw,0)

inst_5:
// rs1==x20, rd==x18, 
// opcode:lw op1:x20; dest:x18; immval:-0x800; align:0
TEST_LOAD(x12,x17,0,x20,x18,-0x800,20,lw,0)

inst_6:
// rs1==x30, rd==x9, 
// opcode:lw op1:x30; dest:x9; immval:-0x800; align:0
TEST_LOAD(x12,x17,0,x30,x9,-0x800,24,lw,0)

inst_7:
// rs1==x18, rd==x11, 
// opcode:lw op1:x18; dest:x11; immval:-0x800; align:0
TEST_LOAD(x12,x17,0,x18,x11,-0x800,28,lw,0)

inst_8:
// rs1==x13, rd==x6, 
// opcode:lw op1:x13; dest:x6; immval:-0x800; align:0
TEST_LOAD(x12,x17,0,x13,x6,-0x800,32,lw,0)

inst_9:
// rs1==x14, rd==x10, 
// opcode:lw op1:x14; dest:x10; immval:-0x800; align:0
TEST_LOAD(x12,x17,0,x14,x10,-0x800,36,lw,0)

inst_10:
// rs1==x9, rd==x3, 
// opcode:lw op1:x9; dest:x3; immval:-0x800; align:0
TEST_LOAD(x12,x17,0,x9,x3,-0x800,40,lw,0)

inst_11:
// rs1==x2, rd==x31, 
// opcode:lw op1:x2; dest:x31; immval:-0x800; align:0
TEST_LOAD(x12,x17,0,x2,x31,-0x800,44,lw,0)

inst_12:
// rs1==x23, rd==x0, 
// opcode:lw op1:x23; dest:x0; immval:-0x800; align:0
TEST_LOAD(x12,x17,0,x23,x0,-0x800,48,lw,0)

inst_13:
// rs1==x3, rd==x19, 
// opcode:lw op1:x3; dest:x19; immval:-0x800; align:0
TEST_LOAD(x12,x17,0,x3,x19,-0x800,52,lw,0)

inst_14:
// rs1==x7, rd==x13, 
// opcode:lw op1:x7; dest:x13; immval:-0x800; align:0
TEST_LOAD(x12,x17,0,x7,x13,-0x800,56,lw,0)

inst_15:
// rs1==x1, rd==x7, 
// opcode:lw op1:x1; dest:x7; immval:-0x800; align:0
TEST_LOAD(x12,x17,0,x1,x7,-0x800,60,lw,0)

inst_16:
// rs1==x19, rd==x14, 
// opcode:lw op1:x19; dest:x14; immval:-0x800; align:0
TEST_LOAD(x12,x17,0,x19,x14,-0x800,64,lw,0)

inst_17:
// rs1==x8, rd==x29, 
// opcode:lw op1:x8; dest:x29; immval:-0x800; align:0
TEST_LOAD(x12,x17,0,x8,x29,-0x800,68,lw,0)

inst_18:
// rs1==x24, rd==x5, 
// opcode:lw op1:x24; dest:x5; immval:-0x800; align:0
TEST_LOAD(x12,x17,0,x24,x5,-0x800,72,lw,0)

inst_19:
// rs1==x31, rd==x16, 
// opcode:lw op1:x31; dest:x16; immval:-0x800; align:0
TEST_LOAD(x12,x17,0,x31,x16,-0x800,76,lw,0)

inst_20:
// rs1==x10, rd==x25, 
// opcode:lw op1:x10; dest:x25; immval:-0x800; align:0
TEST_LOAD(x12,x17,0,x10,x25,-0x800,80,lw,0)

inst_21:
// rs1==x5, rd==x1, 
// opcode:lw op1:x5; dest:x1; immval:-0x800; align:0
TEST_LOAD(x12,x3,0,x5,x1,-0x800,84,lw,0)

inst_22:
// rs1==x15, rd==x22, 
// opcode:lw op1:x15; dest:x22; immval:-0x800; align:0
TEST_LOAD(x12,x3,0,x15,x22,-0x800,88,lw,0)
RVTEST_SIGBASE( x1,signature_x1_0)

inst_23:
// rs1==x17, rd==x27, 
// opcode:lw op1:x17; dest:x27; immval:-0x800; align:0
TEST_LOAD(x1,x3,0,x17,x27,-0x800,0,lw,0)

inst_24:
// rs1==x12, rd==x20, 
// opcode:lw op1:x12; dest:x20; immval:-0x800; align:0
TEST_LOAD(x1,x3,0,x12,x20,-0x800,4,lw,0)

inst_25:
// rs1==x28, rd==x30, 
// opcode:lw op1:x28; dest:x30; immval:-0x800; align:0
TEST_LOAD(x1,x3,0,x28,x30,-0x800,8,lw,0)

inst_26:
// rs1==x25, rd==x28, 
// opcode:lw op1:x25; dest:x28; immval:-0x800; align:0
TEST_LOAD(x1,x3,0,x25,x28,-0x800,12,lw,0)

inst_27:
// rs1==x22, rd==x12, 
// opcode:lw op1:x22; dest:x12; immval:-0x800; align:0
TEST_LOAD(x1,x3,0,x22,x12,-0x800,16,lw,0)

inst_28:
// rs1==x16, rd==x2, 
// opcode:lw op1:x16; dest:x2; immval:-0x800; align:0
TEST_LOAD(x1,x3,0,x16,x2,-0x800,20,lw,0)

inst_29:
// rs1==x29, rd==x21, 
// opcode:lw op1:x29; dest:x21; immval:-0x800; align:0
TEST_LOAD(x1,x3,0,x29,x21,-0x800,24,lw,0)

inst_30:
// rs1==x11, rd==x17, 
// opcode:lw op1:x11; dest:x17; immval:-0x800; align:0
TEST_LOAD(x1,x3,0,x11,x17,-0x800,28,lw,0)

inst_31:
// rd==x23, 
// opcode:lw op1:x12; dest:x23; immval:-0x800; align:0
TEST_LOAD(x1,x3,0,x12,x23,-0x800,32,lw,0)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4

rvtest_data:
.word 0xbabecafe
.word 0xbabecafe
.word 0xbabecafe
.word 0xbabecafe
RVTEST_DATA_END


RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;


signature_x12_0:
    .fill 0*(XLEN/32),4,0xdeadbeef


signature_x12_1:
    .fill 23*(XLEN/32),4,0xdeadbeef


signature_x1_0:
    .fill 9*(XLEN/32),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*(XLEN/32),4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
