# Copyright Google LLC
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#      http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.

# ================================================================================
#                  Regression test list format
# --------------------------------------------------------------------------------
# test            : Assembly test name
# description     : Description of this test
# gen_opts        : Instruction generator options
# iterations      : Number of iterations of this test
# no_iss          : Enable/disable ISS simulator (Optional)
# gen_test        : Test name used by the instruction generator
# asm_tests       : Path to directed, hand-coded assembly test file or directory
# rtl_test        : RTL simulation test name
# cmp_opts        : Compile options passed to the instruction generator
# sim_opts        : Simulation options passed to the instruction generator
# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional)
# compare_opts    : Options for the RTL & ISS trace comparison
# gcc_opts        : gcc compile options
# --------------------------------------------------------------------------------

- import: <riscv_dv_root>/yaml/base_testlist.yaml


- test: riscv_non_compressed_instr_test
  description: >
    Random instruction test without compressed instructions
  iterations: 1
  gen_test: riscv_rand_instr_test
  gen_opts: >
    +disable_compressed_instr=1
  rtl_test: core_base_test


- test: riscv_hint_instr_test
  description: >
    HINT instruction test, verify the processor can detect HINT instruction
    treat it as NOP. No illegal instruction exception is expected
  iterations: 2
  gen_test: riscv_rand_instr_test
  gen_opts: >
    +hint_instr_ratio=5
  rtl_test: core_base_test


- test: riscv_load_store_shared_mem_test
  description: >
    Multi-harts load/store from shared memory regions
  iterations: 2
  gen_test: riscv_rand_instr_test
  gen_opts: >
    +instr_cnt=5000
    +num_of_sub_program=5
    +directed_instr_0=riscv_load_store_shared_mem_stream,10
  rtl_test: core_base_test


- test: riscv_amo_test
  description: >
    RISC-V atomic instruction extension test
  iterations: 2
  gen_test: riscv_rand_instr_test
  gen_opts: >
    +instr_cnt=2000
    +num_of_sub_program=2
    +directed_instr_0=riscv_lr_sc_instr_stream,50
    +directed_instr_1=riscv_amo_instr_stream,50
  rtl_test: core_base_test


- test: riscv_single_hart_test
  description: >
    single hart random test
  iterations: 2
  gen_test: riscv_rand_instr_test
  gen_opts: >
    +instr_cnt=6000
    +num_of_harts=1
  rtl_test: core_base_test

