# Copyright Google LLC
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#      http:#www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.

# The -CFLAGS option is required as some VCS DPI code contains smart quotes
# around some preprocessor macros, making G++ throw errors during compilation.
# As a result, passing -fno-extended-identifiers tells G++ to pretend that
# everything is ASCII, preventing strange compilation errors.
- tool: vcs
  compile:
    cmd:
      - "vcs -f ibex_dv.f  -full64
         -l <out>/compile.log
         -sverilog -ntb_opts uvm-1.2
         +define+UVM
         +define+UVM_REGEX_NO_DPI -timescale=1ns/10ps -licqueue
         -LDFLAGS '-Wl,--no-as-needed'
         -CFLAGS '--std=c99 -fno-extended-identifiers'
         -Mdir=<out>/vcs_simv.csrc
         -o <out>/vcs_simv
         -debug_access+pp
         -xlrm uniq_prior_final
         -CFLAGS '--std=c99 -fno-extended-identifiers'
         -lca -kdb <cmp_opts> <wave_opts> <cov_opts>"
    cov_opts: >
      -cm line+tgl+assert+fsm+branch
      -cm_tgl portsonly
      -cm_tgl structarr
      -cm_report noinitial
      -cm_seqnoconst
      -cm_dir <out>/test.vdb
      -cm_hier cover.cfg
    wave_opts: >
      -debug_access+all -ucli -do vcs.tcl
  sim:
    cmd: >
      env SIM_DIR=<sim_dir>
        <out>/vcs_simv +vcs+lic+wait <sim_opts> <wave_opts> <cov_opts>
          +ntb_random_seed=<seed> +UVM_TESTNAME=<rtl_test> +bin=<binary>
          +ibex_tracer_file_base=<sim_dir>/trace_core
          -l <sim_dir>/sim.log
    cov_opts: >
      -cm line+tgl+assert+fsm+branch
      -cm_dir <out>/test.vdb
      -cm_log /dev/null
      -assert nopostproc
      -cm_name test_<test_name>_<iteration>
    wave_opts: >
      -ucli -do <cwd>/vcs.tcl

- tool: questa
  compile:
    cmd:
      - "vmap mtiUvm $QUESTA_HOME/questasim/uvm-1.2"
      - "vlog -64
              -access=rwc
              -f ibex_dv.f
              -sv
              -mfcu -cuname design_cuname
              +define+UVM_REGEX_NO_DPI
              +define+UVM
              -writetoplevels <out>/top.list
              -l <out>/compile.log <cmp_opts>"
  sim:
    cmd: >
      vsim -64 -c <cov_opts> -do "run -a; quit -f" +designfile -f <out>/top.list <sim_opts>  -sv_seed <seed> +access +r+w +UVM_TESTNAME=<rtl_test> +bin=<binary> +ibex_tracer_file_base="<sim_dir>/trace_core" -l <sim_dir>/sim.log
    cov_opts: >
      -do "coverage save -onexit <out>/cov.ucdb;"

- tool: dsim
  env_var: DSIM,DSIM_LIB_PATH
  compile:
    cmd:
      - "mkdir -p <out>/dsim"
      - "<DSIM> -sv -work <out>/dsim
                -genimage image
                +incdir+$UVM_HOME/src
                $UVM_HOME/src/uvm_pkg.sv
                +define+UVM
                +define+DSIM
                +acc+rwb
                -f ibex_dv.f
                -l <out>/dsim/compile.log
                -suppress EnumMustBePositive"
  sim:
    cmd: >
      <DSIM> <sim_opts> -sv_seed <seed> -pli_lib <DSIM_LIB_PATH>/libuvm_dpi.so +acc+rwb -image image -work <out>/dsim <wave_opts> +UVM_TESTNAME=<rtl_test> +bin=<binary> +ibex_tracer_file_base=<sim_dir>/trace_core -l <sim_dir>/sim.log
    wave_opts: >
      -waves waves.vcd

- tool: riviera
  env_var: ALDEC_PATH
  compile:
    cmd:
      - "vlib <out>/work"
      - "vlog -work <out>/work
        <cmp_opts>
        +incdir+<ALDEC_PATH>/vlib/uvm-1.2/src
        +define+UVM
        -l uvm_1_2
        -f ibex_dv.f"

  sim:
    cmd: >
      vsim -c <sim_opts> <cov_opts> -sv_seed <seed> -lib <out>/work +access +r+w +UVM_TESTNAME=<rtl_test> +bin=<binary> +ibex_tracer_file_base="<sim_dir>/trace_core" -l <sim_dir>/sim.log -do "run -all; endsim; quit -force"
    cov_opts: >
      -acdb_file <out>/cov.acdb

- tool: qrun
  compile:
    cmd:
      - "qrun -f ibex_dv.f -uvmhome uvm-1.2
              +define+UVM
              -svinputport=net
              -access=rw+/. -optimize
              -suppress 2583
              -mfcu -cuname design_cuname
              -sv -o design_opt
              -l <out>/qrun_compile_optimize.log
              -outdir <out>/qrun.out"
  sim:
    cmd: >
      qrun -simulate -snapshot design_opt <cov_opts> <sim_opts> -sv_seed <seed> -outdir <out>/qrun.out
    cov_opts: >
      -coverage -ucdb <out>/cov.ucdb


- tool: xlm
  compile:
    cmd:
      - "xrun -64bit
              -q
              -f ibex_dv.f
              -sv
              -licqueue
              -uvm
              -uvmhome CDNS-1.2
              -define UVM_REGEX_NO_DPI
              -elaborate
              -l <out>/compile.log
              -xmlibdirpath <out>
              <cmp_opts>
              <wave_opts>"
    wave_opts: >
      -access rwc -linedebug
  sim:
    cmd: >
      xrun -64bit
           -R
           -xmlibdirpath <out>
           -l <sim_dir>/sim.log
           -licqueue
           -svseed <seed>
           -svrnc rand_struct
           +UVM_TESTNAME=<rtl_test>
           +bin=<binary>
           +ibex_tracer_file_base=<sim_dir>/trace_core
           -nokey
           <sim_opts>
           <wave_opts>
    wave_opts: >
      -input @"database -open <sim_dir>/waves -shm -default"
      -input @"probe -create core_ibex_tb_top -all -depth all -variables"
      -input @"run"
