diff --git a/dv/uvm/core_ibex/Makefile b/dv/uvm/core_ibex/Makefile
index 5c3e0640..88265961 100644
--- a/dv/uvm/core_ibex/Makefile
+++ b/dv/uvm/core_ibex/Makefile
@@ -311,6 +311,9 @@ compile-vars-prereq = $(call vars-prereq,comp,compiling TB,$(compile-var-deps))
 
 $(call dump-vars-match,$(compile-var-deps),comp)
 
+cov-arg := $(if $(call equal,$(COV),1),--en_cov,)
+wave-arg := $(if $(call equal,$(WAVE),1),--en_wave,)
+
 $(OUT)/rtl_sim/.compile.stamp: \
   $(compile-vars-prereq) $(all-verilog) $(risc-dv-files) | $(OUT)/rtl_sim
 	@python3 ./sim.py \
@@ -318,9 +321,7 @@ $(OUT)/rtl_sim/.compile.stamp: \
      --riscv_dv_root=${GEN_DIR} \
      --steps=compile \
      ${COMMON_OPTS} \
-     --simulator="${SIMULATOR}" \
-     --en_cov=${COV} \
-     --en_wave=${WAVES} \
+     --simulator="${SIMULATOR}" $(cov-arg) $(wave-arg) \
      --cmp_opts="${COMPILE_OPTS}"
 	$(call dump-vars,$(OUT)/rtl_sim/.compile-vars.mk,comp,$(compile-var-deps))
 	@touch $@
@@ -354,9 +355,7 @@ $(metadata)/rtl_sim.run.stamp: \
      --riscv_dv_root=${GEN_DIR} \
      --steps=sim \
      ${TEST_OPTS} \
-     --simulator="${SIMULATOR}" \
-     --en_cov ${COV} \
-     --en_wave ${WAVES} \
+     --simulator="${SIMULATOR}" $(cov-arg) $(wave-arg) \
      --lsf_cmd="${LSF_CMD}" \
      --sim_opts="+signature_addr=${SIGNATURE_ADDR}" \
      ${SIM_OPTS}
diff --git a/dv/uvm/core_ibex/sim.py b/dv/uvm/core_ibex/sim.py
index 7ee67cf2..487d2c97 100644
--- a/dv/uvm/core_ibex/sim.py
+++ b/dv/uvm/core_ibex/sim.py
@@ -320,9 +320,9 @@ def main():
                         help="Compile options for the generator")
     parser.add_argument("--sim_opts", type=str, default="",
                         help="Simulation options for the generator")
-    parser.add_argument("--en_cov", type=str, default=0,
+    parser.add_argument("--en_cov", action='store_true',
                         help="Enable coverage dump")
-    parser.add_argument("--en_wave", type=str, default=0,
+    parser.add_argument("--en_wave", action='store_true',
                         help="Enable waveform dump")
     parser.add_argument("--steps", type=str, default="all",
                         help="Run steps: compile,sim,compare")
@@ -350,8 +350,8 @@ def main():
     matched_list = []
     if steps['compile'] or steps['sim']:
         enables = {
-            'cov_opts': True if args.en_cov == '1' else False,
-            'wave_opts': True if args.en_wave == '1' else False
+            'cov_opts': args.en_cov,
+            'wave_opts': args.en_wave
         }
         compile_cmds, sim_cmd = get_simulator_cmd(args.simulator,
                                                   args.simulator_yaml, enables)