diff --git a/debug_unit.sv b/debug_unit.sv
index 0520ffc0..e191bb71 100644
--- a/debug_unit.sv
+++ b/debug_unit.sv
@@ -64,14 +64,14 @@ module riscv_debug_unit
   output logic [31:0] npc_o,
   output logic        set_npc_o
 
-  );
+);
 
   // registers for debug control
-  logic [1:0]         DSR_DP,  DSR_DN;  // Debug Stop Register: IIE, INTE
-  logic [1:0]         DMR1_DP, DMR1_DN; // only single step trace and branch trace bits
+  logic [1:0] DSR_DP,  DSR_DN;  // Debug Stop Register: IIE, INTE
+  logic [1:0] DMR1_DP, DMR1_DN; // only single step trace and branch trace bits
 
   // BP control FSM
-  enum logic [2:0]   {Idle, Trap, DebugStall, StallCore} BP_State_SN, BP_State_SP;
+  enum logic [2:0] {Idle, Trap, DebugStall, StallCore} BP_State_SN, BP_State_SP;
 
   // ack to debug interface
   assign dbginf_ack_o = dbginf_strobe_i && ((BP_State_SP == StallCore) || (dbginf_addr_i[15:11] == 5'b00110));
@@ -193,8 +193,8 @@ module riscv_debug_unit
         // some other SPR is accessed
         else
         begin
-          sp_mux_o        = 1'b1;
-          regfile_addr_o  = dbginf_addr_i[11:0];
+          sp_mux_o       = 1'b1;
+          regfile_addr_o = dbginf_addr_i[11:0];
 
           if(dbginf_we_i == 1'b1)
             regfile_we_o = 1'b1;
@@ -205,8 +205,8 @@ module riscv_debug_unit
     end
   end
 
-  // normal FF setup
-  always_ff@(posedge clk or negedge rst_n) begin
+  always_ff@(posedge clk, negedge rst_n)
+  begin
     if (~rst_n) begin
       DMR1_DP     <= 2'b0;
       DSR_DP      <= 'b0;
@@ -217,6 +217,6 @@ module riscv_debug_unit
       DSR_DP      <= DSR_DN;
       BP_State_SP <= BP_State_SN;
     end
-  end // always_ff@ (posedge clk or negedge rst_n)
+  end
 
 endmodule // debug_unit
diff --git a/riscv_core.sv b/riscv_core.sv
index 79dfbaac..f9f5eb8f 100644
--- a/riscv_core.sv
+++ b/riscv_core.sv
@@ -145,6 +145,7 @@ module riscv_core
   logic        csr_access_ex;
   logic  [1:0] csr_op_ex;
 
+  logic        csr_access;
   logic  [1:0] csr_op;
   logic [11:0] csr_addr;
   logic [31:0] csr_rdata;
@@ -589,11 +590,13 @@ module riscv_core
   );
 
   // Mux for CSR access through Debug Unit
-  assign csr_addr      = (dbg_sp_mux == 1'b0) ? alu_operand_b_ex[11:0] : dbg_reg_addr;
-  assign csr_wdata     = (dbg_sp_mux == 1'b0) ? alu_operand_a_ex : dbg_reg_wdata;
-  assign csr_op        = (dbg_sp_mux == 1'b0) ? csr_op_ex
-                                              : (dbg_reg_we == 1'b1 ? `CSR_OP_WRITE : `CSR_OP_NONE);
-  assign dbg_rdata     = (dbg_sp_mux == 1'b0) ? dbg_reg_rdata    : csr_rdata;
+  assign csr_access = (dbg_sp_mux == 1'b0) ? csr_access_ex : 1'b1;
+  assign csr_addr   = (dbg_sp_mux == 1'b0) ? alu_operand_b_ex[11:0] : dbg_reg_addr;
+  assign csr_wdata  = (dbg_sp_mux == 1'b0) ? alu_operand_a_ex : dbg_reg_wdata;
+  assign csr_op     = (dbg_sp_mux == 1'b0) ? csr_op_ex
+                                           : (dbg_reg_we == 1'b1 ? `CSR_OP_WRITE
+                                                                 : `CSR_OP_NONE );
+  assign dbg_rdata  = (dbg_sp_mux == 1'b0) ? dbg_reg_rdata : csr_rdata;
 
 
   /////////////////////////////////////////////////////////////