diff --git a/id_stage.sv b/id_stage.sv
index e9703e90..16a1ca1c 100644
--- a/id_stage.sv
+++ b/id_stage.sv
@@ -169,7 +169,6 @@ module riscv_id_stage
     output logic        alu_req_ex_o,
     `endif
 
-
     // CSR ID/EX
     output logic        csr_access_ex_o,
     output logic [1:0]  csr_op_ex_o,
@@ -1472,7 +1471,7 @@ always_ff @(posedge clk, negedge rst_n)
         data_misaligned_ex_o        <= 1'b1;
         // CONFIG_REGION: SPLITTED_ADDER
         `ifdef  SPLITTED_ADDER
-        alu_req_ex_o                <= 1'b0;
+        alu_req_ex_o                <= 1'b1;
         `endif
       end
     end
@@ -1614,9 +1613,11 @@ always_ff @(posedge clk, negedge rst_n)
         `endif // ONLY_ALIGNED
         branch_in_ex_o              <= 1'b0;
       end
+      `ifdef SPLITTED_ADDER
       else begin
         alu_req_ex_o                <= 1'b0; // We cannot deliver new data to ALU (running or not running)
       end
+      `endif
     end
   end
 
diff --git a/include/riscv_config.sv b/include/riscv_config.sv
index 101dc1e3..b74c7bce 100644
--- a/include/riscv_config.sv
+++ b/include/riscv_config.sv
@@ -109,6 +109,10 @@
 // will only allow aligned memory accesses and therefore overlapping mustn't occur
 //`define ONLY_ALIGNED
 
+// CONFIG: SPLITTED_ADDER
+// will split ALU Adder in half and use two cycles to add operands
+`define SPLITTED_ADDER
+
 `endif
 `endif
 `endif