diff --git a/dv/uvm/Makefile b/dv/uvm/Makefile index 9e3374ce..0eb5748e 100644 --- a/dv/uvm/Makefile +++ b/dv/uvm/Makefile @@ -2,40 +2,41 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -DV_DIR := $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST)))) -GEN_DIR := $(realpath ${DV_DIR}/../../vendor/google_riscv-dv) -TOOLCHAIN := ${RISCV_TOOLCHAIN} -OUT := "${DV_DIR}/out" +DV_DIR := $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST)))) +GEN_DIR := $(realpath ${DV_DIR}/../../vendor/google_riscv-dv) +TOOLCHAIN := ${RISCV_TOOLCHAIN} +OUT := "${DV_DIR}/out" # Run time options for the instruction generator -GEN_OPTS := +GEN_OPTS := # Run time options for ibex RTL simulation -SIM_OPTS := +SIM_OPTS := # Enable waveform dumping -WAVES := 1 +WAVES := 1 # Enable coverage dump -COV := 0 +COV := 0 # RTL simulator -SIMULATOR := "vcs" +SIMULATOR := "vcs" # ISS (spike, ovpsim) -ISS := "spike" +ISS := "spike" # ISA -ISA := "rv32imc" +ISA := "rv32imc" # Test name (default: full regression) -TEST := "all" +TEST := "all" # Seed for instruction generator and RTL simulation -SEED := -1 +SEED := -1 # Verbose logging -VERBOSE := +VERBOSE := # Number of iterations for each test, assign a non-zero value to override the # iteration count in the test list -ITERATIONS := 0 +ITERATIONS := 0 # LSF CMD -LSF_CMD := - +LSF_CMD := +# Generator timeout limit in seconds +TIMEOUT := 1800 # Privileged CSR YAML description file -CSR_FILE := ${DV_DIR}/riscv_dv_extension/csr_description.yaml +CSR_FILE := ${DV_DIR}/riscv_dv_extension/csr_description.yaml # Pass/fail signature address at the end of test -END_SIGNATURE_ADDR := 0x8ffffffc +END_SIGNATURE_ADDR := 8ffffffc # Value written to END_SIGNATURE_ADDR that indicates test success PASS_VAL := 0x1 # Value written to END_SIGNATURE_ADDR that indicates test failure @@ -65,7 +66,7 @@ endif # Options used for privileged CSR test generation CSR_OPTS=--csr_yaml=${CSR_FILE} \ --isa=${ISA} \ - --end_signature_addr=${END_SIGNATURE_ADDR} + --end_signature_addr=0x${END_SIGNATURE_ADDR} # Generate random instructions .SILENT gen: @@ -74,6 +75,7 @@ CSR_OPTS=--csr_yaml=${CSR_FILE} \ python3 ./run.py \ --o=${OUT}/instr_gen ${GEN_OPTS} \ --steps=gen \ + --gen_timeout=${TIMEOUT} \ --lsf_cmd="${LSF_CMD}" \ ${COMMON_OPTS} \ ${CSR_OPTS} \ @@ -89,6 +91,7 @@ gcc_compile: --o=${OUT}/instr_gen ${GEN_OPTS} \ --steps=gcc_compile \ ${COMMON_OPTS} \ + --gcc_opts=-mno-strict-align \ --isa=${ISA} \ --mabi=ilp32 diff --git a/dv/uvm/compare b/dv/uvm/compare deleted file mode 100755 index ddcfb95c..00000000 --- a/dv/uvm/compare +++ /dev/null @@ -1,57 +0,0 @@ -#!/bin/bash - -# Copyright lowRISC contributors. -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -RUN_DIR="$1" -report_file="$1/regr.log" -rm -rf "$report_file" -script_path="../../vendor/google_riscv-dv" - -compare_log () { - spike_log="$1" - ibex_log="$2" - # ----------------------------------------------------------------------------- - # Convert spike log to standard instruction trace csv - # ----------------------------------------------------------------------------- - # Remove all the init spike boot instructions - # 0xffffffff80000080 is the first user instruction - sed -i '/0xffffffff80000080/,$!d' "$spike_log" - # Remove all instructions after ecall (end of program excecution) - sed -i '/ecall/q' "$spike_log" - # Convert the spike log to riscv_instr_trace.proto format - spike_csv=$(echo "$spike_log" | sed 's/\.log/.csv/g') - python $script_path/scripts/spike_log_to_trace_csv.py \ - --log $spike_log --csv $spike_csv >> $report_file - - # ----------------------------------------------------------------------------- - # Convert ibex log to standard instruction trace csv - # ----------------------------------------------------------------------------- - # Remove all instructions after ecall (end of program excecution) - sed -i '/ecall/q' "$ibex_log" - # Convert the spike log to riscv_instr_trace.proto format - ibex_csv=$(echo "$ibex_log" | sed 's/\.log/.csv/g') - python ./riscv_dv_extension/ibex_log_to_trace_csv.py \ - --log $ibex_log --csv $ibex_csv >> $report_file - - # ----------------------------------------------------------------------------- - # Compare the trace log - # ----------------------------------------------------------------------------- - python $script_path/scripts/instr_trace_compare.py $spike_csv $ibex_csv \ - "spike" "ibex" >> $report_file -} - -echo "compare simulation result under $RUN_DIR" -while read asm_test; do - SRC=$(echo "$asm_test" | sed 's/^.*\///g' | sed 's/\.S>*$//g') - echo "Test: $asm_test" >> $report_file - compare_log $RUN_DIR/instr_gen/spike_sim/$SRC.S.o.log \ - $RUN_DIR/rtl_sim/$SRC/trace_core_00_0.log -done <"$RUN_DIR/asm_test_list" - -passed_cnt="$(grep -c PASS $report_file)" -failed_cnt="$(grep -c FAIL $report_file)" -echo "$passed_cnt tests PASSED, $failed_cnt tests FAILED" >> $report_file - -cat $report_file diff --git a/dv/uvm/riscv_dv_extension/ibex_log_to_trace_csv.py b/dv/uvm/riscv_dv_extension/ibex_log_to_trace_csv.py index a4a28359..b1c9949d 100644 --- a/dv/uvm/riscv_dv_extension/ibex_log_to_trace_csv.py +++ b/dv/uvm/riscv_dv_extension/ibex_log_to_trace_csv.py @@ -27,6 +27,8 @@ def process_ibex_sim_log(ibex_log, csv): trace_csv = RiscvInstructiontTraceCsv(csv_fd) trace_csv.start_new_trace() for line in f: + if re.search("ecall", line): + break # Extract instruction infromation m = re.search(r"^\s*(?P