diff --git a/dv/riscv_compliance/rtl/riscv_testutil.sv b/dv/riscv_compliance/rtl/riscv_testutil.sv
index ce043c60..cc8e8ba6 100644
--- a/dv/riscv_compliance/rtl/riscv_testutil.sv
+++ b/dv/riscv_compliance/rtl/riscv_testutil.sv
@@ -116,6 +116,7 @@ module riscv_testutil (
   logic [31:0] read_addr_d, read_addr_q;
   always_comb begin
     state_d = state_q;
+    read_addr_d = read_addr_q;
     unique case (state_q)
       WAIT: begin
         if (read_signature_and_terminate) begin
diff --git a/shared/rtl/bus.sv b/shared/rtl/bus.sv
index 6650fec6..2fcf09c2 100644
--- a/shared/rtl/bus.sv
+++ b/shared/rtl/bus.sv
@@ -59,6 +59,7 @@ module bus #(
 
   // Master select prio arbiter
   always_comb begin
+    host_sel_req = '0;
     for (integer host = NrHosts - 1; host >= 0; host = host - 1) begin
       if (host_req_i[host]) begin
         host_sel_req = NumBitsHostSel'(host);
@@ -68,6 +69,7 @@ module bus #(
 
   // Device select
   always_comb begin
+    device_sel_req = '0;
     for (integer device = 0; device < NrDevices; device = device + 1) begin
       if ((host_addr_i[host_sel_req] & cfg_device_addr_mask[device])
           == cfg_device_addr_base[device]) begin