diff --git a/controller.sv b/controller.sv index a28b87bd..52efa12c 100644 --- a/controller.sv +++ b/controller.sv @@ -55,7 +55,6 @@ module controller output logic [1:0] alu_op_a_mux_sel_o, // Operator a is selected between reg value, PC or immediate output logic [1:0] alu_op_b_mux_sel_o, // Operator b is selected between reg value or immediate output logic alu_op_c_mux_sel_o, // Operator c is selected between reg value or PC - output logic alu_pc_mux_sel_o, // selects IF or ID PC for ALU computations output logic [2:0] immediate_mux_sel_o, output logic [1:0] vector_mode_o, // selects between 32 bit, 16 bit and 8 bit vectorial modes @@ -206,7 +205,6 @@ module controller alu_op_a_mux_sel_o = `OP_A_REGA_OR_FWD; alu_op_b_mux_sel_o = `OP_B_REGB_OR_FWD; alu_op_c_mux_sel_o = `OP_C_REGC_OR_FWD; - alu_pc_mux_sel_o = 1'b0; // TODO: Check if still needed (1'b0 never used) vector_mode_o = `VEC_MODE32; scalar_replication_o = 1'b0; @@ -333,7 +331,6 @@ module controller pc_mux_sel_o = `PC_NO_INCR; jump_in_id_o = 2'b01; // Calculate and store PC+4 - alu_pc_mux_sel_o = 1'b1; alu_op_a_mux_sel_o = `OP_A_CURRPC; alu_op_b_mux_sel_o = `OP_B_IMM; immediate_mux_sel_o = `IMM_PCINCR; @@ -352,7 +349,6 @@ module controller pc_mux_sel_o = `PC_NO_INCR; jump_in_id_o = 2'b01; // Calculate and store PC+4 - alu_pc_mux_sel_o = 1'b1; alu_op_a_mux_sel_o = `OP_A_CURRPC; alu_op_b_mux_sel_o = `OP_B_IMM; immediate_mux_sel_o = `IMM_PCINCR; @@ -563,7 +559,6 @@ module controller end `OPCODE_AUIPC: begin // Add Upper Immediate to PC - alu_pc_mux_sel_o = 1'b1; alu_op_a_mux_sel_o = `OP_A_CURRPC; alu_op_b_mux_sel_o = `OP_B_IMM; immediate_mux_sel_o = `IMM_U; @@ -1329,6 +1324,11 @@ module controller if(stall_ex_o == 1'b0) dbg_fsm_ns = DBG_FLUSH; end + + default: + begin + dbg_fsm_ns = DBG_IDLE; + end endcase // case (dbg_fsm_cs) end diff --git a/ex_stage.sv b/ex_stage.sv index 5d834436..3f2b8cef 100644 --- a/ex_stage.sv +++ b/ex_stage.sv @@ -63,7 +63,6 @@ module ex_stage output logic [31:0] data_addr_ex_o, // input from ID stage - input logic stall_ex_i, input logic stall_wb_i, input logic [4:0] regfile_alu_waddr_i, diff --git a/id_stage.sv b/id_stage.sv index c1076e88..b1fde18e 100644 --- a/id_stage.sv +++ b/id_stage.sv @@ -223,7 +223,6 @@ module id_stage logic [1:0] alu_cmp_mode; logic [1:0] alu_vec_ext; - logic alu_pc_mux_sel; logic [2:0] immediate_mux_sel; // Multiplier Control @@ -335,14 +334,7 @@ module id_stage // |___/ // /////////////////////////////////////////////////////////////////////////////////////// - // PC Mux - always_comb - begin : alu_pc_mux - case (alu_pc_mux_sel) - 1'b0: current_pc = current_pc_if_i; // TODO: FIXME 1'b0 is never used - 1'b1: current_pc = current_pc_id_i; - endcase; // case (alu_pc_mux_sel) - end + assign current_pc = current_pc_id_i; // hwloop_cnt_mux always_comb @@ -562,7 +554,6 @@ module id_stage .alu_op_a_mux_sel_o ( alu_op_a_mux_sel ), .alu_op_b_mux_sel_o ( alu_op_b_mux_sel ), .alu_op_c_mux_sel_o ( alu_op_c_mux_sel ), - .alu_pc_mux_sel_o ( alu_pc_mux_sel ), .immediate_mux_sel_o ( immediate_mux_sel ), .scalar_replication_o ( scalar_replication ), diff --git a/if_stage.sv b/if_stage.sv index 1c00ddf7..517bd9ab 100644 --- a/if_stage.sv +++ b/if_stage.sv @@ -7,6 +7,7 @@ // Additional contributions by: // // Igor Loi - igor.loi@unibo.it // // Andreas Traber - atraber@student.ethz.ch // +// Sven Stucki - svstucki@student.ethz.ch // // // // // // Create Date: 01/07/2014 // diff --git a/instr_core_interface.sv b/instr_core_interface.sv index f8578f67..5887abab 100644 --- a/instr_core_interface.sv +++ b/instr_core_interface.sv @@ -28,35 +28,33 @@ module instr_core_interface ( - input logic clk, - input logic rst_n, + input logic clk, + input logic rst_n, + input logic req_i, + input logic [31:0] addr_i, + output logic ack_o, + output logic [31:0] rdata_o, - input logic req_i, - input logic [31:0] addr_i, - output logic ack_o, - output logic [31:0] rdata_o, + output logic instr_req_o, + output logic [31:0] instr_addr_o, + input logic instr_gnt_i, + input logic instr_r_valid_i, + input logic [31:0] instr_r_rdata_i, + input logic stall_if_i, - output logic instr_req_o, - output logic [31:0] instr_addr_o, - input logic instr_gnt_i, - input logic instr_r_valid_i, - input logic [31:0] instr_r_rdata_i, - - input logic stall_if_i, - - input logic drop_request_i + input logic drop_request_i ); enum logic [2:0] {IDLE, PENDING, WAIT_RVALID, WAIT_IF_STALL, WAIT_GNT, ABORT} CS, NS; - logic save_rdata; - logic [31:0] rdata_Q; + logic save_rdata; + logic [31:0] rdata_Q; - logic wait_gnt; - logic [31:0] addr_Q; + logic wait_gnt; + logic [31:0] addr_Q; always_ff @(posedge clk, negedge rst_n) begin @@ -232,4 +230,4 @@ module instr_core_interface endcase end -endmodule \ No newline at end of file +endmodule diff --git a/riscv_core.sv b/riscv_core.sv index 5caffcb1..8f01d41e 100644 --- a/riscv_core.sv +++ b/riscv_core.sv @@ -10,12 +10,12 @@ // // // // // Create Date: 24/3/2015 // -// Design Name: RiscV Minion // +// Design Name: RISCV-V Core // // Module Name: riscv_core.sv // -// Project Name: RISCV // +// Project Name: RI5CY // // Language: SystemVerilog // // // -// Description: RiscV core // +// Description: Main module of the core // // // // // // Revision: // @@ -494,7 +494,6 @@ module riscv_core .csr_rdata_i ( csr_rdata ), // input from ID stage - .stall_ex_i ( stall_ex ), .stall_wb_i ( stall_wb ), .prepost_useincr_i ( useincr_addr_ex ), @@ -798,6 +797,7 @@ module riscv_core // Execution trace generation // synopsys translate_off + /* verilator lint off */ `ifdef TRACE_EXECUTION integer f; string fn;