diff --git a/alu.sv b/alu.sv
index 6b7bb90a..ce57aab0 100644
--- a/alu.sv
+++ b/alu.sv
@@ -46,6 +46,7 @@ module riscv_alu
   input  logic [ 4:0]              bmask_a_i,
   input  logic [ 4:0]              bmask_b_i,
   `endif // BIT_SUPPORT
+  // CONFIG_REGION: VEC_SUPPORT
   `ifdef VEC_SUPPORT
   input  logic [ 1:0]              imm_vec_ext_i,
   `endif // VEC_SUPPORT 
diff --git a/controller.sv b/controller.sv
index 450d432b..9ea4d578 100644
--- a/controller.sv
+++ b/controller.sv
@@ -663,6 +663,7 @@ module riscv_controller
 
       // CONFIG_REGION: MERGE_ID_EX
       `ifdef MERGE_ID_EX
+      // CONFIG_REGION: NO_JUMP_ADDER
       `ifdef NO_JUMP_ADDER
       WAIT_BRANCH_EX:
       begin
diff --git a/ex_stage.sv b/ex_stage.sv
index e09e2f95..eca84b51 100644
--- a/ex_stage.sv
+++ b/ex_stage.sv
@@ -164,7 +164,7 @@ module riscv_ex_stage
   `ifdef MUL_SUPPORT
   assign regfile_alu_wdata_fw_o = mult_en_i ? mult_result : alu_csr_result;
   `else
-  // CONFIG_REGION
+  // CONFIG_REGION: NO_JUMP_ADDER
   `ifdef NO_JUMP_ADDER
   assign regfile_alu_wdata_fw_o = jal_in_ex_i ? alu_operand_c_i : alu_csr_result; // Select return address
   `else
diff --git a/id_stage.sv b/id_stage.sv
index 2229ef2c..27d3b0a2 100644
--- a/id_stage.sv
+++ b/id_stage.sv
@@ -1174,6 +1174,7 @@ module riscv_id_stage
     // Register file control signals
     .regfile_mem_we_o                ( regfile_we_id             ),
     .regfile_alu_we_o                ( regfile_alu_we_id         ),
+    // CONFIG_REGION: THREE_PORT_REG_FILE
     `ifdef THREE_PORT_REG_FILE
     .regfile_alu_waddr_sel_o         ( regfile_alu_waddr_mux_sel ),
     `endif // THREE_PORT_REG_FILE
diff --git a/riscv_tracer.sv b/riscv_tracer.sv
index 2b8fff09..b129e33d 100644
--- a/riscv_tracer.sv
+++ b/riscv_tracer.sv
@@ -616,7 +616,7 @@ module riscv_tracer
     while(1) begin
       instr_ex.get(trace);
 
-      // CONFIG_REGION MERGE_ID_EX
+      // CONFIG_REGION: MERGE_ID_EX
       `ifndef MERGE_ID_EX
       // wait until we are going to the next stage
       do begin
@@ -640,7 +640,7 @@ module riscv_tracer
 
           trace.mem_access.push_back(mem_acc);
         end
-      // CONFIG_REGION MERGE_ID_EX
+      // CONFIG_REGION: MERGE_ID_EX
       `ifndef MERGE_ID_EX
       end while (!ex_valid && !wb_bypass); // ex branches bypass the WB stage
       `endif