diff --git a/controller.sv b/controller.sv index 6bea907a..c9f56d73 100644 --- a/controller.sv +++ b/controller.sv @@ -116,9 +116,7 @@ module controller input logic dbg_set_npc_i, // Change PC to value from debug unit output logic dbg_trap_o, // trap hit, inform debug unit - // SPR Signals - output logic set_carry_o, // to special purpose registers --> carry - output logic set_overflow_o, // to special purpose registers --> overflow + // CSR Signals output logic restore_sr_o, // restores status register after interrupt // Forwarding signals from regfile @@ -161,8 +159,6 @@ module controller logic regfile_alu_we; logic data_we; logic data_req; - logic set_overflow; - logic set_carry; logic deassert_we; logic lsu_stall; @@ -243,9 +239,6 @@ module controller data_reg_offset_o = 2'b00; data_req = 1'b0; - set_overflow = 1'b0; - set_carry = 1'b0; - restore_sr_o = 1'b0; clear_isr_running_o = 1'b0; @@ -1158,8 +1151,6 @@ module controller assign regfile_alu_we_o = (deassert_we) ? 1'b0 : regfile_alu_we; assign data_we_o = (deassert_we) ? 1'b0 : data_we; assign data_req_o = (deassert_we) ? 1'b0 : data_req; - assign set_overflow_o = (deassert_we) ? 1'b0 : set_overflow; - assign set_carry_o = (deassert_we) ? 1'b0 : set_carry; //////////////////////////////////////////////////////////////////////////////////////////// diff --git a/ex_stage.sv b/ex_stage.sv index 8848a493..5d834436 100644 --- a/ex_stage.sv +++ b/ex_stage.sv @@ -48,7 +48,6 @@ module ex_stage input logic [31:0] alu_operand_a_i, input logic [31:0] alu_operand_b_i, input logic [31:0] alu_operand_c_i, - input logic alu_carry_i, input logic [1:0] vector_mode_i, input logic [1:0] alu_cmp_mode_i, @@ -83,21 +82,11 @@ module ex_stage input logic [31:0] hwloop_pc_plus4_i, input logic [31:0] hwloop_cnt_i, - input logic set_overflow_i, - input logic set_carry_i, - // CSR access input logic csr_access_i, input logic [31:0] csr_rdata_i, // Output of EX stage pipeline - - output logic carry_o, - output logic overflow_o, - - output logic set_overflow_o, - output logic set_carry_o, - output logic [4:0] regfile_waddr_wb_o, output logic regfile_wdata_mux_sel_wb_o, output logic regfile_we_wb_o, @@ -123,24 +112,14 @@ module ex_stage ); - // Alu outputs - OVerflow and CarrY - logic alu_overflow_int; - logic alu_carry_int; - // Internal output of the LU logic [31:0] alu_result; logic [31:0] alu_adder_lsu_int; // to LS unit logic [31:0] mult_result; - logic mult_carry_int; - logic mult_overflow_int; - // Result Selection: Select between ALU output signals and MUL - assign carry_o = (mult_en_i == 1'b1) ? mult_carry_int : alu_carry_int; - assign overflow_o = (mult_en_i == 1'b1) ? mult_overflow_int : alu_overflow_int; - assign regfile_alu_we_fw_o = regfile_alu_we_i; assign regfile_alu_waddr_fw_o = regfile_alu_waddr_i; @@ -156,10 +135,6 @@ module ex_stage end // assign regfile_alu_wdata_fw_o = (mult_en_i == 1'b0) ? alu_result : mult_result; - // generate flags: goes to special purpose register - assign set_overflow_o = (stall_ex_i == 1'b0) ? set_overflow_i : 1'b0; - assign set_carry_o = (stall_ex_i == 1'b0) ? set_carry_i : 1'b0; - //NOTE Igor fix: replaced alu_adder_int with alu_adder_lsu_int --> Now data_addr is calculated with //NOTE a dedicated adder, no carry is considered , just op_a + op_b from id stage assign data_addr_ex_o = (prepost_useincr_i == 1'b1) ? alu_adder_lsu_int : alu_operand_a_i; @@ -198,7 +173,8 @@ module ex_stage .operand_a_i ( alu_operand_a_i ), .operand_b_i ( alu_operand_b_i ), .operand_c_i ( alu_operand_c_i ), - .carry_i ( alu_carry_i ), + .carry_i ( 1'b0 ), + .flag_i ( 1'b0 ), .vector_mode_i ( vector_mode_i ), .cmp_mode_i ( alu_cmp_mode_i ), @@ -207,8 +183,9 @@ module ex_stage .adder_lsu_o ( alu_adder_lsu_int ), .result_o ( alu_result ), - .overflow_o ( alu_overflow_int ), - .carry_o ( alu_carry_int ) + .overflow_o ( ), + .carry_o ( ), + .flag_o ( ) ); @@ -231,12 +208,12 @@ module ex_stage .op_a_i ( alu_operand_a_i ), .op_b_i ( alu_operand_b_i ), .mac_i ( alu_operand_c_i ), - .carry_i ( alu_carry_i ), + .carry_i ( 1'b0 ), .result_o ( mult_result ), - .carry_o ( mult_carry_int ), - .overflow_o ( mult_overflow_int ) + .carry_o ( ), + .overflow_o ( ) ); diff --git a/id_stage.sv b/id_stage.sv index d06a2f66..f4b55756 100644 --- a/id_stage.sv +++ b/id_stage.sv @@ -115,10 +115,6 @@ module id_stage input logic data_ack_i, // Grant from data memory input logic data_rvalid_i, - // SPR signals - output logic set_carry_ex_o, - output logic set_overflow_ex_o, - // Interrupt signals input logic irq_i, input logic irq_nm_i, @@ -262,10 +258,6 @@ module id_stage logic csr_access; logic [1:0] csr_op; - // Supervision Register - logic set_carry; - logic set_overflow; - logic prepost_useincr; // Forwarding @@ -633,8 +625,6 @@ module id_stage .dbg_trap_o ( dbg_trap_o ), // SPR Signals - .set_overflow_o ( set_overflow ), - .set_carry_o ( set_carry ), .restore_sr_o ( restore_sr_o ), // regfile port 1 @@ -803,9 +793,6 @@ module id_stage data_misaligned_ex_o <= 1'b0; - set_overflow_ex_o <= 1'b0; - set_carry_ex_o <= 1'b0; - hwloop_we_ex_o <= 3'b0; hwloop_regid_ex_o <= 2'b0; hwloop_wb_mux_sel_ex_o <= 1'b0; @@ -875,9 +862,6 @@ module id_stage data_misaligned_ex_o <= 1'b0; - set_overflow_ex_o <= set_overflow; - set_carry_ex_o <= set_carry; - hwloop_we_ex_o <= hwloop_we; hwloop_regid_ex_o <= hwloop_regid; hwloop_wb_mux_sel_ex_o <= hwloop_wb_mux_sel; diff --git a/riscv_core.sv b/riscv_core.sv index 27ae98ce..a8fa951d 100644 --- a/riscv_core.sv +++ b/riscv_core.sv @@ -121,10 +121,6 @@ module riscv_core logic [1:0] alu_cmp_mode_ex; logic [1:0] alu_vec_ext_ex; - // Result Control - logic carry_ex; - logic overflow_ex; - // Multiplier Control logic mult_en_ex; logic [1:0] mult_sel_subword_ex; @@ -170,15 +166,6 @@ module riscv_core logic [31:0] lsu_data_reg; logic data_ack_int; - // Supervision Register - logic set_carry_ex; - logic set_overflow_ex; - logic set_carry_fw_ex; - logic set_overflow_fw_ex; - - // Direct Supervision-Register access - logic carry_sp; - // Signals between instruction core interface and pipe (if and id stages) logic [31:0] instr_rdata_int; // read instruction from the instruction core interface to if_stage logic instr_req_int; // Id stage asserts a req to instruction core interface @@ -430,9 +417,6 @@ module riscv_core .data_ack_i ( data_ack_int ), // from load store unit .data_rvalid_i ( data_r_valid_i ), - .set_carry_ex_o ( set_carry_ex ), // to ex_stage - .set_overflow_ex_o ( set_overflow_ex ), // to ex_stage - // Interrupt Signals .irq_i ( irq_i ), // incoming interrupts .irq_nm_i ( irq_nm_i ), // incoming interrupts @@ -495,7 +479,6 @@ module riscv_core .alu_operand_a_i ( alu_operand_a_ex ), // from ID/EX pipe registers .alu_operand_b_i ( alu_operand_b_ex ), // from ID/EX pipe registers .alu_operand_c_i ( alu_operand_c_ex ), // from ID/EX pipe registers - .alu_carry_i ( carry_sp ), // from spr carry .vector_mode_i ( vector_mode_ex ), // from ID/EX pipe registers .alu_cmp_mode_i ( alu_cmp_mode_ex ), // from ID/EX pipe registers @@ -508,13 +491,6 @@ module riscv_core .mult_use_carry_i ( mult_use_carry_ex ), .mult_mac_en_i ( mult_mac_en_ex ), -/* - // interface with Special registers - .carry_o ( carry_ex ), - .overflow_o ( overflow_ex ), - .set_overflow_o ( set_overflow_fw_ex ), // to special registers - .set_carry_o ( set_carry_fw_ex ), // to special registers -*/ // interface with CSRs .csr_access_i ( csr_access_ex ), .csr_rdata_i ( csr_rdata ), @@ -539,9 +515,6 @@ module riscv_core .hwloop_cnt_i ( hwlp_cnt_ex ), //From ID stage.Controller - .set_overflow_i ( set_overflow_ex ), - .set_carry_i ( set_carry_ex ), - .regfile_rb_data_i ( regfile_rb_data_ex ), // Output of ex stage pipeline