diff --git a/id_stage.sv b/id_stage.sv index 84cc2a46..55fd0f2d 100644 --- a/id_stage.sv +++ b/id_stage.sv @@ -60,6 +60,7 @@ module id_stage output logic [1:0] exc_pc_mux_o, input logic illegal_c_insn_i, + input logic is_compressed_i, input logic [31:0] current_pc_if_i, input logic [31:0] current_pc_id_i, @@ -152,7 +153,6 @@ module id_stage // Compressed instruction decoding logic [31:0] instr; - logic is_compressed; // Immediate decoding and sign extension logic [31:0] imm_i_type; @@ -269,9 +269,6 @@ module id_stage assign instr = instr_rdata_i; - assign is_compressed = (instr[1:0] != 2'b11); - - assign perf_compressed_o = is_compressed; // immediate extraction and sign extension assign imm_i_type = { {20 {instr[31]}}, instr[31:20] }; @@ -411,7 +408,7 @@ module id_stage `IMM_I: immediate_b = imm_i_type; `IMM_S: immediate_b = imm_s_type; `IMM_U: immediate_b = imm_u_type; - `IMM_PCINCR: immediate_b = is_compressed ? 32'h2 : 32'h4; + `IMM_PCINCR: immediate_b = is_compressed_i ? 32'h2 : 32'h4; default: immediate_b = imm_i_type; endcase; // case (immediate_mux_sel) end diff --git a/if_stage.sv b/if_stage.sv index 80873bad..446786b3 100644 --- a/if_stage.sv +++ b/if_stage.sv @@ -44,7 +44,6 @@ module if_stage // instruction request control input logic req_i, output logic valid_o, - input logic drop_request_i, // instruction cache interface output logic instr_req_o, @@ -55,6 +54,7 @@ module if_stage // Output of IF Pipeline stage output logic [31:0] instr_rdata_id_o, // read instruction is sampled and sent to ID stage for decoding + output logic is_compressed_id_o, // compressed decoder thinks this is a compressed instruction output logic illegal_c_insn_id_o, // compressed decoder thinks this is an invalid instruction output logic [31:0] current_pc_if_o, output logic [31:0] current_pc_id_o, @@ -344,13 +344,14 @@ module if_stage // to ease timing closure logic [31:0] instr_decompressed; logic illegal_c_insn; + logic instr_compressed_int; compressed_decoder compressed_decoder_i ( - .instr_i ( instr_rdata_int ), - .instr_o ( instr_decompressed ), - .is_compressed_o ( ), - .illegal_instr_o ( illegal_c_insn ) + .instr_i ( instr_rdata_int ), + .instr_o ( instr_decompressed ), + .is_compressed_o ( instr_compressed_int ), + .illegal_instr_o ( illegal_c_insn ) ); @@ -359,17 +360,19 @@ module if_stage begin : IF_ID_PIPE_REGISTERS if (rst_n == 1'b0) begin - instr_rdata_id_o <= '0; - illegal_c_insn_id_o <= 1'b0; - current_pc_id_o <= '0; + instr_rdata_id_o <= '0; + illegal_c_insn_id_o <= 1'b0; + is_compressed_id_o <= 1'b0; + current_pc_id_o <= '0; end else begin if (~stall_id_i) begin : ENABLED_PIPE - instr_rdata_id_o <= instr_decompressed; - illegal_c_insn_id_o <= illegal_c_insn; - current_pc_id_o <= current_pc_if_o; + instr_rdata_id_o <= instr_decompressed; + illegal_c_insn_id_o <= illegal_c_insn; + is_compressed_id_o <= instr_compressed_int; + current_pc_id_o <= current_pc_if_o; end end end diff --git a/riscv_core.sv b/riscv_core.sv index 24c84416..6d70da5d 100644 --- a/riscv_core.sv +++ b/riscv_core.sv @@ -83,6 +83,7 @@ module riscv_core // IF/ID signals logic [31:0] instr_rdata_id; // Instruction sampled inside IF stage + logic is_compressed_id; logic illegal_c_insn_id; // Illegal compressed instruction sent to ID stage logic [31:0] current_pc_if; // Current Program counter logic [31:0] current_pc_id; // Current Program counter @@ -91,7 +92,6 @@ module riscv_core logic [1:0] exc_pc_mux_id; // Mux selector for exception PC // ID performance counter signals - logic perf_compressed; logic is_decoding; @@ -233,7 +233,6 @@ module riscv_core // instruction request control .req_i ( instr_req_int ), .valid_o ( instr_ack_int ), - .drop_request_i ( 1'b0 ), // instruction cache interface .instr_req_o ( instr_req_o ), @@ -244,6 +243,7 @@ module riscv_core // outputs to ID stage .instr_rdata_id_o ( instr_rdata_id ), // Output of IF Pipeline stage + .is_compressed_id_o ( is_compressed_id ), .illegal_c_insn_id_o ( illegal_c_insn_id ), .current_pc_if_o ( current_pc_if ), // current pc in IF stage .current_pc_id_o ( current_pc_id ), // current pc in ID stage @@ -311,6 +311,7 @@ module riscv_core .pc_mux_sel_o ( pc_mux_sel_id ), .exc_pc_mux_o ( exc_pc_mux_id ), + .is_compressed_i ( is_compressed_id ), .illegal_c_insn_i ( illegal_c_insn_id ), .current_pc_if_i ( current_pc_if ), @@ -395,7 +396,6 @@ module riscv_core .regfile_we_wb_i ( regfile_we_wb ), // write enable for the register file .regfile_wdata_wb_i ( regfile_wdata ), // write data to commit in the register file - .perf_compressed_o ( perf_compressed ), .perf_jump_o ( perf_jump ), .perf_branch_o ( perf_branch ), .perf_jr_stall_o ( perf_jr_stall ), @@ -547,9 +547,9 @@ module riscv_core .epcr_o ( epcr ), // performance counter related signals - .stall_id_i ( stall_id ), - .is_compressed_i ( perf_compressed ), - .is_decoding_i ( is_decoding ), + .stall_id_i ( stall_id ), + .is_compressed_i ( is_compressed_id ), + .is_decoding_i ( is_decoding ), .instr_fetch_i ( ~instr_ack_int ), @@ -653,7 +653,7 @@ module riscv_core begin // get current PC and instruction instr = id_stage_i.instr[31:0]; - compressed = id_stage_i.is_compressed; + compressed = id_stage_i.is_compressed_i; pc = id_stage_i.current_pc_id_i; // get register values