diff --git a/dv/uvm/core_ibex/riscv_dv_extension/ibex_asm_program_gen.sv b/dv/uvm/core_ibex/riscv_dv_extension/ibex_asm_program_gen.sv
index d64cb50f..5b20a205 100644
--- a/dv/uvm/core_ibex/riscv_dv_extension/ibex_asm_program_gen.sv
+++ b/dv/uvm/core_ibex/riscv_dv_extension/ibex_asm_program_gen.sv
@@ -17,6 +17,9 @@ class ibex_asm_program_gen extends riscv_asm_program_gen;
       MVENDORID,
       MARCHID,
       MHARTID,
+      MCONFIGPTR,
+      MENVCFG,
+      MSTATUSH,
       MIMPID,
       MCYCLE,
       MCYCLEH,
diff --git a/dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.tpl.sv b/dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.tpl.sv
index e87186dd..3b3b8308 100644
--- a/dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.tpl.sv
+++ b/dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.tpl.sv
@@ -120,7 +120,10 @@ const privileged_reg_t implemented_csr[] = {
     MIMPID,           // Implementation ID
     MARCHID,          // Architecture ID
     MHARTID,          // Hardware thread ID
-    MSTATUS,          // Machine status
+    MCONFIGPTR,       // Machine configuration pointer
+    MENVCFG,          // Machine environment configuration (lower 32 bits)
+    MSTATUS,          // Machine status (lower 32 bits)
+    MSTATUSH,         // Machine status (upper 32 bits)
     MISA,             // ISA and extensions
     MTVEC,            // Machine trap-handler base address
     MEPC,             // Machine exception program counter
diff --git a/rtl/ibex_cs_registers.sv b/rtl/ibex_cs_registers.sv
index 7054316d..64c108f1 100644
--- a/rtl/ibex_cs_registers.sv
+++ b/rtl/ibex_cs_registers.sv
@@ -330,6 +330,8 @@ module ibex_cs_registers #(
       CSR_MIMPID: csr_rdata_int = CSR_MIMPID_VALUE;
       // mhartid: unique hardware thread id
       CSR_MHARTID: csr_rdata_int = hart_id_i;
+      // mconfigptr: pointer to configuration data structre
+      CSR_MCONFIGPTR: csr_rdata_int = CSR_MCONFIGPTR_VALUE;
 
       // mstatus: always M-mode, contains IE bit
       CSR_MSTATUS: begin
@@ -341,6 +343,13 @@ module ibex_cs_registers #(
         csr_rdata_int[CSR_MSTATUS_TW_BIT]                               = mstatus_q.tw;
       end
 
+      // mstatush: All zeros for Ibex (fixed little endian and all other bits reserved)
+      CSR_MSTATUSH: csr_rdata_int = '0;
+
+      // menvcfg: machine environment configuration, all zeros for Ibex (none of the relevant
+      // features are implemented)
+      CSR_MENVCFG, CSR_MENVCFGH: csr_rdata_int = '0;
+
       // misa
       CSR_MISA: csr_rdata_int = MISA_VALUE;
 
diff --git a/rtl/ibex_pkg.sv b/rtl/ibex_pkg.sv
index 7f64ab2d..c0260847 100644
--- a/rtl/ibex_pkg.sv
+++ b/rtl/ibex_pkg.sv
@@ -425,10 +425,11 @@ package ibex_pkg;
   // CSRs
   typedef enum logic[11:0] {
     // Machine information
-    CSR_MVENDORID = 12'hF11,
-    CSR_MARCHID   = 12'hF12,
-    CSR_MIMPID    = 12'hF13,
-    CSR_MHARTID   = 12'hF14,
+    CSR_MVENDORID  = 12'hF11,
+    CSR_MARCHID    = 12'hF12,
+    CSR_MIMPID     = 12'hF13,
+    CSR_MHARTID    = 12'hF14,
+    CSR_MCONFIGPTR = 12'hF15,
 
     // Machine trap setup
     CSR_MSTATUS   = 12'h300,
@@ -436,6 +437,10 @@ package ibex_pkg;
     CSR_MIE       = 12'h304,
     CSR_MTVEC     = 12'h305,
     CSR_MCOUNTEREN= 12'h306,
+    CSR_MSTATUSH  = 12'h310,
+
+    CSR_MENVCFG   = 12'h30A,
+    CSR_MENVCFGH  = 12'h31A,
 
     // Machine trap handling
     CSR_MSCRATCH  = 12'h340,
@@ -627,6 +632,11 @@ package ibex_pkg;
   // commit).
   localparam logic [31:0] CSR_MIMPID_VALUE = 32'b0;
 
+  // Machine Configuration Pointer
+  // 0 indicates the configuration data structure does not eixst. Ibex implementors may wish to
+  // alter this to point to their system specific configuration data structure.
+  localparam logic [31:0] CSR_MCONFIGPTR_VALUE = 32'b0;
+
   // These LFSR parameters have been generated with
   // $ opentitan/util/design/gen-lfsr-seed.py --width 32 --seed 2480124384 --prefix ""
   parameter int LfsrWidth = 32;