From 1f2eef760667a8d75a9f2ab86e0f26d75cd19428 Mon Sep 17 00:00:00 2001
From: Andreas Traber <andytraber@gmail.com>
Date: Wed, 23 Mar 2016 13:38:00 +0100
Subject: [PATCH] Disabled simchecker per default again

---
 include/riscv_defines.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/riscv_defines.sv b/include/riscv_defines.sv
index 707a87eb..6dd66d88 100644
--- a/include/riscv_defines.sv
+++ b/include/riscv_defines.sv
@@ -29,7 +29,7 @@
 // no traces for synthesis, they are not synthesizable
 `ifndef SYNTHESIS
 `define TRACE_EXECUTION
-`define SIMCHECKER
+//`define SIMCHECKER
 `endif