diff --git a/rtl/ibex_core.sv b/rtl/ibex_core.sv index dab16801..ac0dbc5e 100644 --- a/rtl/ibex_core.sv +++ b/rtl/ibex_core.sv @@ -109,6 +109,7 @@ module ibex_core #( // IF/ID signals logic instr_valid_id; + logic instr_new_id; logic [31:0] instr_rdata_id; // Instruction sampled inside IF stage logic [15:0] instr_rdata_c_id; // Compressed instruction sampled inside IF stage logic instr_is_compressed_id; @@ -313,6 +314,7 @@ module ibex_core #( // outputs to ID stage .instr_valid_id_o ( instr_valid_id ), + .instr_new_id_o ( instr_new_id ), .instr_rdata_id_o ( instr_rdata_id ), .instr_rdata_c_id_o ( instr_rdata_c_id ), .instr_is_compressed_id_o ( instr_is_compressed_id ), @@ -365,18 +367,19 @@ module ibex_core #( .is_decoding_o ( is_decoding ), .illegal_insn_o ( illegal_insn_id ), - // Interface to instruction memory + // from/to IF-ID pipeline register .instr_valid_i ( instr_valid_id ), + .instr_new_i ( instr_new_id ), .instr_rdata_i ( instr_rdata_id ), .instr_rdata_c_i ( instr_rdata_c_id ), .instr_is_compressed_i ( instr_is_compressed_id ), - .instr_req_o ( instr_req_int ), // Jumps and branches .branch_decision_i ( branch_decision ), // IF and ID control signals .instr_valid_clear_o ( instr_valid_clear ), + .instr_req_o ( instr_req_int ), .pc_set_o ( pc_set ), .pc_mux_o ( pc_mux_id ), .exc_pc_mux_o ( exc_pc_mux_id ), diff --git a/rtl/ibex_decoder.sv b/rtl/ibex_decoder.sv index ad50faba..a8a4798e 100644 --- a/rtl/ibex_decoder.sv +++ b/rtl/ibex_decoder.sv @@ -28,8 +28,6 @@ module ibex_decoder #( parameter bit RV32M = 1 ) ( // singals running to/from controller - input logic branch_mux_i, - input logic jump_mux_i, output logic illegal_insn_o, // illegal instr encountered output logic ebrk_insn_o, // trap instr encountered output logic mret_insn_o, // return from exception instr @@ -39,6 +37,7 @@ module ibex_decoder #( output logic pipe_flush_o, // pipeline flush is requested // from IF/ID pipeline + input logic instr_new_i, // instruction read is new input logic [31:0] instr_rdata_i, // instruction read from memory/cache input logic illegal_c_insn_i, // compressed instruction decode failed @@ -136,7 +135,7 @@ module ibex_decoder #( OPCODE_JAL: begin // Jump and Link jump_in_dec_o = 1'b1; - if (jump_mux_i) begin + if (instr_new_i) begin // Calculate jump target alu_op_a_mux_sel_o = OP_A_CURRPC; alu_op_b_mux_sel_o = OP_B_IMM; @@ -155,7 +154,7 @@ module ibex_decoder #( OPCODE_JALR: begin // Jump and Link Register jump_in_dec_o = 1'b1; - if (jump_mux_i) begin + if (instr_new_i) begin // Calculate jump target alu_op_a_mux_sel_o = OP_A_REG_A; alu_op_b_mux_sel_o = OP_B_IMM; @@ -177,7 +176,7 @@ module ibex_decoder #( OPCODE_BRANCH: begin // Branch branch_in_dec_o = 1'b1; - if (branch_mux_i) begin + if (instr_new_i) begin unique case (instr_rdata_i[14:12]) 3'b000: alu_operator_o = ALU_EQ; 3'b001: alu_operator_o = ALU_NE; diff --git a/rtl/ibex_id_stage.sv b/rtl/ibex_id_stage.sv index d5aee326..980e2cfa 100644 --- a/rtl/ibex_id_stage.sv +++ b/rtl/ibex_id_stage.sv @@ -53,6 +53,7 @@ module ibex_id_stage #( // Interface to IF stage input logic instr_valid_i, + input logic instr_new_i, input logic [31:0] instr_rdata_i, // from IF-ID pipeline registers input logic [15:0] instr_rdata_c_i, // from IF-ID pipeline registers input logic instr_is_compressed_i, @@ -169,9 +170,7 @@ module ibex_id_stage #( logic branch_in_id, branch_in_dec; logic branch_set_n, branch_set_q; - logic branch_mux_dec; logic jump_set; - logic jump_mux_dec; logic jump_in_id, jump_in_dec; logic instr_multicycle; @@ -388,9 +387,6 @@ module ibex_id_stage #( ibex_decoder #( .RV32M ( RV32M ) ) decoder_i ( // controller related signals - .branch_mux_i ( branch_mux_dec ), - .jump_mux_i ( jump_mux_dec ), - .illegal_insn_o ( illegal_insn_dec ), .ebrk_insn_o ( ebrk_insn ), .mret_insn_o ( mret_insn_dec ), @@ -399,6 +395,7 @@ module ibex_id_stage #( .pipe_flush_o ( pipe_flush_dec ), // from IF/ID pipeline + .instr_new_i ( instr_new_i ), .instr_rdata_i ( instr ), .illegal_c_insn_i ( illegal_c_insn_i ), @@ -635,16 +632,12 @@ module ibex_id_stage #( select_data_rf = RF_EX; instr_multicycle = 1'b0; branch_set_n = 1'b0; - branch_mux_dec = 1'b0; jump_set = 1'b0; - jump_mux_dec = 1'b0; perf_branch_o = 1'b0; unique case (id_wb_fsm_cs) IDLE: begin - jump_mux_dec = 1'b1; - branch_mux_dec = 1'b1; unique case (1'b1) data_req_id: begin //LSU operation diff --git a/rtl/ibex_if_stage.sv b/rtl/ibex_if_stage.sv index 1024bedb..0cd1c855 100644 --- a/rtl/ibex_if_stage.sv +++ b/rtl/ibex_if_stage.sv @@ -49,6 +49,7 @@ module ibex_if_stage #( // Output of IF Pipeline stage output logic instr_valid_id_o, // instr in IF-ID is valid + output logic instr_new_id_o, // instr in IF-ID is new output logic [31:0] instr_rdata_id_o, // instr for ID stage output logic [15:0] instr_rdata_c_id_o, // compressed instr for ID stage // (mtval), meaningful only if @@ -232,6 +233,7 @@ module ibex_if_stage #( // IF-ID pipeline registers, frozen when the ID stage is stalled always_ff @(posedge clk_i or negedge rst_ni) begin : if_id_pipeline_regs if (!rst_ni) begin + instr_new_id_o <= 1'b0; instr_valid_id_o <= 1'b0; instr_rdata_id_o <= '0; instr_rdata_c_id_o <= '0; @@ -239,6 +241,7 @@ module ibex_if_stage #( illegal_c_insn_id_o <= 1'b0; pc_id_o <= '0; end else begin + instr_new_id_o <= if_valid_o; if (if_valid_o) begin instr_valid_id_o <= 1'b1; instr_rdata_id_o <= instr_decompressed;