diff --git a/controller.sv b/controller.sv
index 9ea4d578..fcabcca9 100644
--- a/controller.sv
+++ b/controller.sv
@@ -447,8 +447,13 @@ module riscv_controller
             if (id_ready_i) begin
               if ((jump_in_id_i == BRANCH_COND) & branch_taken_ex_i & id_ready_i)
               begin
-                pc_mux_o = PC_BRANCH;
-                pc_set_o = 1'b1;
+                // CONFIG_REGION: NO_JUMP_ADDER
+                `ifdef NO_JUMP_ADDER
+                  ctrl_fsm_ns = WAIT_BRANCH_EX;
+                `else
+                  pc_mux_o = PC_BRANCH;
+                  pc_set_o = 1'b1;
+                `endif
               end
 
               ctrl_fsm_ns = DBG_SIGNAL;
@@ -669,6 +674,7 @@ module riscv_controller
       begin
         // there is a branch in the EX stage that is taken
         branch_stall_o = 1'b1;
+        is_decoding_o = 1'b1;
         halt_if_o = 1'b1;
         if (id_ready_i)
         begin
@@ -963,7 +969,7 @@ module riscv_controller
     `endif // ONLY_ALIGNED
     
     // CONFIG_REGION: MUL_SUPPORT
-    `ifdef MUL_SUPPORT 
+    `ifdef MUL_SUPPORT
     else if (mult_multicycle_i) begin
       operand_c_fw_mux_sel_o  = SEL_FW_EX;
     end
diff --git a/id_stage.sv b/id_stage.sv
index 27d3b0a2..3773e8f2 100644
--- a/id_stage.sv
+++ b/id_stage.sv
@@ -774,11 +774,12 @@ module riscv_id_stage
   always_comb
     begin : operand_a_fw_mux
       case (operand_a_fw_mux_sel)
+        // CONFIG_REGION: MERGE_ID_EX
+        `ifndef MERGE_ID_EX
         SEL_FW_EX:    operand_a_fw_id = regfile_alu_wdata_fw_i;
+        `else
         // CONFIG_REGION: ONLY_ALIGNED
         `ifndef ONLY_ALIGNED
-        // CONFIG_REGION: MERGE_ID_EX
-        `ifdef MERGE_ID_EX
         SEL_MISALIGNED:    operand_a_fw_id = misaligned_addr_i;
         `endif
         `endif