diff --git a/dv/uvm/Makefile b/dv/uvm/Makefile index da77d01f..0de602d3 100644 --- a/dv/uvm/Makefile +++ b/dv/uvm/Makefile @@ -49,7 +49,13 @@ clean: # Generate random instructions gen: mkdir -p ${OUT} - cd ${GEN_DIR}; ./run -o ${OUT}/instr_gen ${GEN_OPTS}; + cd ${GEN_DIR}; \ + ./run -o ${OUT}/instr_gen ${GEN_OPTS} \ + -cmp_opts "+define+RISCV_CORE_SETTING=${DV_DIR}/riscv_dv_extension/ibex_core_setting.sv \ + +define+RISCV_DV_EXT_FILE_LIST=${DV_DIR}/riscv_dv_extension/flist \ + +incdir+${DV_DIR}/riscv_dv_extension/ " \ + -testlist ${DV_DIR}/riscv_dv_extension/testlist \ + -sim_opts "+uvm_set_type_override=riscv_asm_program_gen,ibex_asm_program_gen"; # ISS simulation iss_sim: diff --git a/dv/uvm/compare b/dv/uvm/compare index 7296c595..ddcfb95c 100755 --- a/dv/uvm/compare +++ b/dv/uvm/compare @@ -32,7 +32,7 @@ compare_log () { sed -i '/ecall/q' "$ibex_log" # Convert the spike log to riscv_instr_trace.proto format ibex_csv=$(echo "$ibex_log" | sed 's/\.log/.csv/g') - python $script_path/scripts/ibex_log_to_trace_csv.py \ + python ./riscv_dv_extension/ibex_log_to_trace_csv.py \ --log $ibex_log --csv $ibex_csv >> $report_file # ----------------------------------------------------------------------------- diff --git a/dv/uvm/riscv_dv_extension/flist b/dv/uvm/riscv_dv_extension/flist new file mode 100644 index 00000000..97e836cd --- /dev/null +++ b/dv/uvm/riscv_dv_extension/flist @@ -0,0 +1 @@ +`include "ibex_asm_program_gen.sv" diff --git a/dv/uvm/riscv_dv_extension/ibex_asm_program_gen.sv b/dv/uvm/riscv_dv_extension/ibex_asm_program_gen.sv new file mode 100644 index 00000000..0845308d --- /dev/null +++ b/dv/uvm/riscv_dv_extension/ibex_asm_program_gen.sv @@ -0,0 +1,45 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +//----------------------------------------------------------------------------------------- +// RISC-V assembly program generator for ibex +//----------------------------------------------------------------------------------------- + +class ibex_asm_program_gen extends riscv_asm_program_gen; + + `uvm_object_utils(ibex_asm_program_gen) + `uvm_object_new + + virtual function void gen_program_header(); + // Override the cfg value, below field is not supported by ibex + cfg.mstatus_mprv = 0; + cfg.mstatus_mxr = 0; + cfg.mstatus_sum = 0; + cfg.mstatus_tvm = 0; + // The ibex core load the program from 0x80 + // Some address is reserved for hardware interrupt handling, need to decide if we need to copy + // the init program from crt0.S later. + instr_stream.push_back(".macro init"); + instr_stream.push_back(".endm"); + instr_stream.push_back(".section .text.init"); + instr_stream.push_back(".globl _start"); + instr_stream.push_back("j _start"); + // Align the start section to 0x80 + instr_stream.push_back(".align 7"); + instr_stream.push_back("_start: j _reset_entry"); + // ibex reserves 0x84-0x8C for trap handling, redirect everything mtvec_handler + // 0x84 illegal instruction + instr_stream.push_back(".align 2"); + instr_stream.push_back("j mtvec_handler"); + // 0x88 ECALL instruction handler + instr_stream.push_back(".align 2"); + instr_stream.push_back("j mtvec_handler"); + // 0x8C LSU error + instr_stream.push_back(".align 2"); + instr_stream.push_back("j mtvec_handler"); + // Starting point of the reset entry + instr_stream.push_back("_reset_entry:"); + endfunction + +endclass diff --git a/vendor/google_riscv-dv/src/riscv_core_setting.sv b/dv/uvm/riscv_dv_extension/ibex_core_setting.sv similarity index 100% rename from vendor/google_riscv-dv/src/riscv_core_setting.sv rename to dv/uvm/riscv_dv_extension/ibex_core_setting.sv diff --git a/dv/uvm/riscv_dv_extension/ibex_log_to_trace_csv.py b/dv/uvm/riscv_dv_extension/ibex_log_to_trace_csv.py new file mode 100644 index 00000000..7cfc50a6 --- /dev/null +++ b/dv/uvm/riscv_dv_extension/ibex_log_to_trace_csv.py @@ -0,0 +1,53 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# Convert ibex log to the standard trace CSV format + +import argparse +import re + +from riscv_trace_csv import * + + +def process_ibex_sim_log(ibex_log, csv): + """Process ibex simulation log. + + Extract instruction and affected register information from ibex simulation + log and save to a standard CSV format. + """ + print("Processing ibex log : %s" % ibex_log) + instr_cnt = 0 + ibex_instr = "" + + with open(ibex_log, "r") as f, open(csv, "w") as csv_fd: + trace_csv = RiscvInstructiontTraceCsv(csv_fd) + trace_csv.start_new_trace() + for line in f: + # Extract instruction infromation + m = re.search(r"^\s*(?P