diff --git a/decoder.sv b/decoder.sv
index 275fcd31..bd598e48 100644
--- a/decoder.sv
+++ b/decoder.sv
@@ -145,8 +145,12 @@ module riscv_decoder
 
   // jump/branches
   output logic [1:0]  jump_in_dec_o,           // jump_in_id without deassert
-  output logic [1:0]  jump_in_id_o,            // jump is being calculated in ALU
+  output logic [1:0]  jump_in_id_o            // jump is being calculated in ALU
+  // CONFIG_REGION: NO_JUMP_ADDER
+  `ifdef NO_JUMP_ADDER
+  ,
   output logic [1:0]  jump_target_mux_sel_o    // jump target selection
+  `endif
 );
 
   // write enable/request control
@@ -183,7 +187,10 @@ module riscv_decoder
   always_comb
   begin
     jump_in_id                  = BRANCH_NONE;
+    // CONFIG_REGION: NO_JUMP_ADDER
+    `ifdef NO_JUMP_ADDER
     jump_target_mux_sel_o       = JT_JAL;
+    `endif
 
     alu_operator_o              = ALU_SLTU;
     alu_op_a_mux_sel_o          = OP_A_REGA_OR_FWD;
@@ -401,7 +408,7 @@ module riscv_decoder
           rega_used_o         = 1'b1;
         end
         
-        `else
+        `else // NO_JUMP_ADDER
         jump_target_mux_sel_o = JT_COND;
         jump_in_id            = BRANCH_COND;
         alu_op_c_mux_sel_o    = OP_C_JT;
diff --git a/ex_stage.sv b/ex_stage.sv
index cdd94b9f..e09e2f95 100644
--- a/ex_stage.sv
+++ b/ex_stage.sv
@@ -91,7 +91,7 @@ module riscv_ex_stage
   input  logic        regfile_alu_we_i,
   // CONFIG_REGION: NO_JUMP_ADDER
   `ifdef NO_JUMP_ADDER
-  input  logic        jump_in_ex_i,
+  input  logic        jal_in_ex_i,
   `endif
 
   // directly passed through to WB stage, not used in EX
@@ -166,7 +166,7 @@ module riscv_ex_stage
   `else
   // CONFIG_REGION
   `ifdef NO_JUMP_ADDER
-  assign regfile_alu_wdata_fw_o = jump_in_ex_i ? alu_operand_c_i : alu_csr_result; // Select return address
+  assign regfile_alu_wdata_fw_o = jal_in_ex_i ? alu_operand_c_i : alu_csr_result; // Select return address
   `else
   assign regfile_alu_wdata_fw_o = alu_csr_result;
   `endif
diff --git a/id_stage.sv b/id_stage.sv
index b19dcb91..67ba49f6 100644
--- a/id_stage.sv
+++ b/id_stage.sv
@@ -127,7 +127,7 @@ module riscv_id_stage
 
     // CONFIG_REGION: NO_JUMP_ADDER
     `ifdef NO_JUMP_ADDER
-    output logic        jump_in_ex_o, // Select operand C as return address to save in regfile
+    output logic        jal_in_ex_o, // Select operand C as return address to save in regfile
     `endif
 
     // CONFIG_REGION: BIT_SUPPORT
@@ -1209,9 +1209,12 @@ module riscv_id_stage
 
     // jump/branches
     .jump_in_dec_o                   ( jump_in_dec               ),
-    .jump_in_id_o                    ( jump_in_id                ),
+    .jump_in_id_o                    ( jump_in_id                )
+    // CONFIG_REGION: NO_JUMP_ADDER
+    `ifdef NO_JUMP_ADDER
+    ,
     .jump_target_mux_sel_o           ( jump_target_mux_sel       )
-
+    `endif
   );
 
   ////////////////////////////////////////////////////////////////////
@@ -1764,6 +1767,10 @@ module riscv_id_stage
 
     pc_ex_o                     = pc_id_i;
     branch_in_ex_o              = (jump_in_id == BRANCH_COND);
+    // CONFIG_REGION: NO_JUMP_ADDER
+    `ifdef NO_JUMP_ADDER
+    jal_in_ex_o                = ((jump_in_id == BRANCH_JALR) || (jump_in_id == BRANCH_JAL));
+    `endif
   end
 
 
diff --git a/riscv_core.sv b/riscv_core.sv
index a2c9b625..4764a3f1 100644
--- a/riscv_core.sv
+++ b/riscv_core.sv
@@ -171,7 +171,7 @@ module riscv_core
   logic [31:0] alu_operand_c_ex;
   // CONFIG_REGION: NO_JUMP_ADDER
   `ifdef NO_JUMP_ADDER
-  logic        jump_in_ex;
+  logic        jal_in_ex;
     `endif
 
   // CONFIG_REGION: SPLITTED_ADDER
@@ -536,11 +536,6 @@ module riscv_core
     .ex_valid_i                   ( ex_valid             ),
     .wb_valid_i                   ( wb_valid             ),
 
-    // CONFIG_REGION: MERGE_ID_EX
-    `ifdef MERGE_ID_EX
-    .id_wait_o                    ( id_wait              ),
-    `endif
-
     // From the Pipeline ID/EX
     // CONFIG_REGION: MERGE_ID_EX
     `ifndef MERGE_ID_EX
@@ -558,7 +553,7 @@ module riscv_core
 
     // CONFIG_REGION: NO_JUMP_ADDER
     `ifdef NO_JUMP_ADDER
-    .jump_in_ex_o                 ( jump_in_ex           ),
+    .jal_in_ex_o                 ( jal_in_ex           ),
     `endif
 
     // CONFIG_REGION: BIT_SUPPORT
@@ -767,7 +762,7 @@ module riscv_core
     .regfile_alu_we_i           ( regfile_alu_we_ex            ),
     // CONFIG_REGION: NO_JUMP_ADDER
     `ifdef NO_JUMP_ADDER
-    .jump_in_ex_i               ( jump_in_ex                   ),
+    .jal_in_ex_i               ( jal_in_ex                   ),
     `endif
 
     // CONFIG_REGION: THREE_PORT_REG_FILE
@@ -879,10 +874,6 @@ module riscv_core
     `endif
 
     .ex_valid_i            ( ex_valid           ),
-    // CONFIG_REGION: MERGE_ID_EX
-    `ifdef MERGE_ID_EX
-    .id_wait_i             ( id_wait            ),
-    `endif
     .busy_o                ( lsu_busy           )
   );